ANALOG DEVICES Le*MOS Dual 12-Bit DACPORT AD7237/AD7247 FEATURES Complete Dual 12-Bit DAC Comprising Two 12-Bit CMOS DACs On-Chip Voltage Reference Output Amplifiers Reference Buffer Amplifiers Parallel Loading Structure: AD7247 {8+4) Loading Structure: AD7237 Single or Dual Supply Operation Low Power ~ 165 mW typ in Single Supply GENERAL DESCRIPTION The AD7237/AD7247 is a complete, dual, 12-bit, voltage output digital-to-analog converter with ourput amplifiers and Zener voltage reference on a monolithic CMOS chip. No external user trims are required to achieve full specified performance. Both parts are microprocessor compatible, with high speed data latches and interface logic, The AD7247 accepts 12-bit parallel data which is loaded into the respective DAC latch using the WR input and a separate Chip Select input for each DAC. The AD7237 has a double buffered interface structure and an 8-bit wide data bus with data loaded to the respective input latch in two write operations. An asynchronous LDAC signal on the AD?237 updates the DAC latches and analog outputs. A REF OUT/REF IN function is provided which allows either the on-chip 5 V reference or an external reference to be used as a reference voltage for the part. For single supply operation, two output ranges of 0 to +5 V and 6 to +10 V are available, while these two ranges plus an additional &5 V range are available with dual supplies. The output amplifiers are capable of devel- oping +10 V across a 2 kQ load to GND. The AD7237/AD7247 is fabricated in Linear Compatible CMOS (LCMOS), an advanced, mixed technology process that com- bines precision bipolar circuits with low power CMOS logic. Both parts are available in a 24-pin, 0.3 wide plastic and her- metic dual-in-line package (DIP) and are also packaged in a 24- lead small outline (SOIC) package. DACPORT is a wademark of Analog Devices, Inc. REV.A information furnished by Analog Devices is believed to be accurate and reliable, However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other tights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. FUNCTIONAL BLOCK DIAGRAMS D Rossa Voura 2 i Wi CONTROL Loci LATSR AG ADT237 Al te DGAD AGNO Vu. Voe aR 2a Forsa SAC LATCH A Vouta DAC LATCH BR Po Rr AD7247 eA CONTROL cea LOGE GENO V5 PRODUCT HIGHLIGHTS 1. The AD7237/AD7247 is a dual 12-bit DACPORT on a single chip. This single chip design and smal! package size offer considerable space saving and increased reliability over multichip designs. 2. Between them, the AD7237 and AD7247 offer a versatile interface arrangement to either 8-bit or 16-bit data bus structures. One Technology Way, P.O. Box 9106, Norwood, MA 92062-9106, U.S.A. Fel: 617/329-4700 Fax: 617/326-8702 Twa: 710/394-6577 Telex: 924491 Cabie: ANALOG NORWOODMASSAD7237/AD7247 SPECIFICATIONS R, = 2 kQ2, , = 100 pF. All specifications T,,,, to T,,a, Unless otherwise noted.) > (Wop = +15 ' 5%, Veg = OV or 15 ' +5%, AGND = DGND = 0 V [AD7237], GND = 0 V(AD7247], REF IN = +5 V, Parameter j,A, 8 K, B, T Units Test Conditions/Commeants STATIC PERFORMANCE Resolution 12 12 Bits Relative Accuracy? =] 22 LSB max Differential Nonlinearity? +0.9 +09 LSB max Guaranteed Monotonic Unipolar Offset Error? 23 3 LSB max Ves = OV or ~15 V. DAC Latch Contents All Os Bipolar Zero Error? +4 a4 LSB max Veg * ~15 V. DAC Latch Contents 1600 0000 0060 Full-Scaie Errar + a5 25 LSB max Full-Scale Mismatch* a1 th LSB typ REFERENCE OUTPUT REF OUT J, K, A, B Versions 4.97/5.03 4.97/5,03 Vmin/Vmax $, T Versions 4.95/5.05 4.95/5.05 Vmin/Vmax Reference Temperature Coefficient 225 225 ppmC typ Reference Load Change (AREF OUT vs. AD ~1 ~] mV max Reference Load Current Change (0-100 pA} REFERENCE INPUT Reference Input Range 4.95/5.05 4,95/5.05 V min/V max $V 1% Inpur Current* 25 5 A max DIGITAL INPUTS Input High Voltage, Vinny 2.4 24 min Input Low Voltage, Vin. 0.8 0.8 V max input Current Tw (Data Inputs) x10 16 wA max Vin OV to Von Tov (Control Inputs}? +10 =16 pA max Vin * Vip Law (Contro! Inputs) ~ 150 150 pA max Vin = 0V Input Capacitance 16 16 pF max ANALOG OUTPUTS Output Range Resistors 15/30 15/30 kOt min/k() max Output Voltage Ranges +5, +10 +5, +10 v Vs, = OV. Pin Strappable Outpur Vohage Ranges +5, +10, +5, +106, 5 #5 v Veg = ~ 15 V. Pin Strappable DC Ourput Impedance 0.5 0.5 OQ tp AC CHARACTERISTICS* Voltage Output Settling Time Settling Time to Within = 1/2 LSB of Final Value Full-Scale Change Vop = TIS V, Veg = - 1S V J. K, A, B Versions 10 10 us max $, T Versions 12 12 uS max Digital-to-Analog Glitch Impulse? 36 30 nV secs typ Digital Feedthrough? 16 10 nV secs typ Digital Crosstalk? 30 30 nV secs wp POWER REQUIREMENTS Vop +45 435 V nom 5% for Specified Performance Uniess Otherwise Stated Vs ~ HS ~15 VY nom 5% fer Specified Performance Unless Otherwise Stated lop 15 15 mA max Output Unioaded. Typically 1i mA 1g. (Dual Supplies} $ 5 mA max Qutput Unloaded. Typically 3 mA NOTES Parts are functional at V\,,, = +12 V 210% and Vy, = OV or -12 V +10%, See typical performance graphs. *Temperature ranges are as follows: J, K Versions, ~ 40C to +85C; A, B Versions, -40C to +85C; $, T Versions, 55C to + 128C. *See Terminology. +Measured with respect to REF EN and includes unipolar/bipolar offset error. *Sample tested @ +25C to ensure compliance. _ __ *Controt inputs are AO, Al, CS, WR and CDA for the AD7237 and CSA, CSB and WR for the AD7247. Specifications subject to change withour notice. REV. AAD7237/AD7247 (Vop = +15 V 5%; Veg = OV or 15 V +5%, AGND = DGND = 0 V[AD7237], TIMING CHARACTERISTICS" 2 exo = ov tan7247) Limit at Tins Tmax Limit at This Tmax Parameter . K, A, B Versions) (8S, T Versions) Units Conditions/Comments ty 0 0 ns min CS to WR Setup Time ts 0 6 ns min CS to WR Hold Time ts 130 150 ns min WR Pulse Width ty 128 150 ns min Data Valid to WR Setup Time ts 10 15 ns min Data Valid to WR Hold Time te! 0 0 ns min Address to WR Setup Time t,* 0 0 ns min Address to WR Hold Time ty 100 100 ns min LDAC Pulse Width NOTES Sample tested at #25C to ensure compliance. All input signals are specified with ur = uf = 5 ns (10% to 90% of $ Vy and timed from a voltage level of 1.6 V. *See Figures 5 and 7. Hf @ ns<r,< 10 ns, add t, to ts. If 210 ns, add 10 ns to t,. 4AD7237 only. ABSOLUTE MAXIMUM RATINGS* ORDERING GUIDE (T, = +25C unless otherwise noted) Vop to GND (AD7247) 00. ele, -O0.3 Vt +17 V Relative Von to AGND, DGND (AD7237) ....... ~0.3 Vio +17 V Temperature Accuracy Package a a -0.3 Vio +34V Model! Range (LSB) Option AGND to DGND (AD7237) 2.0.2.0... ~0.3-V, Vip +0.3 V AD7237]N 40C to +85C +] max N24 Voura's Vours' to AGND (GND) AD7237KN | 40C to +85C +2 max | N-24 eee Ves 70.3 Vite Von +0.3V AD7237)R ~40C 10 + 85C 1 max R-24 REF OUT to AGND (GND) .......00.000, 8 V to Vop AD7237KR 40C to +85C + 1/2 max R24 REF IN tc AGND (GND) ........ ~O.3 V to Vop +0.3 V AD7237AQ ~40C to +85C +] max Q-24 Digital Inputs to DGND (GND) .... -0.3 V to Vyp +0.3V AD7237BO 40C to + 85C +1/2 max Q-24 Operating Temperature Range AD72378Q ~55C to +125C | +1 max Q-24 Commercial (], K Versions)... 2.0.0... re to +85C -aD7237TO ~8C to +125C +12 max Q-24 Industrial (A, B Versions}... 2.000002. ~40C te +85C Extended ST Versions)....-.------ ~55C to +125C AD 7247JN | 40C to + 85C #1 max N-24 Storage Temperature Range ........... 65C to + 150C AD?247KN 40C 10 +85C = 1/2 max N-24 Lead Temperature (Soldering, 10 secs}... 0... 0... + 30PC AD7247JR AOC to + 85C =1 max R24 Power Dissipation (Any Package) to +75C 2.0... 1000 mW AD7247KR 40C to + 85C + 1/2 max R-24 Derates above #75C by oo... cee ee romwece = AD?247AQ_ 40C to +85C +1 max Q24 . AD7247BQ ~40C to +85C +1/2 max Q-24 NOTE AD?2478Q ~5C to + 125C +1 max Q-24 Short-cireuit current is typically 80mA, The outputs may be shorted to AD7247TO ~S55C to +125" +? max Q-24 voltages in this range provided the power dissipation of the package is not exceeded. "To order MIL-STD-883, Class B processed parts, add /883B to part num- *Stresses above those listed under Absolute Maximum Ratings may cause ber. Contact local sales office for military data sheet and availability. permanent damage to the device, This is a stress rating only and functional *N = Plastic DIP; Q = Cerdip; R = Small Outline (SOIC). operation of the device at these or any other conditions above those listed in the operational sections of this specification _is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. CAUTION ESD (electrostatic discharge) sensitive device. The digital contro! inputs are diode protected; WARNING! however, permanent damage may occur on unconnected devices subject to high energy electro- static fields. Unused devices must be stored in conductive foam or shunts. The protective foam ill ao should be discharged to the destination socket before devices are inserted. erent a ari era felt REV. A _3-AD7237/AD7247 AD7237 PIN FUNCTION DESCRIPTION (DIP PIN NUMBERS) Pin Mnemonic Description 1 REF INA Voltage Reference Input for DAC A. The reference voltage for DAC A is applied to this pin. It is internally buffered before being applied to the DAC. The nominal reference voltage for correct operation of the AD7237 is $V. 2 REF OUT = Voltage Reference Output. The internal 5 V analog reference is provided at this pin. To operate the part with iternal reference, REF OUT should be connected to REF INA, REF INB. 3 REF INB Voltage Reference Input for DAC B. The reference voltage for DAC B is applied to this pin. It is internally buffered before being applied to the DAC. The nominal reference voltage for correct operation of the AD7237 SV. 4 Rogsg Output Offset Resistor for DAC B. This input configures the output ranges for DAC B. It is connected to Vourr for the +5 V range, to AGND for the +10 V range and to REF INB for the =5 V range. 5 Vourr Analog Output Voltage from DAC B. This is the buffer amplifier output voltage. Three different output voltage ranges can be chosen: 0 to +5 V, to +10 V and +5 V. The amplifier is capable of developing +10 V across a 2 kf) resistor to GND. 6 AGND Analog Ground. Ground reference for DACs, reference and output buffer amplifiers. 7 DB7 Data Bit 7. 8-10 DB6-DB4 Data Bit 6 to Data Bit 4. 1k DB3 Data Bit 3/Data Bit 1] (MSB). 12 DGND Digital Ground, Ground reference for digital circuitry. 13 DB2 Data Bit 2/Data Bu 10. 14 DBI Data Bit 1/Data Bit 9. 15 DBO Data Bit 0 (LSB)/Data Bit 8. 16 Ad Address Input. Least significant address input for input latches. AO and Al select which of the four input latches data is written to (see Table ID). 17 Al Address Inpur. Most significant address input for input latches. 18 cs Chip Select. Active low logic input. The device is selected when this input is active. 19 WR Write Input. WR is an active low logic input which is used in conjunction with CS, AO and Al to write data to the input latches. 20 LDAC Load DAC. Logic input. A new word is loaded into the DAC latches from the respective input latches on the falling edge of this signal. 21 Vop Positive Supply, +15 V. 22 Vouta Analog Output Voltage from DAC A. This is the buffer amplifier output voltage. Three different output voltage ranges can be chosen: 0 to +5 V, 0 te +10 V and <5 V. The amplifier is capable of developing +10 V across a 2 kf) resistor to GND. 23 Vss Negative Supply, 15 V. 24 Rogsa Output Offset Resistor for DAC A. This input configures the output ranges for DAC A. It is connected to Voura for the +5 V range, to AGND for the +10 V range and to REF INA for the 5 V range. 4- REV.AAD7237/AD7247 AD7247 PIN FUNCTION DESCRIPTION (DIP PIN NUMBERS) Pin Mnemonic Description 1 REF OUT Voltage Reference Output. The internal $ V analog reference is provided at this pin. To operate the part with internal reference, REF OUT should be connected to REF IN. 2 Rorss Output Offset Resistor for DAC B. This input configures the output ranges for DAC B. It is connected to Vourr fer the +5 V range, to GND for the +10 V range and to REF IN for the =5 V range. 3 Vouts Analog Output Voltage from DAC B. This is the buffer amplifier output voltage. Three different output voltage tanges can be chosen: 0 to +5 V,0to + 10 V and = V. The amplifier is capable of developing ~10 V across a 2 KO resistor to GND, 4 DBil Data Bit 11 (MSB). 5 DB1O Data Bit 10. 6 GND Ground. Ground reference for all on-chip circuitry. 7-13 DB9-DB1 = Data Bit 9 to Data Bir 1. 16 DBO Data Bit 0 (LSB). 17 CSB Chip Select Input for DAC B. Active Jow logic input. DAC B is selected when this input is active. 18 CSA Chip Select Input for DAC A. Active low logic input. DAC A is selected when this input is active. 19 WR Write Input. WR is an active low logic input which is used in conjunction with CSA and CSB to write data to the DAC latches. 26 pp Positive Supply, +15 V. 21 Vota Analog Output Voltage from DAC A. This is the buffer amplifier output voltage. Three different output voltage ranges can be chosen: 0 to ~3 V, 0 to ~10 V and +5 V. The amplifier is capable of developing +10 V across a 2 kf) resistor to GND. 22 Vox Negative Supply, 15 . 23 Rorsa Output Offset Resistor for DAC A. This input configures the output ranges for DAC A. It is connected to Vocra for the +5 V range, to GND for the +10 V range and to REF IN for the 5 V range. 24 REF IN Voltage Reference Input. The common reference voltage for both DACs is applied to this pin. It is internally buffered before being applied 10 both DACs. The nominal reference voltage for correct operation of the AD?7247 is 5 V. REV. A AD7237 PIN CONFIGURATIONS AD7247 PIN CONFIGURATIONS DIP and SOIC DIP and SOIC VA? NA REF INA [2 * 24] Rossa REF QUT i * 24| REF IN ner out [2 | 23] Ves Rorse [2 | 23] Rorsa rer me [3 | P22] Vous Youre [3 | 22] Ves Rosse [a] 211 Vou DAT fs 21) Vouta Vourr eo 20] LOAC DB10 [s! 291 Vow acnp[ | AD72a7_ [as] wR eno fe] Ad7247 [a] win TOR VIEW TOP VIEW DB? a (Not to Scale} i cs DBS [7 {Nat to Scale} El SA pes fe | 7} a osa [8 | a7} EBB DBS Ce is] AG Der [2 | rs] DBC DBal 10 is] DBO DB6 | 10 rs] DBI pea] 11 ee] DB1 DBS | 17 14) DBZ DGND | +2 3 | DBZ pea | 32 13} DBsAD7237/AD7247 TERMINOLOGY RELATIVE ACCURACY (LINEARITY) Relative Accuracy, or endpoint linearity, is a measure of the maximum deviation of the DAC transfer function from a straight line passing through the endpoints of the transfer func- tion. It is measured after allowing for zero and full-scale errors and is expressed in LSBs or as a percentage of full-scale reading. DIFFERENTIAL NONLINEARITY Differential Nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of +1 LSB or less over the operating temperature range ensures monotonicity. SINGLE SUPPLY LINEARITY AND GAIN ERROR The output amplifiers of the AD7237/AD7247 can have true negative offsets even when the part is operated from a single +15 V supply. However, because the negative supply rail (V5<} is 0 V, the output cannot actually go negative. Instead, when the output offset voltage is negative, the output voltage sits at 0 , resulting in the transfer function shown in Figure 1. This knee is an offset effect, not a linearity error, and the transfer function would have followed the detted line if the output volt- age could have gone negative. 4 OUTPUT VOLTAGE ov _ negative { |. DAC CODE OFFSET . Figure 1, Effect of Negative Offset (Single Supply} Normally, linearity is measured between zero (all 0s input code) and full scale (all ls input code) after offset and full scale have been adjusted out or allowed for, but this is not possible in sin- gle supply operation if the offset is negative, due to the knee in the transfer function. Instead, linearity of the AD7237/AD7247 in the unipolar mode is measured between full scale and the lowest code which is guaranteed to produce a positive output voltage. This code is calculated from the maximurn specification for negative offset, i.e., linearity is measured between Codes 3 and 4095. UNIPOLAR OFFSET ERROR Unipolar Offset Error is the measured output voltage from Voura OF Vour, With all zeros loaded into the DAC latches when the DACs are configured for unipolar output. It is a com- bination of the offset errors of the DAC and output amplifier. BIPOLAR ZERO ERROR Bipolar Zero Error is the voltage measured at Vouta Of Vourn when the DAC is connected in the bipolar mode and loaded with code 2048. It is due to a combination of offset errors in the DAC, amplifier offset and mismatch in the application resistors around the amplifier. FULL-SCALE ERROR Full-Scale Error is a measure of the output error when the am- plfier output is at full scale (fer the bipolar ourput range full scale is either positive or negative full scale). [tis measured with respect to the reference input voltage and includes the offset errors. DIGITAL FEEDTHROUGH Digital Feedthrough is the glitch impulse injected for the digital inputs to the analog output when the data inputs change state, but the data in the DAC latches is not changed. For the AD7237 it is measured with LDAC held high. For the AD7247 it is measured with CSA and CSB held high. DIGITAL CROSSTALK Digital crosstalk is the glitch impulse transferred to the output of one converter due to a change in digital code to the DAC latch of the other converter. It is specified in nV secs. DIGITAL-TO-ANALOG GLITCH IMPULSE This is the voltage spike that appears at the output of the DAC when the digital code changes before the output settles to its final value. The energy in the glitch ts specified in nV secs and is measured for a 1 LSB change around the major carry transi- tion (0111 P11] 1EL] to 1000 6000 0000). _6- REV. ATypical Performance Graphs AD7237/AD7247 13 4 +05 128 Voo = +15 78V 4 95 DAC & +02 tgg (Veg = -15.75} 6 2 L. ; 3 Pa Z Zp vewtnnnnenttee < selon (Vy = O.BV OR 2.4} < 4 E E 1 795 t 44s 54 x 3 | 3 +05 a DAC ft 2 40.2 ya foo [Vin = OV OF Van! 9 -0.2 bo Von = 14.25 J 10.5 1s Ven = OV es Ty = +266 0 2048 4095 19 4 $5 74g +25 +85 +125 CODE TEMPERATURE - C Power Supply Current vs. Temperature DAC-to-DAC Linearity Matching 500 300 Vop = + 15V Veg 7 OV 90 TPUT WITH ALL Ta = 428C Gs ON DAC DECOUPLING Bo 200 \ NO DECOUPLING REFERENCE 70 F OUTPUT WITH ALL {NO DECOUPLING} 18 ON BAC y 3 6a 100 t < . = ~ 2 REFERENCE (DECCUPLED*) = so ~ 56 40 NO DECOUPLING 30 OUTPUT WITH ALL 20 29 s ON DAC Yoo = +18 WITH 100mV p-p SIGNAL 0 a 50 100 200 4500 1k zk Sk 40k 620k 50k 100k 1 00 Tk 10h 4008 FREQUENCY ~ Hz FREQUENCY Hz *REFERENCE DECOUPLING COMPONENTS ARE *POWER SUPPLY DECOUPLING CAPACITORS 4 200.0 RESISTOR iN SERIES WITH A PARALLEL ARE 10,F AND 0 tpF COMBINATION OF 10uF AND 0.1nF TO GND. Noise Spectral Density vs. Frequency Power Supply Rejection Ratio vs. Frequency 5 0.50 4 a4 \ a 4 3 a 8.30 Ee I NN E = a 2 / 2 2.20 wt / Ty, = +25C 1 0.78 8 Qo o 2 a 6 8 Bis} 16.5 1 WZ 3 14 +s 6 OUTPUT VOLTAGE - Volts Von - Volts Single Supply Sink Current vs. Output Voltage Linearity vs, Power Supply Voltage REV. A -7-AD7237/AD7247 CIRCUIT INFORMATION D/A Section The AD7237/AD7247 contains two 12-bit voltage-mode D/A converters consisting of highly stable thin film resistors and high speed NMOS single-pole, double-throw switches. The output voltage from the converters has the same polarity as the refer- ence voltage, REF IN, allowing single supply operation. The simplified circuit diagram for one of the D/A converters is shown in Figure 2. The REF IN voltage is internaily buffered by a unity gain amplifier before being applied to the D/A converters. The D/A converters are configured and scaled for a5 V reference and the device is tested with 5 V applied to REF IN. aR aR Rors Vour 4 , 2A DBI REF IN _ SHOWN FOR ALL 1S ON BAC > AGND (GND. AD7247} BUFFERED REF IN VOLTAGE Figure 2. D/A Simplified Circuit Diagram internal Reference Fhe AD7237/AD7247 has an on-chip temperature compensated buried Zener reference (see Figure 3) which is factory trimmed to 5 V +30 mV (=50 mV for S, T Versions}. The reference voltage is provided at the REF OUT pin. This reference can be used to provide the reference voltage for the D/A converter (by connecting the REF OUT pin to the REF EN pin) and the off- set voltage for bipolar outputs (by connecting REF OUT to Rors): The reference voltage can also be used as a reference for other components and i capable of providing up to 500 pA to an external load. The maximum recommended capacitance on REF OUT for normal operation is 50 pF. If the reference is required for external use, it should be decoupled to AGND (GND) with a 200 (2 resistor in series with parallel! combination of a 10 4F tantalum capacitor and a 0.1 pF ceramic capacitor. Yoo AD7237 (AD7247) af hl Nol AGND (GND) REF OUT ig 1S TEMPERATURE COMPENSATION CURRENT Figure 3. Internal Reference External Reference In some applications, rhe user may require a systern reference or some other external reference to drive the AD7237/AD7247 reference input. References such as the AD586 5 V reference provide the ideal external reference source for the AD7237/ AD?7247 (see Figure 9). Op Amp Section The output of the voltage-mode D/A converter is buffered by a noninverting CMOS amplifier. The Rors input allows different output voltage ranges to be selected. The buffer amplifier is capable of developing +10 V across a 2 kM load to GND. The output amplifier can be operated from a single +15 V supply by tying Vg.=0 V. The amplifier can also be operated from dual supplies (+15 V)} to allow a bipolar output range of 5 V to +5 V. The advantages of having dual supplies for the unipolar output ranges are faster settling time to voltages near 0 V, full sink capability of 2.5 mA maintained over the entire output range and the elimination of the effects of negative offsets on the transfer characteristic (outlined previously). A plot of the single supply output sink capability of the amplifier is shown in the Typical Performance Graphs section. INTERFACE LOGIC INFORMATION ~ AD7247 Table I shows the truth table for AD7247 operation. The part contains a single, parallel 2-bit latch for each DAC. It can be treated as two independent DACs, each with its own CS input and a common WR input. CSA and WR control the loading of data to the DAC A latch while CSB and WR control the foading of the DAC B latch. If CSA and CSB are both low, with WR low, the same data will be written to both DAC latches. Al! con- trol signals are level triggered and therefore either or both latches can be made transparent. Input data is latched to the respective latch on the rising edge of WR. Figure 4 shows the input control logic for the AD7247, while the write cycle timing diagram for the part is shown im Figure 5. DAC A LATCH DAC B LATCH Figure 4. AD7247 Input Control Logic CSA/CSB h } t, | ty >} ta wa i [ a ty a x & em Figure 5. AD724? Write Cycle Timing Diagram DATA REV. AAD7237/AD7247 (BAC es We Ad at &SA | CSB} WR | Function xX xX 1 No Data Transfer } ] x No Data Transfer Q 1 0 DACA Latch Transparent l 9 0 DACE Latch Transparent 0 0 0 Both DAC Latches Transparent K~ Don't Care Table |. AD7247 Truth Table INTERFACE LOGIC INFORMATION AD7237 The input loading structure on the AD7237 is configured for interfacing to microprocessors with an 8-bit-wide data bus. The part contains two 12-bit latches per DAC an input latch and a DAC latch. Each input latch is further subdivided into a least significant 8-bit latch and a most significant 4-bit latch, Only the data held in the DAC latches determines the outputs from the part. The input control Jogic for the AD7237 is shown in Figure 6, while the write cycle timing diagram is shown in Figure 7. CS, WR, AO and Al control the loading of data to the input latches, The eight data inputs accept right-justified data. Data can be loaded to the input latches in any sequence. Provided thar LDAC is held high, there is no analog output change as a result of loading data to the input latches. Address lines AQ and Al determine which latch data is loaded to when CS and WE are low. The selection of the input latches is shown im the truth table for AD7237 operation in Table IL. The CDAC input controls the transfer of 12-bit data from the input latches to the DAC latches. Both DAC latches, and hence both analog outputs, are updated at the same time. The LDAC signal is level triggered and data is latched into the DAC latch on the rising edge of LDAC. The [DAC input is asynchronous and independent of WR. This is useful in many applications especially in the simultaneous updating of multiple AD7237s. REV. A Dac INPUT LATCH DAC A LATCH DAC B LATCH or 12 4 AMS DAC ALS INPUT LATCH 4 DAC B MS DAC 315 INPUT LATCH & BR? DBD Figure 6. AD7237 input Controf Logic AOIL wd Al Function No Data Transfer No Dara Transfer DAC A LS Input Latch Transparent DAC A MS Input Latch Transparent DAC BLS Input Latch Transparent DAC B M Input Latch Transparent DACA and DACB DAC Latches Updated Simultaneously from the Respective Input Latches OO OO ym Mm mH OD i bdo Dm Dd X = Don't Care. Table il, AD7237 Truth Table However, care must be taken while exercising LDAC during a write cycle. If an LISAC operation overlaps a CS and WR oper- ation, there is a possibility of invalid data being latched to the _ output. Te avoid this, LDAC must remain low after CS or WR return high for a period equal to or greater than t,, the mini- mum LDAC pulse width. Y ANDRESS VALID k DATA iDAC Figure 7. AD7237 Write Cycle Timing DiagramAD7237/A07247 APPLYING THE AD7237/AD7247 The internal scaling resistors provided on the AD7237/AD7247 allow several output voltage ranges. The part can produce uni- polar output ranges of 0 V to +3 V or 0 V to +10 V and a bipolar output range of +5 . Connections for the various ranges are outlined below. Since each DAC has its own Ropes input the two DACs on each part can be set up for different output ranges. Unipolar (0 V to +10 V) Configuration The first of the configurations provides an output voltage range of 0 V to +10 V. This is achieved by connecting the output off- set resistor, Rorsa;s Of Rops_, to AGND (GND for AD7247). In this configuration, the AD7237/AD7247 can be operated from single or dual supplies. Figure 8 shows the connection dia- gram for unipolar operation for DAC A of the AD7237, while the table for output voltage versus digital code in the DAC latch is shown in Table III. Similar connections apply to the AD7247. +15 V | Voo ra AD?237 REF OUT 2k q + AEF INA em DACA OVTO +16V BGND OV OR -i5V Figure 8 Unipolar (0 to +70 V) Configuration DAC Latch Contents Unipolar (0 V to +5 V) Configuration The 0 V to +5 V ourput voltage range is achieved by tying Rorsa OF Rogsp t0 Voura OF Voura- Once again, the AD7237/AD7247 can be operated single supply or from dual supplies. The table for output voltage versus digital code is as in Table Ill, with 2. REF IN replaced by REF IN. Note, for this range, 1 LSB = REF IN - (27') = (REF IN/4096). Bipolar Configuration The bipolar configuration for the AD7237/AD7247, which gives an output range of -5 V to +5 V, is achieved by connecting Rogsa; OF Rogsp, to REF IN. The AD7237/AD7247 must be operated from dual supplies to achieve this output voltage range. Figure 9 shows the connection diagram for bipolar operation for DAC A of the AD7247. An AD586 provides the reference volt- age for the DAC but this could be provided by the on-chip ref- erence by connecting REF OUT to REF IN. The code table for bipolar operation is shown in Table IV. Similar connections apply for the AD7237, mL +H 7 Br Vop ADT247 + in AD |Vour 586 > mM REF ine ~ ~8V TO +5V : Figure 9. Bipolar Configuration TS DAC Latch Contents MSB LSB Analog Output, Vour MSB LSB Analog Output, Vour MPP IIEVIE +2 - REF IN - (4095/4096) WALL I +REF IN - (2047/2048) 1000 0000 0001 +2- REF IN - (2049/4096) 1006 6000 6001 +REF IN - (1/2048) 1000 8000 0000 +2. REF IN - (2048/4096) - +REF IN 1006 6000 6000 OV OLUL LUAE ELL +2. REF IN - (2047/4096) OLD LTTE LILLE -REF IN - (1/2048) 0000 3000 0001 +2- REF IN - (1/4096) 6000 9600 0001 ~REF IN - (2047/2048) 0500 0000 0000 OV 0000 0000 0000 REF IN - (2048/2048) = -REF IN Note: ] LSB = REF IN/2048. Table il. Unipolar Cade Table (6 to +10 V Range; Nore: | LSB = REF IN/2048. Table lV. Bipolar Code Tabie ~10- REV. AAD7237/AD7247 MICROPROCESSOR INTERFACING - AD7247 Figures 10 to 12 show interfaces between the AD7247 and the ADSP-2101 DSP processor and the 8086 and 68000 16-bit microprocessors. In all three interfaces, the AD7247 is memory- mapped with a separate memory address for each DAC. ADB7247 ADSP-2101 Interface Figure 10 shows an interface between the AD7247 and the ADSP-2101, The 12-bit word is written to the selected DAC latch of the AD7247 in a single instruction, and the analog out- put responds immediately. Depending on the clock frequency of the ADSP-2101, either one or two wait states will have to be programmed into the data memory wait state contro! register of the ADSP-2103. OMAIS ADDRESS BUS Q pDMAG J ADDR = nj ESA SECODE om OMS eh te] CSE ADSP-2101 ADT247* oMWA Wn pptt Dee DMD18 DATA BUS. { pepo ADDITIONAL PINS OMITTED FOR CLARITY Figure 10. AD7247 to ADSP-2101 interface AD7247 - 8086 Interface Figure 1] shows an interface between the AD7247 and the 8086 microprocessor, The 12-bit word is written to the selected DAC latch of the AD7247 in a single MOV instruction, and the ana- log output responds immediately, ADDRESS BUS q AD7247 - MC68000 Interface interfacing between the AD7247 and the MC68000 microproces- sor is achieved using the circuit of Figure 12. Once again, the 12-bit word is written to the selected DAC latch of the AD7247 in a single MOVE instruction. CSA and CSB have to be AND- gated to provide a DTACK signal for the MC68000 when cither DAC latch is selected. Az3 ADDRESS BUS Al Cd ADDR _ _ vecooe [ ESA KE EN Fee Miceacos ADT247* ora fe to > RAY DB oBo O15 DATA 8US oO *ADDITIONAL PINS OMITTED FOR CLARITY Figure 12. AD7247 to MC68000 Interface MICROPROCESSOR INTERFACING AD7237 Figures 13 to 15 show the AD7237 configured for interfacing to microprocessors with 8-bit databus systems. In all cases, data is right-justified, and the AD7237 is memory-mapped with the two lowest address lines of the microprocessor address bus driving the AO and Al inputs of the converter. AD7237 - 8085A/8088 Interface Figure 13 shows the connection diagram for interfacing the AD7237 to both the 8085A and the 8088. This scheme is also suited to the Z80 microprocessor, but the 780 address/databus does not have to be demultiplexed. The AD7237 requires five separate memory addresses, one for the each MS latch and one for each LS latch and one for the common LDAC input. Data is written to the respective input latch in two write operations. 8086 DECODE 5 >_<_w] ADDR $a ESR CSB ADT247* WR Dat DBo ADS ADO REV. A ADDRESS DATA BUS 4 * ADDITIONAL PINS OMITTED FOR CLARITY Figure 11. AD7247 to 8086 Interface AIS ADDRESS BUS 5 Ag a C T | ADDR fp__set gq ADA __ DECODE cs EN pet En Exerc (BAE OCTAL ALE LATCH AD7237" g0Bba/s088 WR Wa pa? pBe AD? ADDRESS/DATA BUS ADO ADOITIONAL PINS OMITTED FOR CLARITY Figure 13. AD7237 to 8085A/8088 InterfaceAD7237/AD7247 Either high byte or low byte data can be written first to the input latch. A write to the AD7237 DAC Latch address trans- fers the data from the input latches to the respective DAC latches and updates both analog outputs. Alternatively, the LDAC input can be asynchronous or can be common to a num- ber of AD7237s for simultaneous updating of a number of volt- age channels. AD7237 - 68008 Interface An interface between the AD7237 and the 68008 is shown in Figure 14. In the diagram shown, the LDAC is derived from an asynchronous LDAC signal, but this can be derived from the address decoder as in the previous interface diagram. OUTLINE DIMENSIONS Dimensions shown in inches and (mm). Plastic DIP (N-24) AAAAAAAAAAAA YVVVVVVVY VV VY i pmeia SEATING ce ode MW ii 9.02 10.53 FEED 7S) 2.07(1.78) Vazeiai 4) cn | SORA THO FH Tea LL | 0.280 coogy R612 0.03) Q FARIS. 304 O 12813 25h 9 92ig 3283 sare 003140 81 bose z3: NOTES 1. LEAD NO. + IDENTIFIED BY GOT OR NOTCH PLANE TIMER ae ADDRESS BUS ~~ { TI CT] micaacos ADDR _ Ad AT DEcODE 7 co AS EN met [DAG DTACK BTA AD?7237* bs = wet) a De? pao oF ATA BUS. oo|____Parasus "ADDITIONAL PINS CIMITTED FOR CLARITY Figure 14. AD7237 to 68008 Interface 2 PLASTIC LEADS WILL BE EITHER SOLDER DIPPED OF TIN LEAD PLATED IN ACCORDANCE WITH MIL Af. 38570 REQUIREMENTS. Cerdip (Q-24) r~{ 2.16 MAK a BLAME ~o'a26 FF B12 1G. 305) E751 OO 7785 Pa desi 3.62018. y VP lad le 02440553) 0.190 (2,754) 8.985 11.581 w coe o TYP 86} 8 O66 (7 3971 a AD7237 - 6502/6809 Interface Figure 15 shows an interface between the AD7237 and the 6502 or 6809 microprocessor. The procedure for writing data to the AD7237 is as outlined for the 8085/8088 interface. For the 6502 microprocessor, the $2 cleck is used to generate the WR, while for the 6809 the E signal is used. 1. LEAD NO. 1 DENTIFIEG BY DOT OF NOTCH, 2 CERP LEADS WILL BE ESTHER THY PLATED OR SOLDER EXPPED GN ACCORDANCE WATH fi, -M-38540 REQUIREMENTS. SOIC (R-24) ADDITIONAL FINS OMITTED FOR CLARITY Figure 15. AD7237 ta 6502/6809 Interface ~12- AS ADDRESS BUS ~~ s It TI ae AQ OAT ~ sam, b_-[S AR AA BARBARO ar in =p BAC | \ 0299281 | oe a | 6502/6808 ADI237" Sian oe I >e 7 HHHEEERR HUEY Hi $2 ORE wR eae Rie | ane pe 2.938 10.32) oR? Aer Be | ~e a& de OR Aan eae ees ree 905.1122) b 0.648 (0.40) fF aracus DO REV. A Ci324da~10-8/97 PRINTED IN U.S.A.