ONV* seein ANALOG DEVICES Single Supply, Rail-to-Rail Low Power, FET-Input Op Amp AD824 FEATURES Single-Supply Operation: 3 to 30 Volts Very Low Input Bias Current: 2 pA Wide Input Voltage Range Rail-to-Rail Output Swing Low Supply Current: 500 ,.A/Amp Wide Bandwidth: 2 MHz Slew Rate: 2 V/ys No Phase Reversal APPLICATIONS Photo Diode Preamplifier Battery Powered Instrumentation Power Supply Control and Protection Medical Instrumentation Remote Sensors Low Voltage Strain Gage Amplifiers DAC Output Amplifier GENERAL DESCRIPTION The AD824 is a quad, FET input single-supply amplifier featur- ing rail-to-rail outputs. The combination of FET inputs and rail-to-rail outputs makes the AD824 useful in a wide variety of low voltage applications where low input current is a primary consideration. The AD824 is guaranteed to operate from a 3 V single supply up to +15 volt dual supplies. Fabricated on ADI's complementary bipolar process, the AD824 has a unique input stage that allows the input voltage to safely extend beyond the negative supply and to the positive supply without any phase inversion or latchup. The output volt- age swings to within 15 millivolts of the supplies. Capacitive loads to 350 pF can be handled without oscillation. The FET input combined with laser trimming provides an input that has extremely low bias currents with guaranteed offsets be- low 300 pV. This enables high accuracy designs even with high REV.A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. PIN CONFIGURATIONS 14-Lead Epoxy DIP 14-Lead Epoxy SO (N Suffix) (R Suffix) 7 outa [1] [14] ouTo outa [i] {14} our ANA ahd Aga AND dna [2 | 13] ANDO +N A [3] 12] +1ND 4HNA [3] ppngoq [12] #NO v+ [4] ape24 [11] v- ve Top wew [tt] - an [5 | 10] +iNc +NB [5 | (Not to Scale) [10] unc ANB HR APU ANc ne [6 ro} NC ours [7 | [a] ourc ours [7] [8] ourc TOP VIEW source impedances. Precision is combined with low noise mak- ing the AD824 ideal for use in battery powered medical equip- ment. Applications for the AD824 include portable medical equip- ment, photo diode preamplifiers, and high impedance trans- ducer amplifiers. The ability of the output to swing rail-to-rail enables designers to build multistage filters in single supply systems and maintain high signal-to-noise ratios. The AD824 is specified over the extended industrial (-40C to +85C) temperature range and is available in 14-pin DIPs and narrow 14-pin SO packages. Analog Devices, Inc., 1994 One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703- AD824-SPECIFICATIONS ELECTRICAL SPECIFICATIONS (ev, = +5.0V, Vay = 0 V, Var = 0.2 V, Ty = +25C unless otherwise noted) Parameter Symbol Conditions Min Typ Max Units INPUT CHARACTERISTICS Offset Voltage AD824A Vos 0.1 1.0 mV Tain to Taax 1.5 mV Offset Voltage AD824B Vos 300 uv Tan to Tuax 900 pV Input Bias Current Ip 2 12 pA Tein to Taax 300 4000 pA Input Offset Current los 2 10 pA Tum to Tax 300 pA Input Voltage Range -0.2 3.0 Vv Common-Mode Rejection Ratio CMRR Vom = OV to2V 66 80 dB Vem=0V to3V 60 74 dB Tmin to Tmax 60 dB Input Impedance 10'3//3.3 Q\ipF Large Signal Voltage Gain Avo Vo = 0.2 V to 4.0 V Ry = 2 kQ 20 40 VimV R, = 10 kQ 50 100 VimV R, = 100 kQ 250 1000 VimV Tein to Tmax, Ry = 100 kQ 180 400 VimV Offset Voltage Drift AVos/AT 2 wviec OUTPUT CHARACTERISTICS Output Voltage High Vou source = 20 pA 4.975 4,988 V Tan to Tax 4.97 4.985 Vv Isource =2.5mA 4.80 4.85 Vv Tuan to Tax 4.75 4.82 Vv Output Voltage Low VoL Isinx = 20 pA 15 25 mV Tan to Tuax 20 30 mV Isnnx = 2.5 mA 120 150 mV Tain to Tax 140 200 mV Short Circuit Limit Isc Sink/Source +12 mA Twain to Tax +10 mA Open-Loop Impedance Zout f = 1 MHz, Ay=1 100 Q POWER SUPPLY Power Supply Rejection Ratio PSRR Vs = 2.7 Vto12V 70 80 dB Twin to Taax 66 dB Supply Current/Amplifier Isy Twa to Tax 500 600 pA DYNAMIC PERFORMANCE Slew Rate SR R, = 10 kQ, Ay = 1 2 Vips Full-Power Bandwidth BWp 1% Distortion, Vo = 4 V p-p 150 kHz Settling Time ts Vour = 0.2 V to 4.5 V, to 0.01% 2.5 Ls Gain Bandwidth Product GBP 2 MHz Phase Margin oo No Load 50 Degrees Channel Separation CS f =1kHz, Rp =2kQ -123 dB NOISE PERFORMANCE Voltage Noise , p-p 0.1 Hz to 10 Hz 2 LV p-p Voltage Noise Density en f = 1 kHz 16 nV/VHz Current Noise Density in f = 1 kHz 0.8 fANHz Total Harmonic Distortion THD f = 10 kHz, R; =0, Ay=+1 0.005 % -2- REV.AELECTRICAL SP ECIFICATIONS (@ Vs = 15.0 V, Voyr = 0 V, Ty = +25C unless otherwise noted) AD824 Parameter Symbol Conditions Min Typ Max Units INPUT CHARACTERISTICS Offset Voltage AD824A Vos 0.5 2.5 mV Tin to Taax 0.6 4.0 mV Offset Voltage AD824B Vos 0.5 1.5 mV Tin to Trax 0.6 2.5 mV Input Bias Current Ip Vom =O0V 4 35 pA Tmin to Trax 500 4000 pA Input Bias Current Ip Vom =-10V 25 pA Input Offset Current los 3 20 pA Tmin to Tyrax 500 pA Input Voltage Range -15 13 V Common-Mode Rejection Ratio CMRR Vom=-15V to1l3V 70 80 dB Tin to Trax 66 dB Input Impedance 1033.3 Q\|pF Large Signal Voltage Gain Ayo Vo =-10V to +10 V; Ri = 2kQ 12 50 V/mV Ri = 10 kQ 50 200 V/mV R, = 100 kQ 300 2000 VimV Twin to Tmax, R, = 100 kQ 200 1000 VimV Offset Voltage Drift AVos/AT 2 pviPC OUTPUT CHARACTERISTICS Output Voltage High Vou Isource = 20 pA 14.975 14.988 V Tmin to Tax 14.970 14.985 Vv Isource = 2.9 MA 14.80 14.85 Vv Tain to Taax 14.75 14.82 V Output Voltage Low VoL Isink = 20 pA -14.985 -14.975 V Tain to Taax -14.98 -14.97 Vv Isink = 2.5 mA -14.88 -14.85 V Tuan to Tmax -14.86 -14.8 V Short Circuit Limit Isc Sink/Source, Tyn to Tax +8 +20 mA Open-Loop Impedance ZOUT f = 1 MHz, Ay = 1 100 Q POWER SUPPLY Power Supply Rejection Ratio PSRR Vs=2.7Vto 15V 70 80 dB Turin to Tyax 68 dB Supply Current/Amplifier Isy Vo =0V 560 625 pA Tmin to Tyax 675 pA DYNAMIC PERFORMANCE Slew Rate SR R,; = 10 kQ, Ay = 1 2 Vips Full-Power Bandwidth BWp 1% Distortion, Vo = 20 V p-p 33 kHz Settling Time ts Vout =9 V to 10 V, to 0.01% 6 Ls Gain Bandwidth Product GBP 2 MHz Phase Margin ho 50 Degrees Channel Separation CS f= 1 kHz, Rp =2 kQ -123 dB NOISE PERFORMANCE Voltage Noise , P-P 0.1 Hz to 10 Hz 2 UV p- Voltage Noise Density Cn f= 1 kHz 16 nVNHz Current Noise Density in f= 1kHz 1. fAHz Total Harmonic Distortion THD f =10 kHz, Vo = 3 Vrms, Ry = 10 kQ 0.005 % REV. AAD824-SPECIFICATIONS ELECTRICAL SPECI FICATIONS (@ Vy = +3.0 V, Voy = OV, Vouy = 0.2 V, T, = +25C unless otherwise noted) Parameter Symbol Conditions Min Typ Max Units INPUT CHARACTERISTICS Offset Voltage AD824A -3 V Vos 0.2 1.0 mV Tin to Tyax 1.5 mV Input Bias Current Ip 2 12 pA Twain to Tax 250 4000 pA Input Offset Current Ios 2 10 pA Twin to Taax 250 pA Input Voltage Range 0 1 Vv Common-Moade Rejection Ratio CMRR Vom=0V tol V 58 74 dB Tein to Tax 56 dB Input Impedance 103|/3.3 Q\pF Large Signal Voltage Gain Avo Vo = 0.2 V to 2.0 V Ry = 2kQ 10 20 VimV R, = 10 kQ 30 65 VimV R, = 100 kQ 180 500 V/mV Tin to Tax, R, = 100 kQ 90 250 VimV Offset Voltage Drift AVos/AT 2 pvieC OUTPUT CHARACTERISTICS Output Voltage High Vou Isource = 20 pA 2.975 2.988 V Tain to Tyax 2.97 2.985 Vv Isgurce =2.5mA 2.8 2.85 V Tein to Tax 2.75 2.82 V Output Voltage Low VoL Isinx = 20 pA 15 25 mV Twin to Tyax 20 30 mV Ignx = 2.5 mA 120 150 mV Tin to Tax 140 200 mV Short Circuit Limit Isc Sink/Source +8 mA Short Circuit Limit Isc Sink/Source, Tyin to Tax +6 mA Open-Loop Impedance Zout f = 1 MHz, Ay=1 100 Q POWER SUPPLY Power Supply Rejection Ratio PSRR Vs = 2.7 Vto 12 V, 70 dB Tin to Tyax 66 dB Supply Current/Amplifier Isy Vo = 0.2 V, Tuan to Toax 500 600 pA DYNAMIC PERFORMANCE Slew Rate SR R, =10 kQ, Ay = 1 2 Vius Full-Power Bandwidth BWp 1% Distortion, Vo = 2 V p-p 300 kHz Settling Time ts Vout = 0.2 V to 2.5 V, to 0.01% 2 pis Gain Bandwidth Product GBP 2 MHz Phase Margin go 50 degrees Channel Separation CS f=1kHz, RL = 2k -123 dB NOISE PERFORMANCE Voltage Noise ,P-P 0.1 Hz to 10 Hz 2 HV p- Voltage Noise Density en f= 1 kHz 16 nV/VHz Current Noise Density in 0.8 fANHz Total Harmonic Distortion THD f = 10 kHz, Ry =0, Ay = +1 0.01 % -4- REV.AAD824 WAFER TEST LIMITS (@ Vs = +5.0 V, Voy = 0 V, T, = +25C unless otherwise noted) Parameter Symbol Conditions Limit Units Offset Voltage Vos 1.0 mV max Input Bias Current Ip 12 pA max Input Offset Current Ios 20 pA Input Voltage Range Vim -0.2 to 3.0 V min Common-Mode Rejection Ratio CMRR Vom =OVto2V 66 dB min Power Supply Rejection Ratio PSRR V=+2.7Vto+l2V 70 pviv Large Signal Voltage Gain Avo Ry = 2 kQ 15 VimV min Output Voltage High Vou Isource = 20 pA 4.975 V min Output Voltage Low VoL Isinx = 20 pA 25 mV max Supply Current/Amplifier Isy Vo =0V,RL= 600 yA max NOTE Electrical tests and wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice DICE CHARACTERISTICS lot qualifications through sample lot assembly and testing. ABSOLUTE MAXIMUM RATINGS! Supply Voltage 0.6... eee eee eee +18V Input Voltage 0.22... eee eee -Vs - 0.2 V to +Vs Differential Input Voltage ......... 0.0.00 e eee eens +30 V Output Short Circuit Duration toGND ......... Indefinite Storage Temperature Range N, R Package... 2.0.0 ceccceeeeeeues -65C to +150C i ries Operating Temperature Range ie lek am AD824A,B ..... 0. cece cece eee e eens -40C to +85C fey Lj Junction Temperature Range N,R Package ... 0... cee eee e eee -65C to +150C Lead Temperature Range (Soldering, 60 Sec) ....... +300C AD824 Die Size 0.70 X 0.130 inch, 9,100 sq. mils. Substrate (Die Backside) Is Connected to V+. Transistor Package Type Oya jc Units Count, 143. 14-Pin Plastic DIP (N) 76 33 C/IW Voc 14-Pin SOIC (R) 120 36 C/W <I NOTES << . D D 29 Absolute maximum ratings apply to both DICE and packaged parts, unless Mis ofa RO otherwise noted. 29,, is specified for the worst case conditions, {.e., @, is specified for device in socket plex ant for P-DIP packages; 6), is specified for device soldered in circuit board for SOIC 06 package. jes , ORDERING GUIDE Te 2 * 1e a? ee Temperature Wr Po Model Range Package Option skca 22 023 Now 4 AD824AN -40C to +85C 14-Pin Plastic DIP ans asl} AD824BN -40C to +85C 14-Pin Plastic DIP i AD824AR-14 ~40C to +85C 14-Pin SOIC a + AD824AR-14-REEL -40C to +85C 14-Pin SOIC AD824AR-14-3V -40C to +85C 14-Pin SOIC ast AD824AR-14-3V-REEL| -40C to +85C 14-Pin SOIC a28}0] 026 AD824AR-16 -40C to +85C 16-Pin SOIC Ds Ou a AD824AR-16-REEL ~40C to +85C 16-Pin SOIC <<} +> AD824ACHIPS +26C DICE Vee Figure 1. Simplified Schematic of 1/4 AD824 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD824 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! aa ESD SENSITIVE DEVICE REV. A -5-AD824-Typical Characteristics 100 1k 10k 100k 1M 10M Figure 4. Open-Loop Gain/Phase and Small Signal Figure 2. Open-Loop Gain/Phase and Small Signal Response, Vs= +5 V, No Load Response, V;=+15 V, No Load een Figure 3. Open-Loop Gain/Phase and Small Signal Figure 5. Open-Loop Gain/Phase and Small Signal Response, Vs; = +15 V, C, = 100 pF Response, Vs= +5 V, C, = 220 pF _6- REV. AAD824 Figure 6. Open-Loop Gain/Phase and Small Signal Response, Vs = +3 V, No Load 1k 10k 100k iM 10M r a Vv aon Min A ary Figure 7. Open-Loop Gain/Phase and Small Signal Response, Vs = +3 V, C, = 220 pF REV.A ett Figure 9. Phase Reversal with Inputs Exceeding Supply by 7 Volt OUTPUT To RAIL Volts o So 8 & 2 & & & & o = 0 yp OS {op = SOp 100 500HS im) Sms 10m LOAD CURRENT - A Figure 10. Output Voltage to Supply Rail vs. Sink and Source Load CurrentsAD824-Typical Characteristics 14 l COUNT = 60 12 & eo 10 : F ' 5 8 5 40 $ : g 7 Oa Z Rt NM a A AT A yy aN 2 5 10 15 20 FREQUENCY ~ ktz 0 | 25 -20 15 410 -05 0 05 10 15 20 25 OFFSET VOLTAGE DRIFT Figure 11. Voltage Noise Density Figure 14. TC Vos Distribution, -55C to +125C, Vs = 5, 0 150 01 125 S100 0.010 * 7 5 z 3 & 5 0.001 E Oo 25 5 a =o 0.0001 20 100 1k 10k 20k FREQUENCY - Hz 40 40 -20 0 20 40 80 80 100 120 140 TEMPERATURE C Figure 12. Total Harmonic Distortion Figure 15. Input Offset Current vs. Temperature 280 100% COUNT = 860 240 10k 200 4 E t 1k 5 160 fi 5 100 ui 120 2 2 10 = 80 2 ~ 4 45 OA 03 02 01 0 of 02 03 04 05 20 0 60 80 400 129 140 OFFSET VOLTAGE - mV TEMPERATURE C Figure 13. Input Offset Distribution, Vs = 5, 0 Figure 16. Input Bias Current vs. Temperature -R- REV AAD824 120 tk 100 3 E ao IN et 5 N 100 Fs w ' NJ Pr NN a NI u N\ g N g Ww 8 eee NX 5 10 PT N g 8 2 2 0 10 100 1k 10k 100k 1M 10M 1 FREQUENCY Hz 1 10 100 tk 10k 100k FREQUENCY - Hz Figure 17. Common-Mode Rejection vs. Frequency Figure 20. Input Voltage Noise Spectral Density vs. Frequency ~40 120 / 2 100 -60 z / N ~ _ / : IN : y g N N | aw NN ~ -100 A 4 3 aw | NN x ~120 | 0 N 100 1k 10k 100k 10 100 tk 10k 100k 1M 10M FREQUENCY - Hz FREQUENCY - Hz Figure 18. THD vs. Frequency, 3 Vrms Figure 21. Power Supply Rejection vs. Frequency 100 100 30 eo N 80 25 8 \ i 3 1 6 60 > 20 g w +15V \ ' g \ & 40 t wo 2 5 15 8 +3, OV ; 9 & 20 20 w 5 10 N : o N 0 5 NX N NN Oo 100 1k 10k 100k 1m om tk 3k 10k 30k = 100k 300k 1m FREQUENCY - Hz INPUT FREQUENCY Hz Figure 19. Open-Loop Gain and Phase vs. Frequency Figure 22. Large Signal Frequency Response REV.A -g-60 00 /; 100 : Ly. -110 /A id lL Nh 1To 3) 1TO3 -130 -140 XZ 10 100 1k 10k 100k FREQUENCY - Hz Figure 23. Crosstalk vs. Frequency Figure 26. Large Signal Response 10k 2780 1k 2500 a S$ 2250 4 100 : z 2000 a 10 g z /) 2 1780 5 a E ' 1 r 3 1800 o A wt 1250 1 1000 10 100 1k 10k 100k 1M 10M 60 -40 -20 0 20 40 8 Ds100- 120 s:*1140 FREQUENCY - Hz TEMPERATURE - C Figure 24. Output impedance vs. Frequency, Gain = +1 Figure 27. Supply Current vs. Temperature > ' 3 E : a i 0.01 0.10 1.0 10.0 LOAD CURRENT - mA Figure 25. Smali Signal Response, Unity Gain Follower, Figure 28. Output Saturation Voltage 10K| 100 pF Load -10- REV. AAD824 APPLICATION NOTES INPUT CHARACTERISTICS In the AD824, n-channel JFETs are used to provide a low offset, low noise, high impedance input stage. Minimum input common-mode voltage extends from 0.2 V below -Vs to 1 V less than +Vs. Driving the input voltage closer to the positive rail will cause a loss of amplifier bandwidth. The AD824 does not exhibit phase reversal for input voltages up to and including +Vs. Figure 29a shows the response of an AD824 voltage follower to a 0 V to +5 V (+Vs) square wave in- put. The input and output are superimposed. The output tracks the input up to +Vs without phase reversal. The reduced band- width above a 4 V input causes the rounding of the output wave form. For input voltages greater than +Vs, a resistor in series with the AD824s noninverting input will prevent phase reversal, at the expense of greater input voltage noise. This is illustrated in Figure 29b. GND +Vg oN, Vint Figure 29. (a) Response with Rp = 0; Vin from 0 to +Vs5 (b) Vin = Oto + Vs + 200 mV Vour = Oto + Vs Rp = 49.9 kQ Since the input stage uses n-channel JFETs, input current dur- ing normal operation is positive; the current flows out from the input terminals. If the input voltage is driven more positive than +Vsz - 0.4 V, the input current will reverse direction as internal device junctions become forward biased. This is illustrated in Figure 9. REV.A A current limiting resistor should be used in series with the in- put of the AD824 if there is a possibility of the input voltage ex- ceeding the positive supply by more than 300 mV, or if an input voltage will be applied to the AD824 when +Vs = 0. The ampli- fier will be damaged if left in that condition for more than 10 seconds. A | kQ resistor allows the amplifier to withstand up to 10 volts of continuous overvoltage, and increases the input volt- age noise by a negligible amount. Input voltages less than -Vs are a completely different story. The amplifier can safely withstand input voltages 20 volts below the minus supply voltage as long as the total voltage from the positive supply to the input terminal is less than 36 volts. In ad- dition, the input stage typically maintains picoamp level input currents across that input voltage range. OUTPUT CHARACTERISTICS The AD824's unique bipolar rail-to-rail output stage swings within 15 mV of the positive and negative supply voltages. The AD824's approximate output saturation resistance is 100 Q for both sourcing and sinking. This can be used to estimate output saturation voltage when driving heavier current loads. For instance, the saturation voltage will be 0.5 volts from either supply with a 5 mA current load. For load resistances over 20 kQ, the AD824's input error voltage is virtually unchanged until the output voltage is driven to 180 mV of either supply. If the AD824s output is overdriven so as to saturate either of the output devices, the amplifier will recover within 2 ps of its input returning to the amplifiers linear operating region. Direct capacitive loads will interact with the amplifiers effective output impedance to form an additional pole in the amplifier's feedback loop, which can cause excessive peaking on the pulse response or loss of stability. Worst case is when the amplifier is used as a unity gain follower. Figures 5 and 7 show the AD824's pulse response as a unity gain follower driving 220 pF. Configu- rations with less loop gain, and as a result less loop bandwidth, will be much less sensitive to capacitance load effects. Noise gain is the inverse of the feedback attenuation factor provided by the feedback network in use. Figure 30 shows a method for extending capacitance load drive capability for a unity gain follower. With these component val- ues, the circuit will drive 5,000 pF with a 10% overshoot. Figure 30. Extending Unity Gain Follower Capacitive Load Capability Beyond 350 pF -11-AD824 APPLICATIONS Single Supply Voltage-to-Frequency Converter The circuit shown in Figure 31 uses the AD824 to drive a low power timer, which produces a stable pulse of width t,. The positive going output pulse is integrated by R1-C1 and used as one input to the AD824, which is connected as a differential integrator. The other input (nonloading) is the unknown volt- age, Vin. The AD824 output drives the timer trigger input, clos- ing the overall feedback loop. +10V > U4 s F REF02 Te 6 Ver =5V 3 5S Ascae 7 = 10k 4 re 2 / amie > | YT ct Ph + 1/4 Ri AD&24B, Vin W 499k, 1% a ov TO 2.5V FULL SCALE c2 0.01pF, 2% T* VsONotes: four Vin (VRE, ), ty = 1.1R3*CB = 25kHz f, AS SHOWN. * = 1% METAL FILM, <5OppnvC TC * 10%, 20T FILM, <100ppnvC TC t, = 3318 FOR foyy = 20kHz @ V,,, = 2.0V Figure 31. Single Supply Voltage-to-Frequency Converter Typical AD824 bias currents of 2 pA allow megaohm-range source impedances with negligible dc errors. Linearity errors on the order of 0.01% full scale can be achieved with this circuit. This performance is obtained with a 5 volt single supply which delivers less than 3 mA to the entire circuit. Single-Supply Programmable Gain Instrumentation Amplifier The AD824 can be configured as a single supply instrumenta- tion amplifier that is able to operate from single supplies down to 3 V, or dual supplies up to +15 V. AD824 FET inputs 2 pA bias currents minimize offset errors caused by high unbalanced source impedances. An array of precision thin-film resistors sets the in amp gain to be either 10 or 100. These resistors are laser-trimmed to ratio match to 0.01%, and have a rnaximum differential TC of 5 ppm/C. Table I. AD824 In Amp Performance Parameters Vs=3V,0V | V5=1+5V CMRR 74 dB 80 dB Common-Mode Voltage Range -0.2 Vto +2 V} -5.2Vto+4V 3 dB BW, G=10 180 kHz 180 kHz G = 100 18 kHz 18 kHz tSETTLING 2 V Step (Vs = 0 V, 3 V) 2 ys 5 V (V5 =+5 V) 5 ps Noise @ f= 1kHz, G=10 | 270nVNHz | 270 nVWHz G = 100 | 2.2 pVNHz 2.2 pVNHz Figure 32a. Pulse Response of In Amp to a 500 mV p-p Input Signal; Vs = +5 V, 0 V; Gain = 10 (G=10) Vout = (Viggy Vie) (1+ (G=100) Vout = (Vee Vina) (1+ R6 R4+R5 RS + A OHMTEK PART # 1043 )V pee ) #Vpce FOR Ai = RG, R2 = AS, AND R3 A4 Figure 32b. A Single-Supply Programmable Instrumentation Amplifier ~12- REV.AAD824 3 Volt, Single Supply Stereo Headphone Driver The AD824 exhibits good current drive and THD+N perfor- mance, even at 3 V single supplies. At 1 kHz, total harmonic distortion plus noise (THD+N) equals -62 dB (0.079%) for a 300 mV p-p output signal. This is comparable to other single supply op amps which consume more power and cannot run on 3 V power supplies. In Figure 33, each channel's input signal is coupled via a 1 pF Mylar capacitor. Resistor dividers set the de voltage at the noninverting inputs so that the output voltage is midway be- tween the power supplies (+1.5 V). The gain is 1.5. Each half of the AD824 can then be used to drive a headphone channel. A 5 Hz high-pass filter is realized by the 500 pF capacitors and the headphones, which can be modeled as 32 ohm load resistors to ground. This ensures that all signals in the audio frequency range (20 Hz-20 kHz) are delivered to the headphones. ? + = ospe a o0.1pF we Vv oY CHANNEL 10|| MYLAR tto 500uF 95.3 > L i HEADPHONES 5 sox V 320 IMPEDANCE : { Vv Ny R 4.99 1uF $475k |apez4 >*-1|-O CHANNEL 2 O|| + S500pF MYLAR Figure 33. 3 Volt Single Supply Stereo Headphone Driver Low Dropout Bipolar Bridge Driver The AD824 can be used for driving a 350 ohm Wheatstone bridge. Figure 34 shows one half of the AD824 being used to buffer the AD589a 1.235 V low power reference. The output #V5 TO A/D CONVERTER REFERENCE INPUT Figure 34, Low Dropout Bipolar Bridge Driver REV. A of +4.5 V can be used to drive an A/D converter front end. The other half of the AD824 is configured as a unity-gain inverter, and generates the other bridge input of -4.5 V. Resistors R1 and R2 provide a constant current for bridge excitation. The AD620 low power instrumentation amplifier is used to condition the differential output voltage of the bridge. The gain of the AD620 is programmed using an external resistor Rc, and determined by: 49.4 kQ Rg G= +1 A 3.3 Volt/5 Volt Precision Sample-and-Hold Amplifier In battery-powered applications, low supply voltage operational amplifiers are required for low power consumption. Also, low supply voltage applications limit the signal range in precision analog circuitry. Circuits like the sample-and-hold circuit, shown in Figure 35, illustrate techniques for designing precision analog circuitry in low supply voltage applications. To maintain high signal-to-noise ratios (SNRs) in a low supply voltage appli- cation requires the use of rail-to-rail, input/output operational amplifiers. This design highlights the ability of the AD824 to operate rail-to-rail from a single +3 V/+5 V supply, with the advantages of high input impedance. The AD824, a quad JFET- input op amp, is well suited to S/H circuits due to its low input bias currents (3 pA, typical) and high input impedances (3 x 10'3 Q, typical). The AD824 also exhibits very low supply currents such that the total supply current in this circuit is less than 2.5 mA. P FALSE GROUND (FG) R4 2kQ AAA VVV 9 > O+ AD824D 12 14 = SAMPLE! (71) 13 -! FG HOLD Figure 35. 3.3 V/5.5 V Precision Sample and Hold In many single supply applications, the use of a false ground generator is required. In this circuit, Rl and R2 divide the sup- ply voltage symmetrically, creating the false ground voltage at one-half the supply. Amplifier Al then buffers this voltage cre- ating a low impedance output drive. The S/H circuit is config- ured in an inverting topology centered around this false ground level. -13-AD824 A design consideration in sample-and-hold circuits is voltage droop at the output caused by op amp bias and switch leakage currents. By choosing a JFET op amp and a low leakage CMOS switch, this design minimizes droop rate error to better than 0.1 pV/us in this circuit. Higher values of Cy, will yield a lower droop rate. For best performance Cy and C2 should be poly- styrene, polypropylene, or Teflon capacitors. These types of capacitors exhibit low leakage and low dielectric absorption. Addi- tionally, 1% metal film resistors were used throughout the design. In the sample mode, SW1 and SW4 are closed, and the output is Vour = -Vin. The purpose of SW4, which operates in paral- lel with SW1, is to reduce the pedestal, or hold step, error by injecting the same amount of charge into the noninverting input of A3 that SW1 injects into the inverting input of A3. This cre- ates a common-mode voltage across the inputs of A3 and is then rejected by the CMR of A3. Otherwise, the charge injection from SW1 would create a differential voltage step error that -14- would appear at Vout. The pedestal error for this circuit is less than 2 mV over the entire 0 V to 3.3 V/5 V signal range. An- other method of reducing pedestal error is to reduce the pulse amplitude applied to the control pins. In order to control the ADG513, only 2.4 V are required for the ON state and 0.8 V for the OFF state. If possible, use an input control signal whose amplitude ranges from 0.8 V to 2.4 V instead of a full range 0 V to 3.3 V/5 V for minimum pedestal error. Other circuit features include an acquisition time of less than 3 ps to 1%; reducing Cy and C2 will speed up the acquisition time further, but an increased pedestal error will result. Settling time is less than 300 ns to 1%, and the sample-mode signal BW is 80 kHz. The ADG513 was chosen for its ability to work with 3 V/5 V supplies, and for having normally-open and normally-closed precision CMOS switches on a dielectrically isolated process. SW2 is not required in this circuit; however, it was used in par- allel with SW3 to provide a lower Roy analog switch. REV. AAD824 * AD824 SPICE Macro-model 9/94, Rev. A * FSY1 99 0 VP I ARG/ADI FSY2 0 50 VN 1 * DC! 25 99 Dx * Copyright 1994 by Analog Devices, Inc. DC2 50 25 DX * * * Refer to README.DOC" file for License Statement. * MODELS USED * Use of this model indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments MODEL JX NJF(BETA=3.2526E-3 VTO=-2.000 IS=2E-12) .MODEL NPN NPN(BF=120 VAF=150 VAR=!5 RB=2E3 * noninverting input + RE=4 RC=550 IS=1E-16) . | inverting input MODEL PNP PNP(BF=120 VAF=150 VAR=15 RB=2E3 + RE=4 * | { positive supply RC=750 IS=1E-16) * | | | negative supply MODEL DX D(IS=1E-15) . { | | | output MODEL DY DO . itd | MODEL DQ D(IS=1E-16) SSUBCKT AD824 1 2 995025 -ENDS AD824 * INPUT STAGE & POLE AT 3.1 MHz * R3 5 99 1.193E3 R4 6 99 1.193E3 CIN i 2 4E-12 C2 5 6 19.229E-12 Il 4 50 108E-6 10S 1 2 1E-12 EOS 7 1 POLY(1) (12,98) 100E-6 1 Ji 4 2 5 JX J2 4 7 6 JX * GAIN STAGE & DOMINANT POLE * EREF 98 0 (30,0) 1 R5 9 98 2.205E6 C3 9 25 54E-12 Gl 98 9 (6,5) 0.838E-3 V1 8 98 -1 V2 98 10 -1 D1 9 10 DX D2 8 9 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 1! kHz * R21 11 12 1E6 R22 12 98 100 C4 11 12 159E-12 Ei3 11 98 POLY (2) (2,98) (1,98) 0 0.5 0.5 * * POLE AT 10 MHz * R23 18 98 1E6 C15 18 98 15,9E-15 G15 98 18 (9,98) 1E-6 * * OUTPUT STAGE * ES 26 98 (18,98) 1 RS 26 22 500 IBi 98 2} 2.404E-3 IB2 23 98 2.404E-3 D10 21 98 DY D11 98 23 DY C16 20 25 2E-12 C17 24 25 2E-12 DOI 97 20 DQ Q2 20 21 22 NPN Q3 24 23 22 PNP DQ2 24 51 DQ Q5 25 20 97 PNP 20 Q6 25 24 51 NPN 20 VP 96 97 0 VN 51 52 0 EP 96 0 (99,0) 1 EN 52 0 (50,0) t R25 30 99 5E6 R26 30 50 5E6 -15-AD824 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). Mini-DIP (N) Package 4 ' f 0.280 7.11) PRN \ 0.240 (6.10) 1 7 FT YY Tr YD peat), 0.325 (8.28), | 0.726 (18.42) | 1 0.200(7.62) |g 0.060 (1.82) o.210 0.016 (0.38) ois ar 0.130 \ L (3.20) jf 0.015 (9,381) un 0.014 (0.356) @s4) 0.046 (1.15) PLANE Bsc >| TO x45 Le ee eee es +1 ie 0.0098 (0.25) 0.0500 0.0192 (0.49) 0.0008 (0.25) 0.0500 (1.27) 0.0040 (0.10) (2) 9.0188 (0.38) 0.0075 (0.19) 0.0180 (0.41) -16- C1988-18-12/94 PRINTED IN U.S.A.