161 163 fo CONNECTION DIAGRAM (HOU GS p/OUues PINOUT A 54/74161 vA .S/74LS161 ag] fac ce[z] 5) tG 1765 72/84/74163 \B4LS/74LS163 0/057 + Bs Pp, [a 43)O1 SYNCHRONOUS PRESETTABLE Pols a] 0: BINARY COUNTERS ne fe cer[?] [10] CET env [a] [9] PE DESCRIPTION The 161 and 163 are high speed synchronous modulo-16 MR for "161 binary counters. They are synchronously presettable for application in pro- SR for '163 grammable dividers and have two types of Count Enable inputs plus a Ter- LOGIC SYMBOL minal Count output for versatility in forming synchronous multistage counters. The 161 has an asynchronous Master Reset input that overrides all sa ase other inputs and forces the outputs LOW. The 163 has a Synchronous Reset JI tt input that overrides counting and parallel loading and allows the outputs to PE Po Py P2 Po be simultaneously reset on the rising edge of the clock. For functional dere elo description and detail specifications please refer to the 160 data sheet. For 2tep S-TTL and LP-TTL versions please see the 9316 data sheet. = T T T T 1 14 13:12:~11 SYNCHRONOUS COUNTING AND LOADING RIE tor 161 Voo = Pin 16 HIGH SPEED SYNCHRONOUS EXPANSION SR for 163 Gnd = Pin8 LS VERSIONS FULLY EDGE TRIGGERED STATE DIAGRAM ORDERING CODE: See Section 9 PIN COMMERCIAL GRADE MILITARY GRADE PKG PKGS Voc = +5.0 V 45%, Voc = +5.0 V +10%, OUT) Ta=0C to +70C | Ta=-55C to t+125C | TYPE Plastic A 74161PC, 74LS161PC 9B DIP (P) 74163PC, 74LS163PC Ceramic A 74161DC, 74LS161D0C 54161DM, 54LS161DM 7B DIP (D) 74163BC, 74LS163DC 54163DM, 54LS163DM Flatpak A 74161FC, 74LS161FC 54161FM, 54LS161FM 4L (F) 74163FC, 74LS163FC 54163FM, 54LS163FM INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions 54/74 (U.L.) 54/74LS (U.L.) PIN NAMES DESCRIPTION HIGH/LOW HIGH/LOW CEP Count Enable Parallel Input 1.0/1.0 0.6/0.3 CET Count Enable Trickle Input 2.0/2.0 1.0/0.5 cP Clock Pulse Input (Active Rising Edge) 2.0/2.0 0.6/0.3 MR (161) Asynchronous Master Reset Input 1.0/1.0 0.5/0.25 _ (Active LOW) SR (163) Synchronous Reset Input (Active LOW) 1.0/1.0 0.5/0.25 Po P3 Parallel Data Inputs 1.0/1.0 0.5/0.25 PE Parallel Enable Input (Active LOW) 1.0/1.0 0.6/0.3 Qo Qs Ftip-flop Outputs 20/10 10/5.0 (2.5) TC Terminal Count Output 20/10 10/5.0 (2.5) 4-221161 163 LOGIC DIAGRAMS 161 CEP CET cp *LS161 4-222161 163 Pa CEP cET cP CEP cer Qo LOGIC DIAGRAMS "163 P2 P3 Te Qa, Qo Q3 *LS163 4-223