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2001
MOS I NTEGRATED CI RCUIT
µ
µ µ
µ
PD16704
240-OUTPUT TFT-LCD GATE DRIVER
DATA SHEET
Document No. S15809EJ1V0DS00 (1st edition)
Date Published December 2002 NS CP (K)
Printed in Japan
DESCRIPTION
The
µ
PD16704 is a TFT-LCD gate driver equipped wi th 240-output lines. It can output a high-gate scanning voltage in
response to CMOS level input because it is provided with a level-shift circuit inside the IC circuit.
FEATURES
•CMOS level input (3.0 to 3.6 V)
•240 outputs
•High-output voltage (VDD2 to VEE2: 40 V MAX.)
•Double scan inversion function
•COG inversion
ORDERING INFORMATION
Part Number Package
µ
PD16704P Chip
Remark Purchasing the above chip entail the exchange of documents such as a separate memorandum or product
quality, so please contact one of our sales representavies.
Data Sheet S15809EJ1V0DS
2
µ
µµ
µ
PD16704
1. BLOCK DIAGRAM
R,/L
DS
DSOE
CLK
STV
OE
VEE2
LS1 Note
LS1 Note
LS1 Note SR1 SR2 SR3 SR238 SR239 SR240
240 - bit shift resister
LS1 Note
LS1 Note
LS1 Note
LS2 Note LS2 Note LS2 Note LS2 Note LS2 Note LS2 Note
O
1
O
2
O
3
O
239
O
240
O
238
Note LS1: shifts CMOS level and internal level, LS2: shifts interval level and output level (VDD2 to VEE2).
Remark /xxx indica tes a ctive low signal.
Data Sheet S15809EJ1V0DS 3
µ
µµ
µ
PD16704
2. PIN CONFIGURATION (IC Pad Surface)
Chip Size: 1.06 x 15.39 mm2
Remark This figure does not specify the TCP package.
Dummy Dummy VDD2 VDD2 VDD2
Alignment Mark
Dummy
TEST1 O1
TEST1 O2
VEE2
VEE2
VEE2
VEE2
VEE1
VEE1
VEE1
VEE1
Dummy
VDD1
VDD1
VDD1
VDD1
DS
DS
R/L
R/L
STV
STV
CLK
CLK
Dummy
Dummy
OE
OE
DSOE
DSOE
VSS
VSS
VSS
VSS
VCC
VCC
VCCC
VCCC
Dummy
VEE1
VEE1
VEE1
VEE1
VEE2
VEE2
VEE2 O239
VEE2 O240
TEST2 Dummy
TEST2
Alignment Mark
Dummy Dummy VDD2 VDD2 VDD2
0
X(
+
)
Y(
+
)
• Bump size : 40 x 80
µ
m2
: 110 x 60
µ
m2
• Alignment : 50 x 50
µ
m2
Alignment Mark Coordinate (Unit: mm):
(7570, 405) , (−7570, 405)
Data Sheet S15809EJ1V0DS
4
µ
µµ
µ
PD16704
Figure 2−
−−
−1. Pad Coordinate (1/3)
No PAD Name X[
µ
m] Y[
µ
m] Bump size
(
X:Y
)
[
µ
m] No PAD Name X[
µ
m] Y[
µ
m] Bump size
(
X:Y
)
[
µ
m]
1 TEST1 -7061.8 -375.0 110:60 51 VDD2 7556.0 136.0 110:60
2 TEST1 -6931.8 -375.0 110:60 52 VDD2 7556.0 216.0 110:60
3VEE2 -6801.8 -375.0 110:60 53 VDD2 7556.0 296.0 110:60
4VEE2 -6671.8 -375.0 110:60 54 DUMMY 7200.0 310.5 40:80
5VEE2 -6541.8 -375.0 110:60 55 O240 7140.0 310.5 40:80
6VEE2 -6411.8 -375.0 110:60 56 O239 7080.0 310.5 40:80
7VEE1 -6193.8 -375.0 110:60 57 O238 7020.0 310.5 40:80
8VEE1 -6063.8 -375.0 110:60 58 O237 6960.0 310.5 40:80
9V
EE1 -5933.8 -375.0 110:60 59 O236 6900.0 310.5 40:80
10 VEE1 -5803.8 -375.0 110:60 60 O235 6840.0 310.5 40:80
11 DUMMY -5673.8 -375.0 110:60 61 O234 6780.0 310.5 40:80
12 VDD1 -5490.8 -375.0 110:60 62 O233 6720.0 310.5 40:80
13 VDD1 -5360.8 -375.0 110:60 63 O232 6660.0 310.5 40:80
14 VDD1 -4999.0 -375.0 110:60 64 O231 6600.0 310.5 40:80
15 VDD1 -4450.2 -375.0 110:60 65 O230 6540.0 310.5 40:80
16 DS -4120.4 -375.0 110:60 66 O229 6480.0 310.5 40:80
17 DS -3809.4 -375.0 110:60 67 O228 6420.0 310.5 40:80
18 RL -3362.4 -375.0 110:60 68 O227 6360.0 310.5 40:80
19 RL -2924.2 -375.0 110:60 69 O226 6300.0 310.5 40:80
20 STV -2280.2 -375.0 110:60 70 O225 6240.0 310.5 40:80
21 STV -1969.2 -375.0 110:60 71 O224 6180.0 310.5 40:80
22 CLK -1522.2 -375.0 110:60 72 O223 6120.0 310.5 40:80
23 CLK -1084.0 -375.0 110:60 73 O222 6060.0 310.5 40:80
24 DUMMY -440.0 -375.0 110:60 74 O221 6000.0 310.5 40:80
25 DUMMY 182.2 -375.0 110:60 75 O220 5940.0 310.5 40:80
26 OE 826.2 -375.0 110:60 76 O219 5880.0 310.5 40:80
27 OE 1264.4 -375.0 110:60 77 O218 5820.0 310.5 40:80
28 DSOE 1711.4 -375.0 110:60 78 O217 5760.0 310.5 40:80
29 DSOE 2022.4 -375.0 110:60 79 O216 5700.0 310.5 40:80
30 VSS 2194.2 -375.0 110:60 80 O215 5640.0 310.5 40:80
31 VSS 2564.8 -375.0 110:60 81 O214 5580.0 310.5 40:80
32 VSS 2926.6 -375.0 110:60 82 O213 5520.0 310.5 40:80
33 VSS 3056.6 -375.0 110:60 83 O212 5460.0 310.5 40:80
34 VCC 3433.4 -375.0 110:60 84 O211 5400.0 310.5 40:80
35 VCC 4073.4 -375.0 110:60 85 O210 5340.0 310.5 40:80
36 VCCC 4450.2 -375.0 110:60 86 O209 5280.0 310.5 40:80
37 VCCC 5090.2 -375.0 110:60 87 O208 5220.0 310.5 40:80
38 DUMMY 5691.8 -375.0 110:60 88 O207 5160.0 310.5 40:80
39 VEE1 5821.8 -375.0 110:60 89 O206 5100.0 310.5 40:80
40 VEE1 5951.8 -375.0 110:60 90 O205 5040.0 310.5 40:80
41 VEE1 6081.8 -375.0 110:60 91 O204 4980.0 310.5 40:80
42 VEE1 6211.8 -375.0 110:60 92 O203 4920.0 310.5 40:80
43 VEE2 6429.8 -375.0 110:60 93 O202 4860.0 310.5 40:80
44 VEE2 6559.8 -375.0 110:60 94 O201 4800.0 310.5 40:80
45 VEE2 6689.8 -375.0 110:60 95 O200 4740.0 310.5 40:80
46 VEE2 6819.8 -375.0 110:60 96 O199 4680.0 310.5 40:80
47 TEST2 6949.8 -375.0 110:60 97 O198 4620.0 310.5 40:80
48 TEST2 7079.8 -375.0 110:60 98 O197 4560.0 310.5 40:80
49 DUMMY 7556.0 -220.0 80:40 99 O196 4500.0 310.5 40:80
50 DUMMY 7556.0 -80.0 80:40 100 O195 4440.0 310.5 40:80
Data Sheet S15809EJ1V0DS 5
µ
µµ
µ
PD16704
Figure 2−
−−
−1. Pad Coordinate (2/3)
No PAD Name X[um] Y[um] Bump size (X:Y)[um] No PAD Name X
[
µ
m
]
Y
[
µ
m
]
Bum
p
size
(
X:Y
)[
µ
m
]
101 O194 4380.0 310.5 40:80 151 O144 1380.0 310.5 40:80
102 O193 4320.0 310.5 40:80 152 O143 1320.0 310.5 40:80
103 O192 4260.0 310.5 40:80 153 O142 1260.0 310.5 40:80
104 O191 4200.0 310.5 40:80 154 O141 1200.0 310.5 40:80
105 O190 4140.0 310.5 40:80 155 O140 1140.0 310.5 40:80
106 O189 4080.0 310.5 40:80 156 O139 1080.0 310.5 40:80
107 O188 4020.0 310.5 40:80 157 O138 1020.0 310.5 40:80
108 O187 3960.0 310.5 40:80 158 O137 960.0 310.5 40:80
109 O186 3900.0 310.5 40:80 159 O136 900.0 310.5 40:80
110 O185 3840.0 310.5 40:80 160 O135 840.0 310.5 40:80
111 O184 3780.0 310.5 40:80 161 O134 780.0 310.5 40:80
112 O183 3720.0 310.5 40:80 162 O133 720.0 310.5 40:80
113 O182 3660.0 310.5 40:80 163 O132 660.0 310.5 40:80
114 O181 3600.0 310.5 40:80 164 O131 600.0 310.5 40:80
115 O180 3540.0 310.5 40:80 165 O130 540.0 310.5 40:80
116 O179 3480.0 310.5 40:80 166 O129 480.0 310.5 40:80
117 O178 3420.0 310.5 40:80 167 O128 420.0 310.5 40:80
118 O177 3360.0 310.5 40:80 168 O127 360.0 310.5 40:80
119 O176 3300.0 310.5 40:80 169 O126 300.0 310.5 40:80
120 O175 3240.0 310.5 40:80 170 O125 240.0 310.5 40:80
121 O174 3180.0 310.5 40:80 171 O124 180.0 310.5 40:80
122 O173 3120.0 310.5 40:80 172 O123 120.0 310.5 40:80
123 O172 3060.0 310.5 40:80 173 O122 60.0 310.5 40:80
124 O171 3000.0 310.5 40:80 174 O121 0.0 310.5 40:80
125 O170 2940.0 310.5 40:80 175 O120 -60.0 310.5 40:80
126 O169 2880.0 310.5 40:80 176 O119 -120.0 310.5 40:80
127 O168 2820.0 310.5 40:80 177 O118 -180.0 310.5 40:80
128 O167 2760.0 310.5 40:80 178 O117 -240.0 310.5 40:80
129 O166 2700.0 310.5 40:80 179 O116 -300.0 310.5 40:80
130 O165 2640.0 310.5 40:80 180 O115 -360.0 310.5 40:80
131 O164 2580.0 310.5 40:80 181 O114 -420.0 310.5 40:80
132 O163 2520.0 310.5 40:80 182 O113 -480.0 310.5 40:80
133 O162 2460.0 310.5 40:80 183 O112 -540.0 310.5 40:80
134 O161 2400.0 310.5 40:80 184 O111 -600.0 310.5 40:80
135 O160 2340.0 310.5 40:80 185 O110 -660.0 310.5 40:80
136 O159 2280.0 310.5 40:80 186 O109 -720.0 310.5 40:80
137 O158 2220.0 310.5 40:80 187 O108 -780.0 310.5 40:80
138 O157 2160.0 310.5 40:80 188 O107 -840.0 310.5 40:80
139 O156 2100.0 310.5 40:80 189 O106 -900.0 310.5 40:80
140 O155 2040.0 310.5 40:80 190 O105 -960.0 310.5 40:80
141 O154 1980.0 310.5 40:80 191 O104 -1020.0 310.5 40:80
142 O153 1920.0 310.5 40:80 192 O103 -1080.0 310.5 40:80
143 O152 1860.0 310.5 40:80 193 O102 -1140.0 310.5 40:80
144 O151 1800.0 310.5 40:80 194 O101 -1200.0 310.5 40:80
145 O150 1740.0 310.5 40:80 195 O100 -1260.0 310.5 40:80
146 O149 1680.0 310.5 40:80 196 O99 -1320.0 310.5 40:80
147 O148 1620.0 310.5 40:80 197 O98 -1380.0 310.5 40:80
148 O147 1560.0 310.5 40:80 198 O97 -1440.0 310.5 40:80
149 O146 1500.0 310.5 40:80 199 O96 -1500.0 310.5 40:80
150 O145 1440.0 310.5 40:80 200 O95 -1560.0 310.5 40:80
Data Sheet S15809EJ1V0DS
6
µ
µµ
µ
PD16704
Figure 2−
−−
−1. Pad Coordinate (3/3)
No PAD Name X[µm] Y[µm] Bump size (X:Y)[µm] No PAD Name X[µm] Y[µm] Bump size (X:Y)[µm]
201 O94 -1620.0 310.5 40:80 251 O44 -4620.0 310.5 40:80
202 O93 -1680.0 310.5 40:80 252 O43 -4680.0 310.5 40:80
203 O92 -1740.0 310.5 40:80 253 O42 -4740.0 310.5 40:80
204 O91 -1800.0 310.5 40:80 254 O41 -4800.0 310.5 40:80
205 O90 -1860.0 310.5 40:80 255 O40 -4860.0 310.5 40:80
206 O89 -1920.0 310.5 40:80 256 O39 -4920.0 310.5 40:80
207 O88 -1980.0 310.5 40:80 257 O38 -4980.0 310.5 40:80
208 O87 -2040.0 310.5 40:80 258 O37 -5040.0 310.5 40:80
209 O86 -2100.0 310.5 40:80 259 O36 -5100.0 310.5 40:80
210 O85 -2160.0 310.5 40:80 260 O35 -5160.0 310.5 40:80
211 O84 -2220.0 310.5 40:80 261 O34 -5220.0 310.5 40:80
212 O83 -2280.0 310.5 40:80 262 O33 -5280.0 310.5 40:80
213 O82 -2340.0 310.5 40:80 263 O32 -5340.0 310.5 40:80
214 O81 -2400.0 310.5 40:80 264 O31 -5400.0 310.5 40:80
215 O80 -2460.0 310.5 40:80 265 O30 -5460.0 310.5 40:80
216 O79 -2520.0 310.5 40:80 266 O29 -5520.0 310.5 40:80
217 O78 -2580.0 310.5 40:80 267 O28 -5580.0 310.5 40:80
218 O77 -2640.0 310.5 40:80 268 O27 -5640.0 310.5 40:80
219 O76 -2700.0 310.5 40:80 269 O26 -5700.0 310.5 40:80
220 O75 -2760.0 310.5 40:80 270 O25 -5760.0 310.5 40:80
221 O74 -2820.0 310.5 40:80 271 O24 -5820.0 310.5 40:80
222 O73 -2880.0 310.5 40:80 272 O23 -5880.0 310.5 40:80
223 O72 -2940.0 310.5 40:80 273 O22 -5940.0 310.5 40:80
224 O71 -3000.0 310.5 40:80 274 O21 -6000.0 310.5 40:80
225 O70 -3060.0 310.5 40:80 275 O20 -6060.0 310.5 40:80
226 O69 -3120.0 310.5 40:80 276 O19 -6120.0 310.5 40:80
227 O68 -3180.0 310.5 40:80 277 O18 -6180.0 310.5 40:80
228 O67 -3240.0 310.5 40:80 278 O17 -6240.0 310.5 40:80
229 O66 -3300.0 310.5 40:80 279 O16 -6300.0 310.5 40:80
230 O65 -3360.0 310.5 40:80 280 O15 -6360.0 310.5 40:80
231 O64 -3420.0 310.5 40:80 281 O14 -6420.0 310.5 40:80
232 O63 -3480.0 310.5 40:80 282 O13 -6480.0 310.5 40:80
233 O62 -3540.0 310.5 40:80 283 O12 -6540.0 310.5 40:80
234 O61 -3600.0 310.5 40:80 284 O11 -6600.0 310.5 40:80
235 O60 -3660.0 310.5 40:80 285 O10 -6660.0 310.5 40:80
236 O59 -3720.0 310.5 40:80 286 O9-6720.0 310.5 40:80
237 O58 -3780.0 310.5 40:80 287 O8-6780.0 310.5 40:80
238 O57 -3840.0 310.5 40:80 288 O7-6840.0 310.5 40:80
239 O56 -3900.0 310.5 40:80 289 O6-6900.0 310.5 40:80
240 O55 -3960.0 310.5 40:80 290 O5-6960.0 310.5 40:80
241 O54 -4020.0 310.5 40:80 291 O4-7020.0 310.5 40:80
242 O53 -4080.0 310.5 40:80 292 O3-7080.0 310.5 40:80
243 O52 -4140.0 310.5 40:80 293 O2-7140.0 310.5 40:80
244 O51 -4200.0 310.5 40:80 294 O1-7200.0 310.5 40:80
245 O50 -4260.0 310.5 40:80 295 DUMMY -7260.0 310.5 40:80
246 O49 -4320.0 310.5 40:80 296 VDD2 -7556.0 296.0 110:60
247 O48 -4380.0 310.5 40:80 297 VDD2 -7556.0 216.0 110:60
248 O47 -4440.0 310.5 40:80 298 VDD2 -7556.0 136.0 110:60
249 O46 -4500.0 310.5 40:80 299 DUMMY -7556.0 -80.0 80:40
250 O45 -4560.0 310.5 40:80 300 DUMMY -7556.0 -220.0 80:40
Data Sheet S15809EJ1V0DS 7
µ
µµ
µ
PD16704
3. PIN FUNCTIONS
(1/2)
Pin Symbol Pin Name Pad No I/O Description
O1 to O240 Driver output 294 - 55 Output These pins output scan signals that dri ve t he vert i cal direc t i on (gate lines) of
a TFT-LCD. The output signals change in synchronization with the rising
edge of shif t cloc k CLK. The driver out put ampl i tude is VDD2 to VEE2.
R,/L Shift direction
select input
18, 19 Input R,/L = H (right sh i f t) : STV → O1 → O240
R,/L = L (left shift) : STV → O240 → O1
STV Start pulse
input/output
20, 21 I/O Thi s is the i nput of the i nt ernal shift regi ster. The s tart puls e i s written at t he
rising edge of shift clock CLK. The puls e range i s less than one cycle of
CLK. The input l evel i s a VDD1 to VSS (logic level).
CLK S hi f t cloc k input 22, 23 Input Thi s pin inputs a shif t cloc k to the internal shift regis t er.
The shift operation is performed i n synchronizati on with the rising edge of
this i nput .
OE Output enable
input
26, 27 Input When this pin goes low level, the dri ver out put is fi xed to VEE2 level.
The shift regi ster is not cleared. Ref er to 4. TIMING CHART for detail s.
DS Double scan
control i nput
16, 17 Input This pi n out puts scan signals simultaneously from two outputs i n
synchronizat ion with the ris e of CLK when DS = H is written. Refer to 4.
TIMI NG CHART for details.
DSOE Double scan pulse
width control i nput
28, 29 Input This pin controls t he fall t imi ng of one of the s can signal s (the output side in
normal scan mode) when the DS signal is used to output scan signals
sim ultaneousl y from t wo outputs. This signal is input asynchronous ly to the
clock. Refer to 4. TIM ING CHART for details.
VCC,
VCCC
IC internal
reference voltage
34, 35,
36, 37
– Short the VCC pin to the VCCC pin s o t hat these pi ns are in a floating st at e.
TEST1,
TEST2
TEST pins 1, 2,
47, 48
– Short TEST1 and TES T 2 separately ins i de the IC. Thes e pi ns are not
connect ed to any other pins i nside the IC.
Dummy Dummy pin 11, 24, 25, 38,
49, 50, 54,
295, 299, 300
– No dummy pins are connected to any other pi ns i nside the I C.
VDD1 Logic power
supply
12 - 15 – 3.3 ± 0.3 V
VDD2 Driver positive
power supply
51 - 53,
296 - 298
– 15 to 25 V
The driver output: hi gh l evel
Data Sheet S15809EJ1V0DS
8
µ
µµ
µ
PD16704
(2/2)
Pin Symbol Pin Name Pad No I/O Description
VSS Logic ground 30 - 33 – Connect this pi n to the ground of t he system.
VEE1 Negative power
supply for i n t e rnal
operation
7 - 10,
39 - 42
– –15 to –5 V
VEE2 Driver negative
power supply
3 - 6,
43 - 46
– The driver out put: low level (VEE2 to VEE1 < 6.0 V)
Cautions 1. To prevent latch-up, turn on power to VDD1, VEE1, VEE2, VDD2, and logic input in this order. Turn off
power in the reverse order. These power up/down sequence must be observed also during
transition period.
2. Insert a capacitor of about 0.1
µ
µµ
µ
F between each pow er line, as show n below , to secure noise margin
such as VIH and VIL.
V
DD2
V
DD1
0.1
F
V
SS
V
EE1
V
EE2
µ
0.1
F
µ
0.1
F
µ
Data Sheet S15809EJ1V0DS 9
µ
µµ
µ
PD16704
4. TIMING CHART (R,/L = H)
As shown in the figure below, when DS = H, scan signals are output successively from two outputs in synchronization
with the rise of CLK (double scan operation).
It is also possible to accelerate the fall timing of one of the scan signals (the output side in normal scan mode) in a
double scan operation by using the DSOE signal. DSOE is input asynchronously to the clock, and the output is fixed to
VEE2 in the period between the rise of DSOE and the rise of CLK.
The DSOE signal is only enabled during a double scan operation.
CLK
OE
DS
DSOE
STV
O
1
O
2
O
3
O
4
O
5
O
6
O
7
Data Sheet S15809EJ1V0DS
10
µ
µµ
µ
PD16704
5. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°
°°
°C, VSS = 0 V)
Parameter Symbol Rating Unit
Logic Suppl y Voltage VDD1 –0.5 to +7.0 V
Driver Posi tive Supply V o l tage VDD2 –0.5 to +28 V
Power Supply Voltage VDD2 to VEE1, VEE2 –0.5 to +42 V
Internal Operat i on Negative Supply V ol tage VEE1 –16 to + 0.5 V
Driver Negative Suppl y V ol tage VEE2 VEE1 – 0.3 to V EE1 + 7. 0 V
Input Vol tage VI–0.5 to V DD1 + 0.5 V
Operating Ambient Temperature TA–30 to +85 °C
Storage Temperature Tstg –55 t o +125 °C
Caution Product qualify may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge
of suffering physical damage, and therefore the product must be used under conditions that ensure
that the absolute maximum ratings are not exceeded.
Recommended Operating Range (TA = –30 to +85°C, VSS = 0 V)
Parameter Symbol MIN. TYP. MAX. Unit
Logic Suppl y Voltage VDD1 3.0 3.3 3.6 V
Driver Posi tive Supply V o l tage VDD2 15 23 25 V
Internal Operat i on Negative Supply V ol tage VEE1 –15 –10 –5.0 V
Power Supply Voltage VDD2 to VEE1 20 33 40 V
VEE2 to VEE1 06.0V
Clock Frequency fCLK 500 kHz
Electrical Characteristics (TA = –30 to +85°C, VDD1 = 3.3 V ±
±±
±0.3 V, VDD2 = 23 V, VEE1 = VEE2 = –10 V, VSS = 0 V)
Parameter Symbol Condition MIN. TYP. MAX. Unit
High-level Input Volt age VIH 0.8 VDD1 VDD1 V
Low-level Input Voltage VIL
CLK, STV, R,/L, OE
VSS 0.2 VDD1 V
LCD Driver Output ON Res i stance RON VOUT = VEE2 + 1.0 V, or
VDD2 – 1.0 V
2.0 kΩ
Input Leak Current IIL VI = 0 V or 3.6 V , ±1.0
µ
A
Dynamic Current Dis sipati on IDD1 VDD1, fCLK = 50 kHz,
fSTV = 60 Hz, No load
1000
µ
A
IDD2 VDD2, fCLK = 50 kHz,
fSTV = 60 Hz, No load
100
µ
A
IEE VEE1, fCLK = 50 kHz,
fSTV = 60 Hz, No load
−1000
µ
A
Data Sheet S15809EJ1V0DS 11
µ
µµ
µ
PD16704
Switching Characteristics (TA = –30 to +85°C, VDD1 = 3.3 V ±
±±
±0.3 V, VDD2 = 23 V, VEE1 = VEE2 = –10 V, VSS = 0 V)
Parameter Symbol Condition MIN. TYP. MAX. Unit
Driver Output Delay Ti me tPHL2 CL = 300 pF, CLK → On800 ns
tPLH2 800 ns
tPHL3 CL = 300 pF, OE → On800 ns
tPLH3 800 ns
DSOE tPHL4 800 ns
Output Ris e Time tTLH CL = 300 pF 1500 ns
Output Fall Time tTHL 1500 ns
Input Capac i t ance CITA = 25°C 15 pF
Timing Requirements (TA = –30 to +85°C, VDD1 = 3.3 V ±
±±
±0.3 V, VDD2 = 23 V, VEE1 = VEE2 = –10 V, VSS = 0 V, tr = tf =20
ns (10 to 90%) )
Parameter Symbol Condition MIN. TYP. MAX. Unit
Clock Pulse Hi gh Width PWCLK(H) 500 ns
Clock Pulse Low Widt h PWCLK(L) 500 ns
Enable Pulse Widt h PWOE OE 1000 ns
Start P ulse Setup Time tSETUP1 STV ↑ → CLK ↑200 ns
Start P ulse Hold Time tHOLD1 CLK ↑ → STV ↓ 200 ns
Double Scan S et up Ti me tSETUP2 DS ↑ → CLK ↑200 ns
Double Scan Hold Ti me tHOLD2 CLK ↑ → DS ↓ 200 ns
Remark Unless otherwise specified, the input level is defined to be VIH = 0.8 VDD1, VIL = 0.2 VDD1.
Data Sheet S15809EJ1V0DS
12
µ
µµ
µ
PD16704
Switching Characteristics Waveform (R,/L= H)
t
SETUP1
CLK
STV
t
r
90%
50%
50%
90%
10%
10%
90%
10%
t
HOLD1
PW
CLK(L)
PW
CLK
t
f
123
t
PLH2
t
PHL2
t
PLH2
t
PHL2
t
SETUP2
t
HOLD2
DS
DSOE
O
1
O
2
O
3
O
n
O
n + 1
OE
t
PHL3
O
1
-O
240
t
PLH3
50%
90% 10%
PW
OE
4567
t
TLH
t
TLH
PW
CLK(H)
t
PLH2
t
PHL4
t
PLH2
50%
50%
10% 90%
10% 90%
10%
90%
Data Sheet S15809EJ1V0DS 13
µ
µµ
µ
PD16704
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V
DD
or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
µ
µµ
µ
PD16704
Reference Documents
NEC Semiconductor Device Reliability/Quality Control System (C10983E)
Quality Grades On NEC Semiconductor Devices (C11531E)
The information in this document is current as of December, 2002. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
all products and/or types are available in every country. Please check with NEC Electronics sales
representative for availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such NEC Electronics products. No license, express, implied or
otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or
others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
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responsibility of customer. NEC Electronics assumes no responsibility for any losses incurred by customers
or third parties arising from the use of these circuits, software and information.
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customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in NEC
Electronics products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment and anti-failure features.
NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
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The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-
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"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
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The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
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(Note)
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M8E 02. 11
