To our custo mers,
Old Company Name in Catalogs and Other Documents
On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas Electronics Corpor ation took over all the business of both
companies. Therefore, althoug h the old com pany name remains in this docum ent, it is a valid
Renesas Electronics document. W e appreciate your understanding.
Renesas Electronics website: http://www.renesas.com
April 1st, 2010
Renesas Electronics Corporation
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
Notice
1. All information included in this document is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please
confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to
additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website.
2. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights
of third parties by or arising from the use of Renesas Electronics products or technical information described in this document.
No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights
of Renesas Electronics or others.
3. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part.
4. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of
semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software,
and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by
you or third parties arising from the use of these circuits, software, or information.
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incurred by you resulting from errors in or omissions from the information included herein.
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systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare
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8. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics,
especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation
characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or
damages arising out of the use of Renesas Electronics products beyond such specified ranges.
9. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have
specific chara cterist ics such as the o ccurren ce of failure at a certai n rate an d malfunct ion s under certai n u se cond ition s. Further,
Renesas Electronics pr oducts are not subject to radiation resi stance design. Please be sure to implement safety measures to
guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a
Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire
control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because
the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system
manufactured by you.
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(Note 1) “Renesas Electronics” as us ed in this document means Renesas Electronics Corporation and also includes its majo ri ty-
owned subsidiaries.
(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.
R8C/2G Group
Hardware Manual
16
User’s Manual
Rev.1.00 2008.04
RENESAS MCU
R8C FAMILY / R8C/2x SERIES
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Electronics Corp. without notice. Please review the latest information published by
Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
website (http://www.renesas.com).
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate
Renesas products for their use. Renesas neither makes warranties or representations with respect to the
accuracy or completeness of the information contained in this document nor grants any license to any
intellectual property rights or any other rights of Renesas or any third party with respect to the information in
this document.
2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising
out of the use of any information in this document, including, but not limited to, product data, diagrams, charts,
programs, algorithms, and application circuit examples.
3. You should not use the products or the technology described in this document for the purpose of military
applications such as the development of weapons of mass destruction or for the purpose of any other military
use. When exporting the products or technology described herein, you should follow the applicable export
control laws and regulations, and procedures required by such laws and regulations.
4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and
application circuit examples, is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas products listed in this
document, please confirm the latest product information with a Renesas sales office. Also, please pay regular
and careful attention to additional and different information to be disclosed by Renesas such as that disclosed
through our website. (http://www.renesas.com )
5. Renesas has used reasonable care in compiling the information included in this document, but Renesas
assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information
included in this document.
6. When using or otherwise relying on the information in this document, you should evaluate the information in
light of the total system before deciding about the applicability of such information to the intended application.
Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any
particular application and specifically disclaims any liability arising out of the application and use of the
information in this document or Renesas products.
7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas
products are not designed, manufactured or tested for applications or otherwise in systems the failure or
malfunction of which may cause a direct threat to human life or create a risk of human injury or which require
especially high quality and reliability such as safety systems, or equipment or systems for transportation and
traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication
transmission. If you are considering the use of our products for such purposes, please contact a Renesas
sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above.
8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:
(1) artificial life support devices or systems
(2) surgical implantations
(3) healthcare intervention (e.g., excision, administration of medication, etc.)
(4) any other purposes that pose a direct threat to human life
Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who
elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas
Technology Corp., its affiliated companies and their officers, directors, and employees against any and all
damages arising out of such applications.
9. You should use the products described herein within the range specified by Renesas, especially with respect
to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation
characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or
damages arising out of the use of Renesas products beyond such specified ranges.
10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific
characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use
conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and
injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for
hardware and software including but not limited to redundancy, fire control and malfunction prevention,
appropriate treatment for aging degradation or any other applicable measures. Among others, since the
evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or
system manufactured by you.
11. In case Renesas products listed in this document are detached from the products to which the Renesas
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13. Please contact a Renesas sales office if you have any questions regarding the information contained in this
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Notes regarding these materials
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes
on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under
General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each
other, the description in the body of the manual takes precedence.
1. Handling of Unused Pins
Handle unused pins in accord with the directions given under Handling of Unused Pins in the
manual.
The input pins of CMOS products are generally in the high-impedance state. In operation
with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the
vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur
due to the false recognition of the pin state as an input signal become possible. Unused
pins should be handled as described under Handling of Unused Pins in the manual.
2. Processing at Power-on
The state of the product is undefined at the moment when power is supplied.
The states of internal circuits in the LSI are indeterminate and the states of register
settings and pins are undefined at the moment when power is supplied.
In a finished product where the reset signal is applied to the external reset pin, the states
of pins are not guaranteed from the moment when power is supplied until the reset
process is completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on reset
function are not guaranteed from the moment when power is supplied until the power
reaches the level at which resetting has been specified.
3. Prohibition of Access to Reserved Addresses
Access to reserved addresses is prohibited.
The reserved addresses are provided for the possible future expansion of functions. Do
not access these addresses; the correct operation of LSI is not guaranteed if they are
accessed.
4. Clock Signals
After applying a reset, only release the reset line after the operating clock signal has become
stable. When switching the clock signal during program execution, wait until the target clock
signal has stabilized.
When the clock signal is generated with an external resonator (or from an external
oscillator) during a reset, ensure that the reset line is only released after full stabilization of
the clock signal. Moreover, when switching to a clock signal produced with an external
resonator (or by an external oscillator) while program execution is in progress, wait until
the target clock signal is stable.
5. Differences between Products
Before changing from one product to another, i.e. to one with a different part number, confirm
that the change will not lead to problems.
The characteristics of MPU/MCU in the same group but having different part numbers may
differ because of the differences in internal memory capacity and layout pattern. When
changing to products of different part numbers, implement a system-evaluation test for
each of the products.
How to Use This Manual
1. Purpose and Target Readers
This manual is designed to provide the user with an understanding of the hardware functions and electrical
characteristics of the MCU. It is intended for users designing application systems incorporating the MCU. A basic
knowledge of electric circuits, logical circuits, and MCUs is necessary in order to use this manual.
The manual comprises an overview of the product; descriptions of the CPU, system control functions, peripheral
functions, and electrical characteristics; and usage notes.
Particular attention should be paid to the precautionary notes when using the manual. These notes occur
within the body of the text, at the end of each section, and in the Usage Notes section.
The revision history summarizes the locations of revisions and additions. It does not list all revisions. Refer
to the text of the manual for details.
The following documents apply to the R8C/2G Group. Make sure to refer to the latest versions of these documents.
The newest versions of the documents listed may be obtained from the Renesas Technology Web site.
Document Type Description Document Title Document No.
Datasheet Hardware overview and electrical characteristics R8C/2G Group
Datasheet
REJ03B0223
Hardware manual Hardware specifications (pin assignments,
memory maps, peripheral function
specifications, electrical characteristics, timing
charts) and operation description
Note: Refer to the application notes for details on
using peripheral functions.
R8C/2G Group
Hardware Manual
This hardware
manual
Software manual Description of CPU instruction set R8C/Tiny Series
Software Manual
REJ09B0001
Application note Information on using peripheral functions and
application examples
Sample programs
Information on writing programs in assembly
language and C
Available from Renesas
Technology Web site.
Renesas
technical update
Product specifications, updates on documents,
etc.
2. Notation of Numbers and Symbols
The notation conventions for register names, bit names, numbers, and symbols used in this manual are described
below.
(1) Register Names, Bit Names, and Pin Names
Registers, bits, and pins are referred to in the text by symbols. The symbol is accompanied by the word
“register,” “bit,” or “pin” to distinguish the three categories.
Examples the PM03 bit in the PM0 register
P3_5 pin, VCC pin
(2) Notation of Numbers
The indication “b ” is append ed to numer ic values gi ven in binary fo rmat. Ho wever, nothing is ap pended t o the
values of single bits. The indication “h” is appended to numeric values given in hexadecim al format. Nothi ng
is appended to numeric values given in decimal format.
Examples Binary: 11b
Hexadecimal: EFA0h
Decimal: 123 4
3. Register Notation
The symbols and terms used in register diagrams are described below.
*1 Blank: Set to 0 or 1 according to the application.
0: Set to 0.
1: Set to 1.
X: Nothing is assigned.
*2 RW: Read and write.
RO: Read only.
WO: Write only.
−: Nothing is assigned.
*3• Reserved bit
Reserved bit. Set to specified value.
*4• Nothing is assigned
Nothing is assigned to the bit. As the bit may be used fo r future functions, if necessary, set to 0.
• Do not set to a value
Operation is not guaranteed when a value is set.
• Function varies according to the operating mode.
The function of the bit varies with the peripheral function mode. Refer to the register diagram for information
on the individual mode s.
XXX Register
Symbol Address After Reset
XXX XXX 00h
Bit NameBit Symbol RW
b7 b6 b5 b4 b3 b2 b1 b0
XXX bits 1 0: XXX
0 1: XXX
1 0: Do not set.
1 1: XXX
b1 b0
XXX1
XXX0
XXX4
Reserved bits
XXX5
XXX7
XXX6
Function
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined.
XXX bit
Function varies according to the operating
mode.
Set to 0.
0
(b3)
(b2)
RW
RW
RW
RW
WO
RW
RO
XXX bits
0: XXX
1: XXX
*1
*2
*3
*4
4. List of Abbreviations and Acronyms
Abbreviation Full Form
ACIA Asynchronous Communication Interface Adapter
bps bits per second
CRC Cyclic Redundancy Check
DMA Direct Memory Access
DMAC Direct Memory Access Controller
GSM Global System for Mobile Communications
Hi-Z High Impedance
IEBus Inter Equipment Bus
I/O Input / Output
IrDA Infrared Data Association
LSB Least Significant Bit
MSB Most Significant Bit
NC Non-Connect
PLL Phase Locked Loop
PWM Pulse Width Modulation
SIM Subscriber Identity Module
UART Universal Asynchronous Receiver / Transmitter
VCO Voltage Controlled Oscillator
All trademarks and registered trademarks are the property of their respective owners.
A - 1
SFR Page Reference ........................................................................................................................... B - 1
1. Overview ......................................................................................................................................... 1
1.1 Features ..................................................................................................................................................... 1
1.1.1 Applications .......................................................................................................................................... 1
1.1.2 Specifications ........................................................................................................................................ 1
1.2 Product List ............................................................................................................................................... 3
1.3 Block Diagram .................................................................. ........................................................................ 4
1.4 Pin Assignment .......................................................................................................................................... 5
1.5 Pin Functions ............................................................................................................................................. 7
2. Central Processing Unit (CPU) ....................................................................................................... 8
2.1 Data Registers (R0, R1, R2, and R3) ........................................................................................................ 9
2.2 Address Registers (A0 and A1) ................................................................................................................. 9
2.3 Frame Base Register (FB) ......................................................................................................................... 9
2.4 Interrupt Table Register (INTB) ................................................................................................................ 9
2.5 Program Counter (PC) ................ ...................................................... ................................. ........................ 9
2.6 User Stack Pointer (USP ) and Interrupt Stack Pointer (ISP) .................................................................... 9
2.7 Static Base Register (SB) ............................................. ............................................................................. 9
2.8 Flag Register (FLG) .................................................................................................................................. 9
2.8.1 Carry Flag (C) ....................................................................................................................................... 9
2.8.2 Debug Flag (D) ..................................................................................................................................... 9
2.8.3 Zero Flag (Z) ......................................................................................................................................... 9
2.8.4 Sign Flag (S) ......................................................................................................................................... 9
2.8.5 Register Bank Select Flag (B) .............................................................................................................. 9
2.8.6 Overflow Flag (O) ................................................................................................................................ 9
2.8.7 Interrupt Enable Flag (I) ..................................................................................................................... 10
2.8.8 Stack Pointer Select Flag (U) .............................................................................................................. 10
2.8.9 Processor Interrupt Priority Le vel (IPL) ............................................................................................. 10
2.8.10 Reserved Bit .................. ...................................................................................................................... 10
3. Memory .......................................................................................................................................... 11
4. Special Function Registers (SFRs) ............................................................................................... 12
5. Resets ........................................................................................................................................... 24
5.1 Hardware Reset ....................................................................................................................................... 27
5.1.1 When Power Supply is Stable ............................................................................................................. 27
5.1.2 Power On ............................................................................................................................................ 27
5.2 Power-On Reset Function ....................................................................................................................... 29
5.3 Voltage Monitor 0 Reset ......................................................................................................................... 30
5.4 Voltage Monitor 1 Reset ......................................................................................................................... 30
5.5 Voltage Monitor 2 Reset ......................................................................................................................... 30
5.6 Watchdog Timer Reset ............................................................................................................................ 31
5.7 Software Reset ......................................................................................................................................... 31
6. Voltage Detection Circuit .............................................................................................................. 32
6.1 VCC Input Voltage .................................................................................................................................. 40
6.1.1 Monitoring Vdet0 ............................. .................................................................................................. 40
Table of Contents
A - 2
6.1.2 Monitoring Vdet1 ............................. .................................................................................................. 40
6.1.3 Monitoring Vdet2 ............................. .................................................................................................. 40
6.2 Voltage Monitor 0 Reset ......................................................................................................................... 41
6.3 Voltage Monitor 1 Interru pt and Voltage Monitor 1 Reset ..................................................................... 42
6.4 Voltage Monitor 2 Interru pt and Voltage Monitor 2 Reset ..................................................................... 44
7. Comparator ................................................................................................................................... 46
7.1 Overview ................................................................................................................................................. 46
7.2 Register Description ................................................................................................................................ 48
7.3 Monitoring Comparison Results ........... ...................................................... ............................................ 55
7.3.1 Monitoring Comparator 1 ................................................................................................................... 55
7.3.2 Monitoring Comparator 2 ................................................................................................................... 55
7.4 Functional Description ............................................................................................................................ 56
7.4.1 Comparator 1 ...................... ................. ................................................... ............................................ 56
7.4.2 Comparator 2 ...................... ................. ................................................... ............................................ 59
7.5 Comparator 1 and Comparator 2 Interrupts ............................................................................................ 62
7.5.1 Non-Maskable Interrupts .................. ....................................................................... ........................... 62
7.5.2 Maskable Interrupts ............................................................................................................................ 62
7.6 Adjusting Internal Reference Voltage (Vref) ................................... ................... .................... ................ 63
8. I/O Ports ........................................................................................................................................ 65
8.1 Functions of I/O Ports ............................................................................................................................. 65
8.2 Effect on Peripheral Functions ................................................................................................................ 66
8.3 Pins Other than Programmable I/O Ports ................................................................................................ 66
8.4 Port Setting ............................................................................................................. ................................. 75
8.5 Unassigned Pin Handling ........................................................................................................................ 83
8.6 Notes on I/O Ports ................................................................................................................................... 84
8.6.1 Port P4_3, P4_4 .................................................................................................................................. 84
9. Processor Mode ............................................................................................................................ 85
9.1 Processor Modes ................................. ..................................................................................................... 85
10. Bus ................................................................................................................................................ 86
11. Clock Generation Circuit ............................................................................................................... 87
11.1 On-Chip Oscillator Clocks ...................................................................................................................... 96
11.1.1 Low-Speed On-Chip Oscillator Clock ................................................................................................ 96
11.1.2 High-Speed On-Chip Oscillator Clock ............................................................................................... 96
11.2 XCIN Clock ............................................................................................................................................. 97
11.3 CPU Clock and Peripheral Function Clock ............................................................................................. 98
11.3.1 System Clock ...................................................................................................................................... 98
11.3.2 CPU Clock . ................... ...................................................................................................................... 98
11.3.3 Peripheral Function Clock (f1, f2, f4, f8, and f32) ............................................................................. 98
11.3.4 fOCO ................................................................................................................................................... 98
11.3.5 fOCO-F ............................................................................................................................................... 98
11.3.6 fOCO-S ............................................................................................................................................... 98
11.3.7 fC4 and fC32 .............................................................................................. ......................................... 98
11.4 Power Control .......................................................................................................................................... 99
11.4.1 Standard Operating Mode ................................................................................................................... 99
A - 3
11.4.2 Wait Mode ..................................... .................................................................................. ................. 101
11.4.3 Stop Mode ..................................................................................................................... .................... 103
11.5 Notes on Clock Generation Circuit ............................................................................................ ........... 106
11.5.1 Stop Mode ..................................................................................................................... .................... 106
11.5.2 Wait Mode ..................................... .................................................................................. ................. 106
11.5.3 Oscillation Circuit Constants .............................................................................................. .............. 106
12. Protection .................................................................................................................................... 107
13. Interrupts ..................................................................................................................................... 108
13.1 I nterrupt Overview ........................ .................................................................................... .................... 108
13.1.1 Types of Interrupts ........................................................................................................ .................... 108
13.1.2 Software Interrupts ................................................................................................................... ........ 109
13.1.3 Special Interrupts .............................................................................................................................. 110
13.1.4 Peripheral Funct ion Interrup t ............................................................................................................ 110
13.1.5 Interrupts and Interrupt Vectors ................................................................................................ ........ 111
13.1.6 Interrupt Control ....................................................................... ................................ ........................ 113
13.2 INT Interrupt ......................................................................................................................................... 121
13.2.1 INTi Interrupt (i = 0, 1, 2, 4) ..................................................................................................... ........ 121
13.2.2 INTi Input Filter (i = 0, 1, 2, 4) ......................................................................................................... 124
13.3 Key Input Interrupt ................................................................................................................................ 125
13.4 A ddress Match Interrupt .............................. ..................................... ................................ ..................... 127
13.5 Notes on Interrupts ..................................................................................................................... ........... 129
13.5.1 Reading Add ress 00000 h .................................................................................................................. 129
13.5.2 SP Setting ............................................................................................................................ .............. 129
13.5.3 External Interrupt and Key Input Interrupt ....................................................................................... 129
13.5.4 Changing Interrupt Sources .............................................................................................................. 130
13.5.5 Changing Interrupt Control Register Contents ................................................................................. 131
14. ID Code Areas ............................................................................................................................ 132
14.1 Overview ............................................................................................................................................... 132
14.2 Functions ................................................................................................................... ............................ 132
14.3 Notes on ID Code Areas .................................................................................................................. ...... 133
14.3.1 Setting Example of ID Code Areas ................. ... ..................................... .................................. ........ 133
15. Option Function Select Area ....................................................................................................... 134
15.1 Overview ............................................................................................................................................... 134
15.2 OFS Register .............................................................................................................................. ........... 135
15.3 Notes on Option Function Select Area ............................................................................................... ... 136
15.3.1 Setting Example of Option Function Select Area ............................................................................. 136
16. Watchdog Timer .......................................................................................................................... 137
16.1 Count Source Protection Mode Disabled ........................................................................................ ...... 141
16.2 Count Source Protection Mode Enabled ............................................................................................... 142
17. Timers ......................................................................................................................................... 143
17.1 Timer RA ...................................................................................................................... ......................... 145
17.1.1 Timer Mode ........................................................................................................................ .............. 148
17.1.2 Pulse Output Mode .......................................................................................................... ................. 150
A - 4
17.1.3 Event Counter Mode ................................................................................................................... ...... 152
17.1.4 Pulse Width Measurement Mode ...................................................................................................... 154
17.1.5 Pulse Period Measurement Mode ....................................... ..................................... ......................... 157
17.1.6 Notes on Timer RA ........................................................................................................................... 160
17.2 Timer RB ................................................................................................................................. .............. 161
17.2.1 Timer Mode ........................................................................................................................ .............. 165
17.2.2 Programmable Waveform Generation Mode ............................................. ....................................... 168
17.2.3 Programmable One-shot Generation Mode ...................................................................................... 171
17.2.4 Programmable Wait One-Shot Generation Mode ............................................................................. 175
17.2.5 Notes on Timer RB ........................................................................................................................... 178
17.3 Timer RE ......................................................................................................................... ...................... 182
17.3.1 Real-Time Clock Mode .................................................................................................................... 183
17.3.2 Output Compare Mode ........................... ..................................................... ..................................... 191
17.3.3 Notes on Timer RE ........................................................................................................................... 197
17.4 Timer RF ............................................................................................................................................... 200
17.4.1 Input Capture Mode .......................................................................................................................... 205
17.4.2 Output Compare Mode ........................... ..................................................... ..................................... 208
17.4.3 Notes on Timer RF ........................................................................................................................... 212
18. Serial Interface ............................................................................................................................ 213
18.1 Clock Synchronous Serial I/O Mode ............................................................................................... ...... 218
18.1.1 Polarity Select Function .................................................................................................................... 221
18.1.2 LSB First/MSB First Select Function ............................................................................................... 221
18.1.3 Continuous Receive Mode ................................................................................................................ 222
18.2 Clock Asynchronous Serial I/O (UART) Mode ......................... ..................................... ...................... 223
18.2.1 Bit Rate .............. ................................................................................................... ............................ 227
18.3 Notes on Serial Interface ............................................................................................................... ........ 228
19. Hardware LIN .............................................................................................................................. 229
19.1 Features ................................................................................................................................................. 229
19.2 Input/Output Pins ................. ...................................................... ........................................................... 230
19.3 Register Configuration .......................................................................................................................... 231
19.4 Functional Description .................................................................................................................... ...... 233
19.4.1 Master Mode ..................................................................................................................................... 233
19.4.2 Slave Mode ...................................................................................................................... ................. 236
19.4.3 Bus Collision Detection Function ..................................................................................................... 240
19.4.4 Hardware LIN End Processing ......................................................................................................... 241
19.5 Interrupt Requests ....................... ...................................................... ..................................................... 242
19.6 Notes on Hardware LIN ............................................................................................................. ........... 243
20. Flash Memory ............................................................................................................................. 244
20.1 Overview ............................................................................................................................................... 244
20.2 Memory Map ................................................................ ................................................ ......................... 245
20.3 Functions to Prevent Rewriting of Flash Memory ................................................................................ 246
20.3.1 ID Code Check Function .................................................................................................................. 246
20.3.2 ROM Code Protect Function ......................................................................................................... ... 247
20.4 CPU Rewrite Mode ........................................................... ................................................... ................. 248
20.4.1 Register Description ......................................................................................................................... 249
20.4.2 Status Check Procedure .................................................................................................................... 254
A - 5
20.4.3 EW0 Mode ........................................................................................................................................ 255
20.4.4 EW1 Mode ........................................................................................................................................ 261
20.5 Standard Serial I/O Mode ................................................................................................................... ... 266
20.5.1 ID Code Check Function .................................................................................................................. 266
20.6 Parallel I/O Mode .......................... ..................................................... .................................. ................. 268
20.6.1 ROM Code Protect Function ......................................................................................................... ... 268
20.7 Notes on Flash Memory ........................................................................................................................ 269
20.7.1 CPU Rewrite Mode .............................. ...................................................... ................................. ...... 269
21. Reducing Power Consumption ................................................................................................... 271
21.1 Overview ............................................................................................................................................... 271
21.2 Key Points and Processing Methods for Reducing Power Consumption ............................................. 271
21.2.1 Voltage Detection Circuit ................................................................................................... .............. 271
21.2.2 Ports ...................................................................................................................... ............................ 271
21.2.3 Clocks ............................................................................................................................................... 271
21.2.4 Selecting Oscillation Drive Capacity ................................................................................................ 271
21.2.5 Wait Mode, Stop Mode ............................................................................................... ...................... 271
21.2.6 Stopping Peripheral Function Clocks ............. ... ............................................................................... 271
21.2.7 Timers ............................................................................................................................................... 271
21.2.8 Reducing Internal Power Consumption ............................................................................................ 272
21.2.9 Stopping Flash Memory .................................................................... ................................................ 273
21.2.10 Low-Current-Consumption Read Mode ........................................................................................... 274
22. Electrical Characteristics ............................................................................................................ 275
23. Usage Notes ............................................................................................................................... 292
23.1 Notes on I/O Ports ...................................................................................................................... ........... 292
23.1.1 Port P4_3, P4_4 .................................................................................................................. .............. 292
23.2 Notes on Clock Generation Circuit ............................................................................................ ........... 293
23.2.1 Stop Mode ..................................................................................................................... .................... 293
23.2.2 Wait Mode ..................................... .................................................................................. ................. 293
23.2.3 Oscillation Circuit Constants .............................................................................................. .............. 293
23.3 Notes on Interrupts ..................................................................................................................... ........... 294
23.3.1 Reading Add ress 00000 h .................................................................................................................. 294
23.3.2 SP Setting ............................................................................................................................ .............. 294
23.3.3 External Interrupt and Key Input Interrupt ....................................................................................... 294
23.3.4 Changing Interrupt Sources .............................................................................................................. 295
23.3.5 Changing Interrupt Control Register Contents ................................................................................. 296
23.4 Notes on ID Code Areas .................................................................................................................. ...... 297
23.4.1 Setting Example of ID Code Areas ................. ... ..................................... .................................. ........ 297
23.5 Notes on Option Function Select Area ............................................................................................... ... 298
23.5.1 Setting Example of Option Function Select Area ............................................................................. 298
23.6 Notes on Timers ...................................................................................................................... .............. 299
23.6.1 Notes on Timer RA ........................................................................................................................... 299
23.6.2 Notes on Timer RB ........................................................................................................................... 300
23.6.3 Notes on Timer RE ........................................................................................................................... 304
23.6.4 Notes on Timer RF ........................................................................................................................... 307
23.7 Notes on Serial Interface ............................................................................................................... ........ 308
23.8 Notes on Hardware LIN ............................................................................................................. ........... 309
A - 6
23.9 Notes on Flash Memory ........................................................................................................................ 310
23.9.1 CPU Rewrite Mode .............................. ...................................................... ................................. ...... 310
23.10 Notes on Noise ............................................................................................................. ......................... 312
23.10.1 Inserting a Bypass Capacitor between VCC and VSS Pins as a Countermeasure against Noise and
Latch-up ................................................................................................................................. ........... 312
23.10.2 Countermeasures against Noise Error of Port Control Registers ......................... ............................ 312
24. Notes for On-Chip Debugger ...................................................................................................... 313
Appendix 1. Package Dimensions ........................................................................................................ 314
Appendix 2. Connection Examples with On-Chip Debugging Emulator ............................................... 315
Appendix 3. Example of Oscillation Evaluation Circuit ......................................................................... 316
Index ..................................................................................................................................................... 317
B - 1
NOTE:
1. The blank regions are reserved. Do not access locations in these
regions.
Address Register Symbol Page
0000h
0001h
0002h
0003h
0004h Processor Mode Register 0 PM0 85
0005h Processor Mode Register 1 PM1 85
0006h System Clock Control Register 0 CM0 89
0007h System Clock Control Register 1 CM1 90
0008h
0009h
000Ah Protect Register PRCR 107
000Bh
000Ch System Clock Select Register OCD 91
000Dh Watchdog Timer Reset Register WDTR 139
000Eh Watchdog Timer Start Register WDTS 139
000Fh Watchdog Timer Control Register WDC 139
0010h Address Match Interrupt Register 0 RMAD0 128
0011h
0012h
0013h Address Match Interrupt Enable Register AIER 128
0014h Address Match Interrupt Register 1 RMAD1 128
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch Count Source Protection Mode Register CSPR 140
001Dh
001Eh
001Fh
0020h High-Speed On-Chip Oscillator Control Register 0 HRA0 92
0021h High-Speed On-Chip Oscillator Control Register 1 HRA1 92
0022h High-Speed On-Chip Oscillator Control Register 2 HRA2 92
0023h
0024h
0025h
0026h
0027h
0028h Clock Prescaler Reset Flag CPSRF 93
0029h High-Speed On-Chip Oscillator Control Register 4 FRA4 93
002Ah
002Bh High-Speed On-Chip Oscillator Control Register 6 FRA6 93
002Ch
002Dh
002Eh BGR Trimming Auxiliary Register A BGRTRMA 48
002Fh BGR Trimming Auxiliary Register B BGRTRMB 48
0030h
0031h Voltage Detection Register 1 VCA1 35, 49
0032h Voltage Detection Register 2 VCA2 35, 49, 94
0033h
0034h
0035h
0036h Voltage Monitor 1 Circuit Control Register VW1C 37, 50
0037h Voltage Monitor 2 Circuit Control Register VW2C 38, 51
0038h Voltage Monitor 0 Circuit Control Register VW0C 36
0039h
003Ah
003Bh Voltage Detection Circuit External Input Control
Register
VCAB 52
003Ch Comparator Mode Register ALCMR 52
003Dh Voltage Monitor Circuit Edge Select Register VCAC 39, 53
003Eh BGR Control Register BGRCR 53
003Fh BGR Trimming Register BGRTRM 54
Address Register Symbol Page
0040h
0041h Comparator 1 Interrupt Control Register VCMP1IC 113
0042h Comparator 2 Interrupt Control Register VCMP2IC 113
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah Timer RE Interrupt Control Register TREIC 113
004Bh UART2 Transmit Interrupt Control Register S2TIC 113
004Ch UART2 Receive Interrupt Control Register S2RIC 113
004Dh Key Input Interrupt Control Register KUPIC 113
004Eh
004Fh
0050h Compare 1 Interrupt Control Register CMP1IC 113
0051h UART0 Transmit Interrupt Control Register S0TIC 113
0052h UART0 Receive Interrupt Control Register S0RIC 113
0053h
0054h
0055h INT2 Interrupt Control Register INT2IC 114
0056h Timer RA Interrupt Control Register TRAIC 113
0057h
0058h Timer RB Interrupt Control Register TRBIC 113
0059h INT1 Interrupt Control Register INT1IC 114
005Ah
005Bh Timer RF Interrupt Control Register TRFIC 113
005Ch Compare 0 Interrupt Control Register CMP0IC 113
005Dh INT0 Interrupt Control Register INT0IC 114
005Eh INT4 Interrupt Control Register INT4IC 114
005Fh Capture Interrupt Control Register CAPIC 113
0060h
0061h
0062h
0063h
0064h
0065h
0066h
0067h
0068h
0069h
006Ah
006Bh
006Ch
006Dh
006Eh
006Fh
0070h
0071h
0072h
0073h
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
007Eh
007Fh
SFR Page Reference
B - 2
NOTE:
1. The blank regions are reserved. Do not access locations in these
regions.
Address Register Symbol Page
0080h
0081h
0082h
0083h
0084h
0085h
0086h
0087h
0088h
0089h
008Ah
008Bh
008Ch
008Dh
008Eh
008Fh
0090h
0091h
0092h
0093h
0094h
0095h
0096h
0097h
0098h
0099h
009Ah
009Bh
009Ch
009Dh
009Eh
009Fh
00A0h UART0 Transmit/Receive Mode Register U0MR 215
00A1h UART0 Bit Rate Register U0BRG 215
00A2h UART0 Transmit Buffer Register U0TB 216
00A3h
00A4h UART0 Transmit/Receive Control Register 0 U0C0 216
00A5h UART0 Transmit/Receive Control Register 1 U0C1 217
00A6h UART0 Receive Buffer Register U0RB 217
00A7h
00A8h
00A9h
00AAh
00ABh
00ACh
00ADh
00AEh
00AFh
00B0h
00B1h
00B2h
00B3h
00B4h
00B5h
00B6h
00B7h
00B8h
00B9h
00BAh
00BBh
00BCh
00BDh
00BEh
00BFh
Address Register Symbol Page
00C0h
00C1h
00C2h
00C3h
00C4h
00C5h
00C6h
00C7h
00C8h
00C9h
00CAh
00CBh
00CCh
00CDh
00CEh
00CFh
00D0h
00D1h
00D2h
00D3h
00D4h
00D5h
00D6h
00D7h
00D8h
00D9h
00DAh
00DBh
00DCh
00DDh
00DEh
00DFh
00E0h Port P0 Register P0 72
00E1h Port P1 Register P1 72
00E2h Port P0 Direction Register PD0 71
00E3h Port P1 Direction Register PD1 71
00E4h
00E5h Port P3 Register P3 72
00E6h
00E7h Port P3 Direction Register PD3 71
00E8h Port P4 Register P4 72
00E9h
00EAh Port P4 Direction Register PD4 71
00EBh
00ECh Port P6 Register P6 72
00EDh
00EEh Port P6 Direction Register PD6 71
00EFh
00F0h
00F1h
00F2h
00F3h
00F4h
00F5h
00F6h Pin Select Register 2 PINSR2 73
00F7h Pin Select Register 3 PINSR3 73
00F8h Port Mode Register PMR 74
00F9h External Input Enable Register INTEN 121
00FAh INT Input Filter Select Register INTF 122
00FBh Key Input Enable Register KIEN 126
00FCh Pull-Up Control Register 0 PUR0 74
00FDh Pull-Up Control Register 1 PUR1 74
00FEh
00FFh
B - 3
NOTE:
1. The blank regions are reserved. Do not access locations in these
regions.
Address Register Symbol Page
0100h Timer RA Control Register TRACR 146
0101h Timer RA I/O Control Register TRAIOC 146, 148, 151,
153, 155, 158
0102h Timer RA Mode Register TRAMR 147
0103h Timer RA Prescaler Register TRAPRE 147
0104h Timer RA Register TRA 147
0105h
0106h LIN Control Register LINCR 231
0107h LIN Status Register LINST 232
0108h Timer RB Control Register TRBCR 162
0109h Timer RB One-Shot Control Register TRBOCR 162
010Ah Timer RB I/O Control Register TRBIOC 163, 165, 169,
172, 176
010Bh Timer RB Mode Register TRBMR 163
010Ch Timer RB Prescaler Register TRBPRE 164
010Dh Timer RB Secondary Register TRBSC 164
010Eh Timer RB Primary Register TRBPR 164
010Fh
0110h
0111h
0112h
0113h
0114h
0115h
0116h
0117h
0118h Timer RE Second Data Register / Counter
Data Register
TRESEC 185, 193
0119h Timer RE Minute Data Register / Compare
Data Register
TREMIN 185, 193
011Ah Timer RE Hour Data Register TREHR 186
011Bh Timer RE Day of Week Data Register TREWK 186
011Ch Timer RE Control Register 1 TRECR1 187, 194
011Dh Timer RE Control Register 2 TRECR2 188, 194
011Eh Timer RE Count Source Select Register TRECSR 189, 195
011Fh Timer RE Real-Time Clock Precision Adjust
Register
TREOPR 189
0120h
0121h
0122h
0123h
0124h
0125h
0126h
0127h
0128h
0129h
012Ah
012Bh
012Ch
012Dh
012Eh
012Fh
Address Register Symbol Page
0130h
0131h
0132h
0133h
0134h
0135h
0136h
0137h
0138h
0139h
013Ah
013Bh
013Ch
013Dh
013Eh
013Fh
0140h
0141h
0142h
0143h
0144h
0145h
0146h
0147h
0148h
0149h
014Ah
014Bh
014Ch
014Dh
014Eh
014Fh
0150h
0151h
0152h
0153h
0154h
0155h
0156h
0157h
0158h
0159h
015Ah
015Bh
015Ch
015Dh
015Eh
015Fh
B - 4
NOTE:
1. The blank regions are reserved. Do not access locations in these
regions.
Address Register Symbol Page
0160h UART2 Transmit/Receive Mode Register U2MR 215
0161h UART2 Bit Rate Register U2BRG 215
0162h UART2 Transmit Buffer Register U2TB 216
0163h
0164h UART2 Transmit/Receive Control Register 0 U2C0 216
0165h UART2 Transmit/Receive Control Register 1 U2C1 217
0166h UART2 Receive Buffer Register U2RB 217
0167h
0168h
0169h
016Ah
016Bh
016Ch
016Dh
016Eh
016Fh
0170h
0171h
0172h
0173h
0174h
0175h
0176h
0177h
0178h
0179h
017Ah
017Bh
017Ch
017Dh
017Eh
017Fh
0180h
0181h
0182h
0183h
0184h
0185h
0186h
0187h
0188h
0189h
018Ah
018Bh
018Ch
018Dh
018Eh
018Fh
0190h
0191h
0192h
0193h
0194h
0195h
0196h
0197h
0198h
0199h
019Ah
019Bh
019Ch
019Dh
019Eh
019Fh
Address Register Symbol Page
01A0h
01A1h
01A2h
01A3h
01A4h
01A5h
01A6h
01A7h
01A8h
01A9h
01AAh
01ABh
01ACh
01ADh
01AEh
01AFh
01B0h
01B1h
01B2h
01B3h Flash Memory Control Register 4 FMR4 253
01B4h
01B5h Flash Memory Control Register 1 FMR1 252
01B6h
01B7h Flash Memory Control Register 0 FMR0 249
01B8h
01B9h
01BAh
01BBh
01BCh
01BDh
01BEh
01C0h
01C1h
01C2h
01C3h
01C4h
01C5h
01C6h
01C7h
01C8h
01C9h
01CAh
01CBh
01CCh
01CDh
01CEh
01CFh
01D0h
01D1h
01D2h
01D3h
01D4h
01D5h
01D6h
01D7h
01D8h
01D9h
01DAh
01DBh
01DCh
01DDh
01DEh
01DFh
B - 5
NOTE:
1. The blank regions are reserved. Do not access locations in these
regions.
Address Register Symbol Page
01E0h
01E1h
01E2h
01E3h
01E4h
01E5h
01E6h
01E7h
01E8h
01E9h
01EAh
01EBh
01ECh
01EDh
01EEh
01EFh
01F0h
01F1h
01F2h
01F3h
01F4h
01F5h
01F6h
01F7h
01F8h
01F9h
01FAh
01FBh
01FCh
01FDh
01FEh
01FFh
0200h
0201h
0202h
0203h
0204h
0205h
0206h
0207h
0208h
0209h
020Ah
020Bh
020Ch
020Dh
020Eh
020Fh
0210h
0211h
0212h
0213h
0214h
0215h
0216h
0217h
0218h
0219h
021Ah
021Bh
021Ch
021Dh
021Eh
021Fh
Address Register Symbol Page
0220h
0221h
0222h
0223h
0224h
0225h
0226h
0227h
0228h
0229h
022Ah
022Bh
022Ch
022Dh
022Eh
022Fh
0230h
0231h
0232h
0233h
0234h
0235h
0236h
0237h
0238h
0239h
023Ah
023Bh
023Ch
023Dh
023Eh
023Fh
0240h
0241h
0242h
0243h
0244h
0245h
0246h
0247h
0248h
0249h
024Ah
024Bh
024Ch
024Dh
024Eh
024Fh
0250h
0251h
0252h
0253h
0254h
0255h
0256h
0257h
0258h
0259h
025Ah
025Bh
025Ch
025Dh
025Eh
025Fh
B - 6
NOTE:
1. The blank regions are reserved. Do not access locations in these
regions.
Address Register Symbol Page
0260h
0261h
0262h
0263h
0264h
0265h
0266h
0267h
0268h
0269h
026Ah
026Bh
026Ch
026Dh
026Eh
026Fh
0270h
0271h
0272h
0273h
0274h
0275h
0276h
0277h
0278h
0279h
027Ah
027Bh
027Ch
027Dh
027Eh
027Fh
0280h
0281h
0282h
0283h
0284h
0285h
0286h
0287h
0288h
0289h
028Ah
028Bh
028Ch
028Dh
028Eh
028Fh
0290h Timer RF Register TRF 202
0291h
0292h
0293h
0294h
0295h
0296h
0297h
0298h
0299h Timer RF Control Register 2 TRFCR2 203
029Ah Timer RF Control Register 0 TRFCR0 203
029Bh Timer RF Control Register 1 TRFCR1 204
029Ch Capture and Compare 0 Register TRFM0 202
029Dh
029Eh Compare 1 Register TRFM1 202
029Fh
Address Register Symbol Page
02A0h
02A1h
02A2h
02A3h
02A4h
02A5h
02A6h
02A7h
02A8h
02A9h
02AAh
02ABh
02ACh
02ADh
02AEh
02AFh
02B0h
02B1h
02B2h
02B3h
02B4h
02B5h
02B6h
02B7h
02B8h
02B9h
02BAh
02BBh
02BCh
02BDh
02BEh
02BFh
02C0h
02C1h
02C2h
02C3h
02C4h
02C5h
02C6h
02C7h
02C8h
02C9h
02CAh
02CBh
02CCh
02CDh
02CEh
02CFh
02D0h
02D1h
02D2h
02D3h
02D4h
02D5h
02D6h
02D7h
02D8h
02D9h
02DAh
02DBh
02DCh
02DDh
02DEh
02DFh
B - 7
NOTE:
1. The blank regions are reserved. Do not access locations in these
regions.
Address Register Symbol Page
02E0h
02E1h
02E2h
02E3h
02E4h
02E5h
02E6h
02E7h
02E8h
02E9h
02EAh
02EBh
02ECh
02EDh
02EEh
02EFh
02F0h
02F1h
02F2h
02F3h
02F4h
02F5h
02F6h
02F7h
02F8h
02F9h
02FAh
02FBh Pin Select Register 4 PINSR4 39, 54, 73
02FCh
02FDh External Input Enable Register 2 INTEN2 122
02FEh INT Input Filter Select Register 2 INTF2 123
02FFh Timer RF Output Control Register TRFOUT 204
FFFFh Option Function Select Register OFS 26, 135, 140,
247
Rev.1.00 Apr 04, 2008 Page 1 of 318
REJ09B0387-0100
R8C/2G Group
RENESAS MCU
1. Overview
1.1 Features
The R8C/2G Group of single-chip MCUs incorporates the R8C/Tiny Series CPU core, employing sophisticated
instructions for a high level of efficienc y. With 1 Mbyte of address space, and it is capable of executing instructions
at high speed. In addition, the CPU core boasts a multiplier for high-speed operatio n pro c essin g.
Power consumption is low, and the supported operating modes allow additional power control. These MCUs also
use an anti-noise configuration to reduce emissions of electromagnetic noise and are designed to withstand EMI.
Integration of many peripheral functions, including multifunction timer and serial interface, reduces the number of
system components.
1.1.1 Applications
Electric power meters, electronic household appliances, office equipment, audio equipment, consumer
equipment, etc.
1.1.2 Specifications
Ta ble 1.1 out lines the Specifications for R8C/2G Group.
REJ09B0387-0100
Rev.1.00
Apr 04, 2008
R8C/2G Group 1. Overview
Rev.1.00 Apr 04, 2008 Page 2 of 318
REJ09B0387-0100
NOTE:
1. Specify the D version if D version functions are to be used.
Table 1.1 Specifications for R8C/2G Group
Item Function Specification
CPU Central processing
unit
R8C/Tiny series core
• Number of fundamental instructions: 89
• Minimum instruction execution time:
125 ns (System clock = 8 MHz, VCC = 2.7 to 5.5 V)
250 ns (System clock = 4 MHz, VCC = 2.2 to 5.5 V)
• Multiplier: 16 bits × 16 bits → 32 bits
• Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits → 32 bits
• Operation mode: Single-chip mode (address space: 1 Mbyte)
Memory ROM, RAM Refer to Table 1.2 Product List for R8C/2G Group.
Power Supply
Voltage
Detection
Voltage detection
circuit
• Power-on reset
• Voltage detection 3
Comparator • 2 circuits (shared with voltage monitor 1 and voltage monitor 2)
• External reference voltage input is available
I/O Ports • Output-only: 1
• CMOS I/O ports: 27, selectable pull-up resistor
Clock Clock generation
circuits
• 2 circuits: On-chip oscillator (high-speed, low-speed)
(high-speed on-chip oscillator has a frequency adjustment function),
XCIN clock oscillation circuit (32 kHz)
• Frequency divider circuit: Dividing selectable 1, 2, 4, 8, and 16
• Low power consumption modes:
Standard operating mode (low-speed clock, high-speed on-chip oscillator,
low-speed on-chip oscillator), wait mode, stop mode
Real-time clock (timer RE)
Interrupts • External: 5 sources, Internal: 17 sources, Software: 4 sources
• Priority levels: 7 levels
Watchdog Timer 15 bits × 1 (with prescaler), reset start selectable
Timer Timer RA 8 bits × 1 (with 8-bit prescaler)
Timer mode (period timer), pulse output mode (output level inverted every
period), event counter mode, pulse width measurement mode, pulse period
measurement mode
Timer RB 8 bits × 1 (with 8-bit prescaler)
Timer mode (period timer), programmable waveform generation mode (PWM
output), programmable one-shot generation mode, programmable wait one-
shot generation mode
Timer RE 8 bits × 1
Real-time clock mode (count seconds, minutes, hours, days of week), output
compare mode
Timer RF 16 bits × 1 (with capture/compare register pin and compare register pin)
Input capture mode, output compare mode
Serial
Interface
UART0, UART2 Clock synchronous serial I/O/UART × 2
LIN Module Hardware LIN: 1 (timer RA, UART0)
Flash Memory • Programming and erasure voltage: VCC = 2.7 to 5.5 V
• Programming and erasure endurance: 100 times
• Program security: ROM code protect, ID code check
• Debug functions: On-chip debug, on-board flash rewrite function
Operating Frequency/Supply
Voltage
System clock = 8 MHz (VCC = 2.7 to 5.5 V)
System clock = 4 MHz (VCC = 2.2 to 5.5 V)
Current consumption 5 mA (VCC = 5 V, system clock = 8 MHz)
23 µA (VCC = 3 V, wait mode (low-speed on-chip oscillator on))
0.7 µA (VCC = 3 V, stop mode, BGR trimming circuit disabled)
Operating Ambient Temperature -20 to 85°C (N version)
-40 to 85°C (D version)(1)
Package 32-pin LQFP
Package code: PLQP0032GB-A (previous code: 32P6U-A)
R8C/2G Group 1. Overview
Rev.1.00 Apr 04, 2008 Page 3 of 318
REJ09B0387-0100
1.2 Product List
Table 1.2 lists Product List for R8C/2G Group, Figure 1.1 shows a Part Number, Mem ory Size, and Package of
R8C/2G Group.
Figure 1.1 Part Number, Memory Size, and Package of R8C/2G Group
Table 1.2 Product List for R8C/2G Group Current of Apr. 2008
Part No. ROM Capacity RAM Capacity Package Type Remarks
R5F212G4SNFP 16 Kbytes 512 bytes PLQP0032GB-A N version
R5F212G5SNFP 24 Kbytes 1 Kbytes PLQP0032GB-A
R5F212G6SNFP 32 Kbytes 1 Kbytes PLQP0032GB-A
R5F212G4SDFP 16 Kbytes 512 bytes PLQP0032GB-A D version
R5F212G5SDFP 24 Kbytes 1 Kbytes PLQP0032GB-A
R5F212G6SDFP 32 Kbytes 1 Kbytes PLQP0032GB-A
Part No. R 5 F 21 2G 4 S N FP
Package type:
FP: PLQP0032GB-A
Classification
N: Operating ambient temperature -20°C to 85°C
D: Operating ambient temperature -40°C to 85°C
S: Low-voltage version (other no symbols)
ROM capacity
4: 16 KB
5: 24 KB
6: 32 KB
R8C/2G Group
R8C/Tiny Series
Memory type
F: Flash memory version
Renesas MCU
Renesas semiconductor
R8C/2G Group 1. Overview
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1.3 Block Diagram
Figure 1.2 shows a Block Diagram.
Figure 1.2 Block Diagra m
R8C/Tiny Series CPU core Memory
Watchdog timer
(15 bits)
ROM(1)
RAM(2)
Multiplier
R0H R0L
R1H
R2
R3
R1L
A0
A1
FB
SB
USP
ISP
INTB
PC
FLG
I/O ports
NOTES:
1. ROM size varies with MCU type.
2. RAM size varies with MCU type.
System clock
generation circuit
High-speed on-chip oscillator
Low-Speed on-chip oscillator
XCIN-XCOUT
Timers
Timer RA (8 bits)
Timer RB (8 bits)
Timer RE (8 bits)
Timer RF (16 bits)
UART or
clock synchronous serial I/O
(8 bits × 2 channels)
LIN module
(1 channel)
4
Port P0
8
Port P1
8
Port P3
2
Port P4
5
Port P6
Peripheral functions
Voltage detection circuit
(3 circuits)
Comparator
(2 circuits)
1
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1.4 Pin Assignment
Figure 1.3 shows Pin Assignment (Top View). Table 1.3 outlines the Pin Name Information by Pin Number.
Figure 1.3 Pin Assignment (Top View)
R8C/2G Group
PLQP0032GB-A
(32P6U-A)
(top view)
XCIN/(P4_3)(1)
XCOUT/(P4_4)(1)
VSS
RESET
VCC
P3_7/(TRAO)/(TRFO11)(1)
MODE
P4_5/INT0
P1_7/TRAIO/INT1
P3_6/(INT1)(1)
P3_5/TRFO12
P1_0/KI0/TRFO00/VCMP1
P1_4/TXD0
P6_5/CLK2/(TREO)(1)
P1_3/KI3/VCOUT1/(TRBO)(1)
P3_3/TRFO10/TRFI
P1_1/KI1/TRFO01/VCMP2
P1_2/KI2/TRFO02/CVREF
P6_3/TXD2
P6_0/TREO
P6_6/(Kl1)(1)
P6_4/RXD2
P0_7/(Kl0)(1)
P0_6/INT4
P0_5
P1_5/RXD0/(TRAIO)/(INT1)(1)
P1_6/CLK0/VCOUT2
P3_2/INT2
P3_0/TRAO
P3_1/TRBO
P3_4/TRFO11
P0_4/(TREO)(1)
29
28
27
26
25
32
31
30
9
10
11
12
13
14
15
16
24 23 22 21 20 19 18 17
5781234 6
NOTES:
1. Can be assigned to the pin in parentheses by a program.
2. Confirm the pin 1 position on the package by referring to the package dimensions.
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NOTE:
1. Can be assigned to the pin in parentheses by a program.
Table 1.3 Pin Name Information by Pin Number
Pin
Number Control Pin Port I/O Pin Functions for of Peripheral Modules
Interrupt Timer Serial Interface
Comparator
1 P3_5 TRFO12
2 P3_7 (TRAO)/(TRFO11)(1)
3RESET
4 XCOUT (P4_4)
5VSS
6 XCIN (P4_3)
7VCC
8MODE
9 P4_5 INT0
10 P1_7 INT1 TRAIO
11 P3_6 (INT1)(1)
12 P3_1 TRBO
13 P3_0 TRAO
14 P3_2 INT2
15 P1_6 CLK0 VCOUT2
16 P1_5 (INT1)(1) (TRAIO)(1) RXD0
17 P1_4 TXD0
18 P1_3 KI3 (TRBO)(1) VCOUT1
19 P1_2 KI2 TRFO02 CVREF
20 P6_5 (TREO)(1) CLK2
21 P1_1 KI1 TRFO01 VCMP2
22 P1_0 KI0 TRFO00 VCMP1
23 P3_3 TRFO10/TRFI
24 P3_4 TRFO11
25 P0_7 (Kl0)(1)
26 P0_6 INT4
27 P0_5
28 P0_4 (TREO)(1)
29 P6_3 TXD2
30 P6_0 TREO
31 P6_6 (Kl1)(1)
32 P6_4 RXD2
R8C/2G Group 1. Overview
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1.5 Pin Functions
Table 1.4 lists Pin Functions.
I: Input O: Output I/O: Input and output
NOTE:
1. Refer to the oscillator manufacturer for oscillation characteristics.
Table 1.4 Pin Functions
Type Symbol I/O Type Description
Power supply input VCC, VSS –Apply 2.2 V to 5.5 V to the VCC pin. Apply 0 V to the VSS pin.
Reset input RESET I Input “L” on this pin resets the MCU.
MODE MODE I Connect this pin to VCC via a resistor.
XCIN clock input XCIN I These pins are provided for XCIN clock generation circuit I/O.
Connect a crystal oscillator between the XCIN and XCOUT
pins.(1) To use an external clock, input it to the XCIN pin and
leave the XCOUT pin open.
XCIN clock output XCOUT O
INT interrupt input INT0 to INT2, INT4 IINT interrupt input pins
Key input interrupt KI0 to KI3 I Key input interrupt input pins
Timer RA TRAIO I/O Timer RA I/O pin
TRAO O Timer RA output pin
Timer RB TRBO O Timer RB output pin
Timer RE TREO O Divided clock output pin
Timer RF TRFI I Timer RF input pin
TRFO00 to TRFO02,
TRFO10 to TRFO12
O Timer RF output pins
Serial interface CLK0, CLK2 I/O Clock I/O pin
RXD0, RXD2 I Serial data input pin
TXD0, TXD2 O Serial data output pin
Comparator VCMP1, VCMP2 I Analog input pins to comparator
CVREF I Reference voltage input pin to comparator
VCOUT1, VCOUT2 O Comparator output pins
I/O port P0_4 to P0_7,
P1_0 to P1_7,
P3_0 to P3_7,
P4_3, P4_5,
P6_0, P6_3 to P6_6
I/O CMOS I/O ports. Each port has an I/O select direction
register, allowing each pin in the port to be directed for input
or output individually.
Any port set to input can be set to use a pull-up resistor or not
by a program.
Output port P4_4 O Output-only port
R8C/2G Group 2. Central Processing Unit (CPU)
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2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a
register bank. There are two sets of register bank.
Figure 2.1 CPU Registers
R2
b31 b15 b8b7 b0
Data registers(1)
Address registers(1)
R3
R0H (high-order of R0)
R2
R3
A0
A1
INTBH
b15b19 b0
INTBL
FB Frame base register(1)
The 4 high order bits of INTB are INTBH and
the 16 low order bits of INTB are INTBL.
Interrupt table register
b19 b0
USP
Program counter
ISP
SB
User stack pointer
Interrupt stack pointer
Static base register
PC
FLG Flag register
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved bit
Processor interrupt priority level
Reserved bit
C
IPL DZSBOIU
b15 b0
b15 b0
b15 b0
b8 b7
NOTE:
1. These registers comprise a register bank. There are two register banks.
R1H (high-order of R1)
R0L (low-order of R0)
R1L (low-order of R1)
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2.1 Data Registers (R0, R1, R2, and R3)
R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0 can be split
into high-order bits (R 0H) and low-order bit s (R0L) to be used sep aratel y as 8-bit data regist ers. R1H and R 1L are
analogous to R0H and R0L. R2 can be combined with R0 and used a s a 32-bit data regi ster (R2R0). R3R1 is
analogous to R2R0.
2.2 Address Registers (A0 and A1)
A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is also
used for transfer, arithmetic, and logic operations. A1 is analogou s to A0. A1 can be combined with A0 to be used
as a 32-bit address register (A1A0).
2.3 Frame Base Register (FB)
FB is a 16-bit register for FB relative addressing.
2.4 Interrupt Table Register (INTB)
INTB is a 20-bit register that indicates the start address of an interrupt vector table.
2.5 Program Counter (PC)
PC is 20 bits wide and indicates the address of the next instruction to be executed.
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointers (SP), USP, and ISP, are each 16 bits wide. The U flag of FLG is used to switch between
USP and ISP.
2.7 Static Base Register (SB)
SB is a 16-bit register for SB relative addressing.
2.8 Flag Register (FLG)
FLG is an 11-bit register indicating the CPU state.
2.8.1 Carry Flag (C)
The C flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit.
2.8.2 Debug Flag (D)
The D flag is for debugging only. Set it to 0.
2.8.3 Zero Flag (Z)
The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0.
2.8.4 Sign Flag (S)
The S flag is set to 1 when an arithmetic operation results in a negative valu e; otherwise to 0.
2.8.5 Register Bank Select Flag (B)
Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is set to 1.
2.8.6 Overflow Flag (O)
The O flag is set to 1 when an operation results in an overflow; otherwise to 0.
R8C/2G Group 2. Central Processing Unit (CPU)
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2.8.7 Interrupt Enable Flag (I)
The I flag enables maskable interrupts.
Interrupt are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0
when an interrupt request is acknowledged.
2.8.8 Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1.
The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software
interrupt numbers 0 to 31 is executed.
2.8.9 Processor Interrupt Priority Level (IPL)
IPL is 3 bits wide and assigns processor inte rrupt priorit y levels from level 0 to level 7.
If a requested interrupt has higher priority than IPL, the interrupt is enabled.
2.8.10 Reserved Bit
If necessary, set to 0. When read, the content is undefined.
R8C/2G Group 3. Memory
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3. Memory
Figure 3.1 is a Memory Map of R8C/2G Group. The R8C/2G group has 1 Mbyte of address space from addresses
00000h to FFFFFh.
The internal ROM is allocated lower addresses, beginning with address 0FFFFh. For example, a 16-Kbyte internal
ROM area is allocated addresses 0C000h to 0FFFFh.
The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each
interrupt routine.
The internal RAM is allocated higher addresses beginning with address 00400h. For example, a 1-Kbyte internal RAM
area is allocated addresses 00400h to 007FFh. The internal RA M is used not only for storing data bu t also for calling
subroutines and as stacks when interrupt requests are acknowledged.
Special function registers (SFRs) are allocated addresses 0 0000h to 002FFh. The pe ripheral function control regi sters
are allocated here. All addresses within the SFR, which have not hing allocated are reserved for fu ture use and ca nnot
be accessed by users.
Figure 3.1 Memory Map of R8C/2G Group
Undefined instruction
Overflow
BRK instruction
Address match
Single step
Watchdog timer/voltage monitor/comparator
(Reserved)
(Reserved)
Reset
00400h
002FFh
00000h
Internal RAM
SFR
(Refer to 4. Special
Function Registers
(SFRs))
0FFFFh
0FFDCh
NOTE:
1. The blank regions are reserved. Do not access locations in these regions.
FFFFFh
0FFFFh
0YYYYh
Internal ROM
(program ROM)
0XXXh
Part Number
Internal ROM Internal RAM
Size Size
R5F212G4SNFP, R5F212G4SDFP
R5F212G5SNFP, R5F212G5SDFP
R5F212G6SNFP, R5F212G6SDFP
16 Kbytes
24 Kbytes
32 Kbytes
0C000h
0A000h
08000h
512 bytes
1 Kbyte
1 Kbyte
005FFh
007FFh
007FFh
Address 0YYYYh Address 0XXXXh
R8C/2G Group 4. Special Function Registers (SFRs)
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4. Special Function Registers (SFRs)
An SFR (special function register) is a control register for a peripheral function. Tables 4.1 to 4.12 list the special
function registers.
Table 4.1 SFR Information (1)(1)
X: Undefined
NOTES:
1. The blank regions are reserved. Do not access locations in these regions.
2. The CSPROINI bit in the OFS register is set to 0.
Address Register Symbol After reset
0000h
0001h
0002h
0003h
0004h Processor Mode Register 0 PM0 00h
0005h Processor Mode Register 1 PM1 00h
0006h System Clock Control Register 0 CM0 01011000b
0007h System Clock Control Register 1 CM1 00h
0008h
0009h
000Ah Protect Register PRCR 00h
000Bh
000Ch System Clock Select Register OCD 00000100b
000Dh Watchdog Timer Reset Register WDTR XXh
000Eh Watchdog Timer Start Register WDTS XXh
000Fh Watchdog Timer Control Register WDC 00X11111b
0010h Address Match Interrupt Register 0 RMAD0 00h
0011h 00h
0012h 00h
0013h Address Match Interrupt Enable Register AIER 00h
0014h Address Match Interrupt Register 1 RMAD1 00h
0015h 00h
0016h 00h
0017h
0018h
0019h
001Ah
001Bh
001Ch Count Source Protection Mode Register CSPR 00h
10000000b(2)
001Dh
001Eh
001Fh
0020h High-Speed On-Chip Oscillator Control Register 0 HRA0 00h
0021h High-Speed On-Chip Oscillator Control Register 1 HRA1 When Shipping
0022h High-Speed On-Chip Oscillator Control Register 2 HRA2 00h
0023h
0024h
0025h
0026h
0027h
0028h Clock Prescaler Reset Flag CPSRF 00h
0029h High-Speed On-Chip Oscillator Control Register 4 FRA4 When Shipping
002Ah
002Bh High-Speed On-Chip Oscillator Control Register 6 FRA6 When Shipping
002Ch
002Dh
002Eh BGR Trimming Auxiliary Register A BGRTRMA When Shipping
002Fh BGR Trimming Auxiliary Register B BGRTRMB When Shipping
R8C/2G Group 4. Special Function Registers (SFRs)
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Table 4.2 SFR Information (2)(1)
X: Undefined
NOTES:
1. The blank regions are reserved. Do not access locations in these regions.
2. Software reset, watchdog timer reset, voltage monitor 1 reset, or voltage monitor 2 reset do not affect this register.
3. The LVD0ON bit in the OFS register is set to 1 and hardware reset.
4. Power-on reset, voltage monitor 0 reset, or the LVD0ON bit in the OFS register is set to 0 and hardware reset.
5. Software reset, watchdog timer reset, voltage monitor 1 reset, or voltage monitor 2 reset do not affect b2 and b3.
Address Register Symbol After reset
0030h
0031h Voltage Detection Register 1(2) VCA1 00001000b
0032h Voltage Detection Register 2(2) VCA2 00h(3)
00100000b(4)
0033h
0034h
0035h
0036h Voltage Monitor 1 Circuit Control Register(5) VW1C 00001010b
0037h Voltage Monitor 2 Circuit Control Register(5) VW2C 00000010b
0038h Voltage Monitor 0 Circuit Control Register(2) VW0C 1000X010b(3)
1100X011b(4)
0039h
003Ah
003Bh Voltage Detection Circuit External Input Control Register VCAB 00h
003Ch Comparator Mode Register ALCMR 00h
003Dh Voltage Monitor Circuit Edge Select Register VCAC 00h
003Eh BGR Control Register BGRCR 00h
003Fh BGR Trimming Register BGRTRM When Shipping
0040h
0041h Comparator 1 Interrupt Control Register VCMP1IC XXXXX000b
0042h Comparator 2 Interrupt Control Register VCMP2IC XXXXX000b
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah Timer RE Interrupt Control Register TREIC XXXXX000b
004Bh UART2 Transmit Interrupt Control Register S2TIC XXXXX000b
004Ch UART2 Receive Interrupt Control Register S2RIC XXXXX000b
004Dh Key Input Interrupt Control Register KUPIC XXXXX000b
004Eh
004Fh
0050h Compare 1 Interrupt Control Register CMP1IC XXXXX000b
0051h UART0 Transmit Interrupt Control Register S0TIC XXXXX000b
0052h UART0 Receive Interrupt Control Register S0RIC XXXXX000b
0053h
0054h
0055h INT2 Interrupt Control Register INT2IC XX00X000b
0056h Timer RA Interrupt Control Register TRAIC XXXXX000b
0057h
0058h Timer RB Interrupt Control Register TRBIC XXXXX000b
0059h INT1 Interrupt Control Register INT1IC XX00X000b
005Ah
005Bh Timer RF Interrupt Control Register TRFIC XXXXX000b
005Ch Compare 0 Interrupt Control Register CMP0IC XXXXX000b
005Dh INT0 Interrupt Control Register INT0IC XX00X000b
005Eh INT4 Interrupt Control Register INT4IC XX00X000b
005Fh Capture Interrupt Control Register CAPIC XXXXX000b
0060h
0061h
0062h
0063h
0064h
0065h
0066h
0067h
0068h
0069h
006Ah
006Bh
006Ch
006Dh
006Eh
006Fh
R8C/2G Group 4. Special Function Registers (SFRs)
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Table 4.3 SFR Information (3)(1)
X: Undefined
NOTE:
1. The blank regions are reserved. Do not access locations in these regions.
Address Register Symbol After reset
0070h
0071h
0072h
0073h
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
007Eh
007Fh
0080h
0081h
0082h
0083h
0084h
0085h
0086h
0087h
0088h
0089h
008Ah
008Bh
008Ch
008Dh
008Eh
008Fh
0090h
0091h
0092h
0093h
0094h
0095h
0096h
0097h
0098h
0099h
009Ah
009Bh
009Ch
009Dh
009Eh
009Fh
00A0h UART0 Transmit/Receive Mode Register U0MR 00h
00A1h UART0 Bit Rate Register U0BRG XXh
00A2h UART0 Transmit Buffer Register U0TB XXh
00A3h XXh
00A4h UART0 Transmit/Receive Control Register 0 U0C0 00001000b
00A5h UART0 Transmit/Receive Control Register 1 U0C1 00000010b
00A6h UART0 Receive Buffer Register U0RB XXh
00A7h XXh
00A8h
00A9h
00AAh
00ABh
00ACh
00ADh
00AEh
00AFh
R8C/2G Group 4. Special Function Registers (SFRs)
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Table 4.4 SFR Information (4)(1)
X: Undefined
NOTE:
1. The blank regions are reserved. Do not access locations in these regions.
Address Register Symbol After reset
00B0h
00B1h
00B2h
00B3h
00B4h
00B5h
00B6h
00B7h
00B8h
00B9h
00BAh
00BBh
00BCh
00BDh
00BEh
00BFh
00C0h
00C1h
00C2h
00C3h
00C4h
00C5h
00C6h
00C7h
00C8h
00C9h
00CAh
00CBh
00CCh
00CDh
00CEh
00CFh
00D0h
00D1h
00D2h
00D3h
00D4h
00D5h
00D6h
00D7h
00D8h
00D9h
00DAh
00DBh
00DCh
00DDh
00DEh
00DFh
00E0h Port P0 Register P0 00h
00E1h Port P1 Register P1 00h
00E2h Port P0 Direction Register PD0 00h
00E3h Port P1 Direction Register PD1 00h
00E4h
00E5h Port P3 Register P3 00h
00E6h
00E7h Port P3 Direction Register PD3 00h
00E8h Port P4 Register P4 00h
00E9h
00EAh Port P4 Direction Register PD4 00h
00EBh
00ECh Port P6 Register P6 00h
00EDh
00EEh Port P6 Direction Register PD6 00h
00EFh
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Table 4.5 SFR Information (5)(1)
X: Undefined
NOTE:
1. The blank regions are reserved. Do not access locations in these regions.
Address Register Symbol After reset
00F0h
00F1h
00F2h
00F3h
00F4h
00F5h
00F6h Pin Select Register 2 PINSR2 00h
00F7h Pin Select Register 3 PINSR3 00h
00F8h Port Mode Register PMR 00h
00F9h External Input Enable Register INTEN 00h
00FAh INT Input Filter Select Register INTF 00h
00FBh Key Input Enable Register KIEN 00h
00FCh Pull-Up Control Register 0 PUR0 00h
00FDh Pull-Up Control Register 1 PUR1 00h
00FEh
00FFh
0100h Timer RA Control Register TRACR 00h
0101h Timer RA I/O Control Register TRAIOC 00h
0102h Timer RA Mode Register TRAMR 00h
0103h Timer RA Prescaler Register TRAPRE FFh
0104h Timer RA Register TRA FFh
0105h
0106h LIN Control Register LINCR 00h
0107h LIN Status Register LINST 00h
0108h Timer RB Control Register TRBCR 00h
0109h Timer RB One-Shot Control Register TRBOCR 00h
010Ah Timer RB I/O Control Register TRBIOC 00h
010Bh Timer RB Mode Register TRBMR 00h
010Ch Timer RB Prescaler Register TRBPRE FFh
010Dh Timer RB Secondary Register TRBSC FFh
010Eh Timer RB Primary Register TRBPR FFh
010Fh
0110h
0111h
0112h
0113h
0114h
0115h
0116h
0117h
0118h Timer RE Second Data Register / Counter Data Register TRESEC XXh
0119h Timer RE Minute Data Register / Compare Data Register TREMIN XXh
011Ah Timer RE Hour Data Register TREHR X0XXXXXXb
011Bh Timer RE Day of Week Data Register TREWK X0000XXXb
011Ch Timer RE Control Register 1 TRECR1 XXX0X0X0b
011Dh Timer RE Control Register 2 TRECR2 00XXXXXXb
011Eh Timer RE Count Source Select Register TRECSR 00001000b
011Fh Timer RE Real-Time Clock Precision Adjust Register TREOPR 00h
0120h
0121h
0122h
0123h
0124h
0125h
0126h
0127h
0128h
0129h
012Ah
012Bh
012Ch
012Dh
012Eh
012Fh
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Table 4.6 SFR Information (6)(1)
X: Undefined
NOTE:
1. The blank regions are reserved. Do not access locations in these regions.
Address Register Symbol After reset
0130h
0131h
0132h
0133h
0134h
0135h
0136h
0137h
0138h
0139h
013Ah
013Bh
013Ch
013Dh
013Eh
013Fh
0140h
0141h
0142h
0143h
0144h
0145h
0146h
0147h
0148h
0149h
014Ah
014Bh
014Ch
014Dh
014Eh
014Fh
0150h
0151h
0152h
0153h
0154h
0155h
0156h
0157h
0158h
0159h
015Ah
015Bh
015Ch
015Dh
015Eh
015Fh
0160h UART2 Transmit/Receive Mode Register U2MR 00h
0161h UART2 Bit Rate Register U2BRG XXh
0162h UART2 Transmit Buffer Register U2TB XXh
0163h XXh
0164h UART2 Transmit/Receive Control Register 0 U2C0 00001000b
0165h UART2 Transmit/Receive Control Register 1 U2C1 00000010b
0166h UART2 Receive Buffer Register U2RB XXh
0167h XXh
0168h
0169h
016Ah
016Bh
016Ch
016Dh
016Eh
016Fh
R8C/2G Group 4. Special Function Registers (SFRs)
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Table 4.7 SFR Information (7)(1)
X: Undefined
NOTE:
1. The blank regions are reserved. Do not access locations in these regions.
Address Register Symbol After reset
0170h
0171h
0172h
0173h
0174h
0175h
0176h
0177h
0178h
0179h
017Ah
017Bh
017Ch
017Dh
017Eh
017Fh
0180h
0181h
0182h
0183h
0184h
0185h
0186h
0187h
0188h
0189h
018Ah
018Bh
018Ch
018Dh
018Eh
018Fh
0190h
0191h
0192h
0193h
0194h
0195h
0196h
0197h
0198h
0199h
019Ah
019Bh
019Ch
019Dh
019Eh
019Fh
01A0h
01A1h
01A2h
01A3h
01A4h
01A5h
01A6h
01A7h
01A8h
01A9h
01AAh
01ABh
01ACh
01ADh
01AEh
01AFh
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Table 4.8 SFR Information (8)(1)
X: Undefined
NOTE:
1. The blank regions are reserved. Do not access locations in these regions.
Address Register Symbol After reset
01B0h
01B1h
01B2h
01B3h Flash Memory Control Register 4 FMR4 01000000b
01B4h
01B5h Flash Memory Control Register 1 FMR1 1000000Xb
01B6h
01B7h Flash Memory Control Register 0 FMR0 00000001b
01B8h
01B9h
01BAh
01BBh
01BCh
01BDh
01BEh
01BFh
01C0h
01C1h
01C2h
01C3h
01C4h
01C5h
01C6h
01C7h
01C8h
01C9h
01CAh
01CBh
01CCh
01CDh
01CEh
01CFh
01D0h
01D1h
01D2h
01D3h
01D4h
01D5h
01D6h
01D7h
01D8h
01D9h
01DAh
01DBh
01DCh
01DDh
01DEh
01DFh
01E0h
01E1h
01E2h
01E3h
01E4h
01E5h
01E6h
01E7h
01E8h
01E9h
01EAh
01EBh
01ECh
01EDh
01EEh
01EFh
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Table 4.9 SFR Information (9)(1)
X: Undefined
NOTE:
1. The blank regions are reserved. Do not access locations in these regions.
Address Register Symbol After reset
01F0h
01F1h
01F2h
01F3h
01F4h
01F5h
01F6h
01F7h
01F8h
01F9h
01FAh
01FBh
01FCh
01FDh
01FEh
01FFh
0200h
0201h
0202h
0203h
0204h
0205h
0206h
0207h
0208h
0209h
020Ah
020Bh
020Ch
020Dh
020Eh
020Fh
0210h
0211h
0212h
0213h
0214h
0215h
0216h
0217h
0218h
0219h
021Ah
021Bh
021Ch
021Dh
021Eh
021Fh
0220h
0221h
0222h
0223h
0224h
0225h
0226h
0227h
0228h
0229h
022Ah
022Bh
022Ch
022Dh
022Eh
022Fh
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Tab le 4. 10 SFR Information (10)(1)
X: Undefined
NOTE:
1. The blank regions are reserved. Do not access locations in these regions.
Address Register Symbol After reset
0230h
0231h
0232h
0233h
0234h
0235h
0236h
0237h
0238h
0239h
023Ah
023Bh
023Ch
023Dh
023Eh
023Fh
0240h
0241h
0242h
0243h
0244h
0245h
0246h
0247h
0248h
0249h
024Ah
024Bh
024Ch
024Dh
024Eh
024Fh
0250h
0251h
0252h
0253h
0254h
0255h
0256h
0257h
0258h
0259h
025Ah
025Bh
025Ch
025Dh
025Eh
025Fh
0260h
0261h
0262h
0263h
0264h
0265h
0266h
0267h
0268h
0269h
026Ah
026Bh
026Ch
026Dh
026Eh
026Fh
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Table 4.11 SFR Information (11)(1)
X: Undefined
NOTES:
1. The blank regions are reserved. Do not access locations in these regions.
2. After input capture mode.
3. After output compare mode.
Address Register Symbol After reset
0270h
0271h
0272h
0273h
0274h
0275h
0276h
0277h
0278h
0279h
027Ah
027Bh
027Ch
027Dh
027Eh
027Fh
0280h
0281h
0282h
0283h
0284h
0285h
0286h
0287h
0288h
0289h
028Ah
028Bh
028Ch
028Dh
028Eh
028Fh
0290h Timer RF Register TRF 00h
0291h 00h
0292h
0293h
0294h
0295h
0296h
0297h
0298h
0299h Timer RF Control Register 2 TRFCR2 00h
029Ah Timer RF Control Register 0 TRFCR0 00h
029Bh Timer RF Control Register 1 TRFCR1 00h
029Ch Capture and Compare 0 Register TRFM0 0000h(2)
029Dh FFFFh(3)
029Eh Compare 1 Register TRFM1 FFh
029Fh FFh
02A0h
02A1h
02A2h
02A3h
02A4h
02A5h
02A6h
02A7h
02A8h
02A9h
02AAh
02ABh
02ACh
02ADh
02AEh
02AFh
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Tab le 4. 12 SFR Information (12)(1)
X: Undefined
NOTES:
1. The blank regions are reserved. Do not access locations in these regions.
2. The OFS register cannot be changed by a program. Use a flash programmer to write to it.
Address Register Symbol After reset
02B0h
02B1h
02B2h
02B3h
02B4h
02B5h
02B6h
02B7h
02B8h
02B9h
02BAh
02BBh
02BCh
02BDh
02BEh
02BFh
02C0h
02C1h
02C2h
02C3h
02C4h
02C5h
02C6h
02C7h
02C8h
02C9h
02CAh
02CBh
02CCh
02CDh
02CEh
02CFh
02D0h
02D1h
02D2h
02D3h
02D4h
02D5h
02D6h
02D7h
02D8h
02D9h
02DAh
02DBh
02DCh
02DDh
02DEh
02DFh
02E0h
02EFh
02F0h
02F1h
02F2h
02F3h
02F4h
02F5h
02F6h
02F7h
02F8h
02F9h
02FAh
02FBh Pin Select Register 4 PINSR4 00h
02FCh
02FDh External Input Enable Register 2 INTEN2 00h
02FEh INT Input Filter Select Register 2 INTF2 00h
02FFh Timer RF Output Control Register TRFOUT 00h
FFFFh Option Function Select Register OFS (Note 2)
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5. Resets
The following resets are implemented: hardware reset, power-on reset, voltage monitor 0 reset, voltage monitor 1 reset,
voltage monitor 2 reset, watchdog timer reset, and software reset.
Table 5.1 lists the Reset Names and Sources. Figure 5.1 lists the Block Diagram of Reset Circuit.
Figure 5.1 Block Diagram of Rese t Circui t
Tab le 5.1 Reset Names and Sou rce s
Reset Name Source
Hardware reset Input voltage of RESET pin is held “L”
Power-on reset VCC rises
Voltage monitor 0 reset VCC falls (monitor voltage: Vdet0)
Voltage monitor 1 reset VCC falls (monitor voltage: Vdet1)
Voltage monitor 2 reset VCC falls (monitor voltage: Vdet2)
Watchdog timer reset Underflow of watchdog timer
Software reset Write 1 to PM03 bit in PM0 register
RESET
Power-on reset
circuit
Voltage
detection
circuit
Watchdog
timer
CPU
Voltage monitor 0 reset
SFRs
Bits VCA25,
VW0C0, and
VW0C6
SFRs
Bits VCA13, VCA26, VCA27,
VW1C2, VW1C3,
VW2C2, VW2C3,
VW0C1, VW0F0,
VW0F1, and VW0C7
Pin, CPU, and
SFR bits other than
those listed above(1)
VCC
Hardware reset
Power-on reset
Voltage monitor 1 reset
Watchdog timer
reset
Software reset
VCA13: Bit in VCA1 register
VCA25, VCA26, VCA27: Bits in VCA2 register
VW0C0, VW0C1, VW0C6, VW0F0, VW0F1, VW0C7: Bits in VW0C register
VW1C2, VW1C3: Bits in VW1C register
VW2C2, VW2C3: Bits in VW2C register
Voltage monitor 2
reset
SFRs
Bits VCA25,
VW0C0, and
VW0C6
NOTE:
1. The following registers and bits are not reset.
• Registers TRESEC, TREMIN, TREWK, and TRECR2
• Bits PM, H12_H24, and TSTART in the TRECR1 register
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Table 5.2 shows the Pin Functions while RESET Pin Level is “L”, Figure 5.2 shows the CPU Register Status after
Reset, Figure 5.3 shows the Reset Sequence, and Figure 5.4 shows the OFS Register.
Figure 5.2 CPU Register Status after Reset
Figure 5.3 Reset Sequence
Table 5.2 Pin Functions while RESET Pin Level is “L”
Pin Name Pin Functions
P0_4 to P0_7 Input port
P1, P3 Input port
P4_3, P4_5 Input port
P4_4 Output port
P6_0, P6_3 to P6_6 Input port
b19 b0
Interrupt table register(INTB)
Program counter(PC)
User stack pointer(USP)
Interrupt stack pointer(ISP)
Static base register(SB)
Content of addresses 0FFFEh to 0FFFCh
Flag register(FLG)
C
IPL DZSBOIU
b15 b0
b15 b0
b15 b0
b8 b7
b15 b0
0000h
0000h
0000h
0000h
0000h
0000h
0000h
Data register(R0)
Data register(R1)
Data register(R2)
Data register(R3)
Address register(A0)
Address register(A1)
Frame base register(FB)
00000h
0000h
0000h
0000h
0000h
Start time of flash memory
(CPU clock × 14 cycles)
0FFFCh 0FFFEh
0FFFDh Content of reset vector
CPU clock
Address
(internal address
signal)
NOTES:
1. Hardware reset.
2. When the “L” input width to the RESET pin is set to fOCO-S clock × 32 cycles or more, setting the RESET pin to “H” also sets the internal
reset signal to “H” at the same.
CPU clock × 28 cycles
fOCO-S clock × 32 cycles(2)
fOCO-S
Internal reset
signal
RESET pin
10 cycles or more are needed(1)
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Figure 5.4 OFS Register
Option Function Select Register(1)
Symbol Address When Shipping
OFS 0FFFFh FFh(3)
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3. If the block including the OFS register is erased, FFh is set to the OFS register.
—
(b6)
Reserved bit Set to 1. RW
CSPROINI
Count source protect
mode after reset select
bit
0 : Count source protect mode enabled after reset
1 : Count source protect mode disabled after reset RW
Setting the LVD0ON bit is only valid after a hardw are reset. To use the pow er-on reset, set the LVD0ON bit to 0
(voltage monitor 0 reset enabled after hardw are reset).
ROMCP1 ROM code protect bit 0 : ROM code protect enabled
1 : ROM code protect disabled RW
ROMCR ROM code protect
disabled bit
0 : ROM code protect disabled
1 : ROMCP1 enabled RW
—
(b1) RW
Reserved bit Set to 1.
WDTON RW
Watchdog timer start
select bit
0 : Starts w atchdog timer automatically af ter reset
1 : Watchdog timer is inactive after reset
111
b7 b6 b5 b4 b3 b2 b1 b0
—
(b4)
Reserved bit Set to 1. RW
The OFS register is on the flash memory. Write to the OFS register w ith a program. After w riting is completed, do not
w rite additions to the OFS register.
LVD0ON
Voltage detection 0
circuit start bit(2)
0 : Voltage monitor 0 reset enabled after hardw are
reset
1 : Voltage monitor 0 reset disabled after hardw are
reset
RW
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5.1 Hardware Reset
A reset is applied using the RESET pin. When an “L” signal is applied to the RESET pin while the suppl y voltage
meets the recommended operating conditions, pins, CPU, and SFRs are all reset (refer to Table 5.2 Pin Functions
while RESET Pin Level is “L”). When the input level applied to the RESET pin changes from “L” to “H”, a
program is executed beginning with the address indicated by the reset vector. After reset, the low-speed on-chip
oscillator clock divided by 8 is automatically selected as the CPU clock.
Refer to 4. Special Function Registers (SFRs) for the state of the SFRs after reset.
The internal RAM is not reset. If the RESET pin is pulled “L” while writing to the internal RAM is in progress, the
contents of internal RAM will be undefined.
Figure 5.5 shows a n Example of Hardware Reset Circuit and O peration and Figure 5.6 shows an Example of
Hardware Reset Circuit (Usage Example of External Supply Voltage Detection Circuit) and Operation.
5.1.1 When Power Supply is Stable
(1) Apply “L” to the RESET pin.
(2) Wait for 10 µs.
(3) Apply “H” to the RESET pin.
5.1.2 Power On
(1) Apply “L” to the RESET pin.
(2) Let the supply voltage increase until it meets the recommended operating conditions.
(3) Wait for td(P-R) or more to allow the internal power supply to stabilize (refer to 22. Electrical
Characteristics).
(4) Wait for 10 µs.
(5) Apply “H” to the RESET pin.
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Figure 5.5 Example of Hardware Reset Circuit and Operation
Figure 5.6 Example of Hard ware Re se t Circ ui t (Us a ge Exam pl e of Extern al Sup pl y Voltage
Detection Circuit) and Operation
RESET
VCC
VCC
RESET
2.2 V
0 V
0.2 VCC or below
td(P-R) + 10µs or more
0 V
NOTE:
1. Refer to 22. Electrical Characteristics.
RESET VCC
VCC
RESET
2.2 V
0 V
0 V
5 V
5 V
Example when
VCC = 5 V
Supply voltage
detection circuit
NOTE:
1. Refer to 22. Electrical Characteristics.
td(P-R) + 10µs or more
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5.2 Power-On Reset Function
When the RESET pin is connected to the V CC pin via a pull-up resistor, and the VCC pin voltage level rises while
the rise gradient is trth or more, the power-on reset function is enabled and the MCU resets its pins, CPU, and SFR.
When a capacitor is connected to the RESET pin, too, always keep the voltage to the RESET pin 0.8VCC or more.
When the input voltage to the VCC pin reaches the Vdet0 level or above, the low-speed on-chip oscillator clock
starts counting. When the low-speed on-chip oscillator clock count reaches 32, the internal reset signal is held “H”
and the MCU enters the reset sequence (refer to Figur e 5.3). The low-speed on-chip oscillator clock divided by 8 is
automatically selected as the CPU clock after reset.
Refer to 4. Special Function Registers (SFRs) for the states of the SFR after power-on reset.
The voltage monitor 0 reset is enabled after power-on reset.
Figure 5.7 shows an Example of Power-On Reset Circuit and Operation.
Figure 5.7 Example of Power-On Reset Circuit and Operation
RESET
VCC
4.7 kΩ
(reference)
NOTES:
1. When using the voltage monitor 0 digital filter, ensure that the voltage is within the MCU operation voltage
range (2.2 V or above) during the sampling time.
2. The sampling clock can be selected. Refer to 6. Voltage Detection Circuit for details.
3. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit. Refer to 6. Voltage Detection
Circuit for details.
4. Refer to 22. Electrical Character istics.
5. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVD0ON bit in the OFS
register to 0, the VW0C0 and VW0C6 bits in the VW0C register to 1 respectively, and the VCA25 bit in the
VCA2 register to 1.
Vdet0(3)
Vpor1
Internal
reset signal
(“L” valid)
tw(por1) Sampling time(1, 2)
Vdet0(3)
1
fOCO-S × 32 1
fOCO-S × 32
Vpor2
External
Power VCC
trth
trth
2.2 V
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5.3 Voltage Monitor 0 Reset
A reset is applied using the on-chip voltage detection 0 circuit. The voltage detection 0 circuit monitors the input
voltage to the VCC pin. The voltage to monitor is Vdet0.
When the input voltage to the VCC pin reaches the Vdet0 level or below, the pins, CPU, and SFR are reset.
When the input voltage to the VCC pin reaches the Vdet0 level or above, the low-speed on-chip oscillator clock
start counting. When the low-speed on-chip oscillator clock count reaches 32, the internal reset signal is held “H”
and the MCU enters the reset sequence (refer to Figur e 5.3). The low-speed on-chip oscillator clock divided by 8 is
automatically selected as the CPU clock after reset.
The LVD0ON bit in the OFS register can be used to enable or disable voltage monitor 0 reset after a hardware reset.
Setting the LVD0ON bit is only valid after a hardware reset.
To use the power-on reset function, enable voltage mon itor 0 reset by setting the LVD0ON bit in the OFS register
to 0, the VW0C0 and VW0C6 bits in the VW0C register to 1 respectively, and the VCA25 bit in the VCA2 register
to 1.
The LVD0ON bit cannot be changed by a program. To set the LVD0ON bit, write 0 (voltage monitor 0 reset
enabled after hardware reset) or 1 (voltage monitor 0 reset disabled after hardware reset) to bit 5 of address 0FFFFh
using a flash programmer.
Refer to Figure 5.4 OFS Register for details of the OFS register.
Refer to 4. Special Function Registers (SFRs) for the status of the SFR after voltage monitor 0 reset.
The internal RAM is not reset. When the input voltage to the VCC pin reaches the Vdet0 level or below while
writing to the internal RAM is in progress, the contents of internal RAM are undefined.
Refer to 6. Voltage Detection Circuit for details of voltage monitor 0 reset.
5.4 Voltage Monitor 1 Reset
A reset is applied using the on-chip voltage detection 1 circuit. The voltage detection 1 circuit monitors the input
voltage to the VCC pin. The voltage to monitor is Vdet1.
When the input voltage to the VCC pin reaches the Vdet1 level or below, the pins, CPU, and SFR are
reset and a
program is executed beginning with the address indicated by the reset vector. After reset, the low-speed on-chip
oscillator clock divided by 8 is automatically selected as the CPU clock.
The voltage monitor 1 does not reset some portions of the SFR. Refer to 4. Special Function Registers (SFRs) for
details.
The internal RAM is not reset. When the input voltage to the VCC pin reaches the Vdet1 level or below while
writing to the internal RAM is in progress, the contents of internal RAM are undefined.
Refer to 6. Voltage Detection Circuit for details of voltage monitor 1 reset.
5.5 Voltage Monitor 2 Reset
A reset is applied using the on-chip voltage detection 2 circuit. The voltage detection 2 circuit monitors the input
voltage to the VCC pin. The voltage to monitor is Vdet2.
When the input voltage to the VCC pin
reaches
the Vdet2 level or below, the pins, CPU, and SFR are reset and the
program beginning with the address indicated by the reset vector is executed. After reset, the low-speed on-chip
oscillator clock divided by 8 is automatically selected as the CPU clock.
The voltage monitor 2 does not reset some SFRs. Refer to 4. Special Function Registers (SFRs) for details.
The internal RAM is not reset. When the input voltage to the VCC pin reaches the Vdet2 level or below while
writing to the internal RAM is in progress, the contents of internal RAM are undefined.
Refer to 6. Voltage Detection Circuit for details of voltage monitor 2 reset.
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5.6 Watchdog Timer Reset
When the PM12 bit in the PM1 register is set to 1 (reset when watchdog timer underflows), the MCU resets its pins,
CPU, and SFR if the watchd og timer underflows. Then t he program beginning with t he address indicated by the
reset vector is executed. After reset, the low-speed on-chip oscillator clock divided by 8 is automatically selected as
the CPU clock.
The watchdog timer reset does not reset some SFRs. Refer to 4. Special Function Registers (SFRs) for details.
The internal RAM is not reset. When the watchdog tim er underflows, the contents of internal RAM are undefined.
Refer to 16. Watchdog Timer for details of the watchdog timer.
5.7 Software Reset
When the PM03 bit in the PM0 register is set to 1 (MCU reset), the MCU resets its pins, CPU, and SFR. The
program beginning with the address indicated by the reset vector is executed. After reset, the low-speed on-chip
oscillator clock divided by 8 is auto matically selected for the CPU clock.
The software reset does not reset some SFRs. Refer to 4. Special Function Registers (SFRs) for detai ls.
The internal RAM is not reset.
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6. Voltage Detection Circuit
The voltage detection circuit monitors the input voltage to the VCC pin. This circuit can be used to monitor th e VCC
input voltage by a program. Alternately, voltage monitor 0 reset, voltage monitor 1 interrupt, voltage monitor 1 reset,
voltage monitor 2 interrupt, and voltage monitor 2 reset can also be used.
Note that voltage monitor 1 and voltage monitor 2 share the voltage detection circuit with comparator 1 and
comparator 2. Either voltage monitor 1 and voltage monitor 2 or comparator 1 and comparator 2 can be selected.
Table 6.1 lists the Specifications of Voltage Detection Circuit and Figures 6.1 to 6.4 show the Block Diagrams. Figures
6.5 to 6.10 show the Associated Registers.
Table 6.1 Specifications of Voltage Detection Circuit
Item Voltage Detection 0 Voltage Detection 1 Voltage Detection 2
VCC Monitor Voltage to monitor Vdet0 Vdet1 Vdet2
Detection target Whether passing
through Vdet0 by falling
Passing through Vdet1 by
rising or falling
Passing through Vdet2 by
rising or falling
Monitor None VW1C3 bit in VW1C
register
VCA13 bit in VCA1
register
Whether VCC is higher or
lower than Vdet1
Whether VCC is higher or
lower than Vdet2
Process
When Voltage
is Detected
Reset Voltage monitor 0 reset Voltage monitor 1 reset Voltage monitor 2 reset
Reset at Vdet0 > VCC;
restart CPU operation at
VCC > Vdet0
Reset at Vdet1 > VCC;
restart CPU operation
after a specified time
Reset at Vdet2 > VCC;
restart CPU operation
after a specified time
Interrupt None Voltage monitor 1 interrupt Voltage monitor 2 interrupt
Interrupt request at both
or either of Vdet1 > VCC
and VCC > Vdet1
Interrupt request at both
or either of Vdet2 > VCC
and VCC > Vdet2
Digital Filter Switch
enabled/disabled
Available Available Available
Sampling time (Divide-by-n of fOCO-S)
× 4
n: 1, 2, 4, and 8
(Divide-by-n of fOCO-S)
× 2
n: 1, 2, 4, and 8
(Divide-by-n of fOCO-S)
× 2
n: 1, 2, 4, and 8
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Figure 6.1 Block Diagram of Voltage Detection Circuit
Figure 6.2 Block Diagram of Voltage Monitor 0 Reset Generation Circuit
+
-
b3
+
-
VCA25
+
-
b3
≥ Vdet2
Internal
reference
voltage
VCA27
VCA26
VCC
Voltage detection 1
signal
VCA13 bit
Voltage detection 2
signal
Voltage detection 0 signal
≥ Vdet1
≥ Vdet0
VCA1 register
VW1C3 bit
VW1C register
Noise
filter
Noise
filter
VCMP2
VCAB6 = 1
VCAB6 = 0
VCMP1
VCAB5 = 1
VCAB5 = 0
VCA13: Bit in VCA1 register
VCA25, VCA26, VCA27: Bits in VCA2 register
VW1C3: Bit in VW1C register
VCAB5, VCAB6: Bits in VCAB register
Shared with comparator
+
-
1/2 1/2 1/2
Voltage detection 0 circuit
VCA25
VCC
Internal
reference
voltage
Voltage detection 0
signal is held “H” when
VCA25 bit is set to 0
(disabled)
Voltage
detection 0
signal
fOCO-S
VW0F1 to VW0F0
= 00b
= 01b
= 10b
= 11b
VW0C7
Voltage monitor 0
reset signal
Voltage monitor 0 reset generation circuit
VW0C0 to VW0C1, VW0F0 to VW0F1, VW0C6, VW0C7: Bits in VW0C register
VCA25: Bit in VCA2 register
VW0C0
VW0C6
VW0C1
VW0C1
Digital
filter
R8C/2G Group 6. Voltage Detection Circuit
Rev.1.00 Apr 04, 2008 Page 34 of 318
REJ09B0387-0100
Figure 6.3 Block Diagram of Voltage Monitor 1 Interrupt/Reset Generation Circuit
Figure 6.4 Block Diagram of Voltage Monitor 2 Interrupt/Reset Generation Circuit
VW1C1 = 0
VW1C1 = 1 Edge
Selection
circuit
Noise filter
1/2 1/2 1/2
VW1C3
(Filter width: 200 ns)
Voltage detection 1 signal
is held “H” when VCA26 bit
is set to 0 (disabled)
Voltage
detection
1 signal
fOCO-S
VW1F1 to VW1F0
= 00b
= 01b
= 10b
= 11b
VW1C2 bit is set to 0 (not detected) by
writing 0 by a program.
When VCA26 bit is set to 0 (voltage
detection 1 circuit disabled), VW1C2
bit is set to 0
Voltage monitor 1 interrupt/reset generation circuit
VW1C0 to VW1C3, VW1F0, VW1F1, VW1C6, VW1C7: Bits in VW1C register
VCA26: Bit in VCA2 register
VCAB5: Bit in VCAB register
VW1C2
VW1C0
VW1C6
Non-maskable
interrupt signal
Voltage monitor 1
interrupt signal
Watchdog
timer interrupt
signal
Comparator
interrupt signal
Voltage monitor 1
reset signal
+
-
Voltage detection 1 circuit
VCA26
Internal reference
voltage
VCMP1
VCAB5 = 1
VCAB5 = 0
VCC
Digital
filter
VW2C1 = 0
VW2C1 = 1 Edge
Selection
circuit
+
-
1/2 1/2 1/2
Voltage detection 2 circuit
VCA27
Internal reference
voltage
VCA13
(Filter width: 200 ns)
Voltage detection 2 signal
is held “H” when VCA27 bit
is set to 0 (disabled)
Voltage
detection
2 signal
fOCO-S
VW2F1 to VW2F0
= 00b
= 01b
= 10b
= 11b
VW2C2 bit is set to 0 (not detected) by
writing 0 by a program.
When VCA27 bit is set to 0 (voltage
detection 2 circuit disabled), VW2C2
bit is set to 0
VW2C3
Watchdog timer block
Watchdog timer
underflow signal This bit is set to 0 (not detected) by writing 0
by a program.
Voltage monitor 2 interrupt/reset generation circuit
VW2C0 to VW2C3, VW2F0, VW2F1, VW2C6, VW2C7: Bits in VW2C register
VCA13: Bit in VCA1 register
VCA27: Bit in VCA2 register
VCAB6: Bit in VCAB register
VW2C2
VW2C0
VW2C6
Non-maskable
interrupt signal
Voltage monitor 2
interrupt signal
Watchdog
timer interrupt
signal
Comparator
interrupt signal
Voltage monitor 2
reset signal
VCMP2
VCAB6 = 1
VCAB6 = 0
VCC Noise filter
Digital
filter
R8C/2G Group 6. Voltage Detection Circuit
Rev.1.00 Apr 04, 2008 Page 35 of 318
REJ09B0387-0100
Figure 6.5 Registers VCA1 an d VCA2
Voltage Detection Register 1
Symbol Address After Reset(2)
VCA1 0031h 00001000b
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
The VCA13 bit is enabled w hen the VCA27 bit in the VCA2 register is set to 1 (voltage detection 2 circuit enabled).
The VCA13 bit is set to 1 (VCC ≥ Vdet 2) w hen the VCA27 bit in the VCA2 register is set to 0 (voltage detection 2
circuit disabled).
—
(b7-b4)
Reserved bits Set to 0. RW
Set to 0.
0
b7 b6 b5 b4 b3 b2 b1 b0
0000
Softw are reset, w atchdog timer reset, voltage monitor 1 reset, and voltage monitor 2 reset do not affect this
register.
VCA13
Voltage detection 2 signal monitor
flag(1)
00
—
(b2-b0) RW
0 : VCC < Vdet2
1 : VCC ≥ Vdet2 or voltage detection 2
circuit disabled
RO
Reserved bits
Voltage Detection Register 2(1)
Symbol Address After Reset(5)
VCA2 0032h
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
4.
5.
6.
7. When the VCA20 bit is set to 1 (low consumption enabled), do not set the CM10 bit in the CM1 register to 1 (stop
mode).
Use the VCA20 bit only w hen entering to w ait mode. To set the VCA20 bit, follow the procedure show n in Figure
11.9 Handling Procedure of Internal Power Low Consumption Using VCA20 Bit.
VCA20 Internal pow er low
consumption enable bit(6)
0 : Low consumption disabled
1 : Low consumption enabled(7) RW
Set the PRC3 bit in the PRCR register to 1 (w rite enabled) before rew riting to the VCA2 register.
To use the voltage monitor 1 interrupt/reset or the VW1C3 bit in the VW1C register, set the VCA26 bit to 1.
After the VCA26 bit is set to 1 from 0, the voltage detection circuit w aits for td(E-A) to elapse before starting
operation.
To use the voltage monitor 2 interrupt/reset or the VCA13 bit in the VCA1 register, set the VCA27 bit to 1.
After the VCA27 bit is set to 1 from 0, the voltage detection circuit w aits for td(E-A) to elapse before starting
operation.
Softw are reset, w atchdog timer reset, voltage monitor 1 reset, and voltage monitor 2 reset do not affect this
register.
To use the voltage monitor 0 reset, set the VCA25 bit to 1.
After the VCA25 bit is set to 1 from 0, the voltage detection circuit w aits for td(E-A) to elapse before starting
operation.
VCA27 Voltage detection 2 enable
bit(4)
0 : Voltage detection 2 circuit disabled
1 : Voltage detection 2 circuit enabled RW
VCA26 Voltage detection 1 enable
bit(3)
0 : Voltage detection 1 circuit disabled
1 : Voltage detection 1 circuit enabled RW
0000
b3 b2 b1 b0b7 b6 b5 b4
The LVD0ON bit in the OFS register is
set to 1 and hardw are reset : 00h
Pow er-on reset, voltage monitor 0 reset
or LVD0ON bit in the OFS register is
set to 0, and hardw are reset : 00100000b
VCA25 Voltage detection 0 enable
bit(2)
0 : Voltage detection 0 circuit disabled
1 : Voltage detection 0 circuit enabled RW
—
(b4-b1)
Reserved bits Set to 0. RW
R8C/2G Group 6. Voltage Detection Circuit
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REJ09B0387-0100
Figure 6.6 VW0C Register
Voltage Monitor 0 Circuit Control Register (1)
Symbol Address
VW0C 0038h
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
4.
The LVD0ON bit in the OFS register is
set to 1 and hardw are reset : 1000X010b
Pow er-on reset, voltage monitor 0 reset
or LVD0ON bit in the OFS register is set
to 0, and hardw are reset : 1100X011b
After Reset(2)
Set the PRC3 bit in the PRCR register to 1 (w rite enabled) before rew riting to the VW0C register.
The value remains unchanged after a softw are reset, w atchdog timer reset, voltage monitor 1 reset, and voltage
monitor 2 reset.
VW0C6
Voltage monitor 0 circuit
mode select bit
When the VW0C0 bit is set to 1 (voltage monitor 0
reset enabled), set to 1. RW
—
(b3)
Reserved bit
The VW0C0 bit is enabled w hen the VCA25 bit in the VCA2 register is set to 1 (voltage detection 0 circuit enabled).
Set the VW0C0 bit to 0 (disable), w hen the VCA25 bit is set to 0 (voltage detection 0 circuit disabled).
To set VW0C0 bit to 1 (enable), follow the procedure show n in Table 6.2 Procedure for Setting Bits
Associated with Voltage Monitor 0 Reset.
VW0C7
Voltage monitor 0 reset
generation condition select
bit(4)
When the VW0C1 bit is set to 1 (digital filter
disabled mode), set to 1. RW
VW0F1 RW
Sampling clock select bits b5 b4
0 0 : fOCO-S divided by 1
0 1 : fOCO-S divided by 2
1 0 : fOCO-S divided by 4
1 1 : fOCO-S divided by 8
VW0F0 RW
When read, the content is undefined. RO
0 : Digital filter enabled mode
(digital filter circuit enabled)
1 : Digital filter disabled mode
(digital filter circuit disabled)
RW
VW0C2 Reserved bit
VW0C1
Voltage monitor 0 digital filter
disable mode select bit
VW0C0 RW
Voltage monitor 0 reset
enable bit(3)
0 : Disable
1 : Enable
0
b7 b6 b5 b4
The VW0C7 bit is enabled w hen the VW0C1 bit set to 1 (digital filter disabled mode).
b3 b2
Set to 0. RW
b1 b0
R8C/2G Group 6. Voltage Detection Circuit
Rev.1.00 Apr 04, 2008 Page 37 of 318
REJ09B0387-0100
Figure 6.7 VW1C Register
Voltage Monitor 1 Circuit Control Register (1)
Symbol Address After Reset(8)
VW1C 0036h 00001010b
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
4.
5.
6.
7.
8.
9. When the VW1C6 bit is set to 1 (voltage monitor 1 reset mode), set the VW1C7 bit to 1 (w hen VCC reaches Vdet1 or
below ). (Do not set to 0.)
Set the PRC3 bit in the PRCR register to 1 (w rite enabled) before rew riting to the VW1C register.
When the VW1C register is rew ritten, the VW1C2 bit may be set to 1. Set the VW1C2 bit to 0 after rew riting the
VW1C register.
To use the voltage monitor 1 interrupt to exit stop mode and to return again, w rite 0 to the VW1C1 bit before w riting
1.
Bits VW1C2 and VW1C3 are enabled w hen the VCA26 bit in the VCA2 register is set to 1 (voltage detection 1 circuit
enabled).
Set this bit to 0 by a program. When 0 is w ritten by a program, it is set to 0 (and remains unchanged even if 1 is
w ritten to it).
The VW1C6 bit is enabled w hen the VW1C0 bit is set to 1 (voltage monitor 1 interrupt/reset enabled).
The VW1C0 bit is enabled w hen the VCA26 bit in the VCA2 register is set to 1 (voltage detection 1 circuit enabled).
Set the VW1C0 bit to 0 (disable) w hen the VCA26 bit is set to 0 (voltage detection 1 circuit disabled).
To set VW1C0 bit to 1 (enable), follow the procedure show n in Table 6.3 Procedure for Setting Bits
Associated with Voltage Monitor 1 Interrupt and Reset.
The VW1C7 bit is enabled w hen the VCAC1 bit in the VCAC register is set to 0 (one edge). Set the VW1C7 bit after
setting the VCAC1 bit to 0.
Bits VW1C2 and VW1C3 remain unchanged af ter a softw are reset, w atchdog timer reset, voltage monitor 1 reset,
or voltage monitor 2 reset.
VW1C7 Voltage monitor 1 interrupt/reset
generation condition select bit(7, 9)
0 : When VCC reaches Vdet1 or above
1 : When VCC reaches Vdet1 or below RW
VW1C6 Voltage monitor 1 circuit mode
select bit(5)
0 : Voltage monitor 1 interrupt mode
1 : Voltage monitor 1 reset mode RW
VW1C3
Voltage detection 1 signal monitor
flag(3, 8)
VW1F1 RW
Sampling clock select bits b5 b4
0 0 : fOCO-S divided by 1
0 1 : fOCO-S divided by 2
1 0 : fOCO-S divided by 4
1 1 : fOCO-S divided by 8
VW1F0 RW
0 : VCC < Vdet1
1 : VCC ≥ Vdet1 or voltage detection 1
circuit disabled
RO
0 : Digital filter enabled mode
(digital filter circuit enabled)
1 : Digital filter disabled mode
(digital filter circuit disabled)
RW
VW1C2 Voltage change detection
flag(3, 4, 8)
VW1C1
Voltage monitor 1 digital filter
disable mode select bit(2)
VW1C0 RW
Voltage monitor 1 interrupt/reset
enable bit(6)
0 : Disable
1 : Enable
b7 b6 b5 b4 b2
0 : Not detected
1 : Vdet1 crossing detected RW
b1 b0b3
R8C/2G Group 6. Voltage Detection Circuit
Rev.1.00 Apr 04, 2008 Page 38 of 318
REJ09B0387-0100
Figure 6.8 VW2C Register
Volta
g
e Monitor 2 Circuit Control Re
g
iste
r
(1)
Symbol Address After Reset(8)
VW2C 0037h 00000010b
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
4.
5.
6.
7.
8.
9. When the VW2C6 bit is set to 1 (voltage monitor 2 reset mode), set the VW2C7 bit to 1 (w hen VCC reaches Vdet2
or below ). (Do not set to 0.)
Set the PRC3 bit in the PRCR register to 1 (w rite enabled) before rew riting to the VW2C register.
When the VW2C register is rew ritten, the VW2C2 bit may be set to 1. Set the VW2C2 bit to 0 after rew riting the
VW2C register.
To use the voltage monitor 2 interrupt to exit stop mode and to return again, w rite 0 to the VW2C1
bit before w riting 1.
The VW2C2 bit is enabled w hen the VCA27 bit in the VCA2 register is set to 1 (voltage detection 2 circuit
enabled).
Set this bit to 0 by a program. When 0 is w ritten by a program, it is set to 0 (and remains unchanged even if 1 is
w ritten to it).
The VW2C6 bit is enabled w hen the VW2C0 bit is set to 1 (voltage monitor 2 interrupt/reset enabled).
The VW2C0 bit is enabled w hen the VCA27 bit in the VCA2 register is set to 1 (voltage detection 2 circuit enabled).
Set the VW2C0 bit to 0 (disable) w hen the VCA27 bit is set to 0 (voltage detection 2 circuit disabled).
To set VW2C0 bit to 1 (enable), follow the procedure show n in Table 6.4 Procedure for S etting Bits
Associated with Voltage Monitor 2 Interrupt and Reset.
The VW2C7 bit is enabled w hen the VCAC2 bit in the VCAC register is set to 0 (one edge). Set the VW2C7 bit after
setting the VCAC2 bit to 0.
Bits VW2C2 and VW2C3 remain unchanged af ter a softw are reset, w atchdog timer reset, voltage monitor 1 reset,
or voltage monitor 2 reset.
VW2C7 Voltage monitor 2 interrupt/reset
generation condition select bit(7, 9)
0 : When VCC reaches Vdet2 or above
1 : When VCC reaches Vdet2 or below RW
VW2C6 Voltage monitor 2 circuit mode
select bit(5)
0 : Voltage monitor 2 interrupt mode
1 : Voltage monitor 2 reset mode RW
VW2C3 WDT detection flag(4, 8)
VW2F1 RW
Sampling clock select bits b5 b4
0 0 : fOCO-S divided by 1
0 1 : fOCO-S divided by 2
1 0 : fOCO-S divided by 4
1 1 : fOCO-S divided by 8
VW2F0 RW
0 : Not detected
1 : Detected RW
0 : Digital filter enabled mode
(digital filter circuit enabled)
1 : Digital filter disabled mode
(digital filter circuit disabled)
RW
VW2C2 Voltage change detection
flag(3, 4, 8)
VW2C1
Voltage monitor 2 digital filter
disable mode select bit(2)
VW2C0 RW
Voltage monitor 2 interrupt/reset
enable bit(6)
0 : Disable
1 : Enable
b7 b6 b5 b4 b3 b2
0 : Not detected
1 : Vdet2 crossing detected RW
b1 b0
R8C/2G Group 6. Voltage Detection Circuit
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Figure 6.9 VCAC Regist er
Figure 6.10 PINSR4 Register
Voltage Monitor Circuit Edge Select Register
Symbol Address After Reset
VCAC 003Dh 00h
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
b7 b6 b5 b4 b0b3 b2 b1
—
(b0) —
VCAC1 RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Voltage monitor 1 circuit edge
select bit(1)
0 : One edge
1 : Both edges
VCAC2 Voltage monitor 2 circuit edge
select bit(2)
0 : One edge
1 : Both edges RW
The VW2C7 bit in the VW2C register is enabled w hen the VCAC2 bit is set to 0 (one edge). Set the VW2C7 bit after
setting the VCAC2 bit to 0.
The VW1C7 bit in the VW1C register is enabled w hen the VCAC1 bit is set to 0 (one edge). Set the VW1C7 bit after
setting the VCAC1 bit to 0.
—
(b7-b3) —
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Pin Select Register 4
Symbol Address After Reset
PINSR4 02FBh 00h
Bit Symbol Bit Name Function RW
KI0
_
___
pin select bit
KI1
_
___
pin select bit
TREO pin select 2 bit
b0
0 : Voltage monitor 1, voltage monitor 2
1 : Comparator 1, comparator 2
b3 b2 b1b7 b6 b5 b4
RW
COMPSEL
TRFOSEL
000
TRFO11 pin select bit 0 : P3_4
1 : P3_7
Voltage monitor/comparator
select bit
RW
RW
RW
RW
RW
KI0SEL 0 : P1_0
1 : P0_7
—
(b6-b4)
TREOSEL2
Set to 0.Reserved bits
KI1SEL 0 : P1_1
1 : P6_6
0 : TREOSEL bit in PINSR3 register enabled
1 : P6_5
R8C/2G Group 6. Voltage Detection Circuit
Rev.1.00 Apr 04, 2008 Page 40 of 318
REJ09B0387-0100
6.1 VCC Input Voltage
6.1.1 Monitoring Vdet0
Vdet0 cannot be monitored.
6.1.2 Monitoring Vdet1
Set the VCA 26 bit in the VCA2 r egister to 1 (vol tage detection 1 circuit enabled ). After td(E-A ) has elapsed
(refer to 22. Electrical Characteristics), Vdet1 can be monitored by the VW1C3 bit in the VW 1C register.
6.1.3 Monitoring Vdet2
Set the VCA 27 bit in the VCA2 r egister to 1 (vol tage detection 2 circuit enabled ). After td(E-A ) has elapsed
(refer to 22. Electrical Characteristics), Vdet2 can be monitored by the VCA13 bit in the VCA 1 regi ster.
R8C/2G Group 6. Voltage Detection Circuit
Rev.1.00 Apr 04, 2008 Page 41 of 318
REJ09B0387-0100
6.2 Voltage Monitor 0 Reset
Ta ble 6.2 lists the Procedure for Setting Bits Associated with Volt age Monitor 0 Reset and Figure 6.11 shows an
Example of Voltage Monitor 0 Reset Operation. To use the voltage monitor 0 reset to exit stop mode, set the
VW0C1 bit in the VW0C reg ister to 1 (digital filter disabled).
NOTE:
1.
When the VW0C0 bit is set to 0, steps 3, 4, and 5 can be executed simultaneously (with 1 instruction).
Figure 6.11 Example of Voltage Monitor 0 Reset Operation
Table 6.2 Procedure for Setting Bits Associated with Voltage Monitor 0 Reset
Step When Using Digital Filter When Not Using Digital Filter
1 Set the VCA25 bit in the VCA2 register to 1 (voltage detection 0 circuit enabled)
2 Wait for td(E-A)
3
Select the sampling clock of the digital filter
by the VW0F0 to VW0F1 bits in the VW0C
register
Set the VW0C7 bit in the VW0C register to
1
4(1) Set the VW0C1 bit in the VW0C register to
0 (digital filter enabled)
Set the VW0C1 bit in the VW0C register to
1 (digital filter disabled)
5(1) Set the VW0C6 bit in the VW0C register to 1 (voltage monitor 0 reset mode)
6 Set the VW0C2 bit in the VW0C register to 0
7 Set the CM14 bit in the CM1 register to 0
(low-speed on-chip oscillator on)
−
8 Wait for 4 cycles of the sampling clock of
the digital filter
− (No wait time required)
9 Set the VW0C0 bit in the VW0C register to 1 (voltage monitor 0 reset enabled)
Vdet0
Internal reset signal
VCC
The above applies under the following conditions.
• VCA25 bit in VCA2 register = 1 (voltage detection 0 circuit enabled)
• VW0C0 bit in VW0C register = 1 (voltage monitor 0 reset enabled)
• VW0C6 bit in VW0C register = 1 (voltage monitor 0 reset mode)
When the internal reset signal is held “L”, the pins, CPU and SFR are reset.
The internal reset signal level changes from “L” to “H”, and a program is executed beginning with the address indicated by
the reset vector.
Refer to 4. Special Function Registers (SFRs) for the SFR status after reset.
1
fOCO-S × 32
Sampling clock of
digital filter × 4 cycles
When the VW0C1 bit is set
to 0 (digital filter enabled)
Internal reset signal
When the VW0C1 bit is set
to 1 (digital filter disabled)
and the VW0C7 bit is set
to 1
1
fOCO-S × 32
VW0C1 and VW0C7: Bits in VW0C register
R8C/2G Group 6. Voltage Detection Circuit
Rev.1.00 Apr 04, 2008 Page 42 of 318
REJ09B0387-0100
6.3 Voltage Monitor 1 Interrupt and Voltage Monitor 1 Reset
Table 6.3 lists the Procedure for Setting Bits Associated with Voltage Monitor 1 Interrupt and Reset. Figure 6.12
shows an Example of Voltage Monitor 1 Interrupt an d Voltage Monitor 1 Reset Operation. To use the voltage
monitor 1 interrupt or voltage monitor 1 reset to exit stop mode, set the VW1C1 bit in the VW1C register to 1
(digital filter disabled).
NOTES:
1. Set the VW1C7 bit to 1 (when VCC reaches Vdet1 or below) for the voltage monitor 1 reset.
2. When the VW1C0 bit is set to 0, steps 4 and 5 can be executed simultaneously (with 1 instruction).
Table 6.3 Procedure for Setting Bits Associated with Voltage Monitor 1 Interrupt and Reset
Step
When Using Digital Filter When Not Using Digital Filter
Voltage Monitor 1
Interrupt
Voltage Monitor 1
Reset
Voltage Monitor 1
Interrupt
Voltage Monitor 1
Reset
1 Set the COMPSEL bit in the PINSR4 register to 0 (voltage monitor 1, voltage monitor 2)
2 Set the VCA26 bit in the VCA2 register to 1 (voltage detection 1 circuit enabled)
3 Wait for td(E-A)
4
Select the sampling clock of the digital filter
by the VW1F0 to VW1F1 bits in the VW1C
register
Set the VW1C1 bit in the VW1C register to 1
(digital filter disabled)
5(2) Set the VW1C1 bit in the VW1C register to 0
(digital filter enabled)
−
6
Select the timing of the interrupt and reset
request by the VCAC1 bit in the VCAC
register and the VW1C7 bit in the VW1C
register(1)
Select the timing of the interrupt and reset
request by the VCAC1 bit in the VCAC
register and the VW1C7 bit in the VW1C
register(1)
7
Set the VW1C6 bit in
the VW1C register to
0 (voltage monitor 1
interrupt mode)
Set the VW1C6 bit in
the VW1C register to
1 (voltage monitor 1
reset mode)
Set the VW1C6 bit in
the VW1C register to
0 (voltage monitor 1
interrupt mode)
Set the VW1C6 bit in
the VW1C register to
1 (voltage monitor 1
reset mode)
8 Set the VW1C2 bit in the VW1C register to 0 (Vdet1 crossing is not detected)
9Set the CM14 bit in the CM1 register to 0
(low-speed on-chip oscillator on)
−
10 Wait for 2 cycles of the sampling clock of the
digital filter
− (No wait time required)
11 Set the VW1C0 bit in the VW1C register to 1 (voltage monitor 1 interrupt/reset enabled)
R8C/2G Group 6. Voltage Detection Circuit
Rev.1.00 Apr 04, 2008 Page 43 of 318
REJ09B0387-0100
Figure 6.12 Example of Voltage Monitor 1 Interrupt and Voltage Monitor 1 Reset Operation
Vdet1
VW1C3 bit
Internal reset signal
(VW1C6 = 1)
VCC
2.2 V(1)
2 cycles of sampling clock of
digital filter
VW1C2 bit
VW1C2 bit
When the VW1C1 bit is set to 1
(digital filter disabled), and the
VCAC1 bit is set to 0 (one edge),
and the VW1C7 bit is set to 0
(when VCC reaches Vdet1 or
above)
Set to 0 by interrupt request
acknowledgement
2 cycles of sampling clock of
digital filter
Set to 0 by a program
Voltage monitor 1
interrupt request
(VW1C6 = 0)
Voltage monitor 1
interrupt request
(VW1C6 = 0)
Set to 0 by interrupt request
acknowledgement
VW1C2 bit
Voltage monitor 1
interrupt request
(VW1C6 = 0)
Internal reset signal
(VW1C6 = 1)
When the VW1C1 bit is set to 0
(digital filter enabled) and the
VCAC1 bit is set to 1 (both edges)
VW1C2 bit
Set to 0 by interrupt request
acknowledgement
Set to 0 by a program
Voltage monitor 1
interrupt request
(VW1C6 = 0)
When the VW1C1 bit is set to 0
(digital filter enabled), and the
VCAC1 bit is set to 0 (one edge),
and the VW1C7 bit is set to 0
(when VCC reaches Vdet1 or
above)
Internal reset signal
(VW1C6 = 1)
VW1C2 bit
Set to 0 by interrupt request
acknowledgement
Voltage monitor 1
interrupt request
(VW1C6 = 0)
When the VW1C1 bit is set to 0
(digital filter enabled), and the
VCAC1 bit is set to 0 (one edge),
and the VW1C7 bit is set to 1
(when VCC reaches Vdet1 or
below)
Set to 0 by a program
Internal reset signal
(VW1C6 = 1)
VW1C2 bit
Voltage monitor 1
interrupt request
(VW1C6 = 0)
When the VW1C1 bit is set to 1
(digital filter disabled) and the
VCAC1 bit is set to 1 (both edges)
Set to 0 by a program
Set to 0 by interrupt request
acknowledgement
Set to 0 by a program
Set to 0 by interrupt request
acknowledgement
Set to 0 by a program
When the VW1C1 bit is set to 1
(digital filter disabled), and the
VCAC1 bit is set to 0 (one edge),
and the VW1C7 bit is set to 1
(when VCC reaches Vdet1 or
below)
The above applies under the following conditions.
• VCA26 bit in VCA2 register = 1 (voltage detection 1 circuit enabled)
• VW1C0 bit in VW1C register = 1 (voltage monitor 1 interrupt and voltage monitor 1 reset enabled)
NOTE:
1. If voltage monitor 0 reset is not used, set the power supply to VCC ≥ 2.2.
VW1C1, VW1C2, VW1C3, VW1C6, VW1C7: Bits in VW1C register
VCAC1: Bit in VCAC register
0
1
0
1
0
1
0
1
0
1
0
1
0
1
R8C/2G Group 6. Voltage Detection Circuit
Rev.1.00 Apr 04, 2008 Page 44 of 318
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6.4 Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset
Table 6.4 lists the Procedure for Setting Bits Associated with Voltage Monitor 2 Interrupt and Reset. Figure 6.13
shows an Example of Voltage Monitor 2 Interrupt an d Voltage Monitor 2 Reset Operation. To use the voltage
monitor 2 interrupt or voltage monitor 2 reset to exit stop mode, set the VW2C1 bit in the VW2C register to 1
(digital filter disabled).
NOTES:
1. Set the VW2C7 bit to 1 (when VCC reaches Vdet2 or below) for the voltage monitor 2 reset.
2. When the VW2C0 bit is set to 0, steps 4 and 5 can be executed simultaneously (with 1 instruction).
Table 6.4 Procedure for Setting Bits Associated with Voltage Monitor 2 Interrupt and Reset
Step
When Using Digital Filter When Not Using Digital Filter
Voltage Monitor 2
Interrupt
Voltage Monitor 2
Reset
Voltage Monitor 2
Interrupt
Voltage Monitor 2
Reset
1 Set the COMPSEL bit in the PINSR4 register to 0 (voltage monitor 1, voltage monitor 2)
2 Set the VCA27 bit in the VCA2 register to 1 (voltage detection 2 circuit enabled)
3 Wait for td(E-A)
4
Select the sampling clock of the digital filter
by the VW2F0 to VW2F1 bits in the VW2C
register
Set the VW2C1 bit in the VW2C register to 1
(digital filter disabled)
5(2) Set the VW2C1 bit in the VW2C register to 0
(digital filter enabled)
−
6 Select the timing of the interrupt and reset
request by the VCAC2 bit in the VCAC
register and the VW2C7 bit in the VW2C
register(1)
Select the timing of the interrupt and reset
request by the VCAC2 bit in the VCAC
register and the VW2C7 bit in the VW2C
register(1)
7Set the VW2C6 bit in
the VW2C register to
0 (voltage monitor 2
interrupt mode)
Set the VW2C6 bit in
the VW2C register to
1 (voltage monitor 2
reset mode)
Set the VW2C6 bit in
the VW2C register to
0 (voltage monitor 2
interrupt mode)
Set the VW2C6 bit in
the VW2C register to
1 (voltage monitor 2
reset mode)
8 Set the VW2C2 bit in the VW2C register to 0 (Vdet2 crossing is not detected)
9Set the CM14 bit in the CM1 register to 0
(low-speed on-chip oscillator on)
−
10 Wait for 2 cycles of the sampling clock of the
digital filter
− (No wait time required)
11 Set the VW2C0 bit in the VW2C register to 1 (voltage monitor 2 interrupt/reset enabled)
R8C/2G Group 6. Voltage Detection Circuit
Rev.1.00 Apr 04, 2008 Page 45 of 318
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Figure 6.13 Example of Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset Operation
Vdet2
VCA13 bit
Internal reset signal
(VW2C6 = 1)
VCC
2.2 V(1)
2 cycles of sampling clock of
digital filter
VW2C2 bit
VW2C2 bit
When the VW2C1 bit is set to 1
(digital filter disabled), and the
VCAC2 bit is set to 0 (one edge),
and the VW2C7 bit is set to 0
(when VCC reaches Vdet2 or
above)
Set to 0 by interrupt request
acknowledgement
2 cycles of sampling clock of
digital filter
Set to 0 by a program
Voltage monitor 2
interrupt request
(VW2C6 = 0)
Voltage monitor 2
interrupt request
(VW2C6 = 0)
Set to 0 by interrupt request
acknowledgement
VW2C2 bit
Voltage monitor 2
interrupt request
(VW2C6 = 0)
Internal reset signal
(VW2C6 = 1)
When the VW2C1 bit is set to 0
(digital filter enabled) and the
VCAC2 bit is set to 1 (both edges)
VW2C2 bit
Set to 0 by interrupt request
acknowledgement
Set to 0 by a program
Voltage monitor 2
interrupt request
(VW2C6 = 0)
When the VW2C1 bit is set to 0
(digital filter enabled), and the
VCAC2 bit is set to 0 (one edge),
and the VW2C7 bit is set to 0 (when
VCC reaches Vdet2 or above)
Internal reset signal
(VW2C6 = 1)
VW2C2 bit
Set to 0 by interrupt request
acknowledgement
Voltage monitor 2
interrupt request
(VW2C6 = 0)
When the VW2C1 bit is set to 0
(digital filter enabled), and the
VCAC2 bit is set to 0 (one edge),
and the VW2C7 bit is set to 1
(when VCC reaches Vdet2 or
below)
Set to 0 by a program
Internal reset signal
(VW2C6 = 1)
VW2C2 bit
Voltage monitor 2
interrupt request
(VW2C6 = 0)
When the VW2C1 bit is set to 1
(digital filter disabled) and the
VCAC2 bit is set to 1 (both edges)
Set to 0 by a program
Set to 0 by interrupt request
acknowledgement
Set to 0 by a program
Set to 0 by interrupt request
acknowledgement
Set to 0 by a program
When the VW2C1 bit is set to 1
(digital filter disabled), and the
VCAC2 bit is set to 0 (one edge),
and the VW2C7 bit is set to 1
(when VCC reaches Vdet2 or
below)
The above applies under the following conditions.
• VCA27 bit in VCA2 register = 1 (voltage detection 2 circuit enabled)
• VW2C0 bit in VW2C register = 1 (voltage monitor 2 interrupt and voltage monitor 2 reset enabled)
NOTE:
1. When voltage monitor 0 reset is not used, set the power supply to VCC ≥ 2.2.
VCA13: Bit in VCA1 register
VW2C1, VW2C2, VW2C6, VW2C7: Bits in VW2C register
VCAC2: Bit in VCAC register
0
1
0
1
0
1
0
1
0
1
0
1
0
1
R8C/2G Group 7. Comparator
Rev.1.00 Apr 04, 2008 Page 46 of 318
REJ09B0387-0100
7. Comparator
The comparators compare a reference input voltage and an analog input voltage. Comparator 1 and comparator 2 are
independent of each other. Not e that comparator 1 and comparator 2 share the voltage detection circuit with vol tage
monitor 1 and voltage monitor 2. Either comparator 1 and comparator 2 or voltage monitor 1 and voltage monitor 2 can
be selected to use the voltage detection circuit.
7.1 Overview
The comparison result of the reference input voltage and analog input voltage can be read by software. The result
also can be output from the VCOUTi (i = 1 or 2) pin. An internal reference voltage or input voltage to the CVREF
pin can be selected as the reference input voltage. The comparator 1 interrupt and comparator 2 interrupt also can
be used.
Table 7.1 lists the Specifications of Comparator, Figure 7.1 shows the Block Diagram of Comparator, and Table 7.2
lists the Pin Configuration of Comparato r.
Table 7.1 Specifications of Comparator
Item Comparator 1 Comparator 2
Analog input voltage Input voltage to VCMP1 pin Input voltage to VCMP2 pin
Reference input voltage Internal reference voltage or input voltage to CVREF pin
Comparison target Whether passing thorough reference input voltage by rising or falling
Comparison result monitor VW1C3 bit in VW1C register VCA13 bit in VCA1 register
Whether higher or lower than reference input voltage
Interrupt Comparator 1 interrupt (non-makable or
maskable selectable)
Comparator 2 interrupt (non-makable or
maskable selectable)
Interrupt request at both or either of
reference input voltage > input voltage to
VCMP1 pin and input voltage to VCMP1
pin > reference input voltage
Interrupt request at both or either of
reference input voltage > input voltage to
VCMP2 pin and input voltage to VCMP2
pin > reference input voltage
Digital
Filter
Switch
enabled/disabled
Available
Sampling time (fOCO-S divided by n) × 2
n: 1, 2, 4, 8
Comparison result output Output from VCOUT1 pin (Whether the
comparison result output is inverted or not
can be selected)
Output from VCOUT2 pin (Whether the
comparison result output is inverted or not
can be selected)
R8C/2G Group 7. Comparator
Rev.1.00 Apr 04, 2008 Page 47 of 318
REJ09B0387-0100
Figure 7.1 Block Diagram of Comparator
Table 7.2 Pin Configuration of Comparator
Pin Name I/O Function
VCMP1 Input Comparator 1 analog pin
VCOUT1 Output Comparator 1 comparison result output pin
VCMP2 Input Comparator 2 analog pin
VCOUT2 Output Comparator 2 comparison result output pin
CVREF Input Comparator reference voltage pin
+
-
VW1F1 to VW1F0
= 01b
= 10b
= 11b
VCA13: Bit in VCA1 register
VCA26, VCA27: Bits in VCA2 register
VW1C0 to VW1C3, VW1F0 to VW1F1: Bits in VW1C register
VW2C0, VW2C2, VW2F0 to VW2F1: Bits in VW2C register
VCAB5 to VCAB7: Bits in VCAB register
LCM1POR, LCM2POR, CM1OE, CM2OE, IRQ1SEL, IRQ2SEL: Bits in ALCMR register
fOCO-S
fOCO-S/4
fOCO-S/8
VCMP1
0
1
VCAB5
Digital filter
+
-
CVREF
VCMP2
0
1
VCAB6
VCAB7
= 00b Sampling
clock
1
0
VCA26
VW1C3
fOCO-S/2
VW1C1
0
1
VW2F1 to VW2F0
= 01b
= 10b
= 11b
fOCO-S
fOCO-S/4
fOCO-S/8
Digital filter
= 00b Sampling
clock
VCA13
fOCO-S/2
VW2C1
0
1
Internal reference voltage
VCA27
Shared with
voltage monitor 1
circuit
Shared with
voltage monitor 2
circuit
VW1C2
IRQ1SEL
maskable
interrupts
VW1C0
Edge
selection
circuit
non-maskable
interrupts
Pin output
selection circuit
VCOUT1
VCOUT2
LCM1POR
LCM2POR
0
1
CM1OE
0
1
CM2OE
VW2C2
IRQ2SEL
maskable
interrupts
VW2C0
non-maskable
interrupts
Edge
selection
circuit
R8C/2G Group 7. Comparator
Rev.1.00 Apr 04, 2008 Page 48 of 318
REJ09B0387-0100
7.2 Register Description
Figures 7.2 to 7.11 show the registers associated with the comparator when comparator 1 or comparator 2 is selected.
Figure 7.2 Registe rs BGRTRMA and BGRTRMB
BGR Trimming Auxiliary Register A
Symbol Address After Reset
BGRTRMA 002Eh When Shipping
RW
RO
Function
Stores data for internal reference voltage (Vref) correction w hen VCC = 3.6 to 5.5 V. (The
value is the same as that of the BGRTRM register after a reset).
Optimal correction to match the voltage conditions can be achieved by transf erring this value
to the BGRTRM register.
b3 b2 b1 b0b7 b6 b5 b4
BGR Trimming Auxiliary Register B
Symbol Address After Reset
BGRTRMB 002Fh When Shipping
RW
RO
Function
Stores data for internal reference voltage (Vref) correction w hen VCC = 2.2 to 3.6 V.
Optimal correction to match the voltage conditions can be achieved by transferring this value
to the BGRTRM register.
b3 b2 b1 b0b7 b6 b5 b4
R8C/2G Group 7. Comparator
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REJ09B0387-0100
Figure 7.3 Registers VCA1 an d VCA2
Voltage Detection Register 1
Symbol Address After Reset(2)
VCA1 0031h 00001000b
Bit Symbol Bit Name Function RW
NOTES:
1.
2. Softw are reset and w atchdog timer reset do not affect this register.
VCA13
Comparator 2 signal monitor flag(1)
00
—
(b2-b0) RW
0: VCMP2 < reference voltage
1: VCMP2 ≥ ref erence voltage or
comparator 2 circuit disabled
RO
Reserved bits
b0
0000
Set to 0.
0
b7 b6 b5 b4 b3 b2 b1
The VCA13 bit is enabled w hen the VCA27 bit in the VCA2 register is set to 1 (comparator 2 circuit enabled). The
VCA13 bit is set to 1 (VCMP2 ≥ ref erence voltage) w hen the VCA27 bit in the VCA2 register is set to 0 (comparator
2 circuit disabled).
—
(b7-b4)
Reserved bits Set to 0. RW
Voltage Detection Register 2(1)
Symbol Address After Reset(2)
VCA2 0032h
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
4.
5.
6.
7.
The LVD0ON bit in the OFS register is
set to 1 and hardw are reset : 00h
Pow er-on reset, voltage monitor 0 reset
or the LVD0ON bit in the OFS register is
set to 0, and hardw are reset : 00100000b
VCA25 Voltage detection 0 enable
bit(4)
0: Voltage detection 0 circuit disabled
1: Voltage detection 0 circuit enabled RW
—
(b4-b1)
Reserved bits Set to 0. RW
b7 b6 b5 b4 b3 b2 b1 b0
0000
Use the VCA20 bit only w hen the MCU enters w ait mode. To set the VCA20 bit, follow the procedure show n in
Figure 11 .9 Handling Procedure of Internal Power Low Consumption Using VCA20 Bit.
VCA26 Comparator 1 enable bit(5) 0: Comparator 1 circuit disabled
1: Comparator 1 circuit enabled RW
Comparator 2 enable bit(6) 0: Comparator 2 circuit disabled
1: Comparator 2 circuit enabled RW
Softw are reset and w atchdog timer reset do not affect this register.
When the VCA20 bit is set to 1 (low consumption enabled), do not set the CM10 bit in the CM1 register to 1 (stop
mode).
VCA20 Internal pow er low
consumption enable bit(3)
0: Low consumption disabled
1: Low consumption enabled(7) RW
Set the PRC3 bit in the PRCR register to 1 (w rite enabled) before rew riting the VCA2 register.
To use the comparator 1 interrupt or the VW1C3 bit in the VW1C register, set the VCA26 bit to 1.
After the VCA26 bit is set to 1 from 0, the comparator 1 circuit w aits for td(E-A) to elapse before starting operation.
To use the comparator 2 interrupt or the VCA13 bit in the VCA1 register, set the VCA27 bit to 1.
After the VCA27 bit is set to 1 from 0, the comparator 2 circuit w aits for td(E-A) to elapse before starting operation.
To use the voltage monitor 0 reset, set the VCA25 bit to 1.
After the VCA25 bit is set to 1 from 0, the voltage detection circuit w aits for td(E-A) to elapse before starting
operation.
VCA27
R8C/2G Group 7. Comparator
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REJ09B0387-0100
Figure 7.4 VW1C Register
Voltage Monitor 1 Circuit Control Register (1)
Symbol Address Af ter Reset(2)
VW1C 0036h 00001010b
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
4.
5.
6.
7.
b2
[Source for setting this bit to 0]
0: Write 0
[Source for setting this bit to 0]
1: When interrupt request is generated
RW
b1 b0b3b7 b6 b5 b4
0
VW1C0 RW
Comparator 1 interrupt enable bit(3) 0: Disable
1: Enable
0: Digital filter enable mode
(digital filter circuit enabled)
1: Digital filter disable mode
(digital filter circuit disabled)
RW
VW1C2
Comparator 1 interrupt
flag(2, 5, 6)
VW1C1
Comparator 1 digital filter disable
mode select bit(4)
VW1C3
Comparator 1 signal monitor
flag(2, 5)
VW1F1 RW
Sampling clock select bits b5 b4
0 0: fOCO-S divided by 1
0 1: fOCO-S divided by 2
1 0: fOCO-S divided by 4
1 1: fOCO-S divided by 8
VW1F0 RW
0: VCMP1 < reference voltage
1: VCMP1 ≥ reference voltage or
comparator 1 circuit disabled
RO
VW1C6 Reserved bit Set to 0. RW
VW1C7
Comparator 1 interrupt generation
condition select bit(7)
0: When VCMP1 reaches reference
voltage or above
1: When VCMP1 reaches reference
voltage or below
RW
Bits VW1C2 and VW1C3 are enabled w hen the VCA26 bit in the VCA2 register is set to 1 (comparator 1 circuit
enabled).
Set this bit to 0 by a program. When 0 is w ritten by a program, it is set to 0 (and remains unchanged even if 1 is
w ritten to it).
The VW1C7 bit is enabled w hen the VCAC1 bit in the VCAC register is set to 0 (one edge). Set the VW1C7 bit after
setting the VCAC1 bit to 0.
Set the PRC3 bit in the PRCR register to 1 (w rite enabled) before rew riting the VW1C register.
When the VW1C register is rew ritten, the VW1C2 bit may be set to 1. Set the VW1C2 bit to 0 after rew riting the
VW1C register.
Bits VW1C2 and VW1C3 remain unchanged after a softw are reset or w atchdog timer reset.
The VW1C0 is enabled w hen the VCA26 bit in the VCA2 register is set to 1 (comparator 1 circuit enabled).
When the VCA26 bit is set to 0 (comparator 1 circuit disabled), set the VW1C0 bit to 0 (disable).
To set the VW1C0 bit to 1 (enable), follow the procedure show n in Table 7 .3 Procedure for Setting Bi ts
Associated with Comparator 1 Interrupt.
To use the comparator 1 interrupt to exit stop mode and to return again, w rite 1 to the VW1C1 bit after w riting 0.
R8C/2G Group 7. Comparator
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Figure 7.5 VW2C Register
Voltage Monitor 2 Circuit Control Register (1)
Symbol Address After Reset(2)
VW2C 0037h 00000010b
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
4.
5.
6.
7.
b3 b2
[Source for setting this bit to 0]
0: Write 0
[Source for setting this bit to 0]
1: When interrupt request is generated
RW
b1 b0b7 b6 b5 b4
0
VW2C0 RW
Comparator 2 interrupt enable bit(3) 0: Disable
1: Enable
0: Digital filter enabled mode
(digital filter circuit enabled)
1: Digital filter disabled mode
(digital filter circuit disabled)
RW
VW2C2
Comparator 2 interrupt
flag(2, 5, 6)
VW2C1
Comparator 2 digital filter disable
mode select bit(4)
VW2C3 WDT detection flag(2, 6)
VW2F1 RW
Sampling clock select bits b5 b4
0 0: fOCO-S divided by 1
0 1: fOCO-S divided by 2
1 0: fOCO-S divided by 4
1 1: fOCO-S divided by 8
VW2F0 RW
0: Not detected
1: Detected RW
VW2C6 Reserved bit Set to 0. RW
VW2C7
Comparator 2 interrupt generation
condition select bit(7)
0: When VCMP2 reaches reference
voltage or above
1: When VCMP2 reaches reference
voltage or below
RW
The VW2C2 is enabled w hen the VCA27 bit in the VCA2 register is set to 1 (comparator 2 circuit enabled).
Set this bit to 0 by a program. When 0 is w ritten by a program, it is set to 0 (and remains unchanged even if 1 is
w ritten to it).
The VW2C7 bit is enabled w hen the VCAC2 bit in the VCAC register is set to 0 (one edge). Set the VW2C7 bit after
setting the VCAC2 bit to 0.
Set the PRC3 bit in the PRCR register to 1 (w rite enabled) before rew riting the VW2C register.
When the VW2C register is rew ritten, the VW2C2 bit may be set to 1. Set the VW2C2 bit to 0 after rew riting the
VW2C register.
Bits VW2C2 and VW2C3 remain unchanged after a softw are reset or w atchdog timer reset.
The VW2C0 bit is enabled w hen the VCA27 bit in the VCA2 register is set to 1 (comparator 2 circuit enabled). Set
the VW2C0 bit to 0 (disable) w hen the VCA27 bit is set to 0 (comparator 2 circuit disabled).
To set the VW2C0 bit to 1 (enable), follow the procedure show n in Table 7.4 P roc edure for Setting Bits
Associated with Comparator 2 Interrupt.
To use the comparator 2 interrupt to exit stop mode and to return again, w rite 1 to the VW2C1 bit after w riting 0.
R8C/2G Group 7. Comparator
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Figure 7.6 VCAB Regist er
Figure 7.7 ALCMR Register
Voltage Detection Circuit External Input Control Register(1)
Symbol Address Af ter Reset
VCAB 003Bh 00h
Bit Symbol Bit Name Function RW
NOTE:
1.
—
(b4-b0)
Reserved bits Set to 0. RW
b0
0
0: Supply voltage (VCC)
1: VCMP1 pin input voltage
b3 b2
0
b1
00
VCAB5
b7 b6 b5 b4
0
VCMP1 comparison voltage external
input select bit
RW
RW
0: Internal reference voltage
1: CVREF pin input voltage RW
Set the PRC3 bit in the PRCR register to 1 (w rite enabled) before rew riting the VCAB register.
Comparator circuit reference voltage
select bit
VCAB6 VCMP2 comparison voltage external
input select bit
0: Supply voltage (VCC)
1: VCMP2 pin input voltage
VCAB7
Comparator Mode Registe
r
Symbol Address After Reset
ALCMR 003Ch 00h
Bit Symbol Bit Name Function RW
b3 b2
LCM2POR
b0
LCM1POR
b1b7 b6 b5 b4
VCOUT2 output polarity select
bit
RW
VCOUT1 output polarity select
bit
0: Non-inverted comparator 1 comparison
result is output to VCOUT1
1: Inverted comparator 1 comparison
result is output to VCOUT1
RW
0: Non-inverted comparator 2 comparison
result is output to VCOUT2
1: Inverted comparator 2 comparison
result is output to VCOUT2
0: Non-maskable interrupt
1: Maskable interrupt
Comparator 1 interrupt type
select bit
VCOUT2 output enable bit 0: Output disabled
1: Output enabled
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
—
(b7-b6) —
RW
IRQ1SEL
CM1OE VCOUT1 output enable bit 0: Output disabled
1: Output enabled RW
CM2OE RW
IRQ2SEL Comparator 2 interrupt type
select bit
0: Non-maskable interrupt
1: Maskable interrupt RW
R8C/2G Group 7. Comparator
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Figure 7.8 VCAC Regist er
Figure 7.9 BGRCR Register
Voltage Monitor Circuit Edge Select Register
Symbol Address After Reset
VCAC 003Dh 00h
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
b7 b6 b5 b4 b0b3 b2 b1
—
(b0) —
VCAC1 RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Comparator 1 circuit edge select
bit(1)
0: One edge
1: Both edges
VCAC2 Comparator 2 circuit edge select
bit(2)
0: One edge
1: Both edges RW
The VW2C7 bit in the VW2C register is enabled w hen the VCAC2 bit is set to 0 (one edge). Set the VW2C7 bit after
setting the VCAC2 bit to 0.
The VW1C7 bit in the VW1C register is enabled w hen the VCAC1 bit is set to 0 (one edge). Set the VW1C7 bit after
setting the VCAC1 bit to 0.
—
(b7-b3) —
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
BGR Control Register(1)
Symbol Address After Reset
BGRCR 003Eh 00h
Bit Symbol Bit Name Function RW
NOTES:
1.
2. When the BGRCR0 bit is set to 1 (disabled), the accuracy/precision of the follow ing is not guaranteed:
• Internal reference voltage for comparator 1 and comparator 2
• Detection voltage for voltage detection circuit 0 to voltage detection circuit 2
• Oscillation f requency of the high-speed on-chip oscillator
Use these functions w hile the BGRCR0 bit is set to 0 (enabled).
To set the BGRCR0 bit to 1 (disabled), first disable voltage detection circuits 0 to 2 and disable comparators 1 and 2
w ith the internal reference voltage selected. Also stop the high-speed on-chip oscillator. Then set the BGRCR0 bit to
1 (disabled).
Set the PRC3 bit in the PRCR register to 1 (w rite enabled) before rew riting the BGRCR register.
—
(b7-b1) RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
BGRCR0 RW
Internal reference voltage (Vref)
adjustment circuit (BGR trimming
circuit) enable bit(2)
0: Enabled
1: Disabled
b0b3 b2 b1b7 b6 b5 b4
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Figure 7.10 BGRTRM Reg i st er
Figure 7.11 PINSR4 Register
BGR Trimming Register(1)
Symbol Address After Reset
BGRTRM 003Fh When Shipping
RW
NOTE:
1. Set the PRC3 bit in the PRCR register to 1 (w rite enabled) before rew riting the BGRTRM register.
RW
Function
Bits 0 to 7 can be used to adjust the level of the internal reference voltage (Vref ).
Write either of the follow ing values into the BGRTRM register.
• Value stored in the BGRTRMA register
• Value stored in the BGRTRMB register
• 15h
Do not w rite values other than the above into the BGRTRM register.
Follow the procedure show n in Figure 7.16 for w riting data to the BGRTRM register.
b3 b2 b1 b0b7 b6 b5 b4
Pin Select Register 4
Symbol Address After Reset
PINSR4 02FBh 00h
Bit Symbol Bit Name Function RW
KI0
_
___
pin select bit
KI1
_
___
pin select bit
TREO pin select 2 bit
b0
0 : Voltage monitor 1, voltage monitor 2
1 : Comparator 1, comparator 2
b3 b2 b1b7 b6 b5 b4
RW
COMPSEL
TRFOSEL
000
TRFO11 pin select bit 0 : P3_4
1 : P3_7
Voltage monitor/comparator
select bit
RW
RW
RW
RW
RW
KI0SEL 0 : P1_0
1 : P0_7
—
(b6-b4)
TREOSEL2
Set to 0.Reserved bits
KI1SEL 0 : P1_1
1 : P6_6
0 : TREOSEL bit in PINSR3 register enabled
1 : P6_5
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7.3 Monitoring Comparison Results
7.3.1 Monitoring Comparator 1
After the following setting s are made, the com parison result of comparat or 1 can be moni tored by the VW1C3
bit in the VW1C register after td(E-A) has elapsed (refer to 22. Electrical Characteristics).
(1) Set the COMPSEL bit in the PINSR4 register is set to 1 (comparator 1, comparator 2).
(2) Set the VCAB5 bit in the VCAB register to 1 (VCMP1 pin input voltage).
(3) Set the VCA26 bit in the VCA2 register to 1 (co mparator 1 circuit enabled).
7.3.2 Monitoring Comparator 2
After the following settings are made, the comparison result of comparator 2 can be monitored by the VCA13
bit in the VCA1 register after td(E-A) has elapsed (refer to 22. Electrical Characteristics).
(1) Set the COMPSEL bit in the PINSR4 register to 1 (comparator 1, comparator 2).
(2) Set the VCAB6 bit in the VCAB register to 1 (VCMP2 pin input voltage).
(3) Set the VCA27 bit in the VCA2 register to 1 (co mparator 2 circuit enabled).
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7.4 Functional Description
Comparator 1 and comparat or 2 operate independently.
The comparison result of the reference input voltage and analog input voltage can be read by software. The result
can also be output from the VCOUTi (i = 1 or 2) pin. An internal reference voltage or input voltage to the CVREF
pin can be selected as the reference input volta ge. The co mparator 1 interrupt or the comparator 2 interrupt also can
be used by selecting non-maskable or maskable for each interrupt.
7.4.1 Comparator 1
Table 7.3 lists the Procedure for Setting Bits Associated with Comparator 1 Interrupt, Figure 7.12 shows an
Operating Example of Comparator 1 (When Digital Filter Enabled), and Figure 7.13 shows an Operating
Example of Comparator 1 (When Digital Filter Disabled).
NOTE:
1.
When the VW1C0 bit is set to 0, steps 6 and 7 can be executed at the same time (with one instruction)
Table 7.3 Procedure for Setting Bits Associated with Comparator 1 Interrupt
Step When Using Digital Filter When Not Using Digital Filter
1 Set the COMPSEL bit in the PINSR4 register to 1 (comparator 1, comparator 2)
2 Set the VCAB5 bit in the VCAB register to 1 (VCMP1 pin input voltage)
3 Set the VCA26 bit in the VCA2 register to 1 (comparator 1 circuit enabled)
4 Wait for td(E-A)
5 Select the interrupt type by the IRQ1SEL bit in the ALCMR register
6 Select the sampling clock by bits VW1F0
and VW1F1 in the VW1C register
Set the VW1C1 bit in the VW1C register to 1 (digital
filter disabled)
7(1) Set the VW1C1 bit in the VW1C register
to 0 (digital filter enabled)
−
8 Select the interrupt request timing by the VCAC1 bit in the VCAC register and the VW1C7 bit in
the VW1C register
9 Set the VW1C2 bit in the VW1C register to 0
10 Set the CM14 bit in the CM1 register to 0
(low-speed on-chip oscillator on)
−
11 Wait for 2 cycles of the sampling clock of
the digital filter.
− (No wait time required)
12 Set the VW1C0 bit in the VW1C register to 1 (comparator 1 interrupt enabled)
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Figure 7.12 Operating Example of Comparator 1 (When Digital Filter Enabled)
Reference voltage
VW1C3 bit
VCOUT1 output
(LCM1POR = 0)
VCMP1
The above applies under the following conditions.
• VCA26 bit in VCA2 register = 1 (comparator 1 circuit enabled)
• VW1C0 bit in VW1C register = 1 (comparator 1 interrupt enabled)
• CM1OE bit in ALCMR register = 1 (output enabled)
• VCAB5 bit in VCAB register = 1 (VCMP1 pin input)
• COMPSEL bit in PINSR4 register = 1 (comparator 1, comparator 2 selected)
0
1
2 cycles of sampling clock
of digital filter
VW1C2 bit
0
1
VW1C1, VW1C2, VW1C3, VW1C7: Bits in VW1C register
VCAC1: Bit in VCAC register
LCM1POR, IRQ1SEL: Bits in ALCMR register
2 cycles of sampling clock
of digital filter
IR bit in
VCMP1IC register
(IRQ1SEL = 1)
When the VW1C1 bit is set to 0
(digital filter enabled) and the
VCAC1 bit is set to 1 (both edges)
VW1C2 bit
0
1
Set to 0 by a program
When the VW1C1 bit is set to 0
(digital filter enabled), the VCAC1
bit is set to 0 (one edge), and
the VW1C7 bit is set to 0 (VCMP1
reaches reference voltage or above)
VW1C2 bit
0
1
When the VW1C1 bit is set to 0
(digital filter enabled), the VCAC1
bit is set to 0 (one edge), and
the VW1C7 bit is set to 1 (VCMP1
reaches reference voltage or below)
Set to 0 by a program
0
1
0
1
IR bit in
VCMP1IC register
(IRQ1SEL = 1) 0
1
Set to 0 by interrupt request
acknowledgement, or by a program
VCOUT1 output
(LCM1POR = 0) 0
1
IR bit in
VCMP1IC register
(IRQ1SEL = 1) 0
1
Set to 0 by interrupt request
acknowledgement, or by a program
VCOUT1 output
(LCM1POR = 1) 0
1
Set to 0 by interrupt request
acknowledgement, or by a program
Set to 0 by a program
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Figure 7.13 Operating Example of Comparator 1 (When Digital Filter Disabled)
VW1C3 bit
0
1
VW1C2 bit
0
1
When the VW1C1 bit is set to 1
(digital filter disabled), the VCAC1
bit is set to 0 (one edge), and
the VW1C7 bit is set to 0 (VCMP1
reaches reference voltage or above)
VW1C2 bit
0
1
VW1C2 bit
0
1
When the VW1C1 bit is set to 1
(digital filter disabled) and the
VCAC1 bit is set to 1 (both edges)
Set to 0 by a program
Set to 0 by a program
Set to 0 by a program
When the VW1C1 bit is set to 1
(digital filter disabled), the VCAC1
bit is set to 0 (one edge), and
the VW1C7 bit is set to 1 (VCMP1
reaches reference voltage or below)
VCOUT1 output
(LCM1POR = 0)
IR bit in
VCMP1IC register
(IRQ1SEL = 1) 0
1
0
1
VCOUT1 output
(LCM1POR = 0) 0
1
IR bit in
VCMP1IC register
(IRQ1SEL = 1)
Set to 0 by interrupt request
acknowledgement, or by a program
0
1
IR bit in
VCMP1IC register
(IRQ1SEL = 1) 0
1
VCOUT1 output
(LCM1POR = 1) 0
1
Set to 0 by interrupt request
acknowledgement, or by a program
The above applies under the following conditions.
• VCA26 bit in VCA2 register = 1 (comparator 1 circuit enabled)
• VW1C0 bit in VW1C register = 1 (comparator 1 interrupt enabled)
• CM1OE bit in ALCMR register = 1 (output enabled)
• VCAB5 bit in VCAB register = 1 (VCMP1 pin input)
• COMPSEL bit in PINSR4 register = 1 (comparator 1, comparator 2 selected)
VW1C1, VW1C2, VW1C3, VW1C7: Bits in VW1C register
VCAC1: Bit in VCAC register
LCM1POR, IRQ1SEL: Bits in ALCMR register
Reference voltage
VCMP1
Set to 0 by interrupt request
acknowledgement, or by a program
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7.4.2 Comparator 2
Table 7.4 lists the Procedure for Setting Bits Associated with Comparator 2 Interrupt, Figure 7.14 shows an
Operating Example of Comparator 2 (When Digital Filter Enabled), and Figure 7.15 shows an Operating
Example of Comparator 2 (When Digital Filter Disabled).
NOTE:
1.
When the VW2C0 bit is set to 0, steps 6 and 7 can be executed at the same time (with one instruction).
Table 7.4 Procedure for Setting Bits Associated with Comparator 2 Interrupt
Step When Using Digital Filter When Not Using Digital Filter
1 Set the COMPSEL bit in the PINSR4 register to 1 (comparator 1, comparator 2)
2 Set the VCAB6 bit in the VCAB register to 1 (VCMP2 pin input voltage)
3 Set the VCA27 bit in the VCA2 register to 1 (comparator 2 circuit enabled)
4 Wait for td(E-A)
5 Select the interrupt type by the IRQ2SEL bit in the ALCMR register
6Select the sampling clock by bits VW2F0
and VW2F1 in the VW2C register
Set the VW2C1 bit in the VW2C register to 1 (digital
filter disabled)
7(1) Set the VW2C1 bit in the VW2C register
to 0 (digital filter enabled)
−
8 Select the interrupt request timing by the VCAC2 bit in the VCAC register and the VW2C7 bit in
the VW2C register
9 Set the VW2C2 bit in the VW2C register to 0
10 Set the CM14 bit in the CM1 register to 0
(low-speed on-chip oscillator on)
−
11 Wait for 2 cycles of the sampling clock of
the digital filter.
− (No wait time required)
12 Set the VW2C0 bit in the VW2C register to 1 (comparator 2 interrupt enabled)
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Figure 7.14 Operating Example of Comparator 2 (When Digital Filter Enabled)
Reference voltage
VCA13 bit
VCOUT2 output
(LCM2POR = 0)
VCMP2
The above applies under the following conditions.
• VCA27 bit in VCA2 register = 1 (comparator 2 circuit enabled)
• VW2C0 bit in VW2C register = 1 (comparator 2 interrupt enabled)
• CM2OE bit in ALCMR register = 1 (output enabled)
• VCAB6 bit in VCAB register = 1 (VCMP2 pin input)
• COMPSEL bit in PINSR4 register = 1 (comparator 1, comparator 2 selected)
0
1
2 cycles of sampling clock
of digital filter
VW2C2 bit
0
1
VCA13: Bit in VCA1 register
VW2C1, VW2C2, VW2C7: Bits in VW2C register
VCAC2: Bit in VCAC register
LCM2POR, IRQ2SEL: Bits in ALCMR register
2 cycles of sampling clock
of digital filter
IR bit in
VCMP2IC register
(IRQ2SEL = 1)
When the VW2C1 bit is set to 0
(digital filter enabled) and the
VCAC2 bit is set to 1 (both edges)
VW2C2 bit
0
1
When the VW2C1 bit is set to 0
(digital filter enabled), the VCAC2
bit is set to 0 (one edge), and
the VW2C7 bit is set to 0 (VCMP2
reaches reference voltage or above)
VW2C2 bit
0
1
When the VW2C1 bit is set to 0
(digital filter enabled), the VCAC2
bit is set to 0 (one edge), and
the VW2C7 bit is set to 1 (VCMP2
reaches reference voltage or below)
0
1
0
1
IR bit in
VCMP2IC register
(IRQ2SEL = 1) 0
1
VCOUT2 output
(LCM2POR = 0) 0
1
IR bit in
VCMP2IC register
(IRQ2SEL = 1) 0
1
VCOUT2 output
(LCM2POR = 1) 0
1
Set to 0 by interrupt request
acknowledgement, or by a program
Set to 0 by a program
Set to 0 by a program
Set to 0 by a program
Set to 0 by interrupt request
acknowledgement, or by a program
Set to 0 by interrupt request
acknowledgement, or by a program
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Figure 7.15 Operating Example of Comparator 2 (When Digital Filter Disabled)
VCA13 bit
0
1
VW2C2 bit
0
1
When the VW2C1 bit is set to 1
(digital filter disabled), the VCAC2
bit is set to 0 (one edge), and
the VW2C7 bit is set to 0 (VCMP2
reaches reference voltage or above)
VW2C2 bit
0
1
VW2C2 bit
0
1
When the VW2C1 bit is set to 1
(digital filter disabled) and the
VCAC2 bit is set to 1 (both edges)
Set to 0 by a program
Set to 0 by a program
Set to 0 by a program
When the VW2C1 bit is set to 1
(digital filter disabled), the VCAC2
bit is set to 0 (one edge), and
the VW2C7 bit is set to 1 (VCMP2
reaches reference voltage or below)
VCOUT2 output
(LCM2POR = 0)
IR bit in
VCMP2IC register
(IRQ2SEL = 1) 0
1
0
1
VCOUT2 output
(LCM2POR = 0) 0
1
IR bit in
VCMP2IC register
(IRQ2SEL = 1)
Set to 0 by interrupt request
acknowledgement, or by a program
0
1
IR bit in
VCMP2IC register
(IRQ2SEL = 1) 0
1
VCOUT2 output
(LCM2POR = 1) 0
1
Set to 0 by interrupt request
acknowledgement, or by a program
Reference voltage
VCMP2
Set to 0 by interrupt request
acknowledgement, or by a program
The above applies under the following conditions.
• VCA27 bit in VCA2 register = 1 (comparator 2 circuit enabled)
• VW2C0 bit in VW2C register = 1 (comparator 2 interrupt enabled)
• CM2OE bit in ALCMR register = 1 (output enabled)
• VCAB6 bit in VCAB register = 1 (VCMP2 pin input)
• COMPSEL bit in PINSR4 register = 1 (comparator 1, comparator 2 selected)
VCA13: Bit in VCA1 register
VW2C1, VW2C2, VW2C7: Bits in VW2C register
VCAC2: Bit in VCAC register
LCM2POR, IRQ2SEL: Bits in ALCMR register
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7.5 Comp a rator 1 and Comparator 2 Interrupts
Two interrupt requests are generated, one each for comparator 1 and comparator 2. Non-maskable or maskable can
be selected for each interrupt type. Refer to 13. Interrupts for interrupts.
7.5.1 Non-Maskable Interrupts
When IRQiSEL (i = 1 or 2) bit in the ALCMR register is set to 0, the comparator i interrupt fun c tio ns as a non-
maskable interrupt. When the selected interrupt request timing occurs, the VWiC2 bit in the VWiC register is
set to 1. At this time, a non-maskable interrupt request for comparator i is generated.
7.5.2 Maskable Interrupts
When the IRQiSEL (i = 1 or 2) bit in the ALCMR register is set to 1, the comparator i i nterrupt functions as a
maskable interrupt. The comparator i interrupt uses the single VCMPiIC register (b its IR and ILVL0 to ILV L2)
and a single vector. When the selected interrupt request timing occurs, the VWiC2 bit in the VWiC register is
set to 1. At this time, th e IR bit in the VCMPiIC register is set to 1 (interrupt requested).
Refer to 13.1.6 Interrupt Control for the VCMPiI C register and 13.1.5.2 Relocatable Vecto r Tables for
interrupt vectors.
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7.6 Adjusting Internal Reference Voltage (Vref)
The level of the internal reference voltage (Vref) can be adjusted with the value of the BGRTRM register. The
values for correcting the Vref are stored in registers BGRTRMA and BGRTRMB before shipping the MCU. The
value of the BGRTRMA register is the same as that of the BGRTRM register after reset.
To use separate correction values to match the supply voltage ranges, transfer them from registers BGRT RMA and
BGRTRMB to the BGRTRM register. Figure 7.16 shows the Procedure for Adjusting Internal Reference Voltage
(Vref).
When the BGRCR0 bit in the BGRCR register to 1 (disabled), the internal reference voltage (Vref) adjustment
circuit (BGR trimming circuit ) is disabl ed and the valu e of the BGRT RM reg ister is also disabled.
When the BGR trimming circuit is disabled, the accuracy of the internal reference voltage (Vref) is not guaranteed.
Disable voltage detection circuits 0 to 2 and disable comparators 1 and 2 with the internal reference voltage
selected. The high-speed on-chip oscillator should also be stopped as necessary because the precision of its
oscillation frequency is not also guaranteed.
Figure 7.16 Procedure for Adjusting Internal Reference Voltage (Vref)
Start adjusting the internal reference voltage
(Vref)
Determine the supply voltage(1)
Wait for 10µs
Vcc ≥ 3.6 V ?
Adjustment of the internal reference voltage
(Vref) completed
No
Yes
Transfer the value of the BGRTRMA register
to the BGRTRM register
Transfer the value of the BGRTRMB register
to the BGRTRM register
NOTE:
1. The supple voltage can be determined by reading the monitor flag (VCA13 bit in VCA1
register) for voltage detection 2. Figure 7.17 shows an Example of Adjusting Internal
Reference Voltage (Vref) (Voltage Detection 2 Used for Determining Supply Voltage).
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Figure 7.17 Example of Adjusting Internal Reference Voltage (Vref) (Voltage Detection 2 Used for
Determining Supply Voltage)
Start adjusting the internal reference voltage
(Vref)
Wait for 10µs
Adjustment of the internal reference voltage
(Vref) completed
No
Yes
Transfer the value of the BGRTRMA register to
the BGRTRM register
Wait for 10µs
Enable the voltage detection 2 circuit
(Set the VCA27 bit to 1 and the VW2C0 bit to 0)
Wait for td(E-A) or 100µs
Transfer the value of the BGRTRMB register to
the BGRTRM register
VCA13: Bit in VCA1 register
VCA27: Bit in VCA2 register
VW2C0: Bit in VW2C register
VCA13 bit = 0 ?
R8C/2G Group 8. I/O Ports
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8. I/O Ports
There are 27 I/O ports P0_4 to P0_7, P1, P3, P4_3, P4_5, P6_0, P6_3 to P6_6.
When the XCIN clock oscillation circuit is not used, P4_3 can be used as an I/O port and P4_4 can be used as an output
port.
Table 8.1 lists an Overview of I/ O Por ts.
NOTES:
1. In input mode, whether an internal pull-up resistor is connected or not can be selected by PUR0
register.
2. In input mode, whether an internal pull-up resistor is connected or not can be selected by PUR1
register.
3. Do not use port P4_4 as an input port (input mode).
8.1 Functions of I/O Ports
The PDi_j (j = 0 t o 7) bit in the PDi (i = 0, 1, 3, 4, 6) register control s I/O of the ports P0_4 to P0_7 , P1 , P3 , P4_3
to P4_5, P6_0, P6_3 to P6_6 . The Pi register consists of a port latch to hold output data and a circuit to read p in
states.
Figures 8.1 to 8.3 show the Configurations of I/O Ports. Table 8.2 lists the Functions of I/ O Po rts. Also, F igure 8.5
shows the PDi (i = 0, 1, 3, 4, or 6) Register. Figure 8.6 shows the Pi (i = 0, 1, 3, 4, or 6) Register, Fi gure 8.7 shows
Registers PINSR2 , PINSR3, and PINSR4 , Figure 8.8 shows the PMR Register, Figure 8.9 shows Registers PUR0
and PUR1.
i = 0, 1, 3, 4, 6, j = 0 to 7
NOTE:
1. Nothing is assigned to bits PD0_0 to PD0_3, PD4_0 to PD4_2, PD4_6, PD4_7, PD6_1, PD6_2,
PD6_7.
Table 8.1 Overview of I/O Ports
Ports I/O Type of Output I/O Setting Internal Pull-Up Resister
P0_4 to P0_7, P1, P3 I/O CMOS3 State Set per bit Set every 4 bits(1)
P4_3 I/O CMOS3 State Set per bit Set every bit(2)
P4_4 Output CMOS3 State Set per bit(3) None
P4_5 I/O CMOS3 State Set per bit Set every bit(2)
P6_0, P6_3 I/O CMOS3 State Set per bit Set every 2 bits(2)
P6_4 to P6_6 I/O CMOS3 State Set per bit Set every 3 bits(2)
Table 8.2 Functions of I/O Ports
Operation When
Accessing
Pi Register
Value of PDi_j Bit in PDi Register(1)
When PDi_j Bit is Set to 0 (Input Mode) When PDi_j Bit is Set to 1 (Output Mode)
Reading Read pin input level Read the port latch
Writing Write to the port latch Write to the port latch. The value written to
the port latch is output from the pin.
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8.2 Effect on Peripheral Functions
I/O ports function as I/O ports for peripheral functions (refer to Table 1.3 Pin Name Information by Pin
Number).
Table 8.3 lists the Setting of PDi_j Bi t when Funct ioning as I/O Port s for Peripheral Functi ons (i = 0, 1 , 3, 4, 6, j =
0 to 7). Refer to the description of each function for information on how to set peripheral functions.
NOTE:
1. Nothing is assigned to bits PD0_0 to PD0_3, PD4_0 to PD4_2, PD4_6, PD4_7, PD6_1, PD6_2,
PD6_7.
8.3 Pins Other than Programmable I/O Ports
Figure 8.4 shows the Configuratio n of I/ O Pins.
Table 8.3
Setting of PDi_j Bit when Functioning as I/ O Port s fo r Peripheral Functi ons (i = 0, 1, 3, 4, 6, j = 0 to 7)
I/O of Peripheral Functions PDi_j Bit Settings for Shared Pin Functions(1)
Input Set this bit to 0 (input mode).
Output This bit can be set to either 0 or 1 (output regardless of the port setting)
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Figure 8.1 Configuration of I/O Ports (1)
NOTE:
1. symbolizes a parasitic diode.
Ensure the input voltage to each port does not exceed VCC.
P0_4, P1_4, P3_0, P3_1,
P3_4, P3_5, P3_7,
P6_0, and P6_3 Direction
register
Data bus
Pull-up selection
1
Output from individual peripheral function
(Note 1)
(Note 1)
P0_6, P3_2, P3_6,
and P4_5
Port latch
INT0, INT1, INT2, and INT4 input
Data bus
Pull-up selection
Digital
filter
(Note 1)
(Note 1)
Direction
register
Port latch
Port latch
Data bus
Pull-up selection
(Note 1)
(Note 1)
P0_5
Direction
register
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Figure 8.2 Configuration of I/O Ports (2)
Port latch
Input to individual peripheral function
Data bus
Pull-up selection
P0_7,
P6_4, and P6_6
P1_0 to P1_2
1
Analog input
Data bus
Pull-up selection
Input to individual peripheral function
Direction
register
Direction
register
(Note 1)
(Note 1)
(Note 1)
(Note 1)
NOTE:
1. symbolizes a parasitic diode.
Ensure the input voltage to each port does not exceed VCC.
Output from individual peripheral function
Port latch
P1_3, P1_6,
P3_3, and P6_5
1
Data bus
Pull-up selection
Input to individual peripheral function
Output from individual peripheral function
(Note 1)
(Note 1)
Direction
register
Port latch
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Figure 8.3 Configuration of I/O Ports (3)
P4_3/XCIN
Data bus
Pull-up selection
P4_4/XCOUT
Data bus
Clocked inverter(2)
(Note 3)
NOTES:
1. symbolizes a parasitic diode.
Ensure the input voltage to each port does not exceed VCC.
2. When CM10 = 1 or CM04 = 0, the clocked inverter is cut off.
3. When CM04 = 0 the feedback resistor is disconnected.
Port latch
Port latch
(Note 1)
(Note 1)
(Note 1)
(Note 1)
Direction
register
Direction
register
P1_5 and P1_7
Data bus
Pull-up selection
Input to individual peripheral function
1
Output from individual peripheral function
INT1 input
Digital
filter
Direction
register
(Note 1)
(Note 1)
Port latch
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Figure 8.5 PDi (i = 0, 1, 3, 4, or 6) Register
Port Pi Direction Register (i = 0, 1, 3, 4, or 6)(1, 2, 3, 4)
Symbol Address Af ter Reset
PD0 00E2h 00h
PD1 00E3h 00h
PD3 00E7h 00h
PD4 00EAh 00h
PD6 00EEh 00h
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
4.
Bits PD4_0 to PD4_2, PD4_6, and PD4_7 in the PD4 register are unavailable on this MCU.
If it is necessary to set bits PD4_0 to PD4_2, PD4_6, and PD4_7, set to 0 (input mode). When read, the content is 0.
To use port P4_4 as an output port, set the PD4_4 bit to 1 (output mode). Do not use port P4_4 as an input port.
Bits PD6_1, PD6_2, and PD6_7 in the PD6 register are unavailable on this MCU.
If it is necessary to set bits PD6_1, PD6_2, and PD6_7, set to 0 (input mode). When read, the content is 0.
Bits PD0_0 to PD0_3 in the PD0 register are unavailable on this MCU.
If it is necessary to set bits PD0_0 to PD0_3 , set to 0 (input mode). When read, the content is 0.
PDi_3 Port Pi_3 direction bit
Port Pi_1 direction bit
Port Pi_4 direction bit
Port Pi_2 direction bit
PDi_4
RW
RW
Port Pi_5 direction bit
RW0 : Input mode
(functions as an input port)
1 : Output mode
(functions as an output port)
RW
RW
Port Pi_6 direction bit RW
Port Pi_0 direction bit
b7 b6 b5 b4 b3 b2
PDi_2
b1 b0
PDi_1
PDi_0
Set the PD0 register by using the next instruction after setting the PRC2 bit in the PRCR register to 1 (w rite enable).
PDi_6
RW
PDi_7 Port Pi_7 direction bit RW
PDi_5
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Figure 8.6 Pi (i = 0, 1, 3, 4, or 6) Register
Port Pi Register (i = 0, 1, 3, 4, or 6)(1, 2, 3)
Symbol Address Af ter Reset
P0 00E0h 00h
P1 00E1h 00h
P3 00E5h 00h
P4 00E8h 00h
P6 00ECh 00h
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
Bits P4_0 to P4_2, P4_6, and P4_7 in the P4 register are unavailable on this MCU.
If it is necessary to set bits P4_0 to P4_2, P4_6, and P4_7, set to 0 (“L” level). When read, the content is 0.
Bits P6_1, P6_2, and P6_7 in the P6 register are unavailable on this MCU.
If it is necessary to set bits P6_1, P6_2, and P6_7, set to 0 (“L” level). When read, the content is 0.
Pi_7
Pi_6
RW
Bits P0_0 to P0_3 in the P0 register are unavailable on this MCU.
If it is necessary to set bits P0_0 to P0_3, set to 0 (“L” level). When read, the content is 0.
b3 b2 b1 b0
Pi_1
Pi_5
Pi_0
Pi_2
Pi_4
Pi_3
b7 b6 b5 b4
Por t Pi_ 0 bit
Por t Pi_ 1 bit
Por t Pi_ 7 bit
Por t Pi_ 5 bit
Por t Pi_ 4 bit
Por t Pi_ 3 bit
RW
Por t Pi_ 6 bit RW
Por t Pi_ 2 bit
RW
The pin level of any I/O port w hich is set
to input mode can be read by reading the
corresponding bit in this register. The pin
level of any I/O port w hich is set to output
mode can be controlled by w riting to the
corresponding bit in this register.
0 : “L” level
1 : “H” level
RW
RW
RW
RW
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Figure 8.7 Registers PINSR2, PINSR3, and PINSR4
Pin Select Register 2
Symbol Address After Reset
PINSR2 00F6h 00h
Bit Symbol Bit Name Function RW
TRAO pin select bit
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
TRA OSEL 0 : P3_0
1 : P3_7
TRBOSEL
—
(b7)
0 : P3_1
1 : P1_3
TRBO pin select bit
—
(b5)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
RW
RW
—
—
—
—
(b3-b0)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
b7 b6 b5 b4 b0b3 b2 b1
Pin Select Register 3
Symbol Address Af ter Reset
PINSR3 00F7h 00h
Bit Symbol Bit Name Function RW
—
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
—
(b7-b6)
—
TREOSEL
—
(b4-b0)
TREO pin select bit RW
b7 b6 b5 b4 b0
0 : P6_0
1 : P0_4
b3 b2 b1
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Pin Select Register 4
Symbol Address After Reset
PINSR4 02FBh 00h
Bit Symbol Bit Name Function RW
KI0
_
___
pin select bit
KI1
_
___
pin select bit
TREO pin select 2 bit
b0
0 : Voltage monitor 1, voltage monitor 2
1 : Comparator 1, comparator 2
b3 b2 b1b7 b6 b5 b4
RW
COMPSEL
TRFOSEL
000
TRFO11 pin select bit 0 : P3_4
1 : P3_7
Voltage monitor/comparator
select bit
RW
RW
RW
RW
RW
KI0SEL 0 : P1_0
1 : P0_7
—
(b6-b4)
TREOSEL2
Set to 0.Res er v ed bits
KI1SEL 0 : P1_1
1 : P6_6
0 : TREOSEL bit in PINSR3 register enabled
1 : P6_5
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Figure 8.8 PMR Regi st er
Figure 8.9 Registers PUR0 an d PUR1
Port Mode Registe
r
Symbol Address After Reset
PMR 00F8h 00h
Bit Symbol Bit Name Function RW
INT1
_
____ pin select bit
b7 b6 b5 b4 b0b3 b2 b1
INT1SEL 0 : P1_5, P1_7
1 : P3_6 RW
—
(b7-b1) —
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Pull-Up Control Register 0
Symbol Address Af ter Reset
PUR0 00FCh 00h
Bit Symbol Bit Name Function RW
NOTE:
1.
—
—
RW
RW
RW
P0_4 to P0_7 pull-up(1)
PU03 P1_4 to P1_7 pull-up(1)
P1_0 to P1_3 pull-up(1)
PU01
b0
—
(b0)
b7 b6 b5 b4 b3 b2 b1
0 : Not pulled up
1 : Pulled up
When this bit is set to 1 (pulled up), the pin w hose direction bit is set to 0 (input mode) is pulled up.
PU07 RWP3_4 to P3_7 pull-up(1)
PU06 P3_0 to P3_3 pull-up(1) RW
—
(b5-b4)
PU02
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
0 : Not pulled up
1 : Pulled up
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Pull-Up Control Register 1
Symbol Address Af ter Reset
PUR1 00FDh 00h
Bit Symbol Bit Name Function RW
NOTE:
1.
P6_4 to P6_6 pull-up(1)
0 : Not pulled up
1 : Pulled up RW
PU14 P6_0, P6_3 pull-up(1) RW
RW0 : Not pulled up
1 : Pulled up
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
PU11 P4_5 pull-up(1) RW
—
—
(b7-b6)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
PU10 P4_3 pull-up(1)
—
(b3-b2)
PU15
b7 b6 b5 b4 b0
—
When this bit is set to 1 (pulled up), the pin w hose direction bit is set to 0 (input mode) is pulled up.
b3 b2 b1
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8.4 Port Setting
Table 8.4 to Table 8.33 list the port setting.
X: 0 or 1
NOTE:
1. Pulled up by setting the PU01 bit in the PUR0 register to 1.
NOTE:
1. Pulled up by setting the PU01 bit in the PUR0 register to 1.
NOTE:
1. Pulled up by setting the PU01 bit in the PUR0 register to 1.
X: 0 or 1
NOTE:
1. Pulled up by setting the PU01 bit in the PUR0 register to 1.
Ta ble 8.4 P o rt P0 _4 /( TREO)
Register PD0 PINSR4 PINSR3 TRECR1 Function
Bit PD0_4 TREOSEL2 TREOSEL TOENA
Setting
value
0 Other than 011b Input port(1)
1 Other than 011b Output port
X 0 1 1 TREO output
Ta bl e 8. 5 Po r t P0 _5
Register PD0 Function
Bit PD0_5
Setting
value
0Input port(1)
1 Output port
Ta b le 8. 6 Po r t P0 _6 /IN T4
Register PD0 INTEN2 Function
Bit PD0_6 INT4EN
Setting
value
00
Input port(1)
1 0 Output port
01
INT4 input (1)
Ta ble 8.7 P o rt P0 _7 /(KI0)
Register PD0 PINSR4 KIEN Function
Bit PD0_7 KI0SEL KI0EN
Setting
value
0X0
Input port(1)
1 X 0 Output port
011
KI0 input(1)
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X: 0 or 1
NOTE:
1. Pulled up by setting the PU02 bit in the PUR0 register to 1.
X: 0 or 1
NOTE:
1. Pulled up by setting the PU02 bit in the PUR0 register to 1.
X: 0 or 1
NOTE:
1. Pulled up by setting the PU02 bit in the PUR0 register to 1.
Ta ble 8.8 P o rt P1 _0 /KI0/TRFO00/VCMP1
Register PD1 TRFOUT PINSR4 KIEN VCAB Function
Bit PD1_0 TRFOUT0 KI0SEL KI0EN VCAB5
Setting
value
00X00
Input port(1)
1 0 X 0 0 Output port
X1X00
TRFO00 output
00010
KI0 input(1)
00X01
VCMP1 input(1)
Ta ble 8.9 P o rt P1 _1 /KI1/TRFO01/VCMP2
Register PD1 TRFOUT PINSR4 KIEN VCAB Function
Bit PD1_1 TRFOUT1 KI1SEL KI1EN VCAB6
Setting
value
00X00
Input port(1)
1 0 X 0 0 Output port
X1X00
TRFO01 output
00010
KI1 input(1)
00X01
VCMP2 input(1)
Tab le 8. 10 Port P1_2/KI2/TRFO02/CVREF
Register PD1 TRFOUT KIEN VCAB Function
Bit PD1_2 TRFOUT2 KI2EN VCAB7
Setting
value
0000
Input port(1)
1 0 0 0 Output port
X 1 0 0 TRFO02 output
0010
KI2 input(1)
0001
CVREF input(1)
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X: 0 or 1
NOTE:
1. Pulled up by setting the PU02 bit in the PUR0 register to 1.
NOTE:
1. Set the TOCNT bit in the TRBIOC register to 0 in modes except for programmable waveform generation mode.
X: 0 or 1
NOTES:
1. Pulled up by setting the PU03 bit in the PUR0 register to 1.
2. N-channel open-drain output by setting the NCH bit in the U0C0 register to 1.
Tab le 8. 11 Port P1_3/KI3/VCOUT1/(TRBO)
Register PD1 Timer RB Setting KIEN ALCMR Function
Bit PD1_3 −KI3EN CM1OE
Setting
value
0 Other than TRBO usage conditions 0 0 Input port(1)
1 Other than TRBO usage conditions 0 0 Output port
0 Other than TRBO usage conditions 1 0 KI3 input(1)
X Refer to Table 8.12 TRBO Pin Setting 0 0 TRBO output
X Other than TRBO usage conditions 0 1 VCOUT1 output
Tab le 8. 12 TRBO Pin Setting
Register PINSR2 TRBIOC TRBMR Function
Bit TRBOSEL TOCNT(1) TMOD1 TMOD0
Setting
value
1 0 0 1 Programmable waveform generation mode
1 0 1 0 Programmable one-shot generation mode
1 0 1 1 Programmable wait one-shot generation mode
1101
P1_3 output port
Other than above Other than TRBO usage conditions
Tab le 8. 13 Port P1_4/TXD0
Register PD1 U0MR Function
Bit PD1_4 SMD2 SMD1 SMD0
Setting
value
0000
Input port(1)
1 0 0 0 Output port
X
0
0
1
TXD0 output(2)
1
0
1
10
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X: 0 or 1
NOTES:
1. Pulled up by setting the PU03 bit in the PUR0 register to 1.
2. Set the TOPCR bit in the TRAIOC register to 0 in modes except for pulse output mode.
X: 0 or 1
NOTE:
1. Pulled up by setting the PU03 bit in the PUR0 register to 1.
X: 0 or 1
NOTES:
1. Pulled up by setting the PU03 bit in the PUR0 register to 1.
2. Set the TOPCR bit in the TRAIOC register to 0 in modes except for pulse output mode.
Tab le 8. 14 Port P1_5/RXD0/(T RAI O) /(INT 1 )
Register PD1 TRAIOC TRAMR PMR INTEN Function
Bit PD1_5 TIOSEL TOPCR(2) TMOD2 TMOD1 TMOD0 INT1SEL INT1EN
Setting
value
0
0XXXX
X0
Input port(1)
11001
00
10XXXX
X0 Output port
10000
00XXXXX0RXD0 input(1)
1 0 Other than 001b
010000
01INT1 input(1)
11
01 0 Other than 000b, 001b XX
TRAIO input(1)
01 0 Other than 000b, 001b 01
TRAIO input/INT1 input(1)
X10001XX
TRAIO output
Tab le 8. 15 Port P1_6/CLK0/VC OU T2
Register PD1 ALCMR U0MR Function
Bit PD1_6 CM2OE CKDIR SMD2 SMD1 SMD0
Setting
value
000 Other than 001b Input port(1)
1XXX
10X Other than 001b Output port
X00 0 0 1 CLK0 output
001XXX
CLK0 input(1)
X 1 X X X X VCOUT2 output
Tab le 8. 16 Port P1_7/TRAIO/INT 1
Register PD1 TRAIOC TRAMR PMR INTEN Function
Bit PD1_7 TIOSEL TOPCR(2) TMOD2 TMOD1 TMOD0 INT1SEL INT1EN
Setting
value
0
1 X XXX
X0
Input port(1)
01001
00
11 X XXXX 0 Output port
00000
00 000001
INT1 input(1)
11
0 0 0 Other than 000b, 001b X X TRAIO input(1)
0 0 0 Other than 000b, 001b 0 1 TRAIO input/INT1 input(1)
X 0 0 0 0 1 X X TRAIO output
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X: 0 or 1
NOTE:
1. Pulled up by setting the PU06 bit in the PUR0 register to 1.
X: 0 or 1
NOTE:
1. Pulled up by setting the PU06 bit in the PUR0 register to 1.
NOTE:
1. Set the TOCNT bit in the TRBIOC register to 0 in modes except for programmable waveform generation mode.
NOTE:
1. Pulled up by setting the PU06 bit in the PUR0 register to 1.
X: 0 or 1
NOTE:
1. Pulled up by setting the PU06 bit in the PUR0 register to 1.
Tab le 8. 17 Port P3_0/TRAO
Register PD3 PINSR2 TRAIOC Function
Bit PD3_0 TRAOSEL TOENA
Setting
value
0X0
Input port(1)
1 X 0 Output port
X 0 1 TRAO output
Tab le 8. 18 Port P3_1/TRBO
Register PD3 Timer RB Setting Function
Bit PD3_1 −
Setting
value
0 Other than TRBO usage conditions Input port(1)
1 Other than TRBO usage conditions Output port
X Refer to Table 8.19 TRBO Pin Setting TRBO output
Tab le 8. 19 TRBO Pin Setting
Register PINSR2 TRBIOC TRBMR Function
Bit TRBOSEL TOCNT(1) TMOD1 TMOD0
Setting
value
0 0 0 1 Programmable waveform generation mode
0 0 1 0 Programmable one-shot generation mode
0 0 1 1 Programmable wait one-shot generation mode
0101
P3_1 output port
Other than above Other than TRBO usage conditions
Tab le 8. 20 Port P3_2/INT2
Register PD3 INTEN Function
Bit PD3_2 INT2EN
Setting
value
00
Input port(1)
1 0 Output port
01
INT2 input
Tab le 8. 21 Port P3_3/TRFO10 /TR FI
Register PD3 TRFOUT Function
Bit PD3_3 TRFOUT3
Setting
value
00
Input port(1)
1 0 Output port
X 1 TRFO10 output
00
TRFI input(1)
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X: 0 or 1
NOTE:
1. Pulled up by setting the PU07 bit in the PUR0 register to 1.
X: 0 or 1
NOTE:
1. Pulled up by setting the PU07 bit in the PUR0 register to 1.
X: 0 or 1
NOTE:
1. Pulled up by setting the PU07 bit in the PUR0 register to 1.
X: 0 or 1
NOTE:
1. Pulled up by setting the PU07 bit in the PUR0 register to 1.
Tab le 8. 22 Port P3_4/TRFO11
Register PD3 PINSR4 TRFOUT Function
Bit PD3_4 TRFOSEL TRFOUT4
Setting
value
0X0
Input port(1)
1 X 0 Output port
X 0 1 TRFO11 output
Tab le 8. 23 Port P3_5/TRFO12
Register PD3 TRFOUT Function
Bit PD3_5 TRFOUT5
Setting
value
00
Input port(1)
1 0 Output port
X 1 TRFO12 output
Tab le 8. 24 Port P3_6/(INT1)
Register PD3 PMR INTEN Function
Bit PD3_6 INT1SEL INT1EN
Setting
value
0X0
Input port(1)
1 X 0 Output port
011
INT1 input(1)
Tab le 8. 25 Port P3_7/(TRAO) /( TRFO11)
Register PD3 PINSR2 TRAIOC PINSR4 TRFOUT Function
Bit PD3_7 TRAOSEL TOENA TRFOSEL TRFOUT4
Setting
value
0X0X0
Input port(1)
1 X 0 X 0 Output port
X 1 1 X 0 TRAO output
X X 0 1 1 TRFO11 output
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X: 0 or 1
NOTES:
1. Pulled up by setting the PU10 bit in the PUR1 register to 1.
2. Refer to 8.6.1 Port P4_3, P4_4.
X: 0 or 1
NOTE:
1. Refer to 8.6.1 Port P4_3, P4_4.
NOTE:
1. Pulled up by setting the PU11 bit in the PUR1 register to 1.
Tab le 8. 26 Port P4_3/(XCIN)
Register PD4 CM0 CM1 Circuit specifications
Function
Bit PD4_3 CM04 CM10 CM12 Oscillation
buffer
Feedback
resistor
Setting
value
00XXOFFOFF
Input port(1, 2)
10XXOFFOFF
Output port(2)
X 1 0 0 ON ON XCIN clock oscillation (on-chip feedback
resistor enabled)
X 1 0 1 ON OFF XCIN clock oscillation (on-chip feedback
resistor disabled)
X110OFFON
XCIN clock oscillation stop
1OFFOFF
X100ONON
External XCIN clock input
1ONOFF
Tab le 8. 27 Port P4_4/(XCOUT)
Register PD4 CM0 CM1 Circuit specifications
Function
Bit PD4_4 CM04 CM10 CM12 Oscillation
buffer
Feedback
resistor
Setting
value
10XXOFFOFF
Output port(1)
X 1 0 0 ON ON XCIN clock oscillation (on-chip feedback
resistor enabled)
X 1 0 1 ON OFF XCIN clock oscillation (on-chip feedback
resistor disabled)
X110OFFON
XCIN clock oscillation stop
1OFFOFF
X100ONON
External XCOUT clock output (inverted
output of XCIN clock)
1ONOFF
Tab le 8. 28 Port P4_5/INT0
Register PD4 INTEN Function
Bit PD4_5 INT0EN
Setting
value
00
Input port(1)
1 0 Output port
01
INT0 input
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X: 0 or 1
NOTE:
1. Pulled up by setting the PU14 bit in the PUR1 register to 1.
X: 0 or 1
NOTES:
1. Pulled up by setting the PU14 bit in the PUR1 register to 1.
2. N-channel open-drain output by setting the NCH bit in the U2C0 register to 1.
NOTE:
1. Pulled up by setting the PU15 bit in the PUR1 register to 1.
X: 0 or 1
NOTE:
1. Pulled up by setting the PU15 bit in the PUR1 register to 1.
X: 0 or 1
NOTE:
1. Pulled up by setting the PU15 bit in the PUR1 register to 1.
Tab le 8. 29 Port P6_0/TREO
Register PD6 PINSR4 PINSR3 TRECR1 Function
Bit PD6_0 TREOSEL2 TREOSEL TOENA
Setting
value
0 Other than 001b Input port(1)
1 Other than 001b Output port
X001TREO output
Tab le 8. 30 Port P6_3/TXD2
Register PD6 U2MR Function
Bit PD6_3 SMD2 SMD1 SMD0
Setting
value
0000
Input port(1)
1 0 0 0 Output port
X
0
0
1
TXD2 output(2)
1
0
1
10
Tab le 8. 31 Port P6_4/RXD2
Register PD6 Function
Bit PD6_4
Setting
value
0Input port(1)
1 Output port
0RXD2 input(1)
Tab le 8. 32 Port P6_5/CLK2/(T REO )
Register PD6 PINSR4 TRECR1 U2MR Function
Bit PD6_5 TREOSEL2 TOENA CKDIR SMD2 SMD1 SMD0
Setting
value
00X0 Other than 001b Input port(1)
1XXX
1 0 X X Other than 001b Output port
X0X0001CLK2 output
00X1XXX
CLK2 input(1)
X 1 1 X X X X TREO output
Tab le 8. 33 Port P6_6/(KI1)
Register PD6 PINSR4 INTEN Function
Bit PD6_6 KI1SEL INT0EN
Setting
value
0X0
Input port(1)
1 X 0 Output port
011
KI1 input(1)
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8.5 Unassigned Pin Handling
Table 8.34 lists Unassigned Pin Handling.
NOTES:
1. If these ports are set to output mode and left open, they remain in input mode until they are switched
to output mode by a program. The voltage level of these pins may be undefined and the power
current may increase while the ports remain in input mode.
The content of the direction registers may change due to noise or program runaway caused by
noise. In order to enhance program reliability, the program should periodically repeat the setting of
the direction registers.
2. Connect these unassigned pins to the MCU using the shortest wire length (2 cm or less) possible.
3. When the power-on reset function is in use.
Figure 8.10 Unassigned Pin Handling
Table 8.34 Unassigned Pin Handling
Pin Name Connection
Ports P0_4 to P0_7, P1, P3,
P4_3 to P4_5, P6_0, P6_3 to P6_6
• After setting to input mode, connect each pin to VSS via a resistor
(pull-down) or connect each pin to VCC via a resistor (pull-up).(2)
• After setting to output mode, leave these pins open.(1, 2)
RESET (3) Connect to VCC via a pull-up resistor(2)
NOTE:
1. When the power-on reset function is in use.
MCU
Port P0_4 to P0_7,
P1, P3
P4_3 to P4_5,
P6_0, P6_3 to P6_6
(Input mode )
:
:
(Input mode)
(Output mode)
RESET(1)
:
:
Open
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8.6 Notes on I/O Ports
8.6.1 Port P4_3, P4_4
Ports P4_3 and P4_4 are also used as the XCIN function and the XCOUT function, respectively. During a reset
period and after a reset release, these ports are set to the XCIN and XCOUT functions. Pins P4_3 and P4_4 can
be switched to the po rt functions by setti ng the CM04 bit in the CM0 register to 0 (p orts P4_3 and P4_4) by a
program.
To use port s P4_3 and P4_4 as ports, note the following:
•Port P4_3
After a reset until the CM 04 bit is set to 0 (por ts P4_3 and P4_4) by a p rogram, a typical 1 0 MΩ impedance is
connected between the P4_3 pin and the MCU power supply or GND. If the XCIN is set to intermediate-level
input or left floating, a shoot-through cu rrent flows into the oscillation driver.
•Port P4_4
Use port P4_4 as an output port by setting the PD4_4 bit in the PD4 register to 1 (output mode). After a reset
until the CM04 bit is set to 0 (ports P4_3 and P4_4) by a program, the P4_4 pin may output an intermediate
potential of about 2.0 V.
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9. Processor Mode
9.1 Processor Mo des
Single-chip mode can be selected as the processor mode.
Table 9.1 lists Features of Processor Mode. Figu re 9.1 shows the PM0 Register and Figure 9.2 shows the PM1
Register.
Figure 9.1 PM0 Register
Figure 9.2 PM1 Register
Table 9.1 Features of Processor Mode
Processor Mode Accessible Areas Pins Assignable as I/O Port Pins
Single-chip mode SFR, internal RAM, internal ROM All pins are I/O ports or peripheral
function I/O pins
Processor Mode Register 0(1)
Symbol Address After Reset
PM0 0004h 00h
Bit Symbol Bit Name Function RW
NOTE:
1.
RW
Reserved bits Set to 0.
Set the PRC1 bit in the PRCR register to 1 (w rite enable) before rew riting the PM0 register.
The MCU is reset w hen this bit is set to 1.
When read, the content is 0. RW
—
(b7-b4)
PM0 3 Softw are reset bit
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
b7 b6 b5 b4 b3 b2
—
b1 b0
000
—
(b2-b0)
Processor Mode Register 1(1)
Symbol Address Af ter Reset
PM1 0005h 00h
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
—
(b6-b3)
PM1 2 WDT interrupt/reset sw itch bit
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
The PM12 bit is set to 1 by a program (It remains unchanged even if 0 is w ritten to it).
When the CSPRO bit in the CSPR register is set to 1 (count source protect mode enabled), the PM12 bit is
automaticall
y
set to 1.
Reserved bit Set to 0.
Set the PRC1 bit in the PRCR register to 1 (w rite enable) before rew riting the PM1 register.
—
(b7) RW
b3 b2
—
b1 b0
00
0 : Watchdog timer interrupt
1 : Watchdog timer reset(2) RW
b7 b6 b5 b4
0
—
(b1-b0) RW
Reserved bits Set to 0.
R8C/2G Group 10. Bus
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REJ09B0387-0100
10. Bus
The bus cycles differ when accessing ROM/RAM, and when accessing SFR.
Table 10.1 lists Bus Cycles by Access Space of the R8C/2G Group.
ROM/RAM and SFR are connected to the CPU by an 8-bit bus. When accessing in word (16-bit) units, these areas are
accessed twice in 8-bit units.
Table 10.2 lists Access Units and Bus Operations.
Table 10.2 Access Units and Bus Operations
Table 10.1 Bus Cycles by Access Space of the R8C/2G Group
Access Area Bus Cycle
SFR 2 cycles of CPU clock
ROM/RAM 1 cycle of CPU clock
Area SFR
Even address
Byte access
ROM, RAM
Odd address
Byte access
Even address
Word access
Odd address
Word access
CPU clock
Data Data Data
Even Even
Address
CPU
clock
Data
Address
CPU
clock
Data
Address
CPU
clock
Data
Address
CPU
clock
Data
Address
CPU
clock
Data
Address
CPU
clock
Data
Address
CPU
clock
Data
Address
Data Data
Odd Odd
Data
Even Even + 1
Data
Data
Odd Odd + 1
Data
Data
Even Even + 1
Data
Data
Odd Odd + 1
Data
R8C/2G Group 11. Clock Generation Circuit
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11. Clock Generation Circuit
The clock generation circuit has:
• XCIN clock oscillation circuit
• Low-speed on-chip oscillator
• High-speed on-chip oscillator
Table 1 1.1 lists Specifications of Clock Generation Circuit. Figure 1 1.1 shows a Clock Generation Circuit. Figures 11.2
to 11 .8 show clock associated registers. Figure 11.9 shows a Handling Procedure of Intern al Power Low Consumption
Using VCA20 Bit.
NOTES:
1. These pins can be used as P4_3 or P4_4 when using the on-chip oscillator clock as the CPU clock while the
XCIN clock oscillation circuit is not used.
2. Set the CM04 bit in the CM0 register to 1 (XCIN-XCOUT pin) when an external clock is input.
Table 11.1 Specifications of Clock Generation Circuit
Item XCIN Clock Oscillation Circuit On-Chip Oscillator
High-Speed On-Chip Oscillator Low-Speed On-Chip Oscillator
Applications • CPU clock source
• Peripheral function clock
source
• CPU clock source
• Peripheral function clock
source
• CPU clock source
• Peripheral function clock
source
Clock frequency 32.768 kHz Approx. 8 MHz Approx. 125 kHz
Connectable
oscillator
• Crystal oscillator −−
Oscillator
connect pins
XCIN, XCOUT(1) −(1) −(1)
Oscillation stop,
restart function
Usable Usable Usable
Oscillator status
after reset
Oscillate Stop Oscillate
Others • Externally generated clock can
be input(2)
• On-chip feedback resistor
RfXCIN (connected/ not
connected, selectable)
−−
R8C/2G Group 11. Clock Generation Circuit
Rev.1.00 Apr 04, 2008 Page 88 of 318
REJ09B0387-0100
Figure 11.1 Clock Generation Circuit
Divider
SQ
R
1/2 1/2 1/2 1/2 1/2
SQ
R
HRA00 High-speed
on-chip
oscillator
HRA01 = 1
HRA01 = 0
CM14
CPU clock
a
b
c
d
e
OCD2 = 0
OCD2 = 1
CM02
WAIT instruction
RESET
CM10 = 1 (stop mode)
a
d
c
h
b
CM06 = 0
CM17 to CM16 = 11b
CM06 = 1
CM06 = 0
CM17 to CM16 = 10b
CM06 = 0
CM17 to CM16 = 01b
CM06 = 0
CM17 to CM16 = 00b
Detail of divider
eg
UART0Timer RETimer RBTimer RA
fOCO
fOCO-S
g
f1
f2
f4
f8
f32
INT0
Watchdog
timer
System clock
HRA2 register
Frequency adjustable
UART2
On-chip oscillator
clock
fOCO-F
XCOUT
Power-on
reset circuit
Voltage
detection
circuit
Power-on reset
Software reset
Interrupt request
CM04
XCIN
clock
Low-speed
on-chip
oscillator
CM02, CM04, CM06: Bits in CM0 register
CM10, CM14, CM16, CM17: Bits in CM1 register
OCD2: Bits in OCD register
HRA00, HRA01: Bits in HRA0 register
Stop signal
fC4
fC32
fC 1/81/4
Timer RF
HRA1 register
XCIN
Clock prescaler
R8C/2G Group 11. Clock Generation Circuit
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REJ09B0387-0100
Figure 11.2 CM0 Register
System Clock Control Register 0(1)
Symbol Address Af ter Reset
CM0 0006h 01011000b
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
4.
5. When entering stop mode, the CM06 bit is set to 1 (divide-by-8 mode).
—
(b1)
Reserved bit Set to 0. RW
CM03 XCIN-XCOUT drive capacity
select bit(2)
0 : LOW
1 : HIGH RW
CM04
b7 b6 b5 b4 b3 b2 b1 b0
0 0
—
(b0) —
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
CM02
WAIT peripheral function clock
stop bit
0 : Peripheral function clock does not stop
in w ait mode
1 : Peripheral function clock stops in w ait
mode
RW
Port, XCIN-XCOUT sw itch bit(3, 4) 0 : Ports P4_3, P4_4
1 : XCIN-XCOUT pin RW
—
(b5) —
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
CM06 System clock division select bit
0(5)
0 : CM16, CM17 enabled
1 : Divide-by-8 mode RW
—
(b7)
Reserved bit Set to 0. RW
P4_3 and P4_4 can be used as ports w hen the CM04 bit is set to 0 (ports P4_3 and P4_4).
To use the XCIN clock, set the CM04 bit to 1 (XCIN-XCOUT pin). Also, set port P4_3 as input port w ithout pull-up.
Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting the CM0 register.
When entering stop mode, the CM03 bit is set to 1 (HIGH). Rew rite the CM03 bit w hile the XCIN clock oscillation
stabilizes.
If the CM10 bit in the CM1 register is set to 1 (stop mode), w hen the CM04 bit is set to 1 (XCIN-XCOUT pin), the
XCIN(P4_3) pin is set to the high-impedance state and the XCOUT (P4_4) pin is set to “H”. When the CM04 bit is set to
0 (I/O ports P4_3 and P4_4), pins XCIN (P4_3) and XOUT (P4_4) retain the I/O status (status just before stop mode is
entered).
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REJ09B0387-0100
Figure 11.3 CM1 Register
System Clock Control Register 1(1)
Symbol Address After Reset
CM1 0007h 00h
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
4.
5.
6.
7.
8.
Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting the CM1 register.
b7 b6 b5 b4 b3 b2 b1 b0
—
(b1) —
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
CM10 All clock stop control bit(2, 3, 4) 0 : Clock operates
1 : Stops all clocks (stop mode) RW
—
(b3) —
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
CM12 XCIN-XCOUT on-chip feedback
resistor select bit
0 : On-chip feedback resistor enabled
1 : On-chip feedback resistor disabled RW
—
(b5) —
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
CM14 Low -speed on-chip oscillation stop
bit(4, 5, 6, 7)
0 : Low -speed on-chip oscillator on
1 : Low -speed on-chip oscillator of f RW
CM17 RW
b7 b6
0 0 : No division mode
0 1 : Divide-by-2 mode
1 0 : Divide-by-4 mode
1 1 : Divide-by-16 mode
System clock division select bits 1(8)
CM16 RW
When using the voltage monitor 1 interrupt or voltage monitor 2 interrupt (w hen using the digital filter), set the CM14
bit to 0 (low -speed on-chip oscillator on).
In count source protect mode enabled, the CM14 bit is set to 0 (low -speed on-chip oscillator on). It remains
unchanged even if 1 is w ritten to it.
When the CM06 bit in the CM0 register is set to 0 (bits CM16, CM17 enabled), bits CM16 to CM17 are enabled.
If the CM10 bit is set to 1 (stop mode), the on-chip feedback resistor is disabled.
If the CM10 bit is set to 1 (stop mode), w hen the CM04 bit in the CM0 register is set to 1 (XCIN-XCOUT pin), the
XCIN(P4_3) pin is set to the high-impedance state and the XCOUT (P4_4) pin is set to “H”. When the CM04 bit is set to
0 (I/O ports P4_3 and P4_4), pins XCIN (P4_3) and XOUT (P4_4) retain the I/O status (status just before stop mode is
entered).
In count source protect mode enabled of w atchdog timer (refer to 16.2 Count Source Protection Mode
Enabled), the value remains unchanged even if bits CM10 and CM14 are set.
When the OCD2 bit in the OCD register is set to 0 (XCIN clock selected), the CM14 bit is set to 1 (low -speed on-chip
oscillator of f ). When the OCD2 bit is set to 1 (on-chip oscillator clock selected), the CM14 bit is set to 0 (low -speed
on-chip oscillator on). It remains unchanged even if 1 is w ritten to it.
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REJ09B0387-0100
Figure 11 .4 OCD Register
System Clock Select Register(1)
Symbol Address Af ter Reset
OCD 000Ch 00000100b
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
b7 b6 b5 b4 b3 b2 b1 b0
000
—
(b1-b0) —
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Nothing is assigned. If necessary, set to 0.
When read, the content is 0. —
OCD2 System clock select bit 0 : Selects XCIN clock
1 : Selects on-chip oscillator clock(2) RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
—
(b3) —
The CM14 in the CM1 register bit is set to 0 (low -speed on-chip oscillator on) if the OCD2 bit is set to 1 (on-chip
oscillator clock selected).
Set the PRC0 bit in the PRCR register to 1 (w rite enable) bef ore rew riting to the OCD register.
—
(b6-b4)
Reserved bits Set to 0. RW
—
(b7)
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Figure 11.5 Registers HRA0, HRA1, and HRA2
High-Speed On-Chip Oscillator Control Register 0(1)
Symbol Address After Reset
HRA 0 0020h 00h
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
b7 b6 b5 b4 b3 b2 b1 b0
HRA 00 RW
HRA 01 RW
High-speed on-chip oscillator
enable bit
0 : High-speed on-chip oscillator of f
1 : High-speed on-chip oscillator on
High-speed on-chip oscillator
select bit(2)
0 : Selects low -speed on-chip oscillator(3)
1 : Selects high-speed on-chip oscillator
Change the HRA01 bit under the f ollow ing conditions.
• HRA00 = 1 (high-speed on-chip oscillation on)
• The CM14 bit in the CM1 register = 0 (low -speed on-chip oscillator on)
When setting the HRA01 bit to 0 (low -speed on-chip oscillator selected), do not set the HRA00 bit to 0 (high-speed
on-chip oscillator off) at the same time. Set the HRA00 bit to 0 after setting the HRA01 bit to 0.
—
(b7-b2) —
Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting the HRA0 register.
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
High-Speed On-Chip Oscillator Control Register 1(1)
Symbol Address After Reset
HRA 1 0021h When Shipping
RW
NOTES:
1.
2.
Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting the HRA1 register.
RW
Function
The frequency of the high-speed on-chip oscillator is adjusted w ith bits 0 to 7.(2)
High-speed on-chip oscillator frequency = 8 MHz
(HRA1 register = value w hen shipping; fOCO-fast mode 0)
Setting the HRA1 register to a low er value results in a higher frequency.
Setting the HRA1 register to a higher value results in a low er frequency.
When changing the values of the HRA1 register, adjust these bits not to exceed the maximum value of the system
clock.
b7 b6 b5 b4 b3 b2 b1 b0
High-Speed On-Chip Oscillator Control Register 2(1)
Symbol Address After Reset
HRA 2 0022h 00h
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3. Set this bit not to exceed the maximum value of the system clock.
RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting the HRA2 register.
Sw itching fOCO-f ast mode 0 to fOCO-f ast mode 2 multiplies the frequency by 0.5.
—
(b7-b5) —
b7 b6 b5 b4 b3 b2 b1 b0
00
HRA 21 RW
00
—
(b0) RW
High-speed on-chip oscillator
mode select bit(3)
0: fOCO-fast mode 0
(8 MHz w hen the HRA1 register is set to
the value w hen shipping )
1: fOCO-fast mode 2(2)
Reserved bit Set to 0.
—
(b4-b2)
Reserved bits Set to 0.
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REJ09B0387-0100
Figure 11.6 CPSRF Register
Figure 11.7 Registers FRA4 and FRA6
Clock Prescaler Reset Flag
Symbol Address After Reset
CPSRF 0028h 00h
Bit Symbol Bit Name Function RW
NOTE:
1. Only w rite 1 to this bit w hen selecting the XCIN clock as the CPU clock, .
CPSR Clock prescaler reset flag(1) Setting this bit to 1 initializes the clock
prescaler. (When read, the content is 0) RW
—
(b6-b0)
Reserved bits Set to 0. RW
0000000
b3 b2 b1 b0b7 b6 b5 b4
High-Speed On-Chip Oscillator Control Register 4
Symbol Address After Reset
FRA 4 0029h When Shipping
RW
RO
Function
Stores data for frequency correction w hen VCC = 2.7 to 5.5 V. (The value is the same as that
of the HRA1 register after a reset.) Optimal frequency correction to match the voltage
conditions can be achieved by transferring this value to the HRA1 register.
b3 b2 b1 b0b7 b6 b5 b4
High-Speed On-Chip Oscillator Control Register 6
Symbol Address After Reset
FRA 6 002Bh When Shipping
RW
RO
Function
Stores data for frequency correction w hen VCC = 2.2 to 5.5 V. Optimal frequency correction
to match the voltage conditions can be achieved by transferring this value to the HRA1
register.
b3 b2 b1 b0b7 b6 b5 b4
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REJ09B0387-0100
Figure 11.8 VCA2 Register
Voltage Detection Register 2(1)
Symbol Address After Reset(5)
VCA2 0032h
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
4.
5.
6.
7. When the VCA20 bit is set to 1 (low consumption enabled), do not set the CM10 bit in the CM1 register to 1 (stop
mode).
Use the VCA20 bit only w hen entering to w ait mode. To set the VCA20 bit, follow the procedure show n in Figure
11.9 Handling Procedure of Internal Power Low Consumption Using VCA20 Bit.
VCA20 Internal pow er low
consumption enable bit(6)
0 : Low consumption disabled
1 : Low consumption enabled(7) RW
Set the PRC3 bit in the PRCR register to 1 (w rite enabled) before rew riting to the VCA2 register.
To use the voltage monitor 1 interrupt/reset or the VW1C3 bit in the VW1C register, set the VCA26 bit to 1.
After the VCA26 bit is set to 1 from 0, the voltage detection circuit w aits for td(E-A) to elapse before starting
operation.
To use the voltage monitor 2 interrupt/reset or the VCA13 bit in the VCA1 register, set the VCA27 bit to 1.
After the VCA27 bit is set to 1 from 0, the voltage detection circuit w aits for td(E-A) to elapse before starting
operation.
Softw are reset, w atchdog timer reset, voltage monitor 1 reset, and voltage monitor 2 reset do not affect this
register.
To use the voltage monitor 0 reset, set the VCA25 bit to 1.
After the VCA25 bit is set to 1 from 0, the voltage detection circuit w aits for td(E-A) to elapse before starting
operation.
VCA27 Voltage detection 2 enable
bit(4)
0 : Voltage detection 2 circuit disabled
1 : Voltage detection 2 circuit enabled RW
VCA26 Voltage detection 1 enable
bit(3)
0 : Voltage detection 1 circuit disabled
1 : Voltage detection 1 circuit enabled RW
0000
b3 b2 b1 b0b7 b6 b5 b4
The LVD0ON bit in the OFS register is
set to 1 and hardw are reset : 00h
Pow er-on reset, voltage monitor 0 reset
or LVD0ON bit in the OFS register is
set to 0, and hardw are reset : 00100000b
VCA25 Voltage detection 0 enable
bit(2)
0 : Voltage detection 0 circuit disabled
1 : Voltage detection 0 circuit enabled RW
—
(b4-b1)
Reserved bits Set to 0. RW
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Figure 11.9 Handling Procedure of Internal Power Low Consumption Using VCA20 Bit
NOTES:
1. Execute this routine to handle all interrupts generated in wait mode.
However, this does not apply if it is not necessary to start high-speed on-chip oscillator during the interrupt routine.
2. Do not set the VCA20 bit to 0 with the instruction immediately after setting the VCA20 bit to 1. Also, do not do the opposite.
3. When entering wait mode, follow 11.5.2 Wait Mode.
Handling procedure of internal power
low consumption enabled by VCA20 bit
Enter low-speed clock mode or low-speed
on-chip oscillator mode
Stop high-speed on-chip oscillator clock
VCA20 ← 1 (internal power low consumption
enabled)(2)
Enter wait mode(3)
VCA20 ← 0 (internal power low consumption
disabled)(2)
Start high-speed on-chip oscillator clock
(Wait until high-speed on-chip oscillator clock
oscillation stabilizes)
In interrupt routine
VCA20 ← 0 (internal power low consumption
disabled)(2)
Start high-speed on-chip oscillator clock
Enter high-speed on-chip oscillator mode
Enter low-speed clock mode or
low-speed on-chip oscillator mode
Exit wait mode by interrupt
Stop high-speed on-chip oscillator clock
VCA20 ← 1 (internal power low consumption
enabled)(2, 3)
Interrupt handling completed
Step (1)
Step (2)
Step (3)
Step (4)
Step (5)
Step (6)
Step (7)
Step (5)
Step (6)
Step (7) (Wait until high-speed on-chip oscillator clock
oscillation stabilizes)
Step (1)
Step (2)
Step (3)
If it is necessary to start
the high-speed on-chip
oscillator in the interrupt
routine, execute steps (5)
to (8) in the interrupt
routine.
If high-speed on-chip
oscillator is started in the
interrupt routine, execute
steps (1) to (3) at the last of
the interrupt routine.
(Note 1)
Interrupt handling
VCA20: Bit in VCA2 register
Step (8)
Enter high-speed on-chip oscillator modeStep (8)
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The clocks generated by the clock generation circuits are described below.
11.1 On-Chip Oscillator Clocks
These clocks are supplied by the on-chip oscillators (high-speed on-chip oscillator and a low-speed on-chip
oscillator). The on-chip oscillator clock is selected by the HRA01 bit in the HRA0 register.
11.1.1 Low-Speed On-Chip Oscillator Clock
The clock generated by the low-speed on-chip oscillator is used as the clock source for the CPU clock,
peripheral function clock, fOCO, and fOCO-S.
After reset, the on-chip oscillator clock generated by the low-speed on-chip oscillator divided by 8 is selected as
the CPU clock.
The frequency of the low-speed on-chip oscillator var ies depending on the supply voltage and the operating
ambient temperature. Application products must be designed with sufficient margin to allow for frequency
changes.
11.1.2 High-Speed On-Chip Oscillator Clock
The clock generated by the high-speed on-chip oscillator is used as the clock source for the CPU clock,
peripheral function clock, fOCO, and fOCO-F.
After reset, the on-chip oscillator clock ge nerated by the high-speed on-chip oscillator stop s. Oscillation is
started by setting the HRA00 bit in the HRA0 register to 1 (high-speed on-chip oscillator on). The freq uency
can be adjusted by registers HRA1 and HRA2.
Furthermore, frequency correction data corresponding to the supply voltage ranges listed below is stored in
registers FRA4 and FRA6. To use separate correction values to match these voltage ranges, transfer them from
register FRA4 or FRA6 to the HRA1 register.
•FRA4 register: Stores data for frequency correction corresponding to VCC = 2.7 V to 5.5 V.
(The value is the same as that of the HRA1 register after a reset.)
•FRA6 register: Stores data for frequency correction corresponding to VCC = 2.2 V to 5.5 V.
Since there are differences in the amount of frequency adjustment among the bits in the HRA1 register, make
adjustments by changing the settings of individual bits. Adjust the HRA1 register so that the frequency of the
high-speed on-chip oscillator clock does not exceed the maximum value of the system clock.
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11.2 XCIN Clock
This clock is supplied by the XCIN clock oscillation circuit. This clock is used as the clock source for the CPU
clock, peripheral function clock. The XCIN clock oscillation circuit is configured by connecting a resonator
between the XCIN and XCOUT pins. The XCIN clock oscillation circuit includes an on-chip a feedback resistor,
which is disconnected from the oscillation circuit in stop mode in order to reduce the amount of power consumed in
the chip. The XCIN clock oscillation circuit may also be configured by feeding an externally generated clock to the
XCIN pin.
Figure 1 1.10 shows Examples of XCIN Clock Connection Circuits.
During and after reset, the XCIN clock oscillates.
The XCIN clock starts oscillating when the CM04 bit in the CM0 register is set to 1 (XCIN-XCOUT pin).
To use the XCIN clock for the CPU clock source, set the OCD2 bit in the OCD register to 0 (selects XCIN clock)
after the XCIN clock is oscillating stably.
This MCU has an on-chip feedback resistor and on-chip resistor disab le/enable switchin g is possible b y the CM12
bit in the CM1 register.
In stop mode, all clocks including the XCIN clock stop. Refer to 11.4 Power Control for details.
Figure 11.10 Examples of XCIN Clock Connection Circuits
XCIN XCOUT
MCU
(on-chip feedback resistor)
Rd(1)
COUTCIN
XCIN XCOUT
MCU
(on-chip feedback resistor)
Externally derived clock
VCC
VSS
NOTE:
1. Insert a damping resistor and feedback resistor if required. The resistance will vary depending on the oscillator and
the oscillation drive capacity setting. Use the value recommended by the manufacturer of the oscillator.
When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's
data sheet specifies that a feedback resistor be added to the chip externally, insert a feedback resistor between
XCIN and XCOUT following the instructions.
Open
External crystal oscillator circuit External clock input circuit
Rf(1)
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11.3 CPU Clock and Peripheral Function Clock
There are a CPU clock to operate the CPU and a peripheral function clock to operate the peripheral functions. Refer
to Figure 11.1 Clock Generation Circuit.
11.3.1 System Clock
The system clock is the clock source for the CPU and peripheral function clocks. Either the XCIN clock or the
on-chip oscillator clock can be selected.
11.3.2 CPU Clock
The CPU clock is an operating clock for the CPU and watchdog timer.
The system clock can b e divid ed b y 1 (no division ), 2 , 4, 8, or 16 to produce the CPU clock. Use the CM06 bit
in the CM0 register and bits CM16 to CM17 in the CM1 register to select the value of the division.
Use the XCIN clock while the XCIN clock oscillation stabilizes.
After reset, the low-speed on-chip oscill ator clock div ided by 8 prov ides the CPU clock.
When entering stop mode from high-speed clock mode, the CM06 bit is set to 1 (divide-by-8 mode).
11.3.3 Peripheral Function Clock (f1, f2, f4, f8, and f32)
The peripheral function clock is the operating clock fo r the peripheral functions.
The clock fi (i = 1, 2, 4, 8, and 32) is generated by the system clock divided by i. The clock fi is used for tim ers
RA, RB, RE, and RF, and the serial interface.
When the WAIT instruction is executed after setting the CM02 bit i n the CM0 register to 1 (peripheral function
clock stops in wait mode), the clock fi stop.
11.3.4 fOCO
fOCO is an operating clock for the peripheral functions.
fOCO runs at the same frequency as the on-chip oscillator clock and can be used as the source for timer RA.
When the WAIT instruction is executed, the clocks fOCO does not stop.
11.3.5 fOCO-F
fOCO-F is generated by the high- speed on-chip oscill ator and supplied by setti n g the HRA00 bit to 1.
When the WAIT instruction is executed, the clock fOCO-F does not stop.
11.3.6 fOCO-S
fOCO-S is an operating clock for the watchdog timer and voltage detection circuit. fOCO-S is supplied by
setting the CM14 bit to 0 (low-speed on-chip oscillator on) and uses the clock generated by the low-speed on-
chip oscillator. When the WAIT instruction is executed or in count source pro tect mode of the watchdog timer,
fOCO-S does not stop.
11.3.7 fC4 and fC32
The clock fC4 is used for timer RE and the clock fC32 is used for timer RA, ti mer RF, and watchdog timer.
Use fC4 and fC32 while the XCIN clock oscillation stabilizes.
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11.4 Power Control
There are three power control modes. All modes other than wait mode and stop mode are referred to as standard
operating mode.
11.4.1 Standard Operating Mode
Standard operating mode is further separated into three modes.
In standard operating mode, the CPU clock and the peripheral function clock are supplied to operate the CPU
and the peripheral function clocks. Power consumption control is enabled by controlling the CPU clock
frequency. The higher the CPU clock frequency, the more processing power increases. The lower the CPU
clock frequency, the more power consumption decreases. When unnecessary oscillator circuits stop, power
consumption is further reduced.
Before the clock sources for the CPU clock can be switched over, the new clock source needs to be oscillating
and stable. If the new clock source is the XCIN clock, allow sufficient wait time in a program until oscillation is
stabilized before exiting.
−: Can be 0 or 1, no change in outcome
Table 11.2 Settings and Modes of Clock Associated Bits
Modes OCD Register CM1 Register CM0 Register HRA0 Register
OCD2 CM17, CM16 CM14 CM06 CM04 HRA01 HRA00
High-speed on-chip
oscillator mode
No division 1 00b −0−11
Divide-by-2 1 01b −0−11
Divide-by-4 1 10b −0−11
Divide-by-8 1 −−1−11
Divide-by-16 1 11b −0−11
Low-speed on-chip
oscillator mode
No division 1 00b 0 0 −0−
Divide-by-2 1 01b 0 0 −0−
Divide-by-4 1 10b 0 0 −0−
Divide-by-8 1 −01−0−
Divide-by-16 1 11b 0 0 −0−
Low-speed clock
mode
No division 0 00b −01−−
Divide-by-2 0 01b −01−−
Divide-by-4 0 10b −01−−
Divide-by-8 0 −−11−−
Divide-by-16 0 11b −01−−
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11.4.1.1 High-Speed On-Chip Oscillator M o de
The high-speed on-chip oscillator is used as the on-chip oscillator clock when the HRA00 bit in the HRA0
register is set to 1 (high-speed on-chip oscillator on) and the HRA01 bit in the HRA0 register is set to 1. The on-
chip oscillator divided by 1 (no division ), 2, 4, 8, or 16 provides the CPU clo ck. Set the CM06 bit to 1 (divide-
by-8 mode) when transiting to high-speed clock mode.
When the CM14 bit is set to 0 (low-speed on-chip oscillator on), fOCO-S can be used as the watchdog timer
and voltage detection circuit.
11.4.1.2 Low-Speed On-Chip Oscillator Mode
If the CM14 bit in the CM1 register is set to 0 (low-speed on-chip oscillator on) or the HRA01 bit i n the HRA0
register is set to 0, the low-speed on-chip oscillator provides the on-chip oscillato r clock.
The on-chip oscillator clock divided by 1 (no division), 2, 4, 8 or 16 provides the CPU clock. The on-chip
oscillator clock is also the clock source for the peripheral functio n clocks.
When the CM14 bit is set to 0 (low-speed on-chip oscillator on), fOCO-S can be used as the watchdog timer
and voltage detection circuit.
In this mode, stopping the high-speed on-chip oscillator, and setting the FMR47 bit in the FMR4 register to 1
(flash memory low consumption current read mode enabled) enables low consumption operation.
To enter wait mode from low-speed on-chip oscillator mode, setting the VCA20 bit in the VCA2 register to 1
(internal power low consumptio n enabled) enables lower consumption current in wait mod e .
Refer to 21. Reducing Power Consumption for how to reduce the power consumption.
11.4.1.3 Low-Speed Clock Mode
The XCIN clock divided by 1 (no division), 2, 4, 8, or 16 provides the CPU clock. Set the CM06 bit to 1 (divide
by-8 mode) when transiting to high-speed on-chip oscillator mod e, low-speed on-chip oscillator mode. If the
CM14 bit i s set to 0 (l ow-speed on-chip os cillator on) o r the HRA00 bit in the HRA0 register is set to 1 (high
speed on-chip oscillator on), fOCO can be used as timer RA.
When the CM14 bit is set to 0 (low-speed on-chip oscillator on), fOCO-S can be used as the watchdog timer
and voltage detection circuit.
In this mode, stopping the high-speed on-chip oscillator, and setting the FMR47 bit in the FMR4 register to 1
(flash memory low consumption current read mode enabled) enables low consumption operation.
To enter wait mode from low-speed clock mode, setting the VCA20 bit in the VCA2 register to 1 (internal
power low consumption enabled) enables lowe r consum ption current in wait mode.
Refer to 21. Reducing Power Consumption for how to reduce the power consumption.
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11.4.2 Wait Mode
Since the CPU clock stops in wait mode, the CPU, which operates using the CPU clock, and the watchdog
timer , when count source protection mode is disabled, stop. The XCIN clock and on-chip oscillator clock do not
stop and the peripheral function s using these clocks continue operating.
11.4.2.1 Peripheral Function Clock Stop Function
If the CM02 bit is set to 1 (peripheral function clock stops in wait mode), the f1 , f2, f4, f 8, and f32 clocks st op
in wait mode. This reduces power consumption.
11.4.2.2 Entering Wait Mode
The MCU enters wait mode when the WAIT instruction is executed.
11.4.2.3 Pin Status in Wait Mode
The I/O port is the status before wait mode was entered is maintained.
11.4.2.4 Exiting Wait Mode
The MCU exits wait mode by a reset or a peripheral function inte rrupt .
The peripheral function interrupts are affected by the CM02 bit. When the CM02 bit is set to 0 (peripheral
function clock does not stop in wait mode), all peripheral function interrupts can be used to exit wait mode.
When the CM02 bit is set to 1 (peripheral function clock stops in wait mode), the peripheral functions using the
peripheral function clock stop operating and the peripheral functions operated by external signals or on-chip
oscillator clock can be used to exit wait mode.
Ta ble 11.3 lists Interrupts to Exit Wait Mode and Usage Conditions.
Table 11.3 Interrupts to Exit Wait Mode and Usage Conditions
Interrupt CM02 = 0 CM02 = 1
Serial interface interrupt Usable when operating with
internal or external clock
Usable when operating with external
clock
Key input interrupt Usable Usable
Timer RA interrupt Usable in all modes Can be used if there is no filter in
event counter mode.
Usable by selecting fOCO or fC32 as
count source.
Timer RB interrupt Usable in all modes (Do not use)
Timer RE interrupt Usable in all modes Usable when operating in real time
clock mode
Timer RF interrupt Usable in all modes (Do not use)
INT0, INT1, INT2, INT4 interrupt Usable Can be used if there is no filter
Voltage monitor 1 interrupt Usable Usable
Voltage monitor 2 interrupt Usable Usable
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Figure 11.11 shows the Time from Wait Mode to Interrupt Routine Execution.
When using a peripheral function interrupt to exit wait mode, set up the following before executing the WAIT
instruction.
(1) Set the interrupt priority level in bits ILVL2 to ILVL0 in the in terrup t control regist ers of the peripheral
function interrupts to be used for exiting wait mode. Set bits ILVL2 to ILVL0 of the peripheral function
interrupts that are not to be used for exiting wait mod e to 000b (interrupt disabled).
(2) Set the I flag to 1.
(3) Operate the peripheral function to be used for exiting wait mode.
When exiting by a peripheral function interrupt, the time (number of cycles) between interrupt request
generation and interrupt routine execution is determined by the settings of the FMSTP bit in the FMR0 register,
as described in Figure 11.11.
The CPU clock, when exiting wait mode by a peripheral function interrupt, is the same clock as the CPU clock
when the WAIT instruction is executed.
Figure 11.11 Time from Wait Mode to Interrupt Routine Execution
Wait mode Flash memory
activation sequence
T1
CPU clock restart sequence
T2
Interrupt sequence
T3
Interrupt request generated
Time for Interrupt
Sequence (T3) Remarks
Time until Flash Memory
is Activated (T1)
Time until CPU Clock
is Supplied (T2)
Period of CPU clock
× 20 cycles
Same as above
Following total
time is the time
from wait mode
until an interrupt
routine is
executed.
Period of system clock
× 12 cycles + 30 µs (max.)
Period of system clock
× 12 cycles
Period of CPU clock
× 6 cycles
Same as above
FMSTP Bit
FMR0 Register
0
(flash memory operates)
1
(flash memory stops)
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11.4.3 St op Mode
Since the oscillator circuits stop in stop mode, the CPU clock and peripheral function clock stop and the CPU
and peripheral functions that use these clocks stop operating. The least power required to operate the MCU is in
stop mode. If the voltage applied to the VCC pin is VRAM or more, the contents of internal RAM is
maintained.
The peripheral functions clocked by external signals conti nue operating.
Ta ble 11.4 lists Interrupts to Exit Stop Mode and Usage Conditions.
11.4.3.1 Entering Stop Mode
The MCU enters stop mode when the CM10 bit in the CM1 register is set to 1 (all clocks stop). At the same
time, the CM06 bit in the CM0 register is set to 1 (divide-by-8 mode), the CM03 bit in the CM0 register is set to
1 (XCIN clock oscillator circuit drive capacity high).
11.4.3.2 Pin Status in Stop Mode
The status before wait mode was entered is maintained.
When the CM04 bit in the CM0 register is set to 1 (XCIN-XCOUT pin), the XCIN(P4_3) pin is set to the high-
impedance state and the XCOUT (P4_4) pin is set to “H”. When the CM04 bit is set to 0 (I/O ports P4_3 and
P4_4), pins XCIN (P4_3) and XOUT (P 4_4) retain the I/O status (status just before stop mode is entered).
Table 11.4 Interrupts to Exit Stop Mode and Usage Conditions
Interrupt Usage Conditions
Key input interrupt −
INT0, INT1, INT2, INT4 interrupt Can be used if there is no filter
Timer RA interrupt When there is no filter and external pulse is counted in event counter
mode
Serial interface interrupt When external clock is selected
Voltage monitor 1 interrupt Usable in digital filter disabled mode (VW1C1 bit in VW1C register is
set to 1)
Voltage monitor 2 interrupt Usable in digital filter disabled mode (VW2C1 bit in VW2C register is
set to 1)
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11.4.3.3 Exiting Stop Mode
The MCU exits stop mode by a reset or peripheral function interrupt.
Figure 11.12 shows the Time from St op Mode to Interrupt Routine Execution.
When using a peripheral function interrupt to exit stop mode, set up the following before setti ng the CM10 bit
to 1.
(1) Set the interrupt priority level in bits ILVL2 to ILVL0 of the peripheral function interrupts to be used for
exiting stop mode . Set bit s ILVL2 to ILVL0 of th e peripheral functio n interrupts th at are not to b e used
for exiting stop mode to 000b (interrupt disabled).
(2) Set the I flag to 1.
(3) Operates the peripheral function to be used for exiting stop mode.
When exiting by a peripheral fun ction in terrup t, the in terrupt sequence is executed when an interrupt request is
generated and the CPU clock supply is started.
If the clock used immediately before stop mode is a system clock and stop mode is exited by a peripheral
function interrupt, the CPU clock becomes the prev ious system clock divided by 8.
Figure 11.12 Time fro m Stop Mode to Interrupt Routine Execution
T2
Following total
time of T0 to T4 is
the time from stop
mode until an
interrupt handling
is executed.
Flash memory
activation sequence
CPU clock restart
sequence Interrupt sequence
Oscillation time of
CPU clock source
used immediately
before stop mode
Stop
mode
T3 T4
Internal
power
stability time
T1T0
Interrupt
request
generated
150 µs
(max.)
Time until Flash Memory
is Activated (T2)
Time until CPU Clock
is Supplied (T3)
Time for Interrupt
Sequence (T4) Remarks
FMSTP Bit
FMR0 Register
Period of CPU clock
× 6 cycles
Period of CPU clock
× 20 cycles
Period of system clock
× 12 cycles + 30 µs (max.)
Period of system clock
× 12 cycles Same as above Same as above
0
(flash memory operates)
1
(flash memory stops)
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Figure 11.13 shows the State Transit ion s in Power Control Mode.
Figure 11.13 State Transitions in Power Control Mode
CM10 = 1
CPU operation stops
Stop mode
Reset
Wait mode
Low-speed on-chip oscillator mode
CM14 = 0
OCD2 = 1
HRA01 = 0
High-speed on-chip oscillator mode
OCD2 = 1
HRA00 = 1
HRA01 = 1
Standard operating mode
HRA00 = 1
HRA01 = 1
CM14 = 0
HRA01 = 0
All oscillators stop
InterruptWAIT instructionInterrupt
CM04: Bit in CM0 register
CM10, CM14: Bits in CM1 register
OCD2: Bit in OCD register
HRA00, HRA01: Bits in HRA0 register
Low-speed clock mode
CM04 = 1
OCD2 = 0
CM14 = 0
OCD2 = 1
HRA01 = 0
CM04 = 1
OCD2 = 0
OCD2 = 1
HRA00 = 1
HRA01 = 1
CM04 = 1
OCD2 = 0
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11.5 Notes on Clock Generation Circuit
11.5.1 St op Mode
When entering stop mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and the
CM10 bit in the CM1 register to 1 (stop mode). An instruction queue pre-reads 4 bytes from the instr uction
which sets the CM10 bit to 1 (stop mode) and the program stops.
Insert at least 4 NOP instructions following the JMP.B instruction after the instruction which sets th e CM10 b it
to 1.
• Program example to enter stop mode
BCLR 1,FMR0 ; CPU rewrite mode disabled
BSET 0,PRCR ; Protect disabled
FSET I ; Enable interrupt
BSET 0,CM1 ; Stop mode
JMP.B LABEL_001
LABEL_001 :
NOP
NOP
NOP
NOP
11.5.2 Wait Mode
When entering wait m ode, set the FMR01 bit in the FMR0 regist er to 0 (CPU rewrite mode disabled) and
execute the WAIT instruction. An instruct ion queue pre-reads 4 bytes from the WAIT instruction and the
program stops. Insert at least 4 NOP instructions after the WAIT instruction.
• Program example to execute the WAIT instru ction
BCLR 1,FMR0 ; CPU rewrite mode disabled
FSET I ; Enable interrupt
WAIT ; Wait mo de
NOP
NOP
NOP
NOP
11.5.3 Oscillation Circuit Constants
Ask the manufacturer of the oscillator to specify the best oscillation circuit constants for your system.
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12. Protection
The protection function protects important registers from being easily overwritten when a program runs out of control.
Figure 12.1 shows the PRCR Register. The registers protected by the PRCR register are listed below.
• Registers protected by PRC0 bit: Registers CM0, CM1, OCD, HRA0, HRA1, and HRA2
• Registers protected by PRC1 bit: Registers PM0 and PM1
• Registers protected by PRC2 bit: PD0 register
• Registers protected by PRC3 bit: Registers VCA2, VW0C, VW1C, VW2C, VCAB, BGRCR, and BGRTRM
Figure 12.1 PRCR Register
Protect Register
Symbol Address After Reset
PRCR 000Ah 00h
Bit Symbol Bit Name Function RW
NOTE:
1. This PRC2 bit is set to 0 after w riting 1 to this bit and executing a w rite to any address. Since the other bits are not
set to 0, set them to 0 by a program.
PRC2
Protect bit 2 Writing to the PD0 register is enabled.
0 : Disables w riting
1 : Enables w riting(1)
RW
RW
—
(b5-b4)
Reserved bits Set to 0. RW
PRC0 RW
PRC1 RW
Protect bit 0 Writing to registers CM0, CM1, OCD, HRA0, HRA1,
and HRA2 is enabled.
0 : Disables w riting
1 : Enables w riting
Protect bit 1 Writing to registers PM0 and PM1 is enabled.
0 : Disables w riting
1 : Enables w riting
00
b3 b2 b1 b0b7 b6 b5 b4
—
PRC3
Protect bit 3 Writing to registers VCA2, VW0C, VW1C, VW2C,
VCAB, BGRCR, and BGRTRM is enabled.
0 : Disables w riting
1 : Enables w riting
—
(b7-b6)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
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13. Interrupts
13.1 Interrupt Overview
13.1.1 Types of Interrupts
Figure 13.1 shows the Types of Interrupts.
Figure 13.1 Types of Interrupts
•Maskable Interrupts: The interrupt enable flag (I flag) enables or disables these interrupts. The
interrupt priority order can be changed based on the interrupt priority level.
•Non-Maskable Interrupts: The interrupt en able flag (I flag) does not enable or disable these interrupts.
The interrupt priority order cannot be changed based on interrupt priority
level.
Interrupts
(non-maskable interrupts)
Hardware
Software
(non-maskable interrupts)
(maskable interrupts)
Special
Peripheral functions(1)
Undefined instruction (UND instruction)
Overflow (INTO instruction)
BRK instruction
INT instruction
Watchdog timer
Voltage monitor 1
Voltage monitor 2
Comparator 1(2)
Comparator 2(2)
Single step(3)
Address break(3)
Address match
NOTES:
1. Peripheral function interrupts in the MCU are used to generate peripheral interrupts.
2. When non-maskable interrupts is selected.
3. Do not use this interrupt. This is for use with development tools only.
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13.1.2 Software Interrupts
A software interrupt is generated when an instructio n is executed. Software interrupts are non-maskable.
13.1.2.1 Undefined Instruction Interrupt
The undefined instruction interrup t is generat e d when the UND instruction is executed.
13.1.2.2 Overflow Interrupt
The overflow interrupt is generated when the O flag is set to 1 (arithmetic operation overflow) and the INTO
instruction is executed. Instructions that set the O flag are: ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX,
NEG, RMPA, SBB, SHA, and SUB.
13.1.2.3 BRK Interrupt
A BRK interrupt is generated when the BRK instruction is executed.
13.1.2.4 INT Instruction Interrupt
An INT instruction int errupt is generated when the INT instruction is executed. The INT instruction can select
software interrupt numbers 0 to 63. Software interrupt numbers 3 to 31 are assigned to the peripheral function
interrupt. Therefore, the M CU executes the same interrupt routine when the INT instruction is executed as
when a peripheral function interrupt is generated. For software interrupt numbers 0 to 31, the U flag is saved to
the stack during instruction execution and the U flag is set to 0 (ISP selected) before the interrupt sequence is
executed. The U flag is restored from the stack when returning from the interrupt routine. For software interrupt
numbers 32 to 63, the U flag does not change state during instruction execution, and the selected SP is used.
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13.1.3 Special Interrupts
Special interrupts are non-maskable. However, the comparator 1 and comparator 2 can select maskable
interrupts, too.
13.1.3.1 Watchdog Timer Interrupt
The watchdog timer interrupt is generated by the watchdog timer. For details of the watchdog timer, refer to 16.
Watchdog Timer.
13.1.3.2 Voltage Monitor 1 Interrupt
The voltage monito r 1 interrupt is generated by the v oltage monitor 1 circuit. For deta ils of the voltage monitor
1 circuit, refer to 6. Voltage Detection Circuit.
13.1.3.3 Voltage Monitor 2 Interrupt
The voltage monito r 2 interrupt is generated by the v oltage monitor 2 circuit. For deta ils of the voltage monitor
2, refer to 6. Voltage Detection Circuit .
13.1.3.4 Comparator 1 Interrupt
The comparator 1 interrupt is generated by the comparator 1. The non-maskable interrupt or maskable interrupt
can be selected. For details of the comparator 1 interrupt, refer to 7. Comparator.
13.1.3.5 Comparator 2 Interrupt
The comparator 2 interrupt is generated by the comparator 2. The non-maskable interrupt or maskable interrupt
can be selected. For details of the comparator 2 interrupt, refer to 7. Comparator.
13.1.3.6 Single-Step Interrupt, and Address Break Interrupt
Do not use these interrupts. They are for use by develo pm ent tools only.
13.1.3.7 Address Match Interrupt
The address match interrupt is generat ed immediately before executing an instruction that is stored at an
address indicated by registers RMAD0 to RMAD1 when the AIER0 or AIER 1 bit in the AIER reg ister is set to
1 (address match interrupt enable). For details of the address match in terrupt, refer to 13.4 Address Match
Interrupt.
13.1.4 Peripheral Function Interrupt
The peripheral function interrupt is generated by the internal peripheral function o f the MCU and is a maskable
interrupt. Refer to Table 13.2 Relocatable Vector Tables for sources of the peripheral function interrupt. For
details of peripheral functions, refer to th e descript ions of individual peripheral functions.
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13.1.5 Interrupts and Interrupt Vectors
There are 4 bytes in each vector. Set the starting address of an interrupt routine in each interrupt vector. When
an interrupt request is acknowledged, the CPU branches to the address set in the corresponding interrupt vector.
Figure 13.2 shows an Interrupt Vector.
Figure 13.2 Interrupt Vector
13.1.5.1 Fixed Vector Tables
The fixed vector tables are allocated addresses 0FFDCh to 0FFFFh.
Table 13.1 lists the Fixed Vector Tables. The vector address es (H) of fixed vectors are used by the ID code
check function. For details, refer to 20.3 Functions to Prevent Rewriting of Flash Memory .
NOTE:
1. Do not use these interrupts. They are for use by development tools only.
Table 13.1 Fixed Vector Tables
Interrupt Source Vector Addresses
Address (L) to (H) Remarks Reference
Undefined instruction 0FFDCh to 0FFDFh Interrupt on UND
instruction
R8C/Tiny Series Software
Manual
Overflow 0FFE0h to 0FFE3h Interrupt on INTO
instruction
BRK instruction 0FFE4h to 0FFE7h If the content of address
0FFE7h is FFh,
program execution
starts from the address
shown by the vector in
the relocatable vector
table.
Address match 0FFE8h to 0FFEBh 13.4 Address Match
Interrupt
Single step(1) 0FFECh to 0FFEFh
Watchdog timer,
Voltage monitor 1,
Voltage monitor 2,
Comparator 1,
Comparator 2
0FFF0h to 0FFF3h 16. Watchdog Timer
6. Voltage Detection Circuit
7. Comparator
Address break(1) 0FFF4h to 0FFF7h
(Reserved) 0FFF8h to 0FFFBh
Reset 0FFFCh to 0FFFFh 5. Resets
Vector address (L)
Vector address (H)
MSB LSB
Low address
Mid address
High address0 0 0 0
0 0 0 0 0 0 0 0
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13.1.5.2 Relocatable Vector Tables
The relocatable vector tables occupy 256 bytes beginning from the starting address set in the INTB register.
Table 13.2 lists the Relocatable Vector Tables.
NOTES:
1. These addresses are relative to those in the INTB register.
2. The I flag does not disable these interrupts.
Ta b le 13 .2 Relocatable Vector Tables
Interrupt Source Vector Addresses(1)
Address (L) to Address (H)
Software
Interrupt
Number
Interrupt Control
Register Reference
BRK instruction(2) +0 to +3(0000h to 0003h) 0 −R8C/Tiny Series Software
Manual
Comparator 1 +4 to +7(0004h to 0007h) 1 VCMP1IC 7. Comparator
Comparator 2 +8 to +11(0008h to 000Bh) 2 VCMP2IC
(Reserved) 3 to 9 −−
Timer RE +40 to +43(0028h to 002Bh) 10 TREIC 17.3 Timer RE
UART2 transmit +44 to +47(002Ch to 002Fh) 11 S2TIC 18. Serial Interface
UART2 receive +48 to +51(0030h to 0033h) 12 S2RIC
Key input +52 to +55(0034h to 0037h) 13 KUPIC 13.3 Key Input Interrupt
(Reserved) 14 −−
(Reserved) 15 −−
Compare 1 +64 to +67(0040h to 0043h) 16 CMP1IC 17.4 Timer RF
UART0 transmit +68 to +71(0044h to 0047h) 17 S0TIC 18. Serial Interface
UART0 receive +72 to +75(0048h to 004Bh) 18 S0RIC
(Reserved) 19 −−
(Reserved) 20 −−
INT2 +84 to +87(0054h to 0057h) 21 INT2IC 13.2 INT Interrupt
Timer RA +88 to +91(0058h to 005Bh) 22 TRAIC 17.1 Timer RA
(Reserved) 23 −−
Timer RB +96 to +99(0060h to 0063h) 24 TRBIC 17.2 Timer RB
INT1 +100 to +103(0064h to 0067h) 25 INT1IC 13.2 INT Interrupt
(Reserved) 26 −
Timer RF +108 to +111(006Ch to 006Fh) 27 TRFIC 17.4 Timer RF
Compare 0 +112 to +115(0070h to 0073h) 28 CMP0IC
INT0 +116 to +119(0074h to 0077h) 29 INT0IC 13.2 INT Interrupt
INT4 +120 to +123(0078h to 007Bh) 30 INT4IC
Capture +124 to +127(007Ch to 007Fh) 31 CAPIC 17.4 Timer RF
Software interrupt(2) +128 to +131(0080h to 0083h) to
+252 to +255(00FCh to 00FFh)
32 to 63 −R8C/Tiny Series Software
Manual
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13.1.6 Interrupt Control
The following describes enabling and disabling the maskable interrupts and setting the priority for
acknowledgement. The explanation does not apply to nonmaskable interrupts.
Use the I flag in the FLG register, IP L, and bits ILVL2 to ILVL0 in each interrupt control register to enable or
disable maskable interrupts. Whether an interrupt is requested is indicated by the IR bit in each interrupt control
register.
Figure 13.3 shows the Interrupt Control Register and Figure 13.4 shows the INTiIC Register (i=0, 1, 2, 4).
Figure 13.3 Interrupt Control Register
Interrupt Control Register(2)
Address Af ter Reset
0041h XXXXX000b
0042h XXXXX000b
004Ah XXXXX000b
004Bh XXXXX000b
004Ch XXXXX000b
004Dh XXXXX000b
0050h XXXXX000b
0051h XXXXX000b
0052h XXXXX000b
0056h XXXXX000b
0058h XXXXX000b
005Bh XXXXX000b
005Ch XXXXX000b
005Fh XXXXX000b
Bit Symbol Function RW
NOTES:
1.
2.
TRFIC
S0TIC
S0RIC
TRA IC
TRBIC
S2TIC
S2RIC
KUPIC
CMP1IC
Only 0 can be w ritten to the IR bit. Do not w rite 1.
IR 0 : Requests no interrupt
1 : Requests interrupt RW(1)
—
(b7-b4) —
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined.
RW
b2 b1 b0
0 0 0 : Level 0 (interrupt disable)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
ILV L1 RW
ILV L2 RW
Rew rite the interrupt control register w hen the interrupt request w hich is applicable for its register is not generated.
Ref er to 13.5.5 Changing Interrupt Control Register Contents.
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Bit Name
Interrupt priority level select bits
Interrupt request bit
ILV L0
CA PIC
CMP0IC
VCMP1IC
VCMP2IC
TREIC
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Figure 13.4 INTiIC Register (i=0, 1, 2, 4)
INTi Interrupt Control Register (i=0, 1, 2, 4)(2)
Symbol Address After Reset
INT2IC 0055h XX00X000b
INT1IC 0059h XX00X000b
INT0IC 005Dh XX00X000b
INT4IC 005Eh XX00X000b
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
4.
Rew rite the interrupt control register w hen the interrupt request w hich is applicable for the register is not generated.
Ref er to 13.5.5 Changing Interrupt Control Register Contents.
If the INTiPL bit in registers INTEN and INTEN2 are set to 1 (both edges), set the POL bit to 0 (selects falling edge).
The IR bit may be set to 1 (requests interrupt) w hen the POL bit is rew ritten. Refer to 13.5.4 Changing Interrupt
Sources.
b7 b6 b5 b4 b3 b2 b1 b0
0
ILV L0 RW
Interrupt priority level select bits b2 b1 b0
0 0 0 : Level 0 (interrupt disable)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
ILV L1 RW
ILV L2 RW
IR Interrupt request bit 0 : Requests no interrupt
1 : Requests interrupt RW(1)
POL Polarity sw itch bit(4) 0 : Selects falling edge
1 : Selects rising edge(3) RW
—
(b5)
Reserved bit Set to 0. RW
—
(b7-b6) —
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined.
Only 0 can be w ritten to the IR bit. (Do not w rite 1.)
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13.1.6.1 I Flag
The I flag enables or disables maskable interrupts. Setting the I flag to 1 (enabl ed) enables maskable interrupt s.
Setting the I flag to 0 (disabled) disables all maskable interrupts.
13.1.6.2 IR Bit
The IR bit is set to 1 (interrupt requested) when an interrupt request is generated. Then, when the interrupt
request is acknowledged and the CPU branches to the corresponding interrupt vector, the IR bit is set to 0 (=
interrupt not request ed).
The IR bit can be set to 0 by a program. Do not write 1 to this bit.
13.1.6.3 ILVL2 to ILVL0 Bits and IPL
Interrupt priority levels can be set using bits ILVL2 to ILVL0.
Table 13.3 lists the Settings of Interrupt Priority Levels and Table 13.4 lists the Interrupt Priority Levels
Enabled by IPL.
The following are conditions under which an interrup t is acknowledged:
•I flag = 1
•IR bit = 1
•Interrupt priority level > IPL
The I flag, IR bit, bits ILVL2 to ILVL0, and IPL are independent of each other. They do not affect one another.
Table 13.3 Settings of Interrupt Priority
Levels
ILVL2 to ILVL0 Bits Interrupt Priority Level Priority Order
000b Level 0 (interrupt disabled) −
001b Level 1 Low
010b Level 2
011b Level 3
100b Level 4
101b Level 5
110b Level 6
111b Level 7 High
T able 13.4 Interrupt Priority Levels Enabled by
IPL
IPL Enabled Interrupt Priority Levels
000b Interrupt level 1 and above
001b Interrupt level 2 and above
010b Interrupt level 3 and above
011b Interrupt level 4 and above
100b Interrupt level 5 and above
101b Interrupt level 6 and above
110b Interrupt level 7 and above
111b All maskable interrupts are disabled
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13.1.6.4 Interrupt Sequence
An interrupt sequence is p erformed between an interrupt request acknowled gement and interrupt routine
execution.
When an interrupt request is generated while an instruction is being executed, the CPU det ermines it s interrupt
priority level after the instruction is completed. The CPU starts the interrupt sequence from the following cycle.
However, for the SMOVB, SMOVF, SSTR, or RMPA instructions, if an interrupt request is generated while the
instruction is being executed, the MCU su spends the instruction to start the inter rupt sequence. The interrup t
sequence is performed as indicated below.
Figure 13.5 show s th e Time Required for Executing Interrupt Sequence.
(1) The CPU gets interrupt information (interrupt number and interrupt request level) by reading address
00000h. The IR bit for the corresponding interru pt is set to 0 (interrupt not requested).
(2) The FLG register is saved to a temporary register(1) in the CPU immediately before entering the
interrupt sequence.
(3) The I, D and U flags in the FLG register are set as follows:
The I flag is set to 0 (interrupts disabled).
The D flag is set to 0 (single-step interrupt disabled).
The U flag is set to 0 (ISP selected).
However, the U flag does not change state if an INT instruction for software interrupt n umber 32 to 63
is executed.
(4) The CPU’s internal temporary regi ster(1) is saved to the stack.
(5) The PC is saved to the stack.
(6) The interrupt priority level of the acknowledged interrupt is set in the IPL.
(7) The starting address of the interrupt routine set in the interrupt vecto r is stored in the PC.
After the inte rrupt sequence is compl eted, instructions are executed from the starting address of the interrupt
routine.
Figure 13.5 Time Required for Executing Interrupt Sequence
NOTE:
1. This register cannot be used by user.
1234567891011 12 13 14 15 16 17 18 19 20
CPU Clock
Address Bus
Data Bus
RD
WR
Address
0000h Undefined
Undefined
Undefined
Interrupt
information
SP-2 SP-1 SP-4 SP-3 VEC VEC+1 VEC+2 PC
SP-2
contents SP-1
contents SP-4
contents SP-3
contents VEC
contents VEC+1
contents VEC+2
contents
The indeterminate state depends on the instruction queue buffer. A read cycle occurs when the instruction queue buffer is
ready to acknowledge instructions.
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13.1.6.5 Interrupt Response Time
Figure 13.6 shows the Interrupt Respo nse Time. The interr upt response time is the period between an interrupt
request generation and the execution of the first i nstructio n in the int errupt routine. The int errupt response ti me
includes the period between interrupt request generation and the completion of execution of the instruction
(refer to (a) in Figure 13.6) and the period required to perform the interrupt sequence (20 cycles, refer to (b) in
Figure 13.6).
Figure 13.6 Interrupt Response Time
13.1.6.6 IPL Change when Interrupt Request is Acknowledged
When an interrupt request of a maskable interrupt is acknowledged, the interrupt priority level of the
acknowledged interrupt is set in the IPL.
When a software interrupt or special interrupt request is acknowledged, the level listed in Table 13.5 is set in the
IPL.
Ta ble 13.5 lists the IPL Value When Software or Special Interrupt Is Acknowledged.
NOTE:
1. When non-maskable interrupts is selected.
Table 13.5 IPL Value When Software or Special Interrupt Is Acknowledged
Interrupt Source Value Set in IPL
Watchdog timer, voltage monitor 1, voltage monitor 2,
comparator 1(1), comparator 2(1), address break
7
Software, address match, single-step Not changed
Interrupt request is generated. Interrupt request is acknowledged.
Instruction Interrupt sequence Instruction in
interrupt routine
Time
(a) 20 cycles (b)
Interrupt response time
(a) Period between interrupt request generation and the completion of execution of an
instruction. The length of time varies depending on the instruction being executed. The
DIVX instruction requires the longest time, 30 cycles (no wait and when the register is set
as the divisor)
(b) 21 cycles for address match and single-step interrupts.
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13.1.6.7 Saving a Register
In the interrupt sequence, the FLG register and PC are saved to the stack.
After an extended 16 bits, 4 high-order bits in the PC and 4 high-order (IPL) and 8 low-order bits in the FLG
register, are saved to the stack, the 16 low-ord e r bits in the PC are saved.
Figure 13.7 shows the Stack State Before and After Acknowledg e ment of Interrupt Request.
The other necessary registers are saved by a program at the beginning of the interrupt routine. The PUSHM
instruction can save several registers in the register bank being currently used(1) with a single instruction.
NOTE:
1. Selectable from registers R0, R1, R2, R3, A0, A1, SB, and FB .
Figure 13.7 Stack State Before and After Acknowledgement of Interrupt Request
The register saving operation, wh ich is performed as part o f the interrupt sequence, saved in 8 bits at a time in
four steps.
Figure 13.8 shows the Register Saving Operation.
Figure 13.8 Register Saving Operation
Stack
[SP]
SP value before
interrupt is generated
Previous stack contents
LSBMSB
Address
Previous stack contents
m−4
m−3
m−2
m−1
m
m+1
Stack state before interrupt request
is acknowledged
[SP]
New SP value
Previous stack contents
LSBMSB
Previous stack contents
m
m+1
Stack state after interrupt request
is acknowledged
PCL
PCM
FLGL
FLGH PCH
m−4
m−3
m−2
m−1
Stack
Address
PCH : 4 High-order bits of PC
PCM : 8 Middle-order bits of PC
PCL : 8 Low-order bits of PC
FLGH : 4 High-order bits of FLG
FLGL : 8 Low-order bits of FLG
NOTE:
1.When executing software number 32 to 63 INT instructions,
this SP is specified by the U flag. Otherwise it is ISP.
Stack
Completed saving
registers in four
operations.
Address
[SP]−5
[SP]
PCL
PCM
FLGL
FLGH PCH
(3)
(4)
(1)
(2)
Saved, 8 bits at a time
Sequence in which
order registers are
saved
NOTE:
1. [SP] indicates the initial value of the SP when an interrupt request is acknowledged.
After registers are saved, the SP content is [SP] minus 4. When executing
software number 32 to 63 INT instructions, this SP is specified by the U
flag. Otherwise it is ISP.
[SP]−4
[SP]−3
[SP]−2
[SP]−1
PCH : 4 High-order bits of PC
PCM : 8 Middle-order bits of PC
PCL : 8 Low-order bits of PC
FLGH : 4 High-order bits of FLG
FLGL : 8 Low-order bits of FLG
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13.1.6.8 Returning from an Interrupt Routine
When the REIT instruction is executed at the end of an interrupt routine, the FLG register and PC, which have
been saved to the stack, are automatically restored. The program, that was running before the i nterrupt request
was acknowledged, starts running again.
Restore registers saved by a program in an interrupt routine using the POPM instruction or others before
executing the REIT instruction.
13.1.6.9 Interrupt Priority
If two or more interrupt requests are generated while a single instruction is being executed, the interrupt with
the higher priority is acknowledged.
Set bits ILVL2 to ILVL0 to select the desired priority level for maskable interrupts (peripheral functions).
However, if two or more maskable interrupts have the same priority level, th eir interrupt priori ty is resolv ed by
hardware, and the higher priority interrupts acknowledged.
The priority levels of special interrupts, such as reset (reset has the highest priority) and watchdog timer, are set
by hardware.
Figure 13.9 shows the Priority Levels of Hard ware Interrupts.
The interrupt priori ty does not affect software interrupts. The MCU jumps to the interrup t routine when the
instruction is executed.
Figure 13.9 Priority Levels of Hardware Interrupts
Address break
Watchdog timer
Voltage monitor 1
Voltage monitor 2
Comparator 1(1)
Comparator 2(1)
Peripheral function
Single step
Address match
High
Low
Reset
NOTE:
1. When non-maskable interrupts is selected.
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13.1.6.10 Interrupt Priority Judgement Circuit
The interrupt priority ju dgem e nt circuit selects the highest priority interrupt, as shown in Figure 13.10.
Figure 13.10 Interrupt Priority Level Judgement Circuit
Compare 0
Timer RB
Timer RA
INT0
Timer RF
UART0 receive
Compare 1
UART2 receive
UART0 transmit
UART2 transmit
IPL
Priority level of interrupt
Level 0 (default value)
Lowest
Highest
Priority of peripheral function interrupts
(if priority levels are same)
Interrupt request level
judgment output signal
Interrupt request
acknowledged
I flag
Address match
Watchdog timer
Voltage monitor 1
Voltage monitor 2
INT2
Timer RE
INT1
Comparator 1(2)
INT4
Comparator 2(1)
Capture
Key input
Comparator 1(1)
Comparator 2(2)
NOTES:
1. When maskable interrupts is selected.
2. When non-maskable interrupts is selected.
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13.2 INT Interrupt
13.2.1 INTi Interrupt (i = 0, 1, 2, 4)
The INTi interrupt is ge nerat e d by an INTi input. Table 13.6 list s the Pin Configuration of INT Interrupt. When
using the INTi interrupt, the INTiEN bit in registers INTEN and INTEN2 are set to 1 (enable). The edge
polarity is selected using the INTiPL bit in registers INTEN and INTEN2, and the POL bit in the INTiIC
register.
Inputs can be passed through a digital filter wit h three di fferent sampling clocks.
Figure 13.11 shows the INTEN Register. Figure 13.12 shows the INTF Register. Figure 13.13 shows the
INTEN2 Register. Figure 13.14 shows the IN TF2 Register.
NOTE:
1. The INT1 pin is selected by the INT1SEL bit in the PMR register and the TIOSEL bit in the TRAIOC
register. Refer to 8. I/O Ports for details.
Figure 13.11 INTEN Register
Table 13.6 Pin Configuration of INT Interrupt
Pin name Input/Output Function
INT0 (P4_5) Input INT0 interrupt input, Timer RB external trigger input
INT1 (P1_5, P1_7, or P3_6)(1) Input INT1 interrupt input
INT2 (P3_2) Input INT2 interrupt input
INT4 (P0_6) Input INT4 interrupt input
External Input Enable Register
Symbol Address After Reset
INTEN 00F9h 00h
Bit Symbol Bit Name Function RW
INT0
_
____ input enable bit
INT0
_
____ input polarity select bit(1, 2)
INT1
_
____ input enable bit
INT1
_
____ input polarity select bit(1, 2)
INT2
_
____ input enable bit
INT2
_
____ input polarity select bit(1, 2)
NOTES:
1.
2.
0
—
(b7-b6)
b3 b2 b1 b0b7 b6 b5 b4
0
RW
INT0EN
RW
INT1PL 0 : One edge
1 : Both edges RW
INT2PL
When setting the INTiPL bit (i = 0, 1, 2) to 1 (both edges), set the POL bit in the INTiIC register to 0 (selects falling
edge).
The IR bit in the INTiIC register may be set to 1 (requests interrupt) w hen the INTiPL bit is rew ritten. Refer to 13.5.4
Changing Interrupt Sources.
0 : Disable
1 : Enable
0 : One edge
1 : Both edges
Set to 0.
RW
INT0PL RW
INT1EN 0 : Disable
1 : Enable
Reserved bits
RW
INT2EN RW
0 : One edge
1 : Both edges
0 : Disable
1 : Enable
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Figure 13.1 2 INTF Regist er
Figure 13.13 INTEN2 Register
INT
_
____
Input Filter Select Registe
r
Symbol Address Af ter Reset
INTF 00FAh 00h
Bit Symbol Bit Name Function RW
INT0
_____ input filter select bits
INT1
_____ input filter select bits
INT2
_
____ input filter select bits
RW
0
—
(b7-b6)
INT2F1
0
b1 b0
0 0 : No filter
0 1 : Filter w ith f1 sampling
1 0 : Filter w ith f8 sampling
1 1 : Filter w ith f32 sampling
RW
INT0F1 RW
RW
INT2F0 RW
INT1F0
b3 b2
0 0 : No filter
0 1 : Filter w ith f1 sampling
1 0 : Filter w ith f8 sampling
1 1 : Filter w ith f32 sampling
RW
INT1F1
Set to 0.
b5 b4
0 0 : No filter
0 1 : Filter w ith f1 sampling
1 0 : Filter w ith f8 sampling
1 1 : Filter w ith f32 sampling
RW
b7 b6 b5 b4 b3 b2 b1
Reserved bits
INT0F0
b0
External Input Enable Register 2
Symbol Address After Reset
INTEN2 02FDh 00h
Bit Symbol Bit Name Function RW
INT4
_
____ input enable bit
INT4
_
____ input polarity select bit(1, 2)
NOTES:
1.
2.
—
(b7-b2)
b3 b2 b1 b0b7 b6 b5 b4
—
INT4EN
When setting the INT4PL bit to 1 (both edges), set the POL bit in the INT4IC register to 0 (selects falling edge).
The IR bit in the INT4IC register may be set to 1 (requests interrupt) w hen the INT4PL bit is rew ritten. Refer to 13.5.4
Changing Interrupt Sources.
0 : Disable
1 : Enable
0 : One edge
1 : Both edges
RW
INT4PL RW
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined.
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Figure 13.14 INTF2 Register
INT
_
____
Input Filter Select Register 2
Symbol Address Af ter Reset
INTF2 02FEh 00h
Bit Symbol Bit Name Function RW
INT4
_____ input filter select bits
—
(b7-b2)
b1 b0
0 0 : No filter
0 1 : Filter w ith f1 sampling
1 0 : Filter w ith f8 sampling
1 1 : Filter w ith f32 sampling
—
RW
INT4F1 RW
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined.
b7 b6 b5 b4 b3 b2 b1
INT4F0
b0
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13.2.2 INTi Input Filter (i = 0, 1, 2, 4)
The INTi input contains a digital filter. The sam pling clock is selected by bits INTiF1 to INTiF0 in registers
INTF and INTF2. The IR bit in th e INTiI C register is set to 1 (interrupt requested) when the INTi level is
sampled for every sampling clock and the sampled input level matches three times.
Figure 13.15 sh ows the Configuration of INTi Input Filter. Figure 13.16 shows an Operating Example of INTi
Input Filter.
Figure 13.15 Configuration of INTi Input Filter
Figure 13.16 Operating Example of INTi Input Filter
INTiF0, INTiF1: Bits in registers INTF and INTF2
INTiEN, INTiPL: Bits in registers INTEN and INTEN2
i = 0, 1, 2, 4
= 01b
INTi
Port direction
register(1)
Sampling clock
Digital filter
(input level
matches 3x)
INTi interrupt
= 10b
= 11b
f32
f8
f1
INTiF1 to INTiF0
INTiEN
Other than
INTiF1 to INTiF0
= 00b
= 00b INTiPL = 0
INTiPL = 1
NOTE:
1. INT0: Port P4_5 direction register
INT1: Port P1_5 direction register when using the P1_5 pin,
Port P1_7 direction register when using the P1_7 pin,
Port P3_6 direction register when using the P3_6 pin
INT2: Port P3_2 direction register
INT4: Port P0_6 direction register
Both edges
detection
circuit
INTi input
Sampling
timing
IR bit in
INTiIC register
Set to 0 by a program
NOTE:
1. This is an operation example when bits INTiF1 to INTiF0 in registers INTF and INTF2 are set to 01b, 10b, or 11b
(passing digital filter).
i = 0, 1, 2, 4
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13.3 Key Input In terrupt
A key input interrupt request is generated by one of the input edges of the K10 to K13 pins. Table 13.7 lists the Pin
Configuration of Key Input Interrupt. The key input interrupt can be used as a key-on wake-up function to exit wait
or stop mode.
The KIiEN (i = 0 to 3) bit in the KIEN register can select whether the pins are used as KIi input. The KIiPL bit in
the KIEN register can select the input polarity.
When inputting “L” to the KIi pin which sets the KIiPL bit to 0 (falling edge), the input of the other pins K10 to
K13 is not detected as interrupts. Also, when inputting “H” to the KIi pin, which sets the KIiPL bit to 1 (rising
edge), the input of the other pins K10 to K13 is not detected as interrupts.
Figure 13.17 shows a Block Diag ram of Key In put Interrupt and Figure 13.18 shows the KIEN Register.
NOTES:
1. The KI0 pin is selected by the KI0SEL bit in the PINSR4 register. Refer to 8. I/O Ports for details.
2. The KI1 pin is selected by the KI1SEL bit in the PINSR4 register. Refer to 8. I/O Ports for details.
Figure 13.17 Block Diagram of Key Input Interrupt
Table 13.7 Pin Configuration of Key Input Interrupt
Pin name Input/Output Function
KI0 (P0_7 or P1_0(1))Input KI0 input
KI1 (P1_1 or P6_6(2))Input KI1 input
KI2 (P1_2) Input KI2 input
KI3 (P1_3) Input KI3 input
KI3
Pull-up
transistor
KI2
Pull-up
transistor
KI3PL = 0
KI3PL = 1
PD1_3 bit
KI3EN bit
PU02 bit in PUR0 register
PD1_3 bit in PD1 register
KUPIC register
Interrupt control
circuit
Key input interrupt
request
KI2PL = 0
KI2PL = 1
PD1_2 bit
KI2EN bit
KI1
Pull-up
transistor KI1PL = 0
KI1PL = 1
PD1_1 bit
KI1EN bit
KI0
Pull-up
transistor KI0PL = 0
KI0PL = 1
PD1_0 bit
KI0EN bit KI0EN, KI1EN, KI2EN, KI3EN,
KI0PL, KI1PL, KI2PL, KI3PL: Bits in KIEN register
PD1_0, PD1_1, PD1_2, PD1_3: Bits in PD1 register
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Figure 13.1 8 KIEN Register
Key Input Enable Register(1)
Symbol Address After Reset
KIEN 00FBh 00h
Bit Symbol Bit Name Function RW
NOTE:
1.
KI3 input polarity select bit 0 : Falling edge
1 : Rising edge
KI0EN RW
KI0PL RW
KI0 input enable bit 0 : Disable
1 : Enable
RW
0 : Disable
1 : Enable
The IR bit in the KUPIC register may be set to 1 (requests interrupt) w hen the KIEN register is rew ritten.
Ref er to 13.5.4 Changing Interrupt Sources.
KI1EN RW
KI3EN KI3 input enable bit
KI3PL RW
KI2PL KI2 input polarity select bit 0 : Falling edge
1 : Rising edge
b1 b0b7 b6 b5 b4 b3 b2
RW
KI2EN RW
KI1PL KI1 input polarity select bit 0 : Falling edge
1 : Rising edge
KI2 input enable bit 0 : Disable
1 : Enable
RW
KI0 input polarity select bit 0 : Falling edge
1 : Rising edge
KI1 input enable bit 0 : Disable
1 : Enable
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13.4 Address Match Interrupt
An address ma tch interrupt reques t is generated imme diately before execution of the instruction at the address
indicated by the RMADi register (i = 0 or 1). This interrupt is used as a break function by the debugger. When
using the on-chip debugger, do not set an address match interrupt (registers of AIER, RMAD0, and RMAD1 and
fixed vector tables) in a user system.
Set the starting address of any instruction in the RMADi register. Bits AIER0 and AIER1 in the AIER0 register can
be used to select enable or disable of the interrupt. The I flag and IPL do not affect the address match interrupt.
The value of the PC (refer to 13.1.6.7 Saving a Register for the valu e of the PC) w hich is saved to the stack w hen
an address match inter rupt is acknowledged varies depending on the instruction at the address indicated by the
RMADi register. (The appropriate return address is not saved on the stack.) When returning from the address match
interrupt, return by one of the following means:
•Change the content of the stack and use the REIT instruction.
•Use an instruction such as POP to restore the stack as it was before the interrupt request was acknowl edged.
Then use a jump instruction.
Table 13.8 lists the Va lues of PC Saved to Stack when Address Match Interrupt is Acknowledged and Table 13.9
lists the Correspondence Between Address Match Interrupt Sources and Associated Registers.
Figure 13.19 shows Registers AIER and RMAD0 to RMAD1.
NOTES:
1. Refer to the 13.1.6.7 Savi n g a Register for the PC value saved.
2. Operation code: Refer to the R8C/Tiny Series Software Manual (REJ09B0001).
Chapter 4. Instruction Code/Number of Cycles contains diagrams showing
operation code below each syntax. Operation code is shown in the bold frame in
the diagrams.
Table 13.8 Values of PC Saved to Stack when Address Match Interrupt is Acknowledged
Address Indicated by RMADi Register (i = 0 or 1) PC Value Saved(1)
• Instruction with 2-byte operation code(2)
• Instruction with 1-byte operation code(2)
ADD.B:S #IMM8,dest SUB.B:S #IMM8,dest AND.B:S #IMM8,dest
OR.B:S #IMM8,dest MOV.B:S #IMM8,dest STZ #IMM8,dest
STNZ #IMM8,dest STZX #IMM81,#IMM82,dest
CMP.B:S #IMM8,dest PUSHM src POPM dest
JMPS #IMM8 JSRS #IMM8
MOV.B:S #IMM,dest (however, dest = A0 or A1)
Address indicated by
RMADi register + 2
Instructions other than the above Address indicated by
RMADi register + 1
Ta b le 13 .9
Correspondence Between Address Match Interrupt Sources and Associated Registers
Address Match Interrupt Source Address Match Interrupt Enable Bit Address Match Interrupt Register
Address match interrupt 0 AIER0 RMAD0
Address match interrupt 1 AIER1 RMAD1
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Figure 13.1 9 Registers AIER and RMAD0 to RMAD1
A
ddress Match Interrupt Enable Registe
r
Symbol Address After Reset
AIER 0013h 00h
Bit Symbol Bit Name Function RW
AIER1 Address match interrupt 1 enable bit
AIER0 0 : Disable
1 : Enable RW
b2 b1 b0
Address match interrupt 0 enable bit
—
(b7-b2) —
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
b7 b6 b5 b4
0 : Disable
1 : Enable RW
b3
Address Match Interrupt Register i (i = 0 or 1)
b0
Symbol Address After Reset
RMA D0 0012h-0010h 000000h
RMA D1 0016h-0014h 000000h
Setting Range RWFunc tion
RW
(b19)
b3
(b15)
b7
(b8)
b0 b7
(b16)
b0
—
—
(b7-b4)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Address setting register for address match interrupt 00000h to FFFFFh
(b23)
b7
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13.5 Notes on Interrupts
13.5.1 Reading Address 00000h
Do not read address 0000 0h by a program. When a maskable interrupt requ est is acknowledged, the CPU reads
interrupt information (interrupt number and interrupt request level) from 00000h in the interrupt sequence. At
this time, the acknowledged interrupt IR bit is set to 0.
If address 00000h is read by a program, the IR bit for the interrupt which has the highest priority among the
enabled interrupts is set to 0. This may cause the interrupt to be canceled, or an unexpected interrupt to be
generated.
13.5.2 SP Setting
Set any value in the SP before an interrupt is acknowl edged. The SP i s set to 000 0h after reset. Therefore, if an
interrupt is acknowledged before setting a value in the SP, the program ma y ru n out of control.
13.5.3 External Interrupt and Key Input Interrupt
Either “L” level or an “H” level of width shown in the Electrical Characteristics is ne cessary for the signal input
to pins INT0, INT1, INT2, INT4 and pins KI0 to KI3, regardless of the CPU clock.
For details, refer to Table 22.17 (VCC = 5V), Table 22.23 (VCC = 3V), and Table 22.29 (VCC = 2.2V)
External Interrupt INTi (i = 0, 1, 2, 4) Input.
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13.5.4 Changing Interrupt Sources
The IR bit in the interrupt control register may be set to 1 (interrupt requested) when the interrupt source
changes. When using an interrupt, set the IR bit to 0 (no interrupt requested) after changing the interrupt source.
In addition, changes of interrupt sources include all factors that change the interrupt sources assigned to
individual software interrupt numbers, polarities, and timing. Therefore, if a mode change of a peripher al
function involve s interrupt so urces, edge polarities, an d timing, set t he IR bit to 0 (no i nterrupt requested) after
the change. Refer to the individual peripheral function for its related interrupts.
Figure 13.20 shows an Examp le of Procedure for Changing Interrupt Sources.
Figure 13.20 Example of Procedure for Changing Interrupt Sources
NOTES:
1. Execute the above settings individually. Do not execute two
or more settings at once (by one instruction).
2. To prevent interrupt requests from being generated, disable
the peripheral function before changing the interrupt
source. In this case, use the I flag if all maskable interrupts
can be disabled. If all maskable interrupts cannot be
disabled, use bits ILVL0 to ILVL2 of the interrupt whose
source is changed.
3. Refer to 13.5.5 Changing Interrupt Control Register
Contents for the instructions to be used and usage notes.
Interrupt source change
Disable interrupts(2, 3)
Set the IR bit to 0 (interrupt not requested)
using the MOV instruction(3)
Change interrupt source (including mode
of peripheral function)
Enable interrupts(2, 3)
Change completed
IR bit: The interrupt control register bit of an
interrupt whose source is changed.
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13.5.5 Changing Interrupt Control Register Contents
(a) The contents of an interrupt control register can only be changed while no interrupt requests
corresponding to that register are gen erated. If interrupt requests may be generated, disable interrupts
before changing the interrupt control register contents.
(b) When changing the contents of an interrupt control register after disabling interrupts, be careful to
choose appropriate instructions.
Changing any bit other than IR bit
If an interrupt request corresponding to a register is generated while executing the instruction, the IR bit
may not be set to 1 (interrupt req uested), and the interrupt request may be ignored. If this causes a
problem, use the following instructions to change the register: AND, OR, BCLR, BSET
Changing IR bit
If the IR bit is set to 0 (interrupt not requested), it may not be set to 0 depending on the instruction used.
Therefore, use the MOV instruction to set the IR bit to 0.
(c) When di sabling interrupts using the I flag, set the I flag as shown in the sample programs b elow. Refer
to (b) regarding changing the contents of interrupt control registers by the sample programs.
Sample programs 1 to 3 are for preventing the I flag from being set to 1 (interrupts enabled) before the interrupt
control register is changed for reasons of the internal bus or the instruction queue buffer.
Example 1: Use NOP instructions to prevent I flag from being set to 1 before interrupt control register
is changed
INT_SWITCH1:
FCLR I ; Disable interrupts
AND.B #00H,0056H ; Set TRAIC register to 00h
NOP ;
NOP
FSET I ; Enable interrupts
Example 2: Use dummy read to delay FSET instruction
INT_SWITCH2:
FCLR I ; Disable interrupts
AND.B #00H,0056H ; Set TRAIC register to 00h
MOV.W MEM,R0 ; Dummy read
FSET I ; Enable interrupts
Example 3: Use POPC instruction to change I flag
INT_SWITCH3:
PUSHC FLG
FCLR I ; Disable interrupts
AND.B #00H,0056H ; Set TRAIC register to 00h
POPC FLG ; Enable interrupts
R8C/2G Group 14. ID Code Areas
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14. ID Code Areas
14.1 Overview
The ID code areas are used to implement a function that prevents the flash memory from being rewritten in
standard serial I/O mode. This function prevents the flash memory from read, rewritten, or erased.
The ID code areas are assigned to 0FFDFh, 0FFE3h, 0FFEBh, 0FFEFh, 0FFF3h, 0FFF7h, and 0FFFBh of the
respective vector highest-order addresses of the fixed vector table. Fi gure 14.1 sh ows the ID Code Areas.
Figure 14.1 ID Code Areas
14.2 Functions
The ID code areas are used in standard serial I/O mode. Unless 3 bytes (addresses from 0FFFCh to 0FFFEh) of the
reset vector are set to FFFFFFh, the ID codes stored in the ID code areas and the ID codes sent from the serial
programmer or the on-chip debugging emulator are checked to see if they match. If the ID codes match, the
commands sent from the serial programmer or the on-chip debugging emulator are acknowledged. If the ID codes
do not match, the command s are not acknowledged . To use the serial programmer or the o n-chip debugging
simulator , first write predetermined ID codes to the ID code areas.
As the ID code areas are allocated in the flash memory (not in the SFRs), they cannot be rewritten by executing an
instruction. Write appropriate values when creating a program .
4 bytes
Address
Watchdog timer/voltage monitor 1 and voltage
monitor 2/comparator 1 and comparator 2 vector
(Reserved)
Undefined instruction vector
Overflow vector
BRK instruction vector
Address match vector
Single step vector
Address break vector
Reset vector
ID code areas
ID1
ID2
ID3
ID4
ID5
ID6
ID7
OFS
0FFDFh to 0FFDCh
0FFE3h to 0FFE0h
0FFE7h to 0FFE4h
0FFEBh to 0FFE8h
0FFEFh to 0FFECh
0FFF3h to 0FFF0h
0FFF7h to 0FFF4h
0FFFBh to 0FFF8h
0FFFFh to 0FFFCh
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14.3 Notes on ID Code Areas
14.3.1 Setting Example of ID Code Areas
As the ID code areas are allocated in the flash memory (not in the SFRs), they cannot be rewritten by executing
an instruction. Write appropriate values when creating a program . The following shows a setting example.
•To set 55h in all of the ID code areas
.org 00FFDCH
.lword dummy | (55000000h) ; UND
.lword dummy | (55000000h) ; INTO
.lword dummy ; BREAK
.lword dummy | (55000000h) ; ADDRESS MATCH
.lword dummy | (55000000h) ; SET SINGLE STEP
.lword dummy | (55000000h) ; WDT
.lword dummy | (55000000h) ; ADDRESS BREAK
.lword dummy | (55000000h) ; RESERVE
(Programming form ats vary depending on the compiler. Check the compiler manual.)
R8C/2G Group 15. Option Function Select Area
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15. Option Function Select Area
15.1 Overview
The option function select area is used to select the MCU state after reset or the function to prevent rewriting in
parallel I/O mode. The reset vector highest-order-address, 0FFFFh, is assigned as the option function select area.
Figure 15.1 shows the Option Functi on Select Area.
Figure 15.1 Option Function Select Area
4 bytes
Address
0FFFFh to 0FFFCh OFS Reset vector
Option function select area
R8C/2G Group 15. Option Function Select Area
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15.2 OFS Register
The OFS register is used to select the MCU state a fter reset or the function to prevent rewriting in parallel I/O
mode. Figure 15.2 shows the OFS Regi ster.
Figure 15.2 OFS Register
Option Function Select Register(1)
Symbol Address When Shipping
OFS 0FFFFh FFh(3)
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3. If the block including the OFS register is erased, FFh is set to the OFS register.
—
(b6)
Reserved bit Set to 1. RW
CSPROINI
Count source protect
mode after reset select
bit
0 : Count source protect mode enabled after reset
1 : Count source protect mode disabled after reset RW
Setting the LVD0ON bit is only valid after a hardw are reset. To use the pow er-on reset, set the LVD0ON bit to 0
(voltage monitor 0 reset enabled after hardw are reset).
ROMCP1 ROM code protect bit 0 : ROM code protect enabled
1 : ROM code protect disabled RW
ROMCR ROM code protect
disabled bit
0 : ROM code protect disabled
1 : ROMCP1 enabled RW
—
(b1) RW
Reserved bit Set to 1.
WDTON RW
Watchdog timer start
select bit
0 : Starts w atchdog timer automatically af ter reset
1 : Watchdog timer is inactive after reset
111
b7 b6 b5 b4 b3 b2 b1 b0
—
(b4)
Reserved bit Set to 1. RW
The OFS register is on the flash memory. Write to the OFS register w ith a program. After w riting is completed, do not
w rite additions to the OFS register.
LVD0ON
Voltage detection 0
circuit start bit(2)
0 : Voltage monitor 0 reset enabled after hardw are
reset
1 : Voltage monitor 0 reset disabled after hardw are
reset
RW
R8C/2G Group 15. Option Function Select Area
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15.3 Notes on Option Function Select Area
15.3.1 Setting Example of Option Function Select Area
As the option function select area is allocated in the flash memory (not in the SFRs), they cannot be rewritten by
executing an instruction. Write appropriate value s when creating a program. The following shows a setting
example.
•To set FFh in the OFS register
.org 00FFFCH
.lword reset | (0FF000000h) ; RESET
(Programming form ats vary depending on the compiler. Check the compiler manual.)
R8C/2G Group 16. Watchdog Timer
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16. Watchdog Timer
The watchdog timer is a function that detects when a program is out of control. Use of the watchdog timer is
recommended to improve the reliability of the system. The watchdog timer contains a 15-bit counter and allows
selection of count source protection mode enable or disable.
Table 16.1 lists information on the Watchdog Timer Specifications.
Refer to 5.6 Watchdog Timer Reset for details on the watchdog timer.
Figure 16.1 shows the Block Diag ram of Watchdog Timer. Figure 16.2 shows t he Registers WDTR, WDTS, and
WDC. Figure 16.3 shows the Registers CSPR and OFS.
Table 16.1 Watchdog Timer Specifications
Item Count Source Protection
Mode Disabled
Count Source Protection
Mode Enabled
Count source CPU clock XCIN clock divided by 32
(fC32)
Low-speed on-chip oscillator
clock
Count operation Decrement
Count start condition Either of the following can be selected
• After reset, count starts automatically
• Count starts by writing to WDTS register
Count stop condition Stop mode, wait mode Stop mode None
Reset condition of
watchdog timer
• Reset
• Write 00h to the WDTR register before writing FFh
• Underflow
Operation at the time
of underflow
Watchdog timer interrupt or watchdog timer reset Watchdog timer reset
Select functions • Division ratio of prescaler (when select the CPU clock as the count source)
Selected by the WDC7 bit in the WDC register
• The default value of the watchdog timer (when select fC32 as the count source)
Selected by bits CVS0 to CVS1 in the CSPR register
• Count source protection mode
Whether count source protection mode is enabled or disabled after a reset can
be selected by the CSPROINI bit in the OFS register (flash memory). If count
source protection mode is disabled after a reset, it can be enabled or disabled by
the CSPRO bit in the CSPR register (program).
• Starts or stops of the watchdog timer after a reset
Selected by the WDTON bit in the OFS register (flash memory).
R8C/2G Group 16. Watchdog Timer
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Figure 16.1 Block Diagram of Watchdog Timer
Internal reset signal
Write to WDTR register
Set to
default
value(1)
PM12 = 1
Watchdog
timer reset
PM12 = 0
Watchdog timer
interrupt request
CSS, CSPRO: Bits in CSPR register
WDC7: Bit in WDC register
PM12: Bit in PM1 register
NOTE:
1. When the CSPRO bit is set to 1 (count source protection mode enabled), 0FFFh is set.
When the CSPRO bit is set to 0 (count source protection mode disabled), the initial value depends on the
settings of bits CVS0, CVS1, and CSS in the CSPR register.
CSPRO = 0
CSPRO = 1
Watchdog timer
CPU clock
fOCO-S
CSS = 0
CSS = 1
fC32
1/16
1/128
WDC7 = 0
WDC7 = 1
Prescaler
R8C/2G Group 16. Watchdog Timer
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Figure 16.2 Registers WDTR, WDTS, and WDC
Watchdog Timer Reset Register
RW
CSPRO CSS CV S1 CVS0
0 0 X X 7FFFh
010001FFh
010103FFh
011007FFh
01110FFFh
1(2) X X X 0FFFh
X: 0 or 1
NOTES:
1.
2.
Do not generate an interrupt betw een w hen 00h and FFh are w ritten.
When the CSPRO bit in the CSPR register is set to 1 (count source protection mode enabled),
0FFFh is set in the w atchdog timer.
WO
Function
When 00h is w ritten before w riting FFh, the w atchdog timer is reset.(1)
The w atchdog timer initial value depends on the CSPR register setting.
CSPR register Default value
After Reset
WDTR 000Dh Undefined
Symbol Address
b7 b0
Watchdog Timer Control Register
Symbol Address After Reset
WDC 000Fh 00X11111b
Bit Symbol Bit Name Function RW
b3 b2 b1 b0
RW
High-order bits of w atchdog timer—
(b4-b0)
RW
—
(b5) RW
00
b7 b6 b5 b4
Reserved bit Set to 0. When read, the content is undefined.
RO
WDC7
—
(b6)
Reserved bit Set to 0.
Prescaler select bit 0 : Divide-by-16
1 : Divide-by-128
Watchdog Timer Start Register
Symbol Address After Reset
WDTS 000Eh Undefined
RW
WO
Function
The w atchdog timer starts counting after a w rite instruction to this register.
b0b7
R8C/2G Group 16. Watchdog Timer
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Figure 16.3 Registers CSPR and OFS
Count Source Protection Mode Register
Symbol Address After Reset(1)
CSPR 001Ch 00h
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
4.
b7 b6 b5 b4 b3 b2 b1 b0
CSPRO Count source protection mode
select bit(4)
0 : Count source protection mode disabled
1 : Count source protection mode enabled
—
Watchdog timer def ault value
select bit(2)
b1 b0
0 0 : 01FFh (512)
0 1 : 03FFh (1024)
1 0 : 07FFh (2048)
1 1 : 0FFFh (4096)
Write 0 before w riting 1 to set the CSPRO bit to 1. 0 cannot be set by a program.
When 0 is w ritten to the CSPROINI bit in the OFS register, the value after reset is 10000000b.
RW
—
(b6-b3)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
When the CSPRO bit is set to 0 (count source protection mode disabled), the CSS bit is enabled.
RW
RW
RW
When the CSS bit is set to 1 (fC32), Bits CVS0 to CVS1 are enabled.
CV S0
CV S1
CSS Count source select bit(3) 0 : CPU clock
1 : fC32
Option Function Select Register(1)
Symbol Address When Shipping
OFS 0FFFFh FFh(3)
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3. If the block including the OFS register is erased, FFh is set to the OFS register.
—
(b6)
Reserved bit Set to 1. RW
CSPROINI
Count source protect
mode after reset select
bit
0 : Count source protect mode enabled after reset
1 : Count source protect mode disabled after reset RW
Setting the LVD0ON bit is only valid after a hardw are reset. To use the pow er-on reset, set the LVD0ON bit to 0
(voltage monitor 0 reset enabled after hardw are reset).
ROMCP1 ROM code protect bit 0 : ROM code protect enabled
1 : ROM code protect disabled RW
ROMCR ROM code protect
disabled bit
0 : ROM code protect disabled
1 : ROMCP1 enabled RW
—
(b1) RW
Reserved bit Set to 1.
WDTON RW
Watchdog timer start
select bit
0 : Starts w atchdog timer automatically after reset
1 : Watchdog timer is inactive after reset
111
b7 b6 b5 b4 b3 b2 b1 b0
—
(b4)
Reserved bit Set to 1. RW
The OFS register is on the flash memory. Write to the OFS register w ith a program. After w riting is completed, do not
w rite additions to the OFS register.
LVD0ON
Voltage detection 0
circuit start bit(2)
0 : Voltage monitor 0 reset enabled after hardw are
reset
1 : Voltage monitor 0 reset disabled after hardw are
reset
RW
R8C/2G Group 16. Watchdog Timer
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16.1 Count Source Protection Mode Disabled
The count source of the watchdog timer is either the CPU clock or the XCIN clock divided by 32 (fC32) can be
selected when count source protection m ode is disabled. fC32 does not stop in wait mode, the watchdog timer to
count continues.
Table 16.2 lists the Watchdog Timer Specifications (with Count Source Protection Mode Disabled).
NOTES:
1. The watchdog timer is reset when 00h is written to the WDTR register before FFh.
2. The prescaler is reset after the MCU is reset. Some errors in the period of the watchdog timer may be caused
by the prescaler.
3. The WDTON bit cannot be changed by a program. To set the WDTON bit, write 0 to bit 0 of address 0FFFFh
with a flash programmer.
Table 16.2 Watchdog Timer Specifications (with Count Source Protection Mode Disabled)
Item Specification
Count source CPU clock XCIN clock divided by 32 (fC32)
Count operation Decrement
Period count value of watchdog
timer (32768)(1, 2) count value of watchdog timer (m)(1)
n: 16 or 128 (selected by WDC7 bit in WDC
register)
Example: When the CPU clock frequency is 8 MHz
and prescaler divided by 16, the period is
approximately 65.5 ms
m: 512, 1024, 2048 or 4096 (selected by bits
CVS0 to CVS1 in the CSPR register)
Example: When the XCIN clock frequency is
32.768 kHz and the count value by
512, the period is 0.5 s
Reset condition
of watchdog
timer
•Reset
• Write 00h to the WDTR register before writing FFh
• Underflow
Count start
condition
The WDTON bit(3) in the OFS register (0FFFFh) selects the operation of the watchdog timer after a
reset
• When the WDTON bit is set to 1 (watchdog timer is in stop state after reset)
The watchdog timer and prescaler stop after a reset and the count starts when the WDTS register
is written to
• When the WDTON bit is set to 0 (watchdog timer starts automatically after exiting)
The watchdog timer and prescaler start counting automatically after a reset
Count stop
condition
Stop and wait modes (inherit the count from the
held value after exiting modes)
Stop mode (inherit the count from the held
value after exiting modes)
Operation at
time of
underflow
• When the PM12 bit in the PM1 register is set to 0
Watchdog timer interrupt
• When the PM12 bit in the PM1 register is set to 1
Watchdog timer reset (refer to 5.6 Watchdog Timer Reset)
Division ratio of prescaler (n)
CPU clock
----------------------------------------------------------------------------×32
XCIN clock
----------------------------- ×
R8C/2G Group 16. Watchdog Timer
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16.2 Count Source Protection Mode Enabled
The count source of the watchdog timer is the low-speed on-chip oscillator clock when count source protection
mode is enabled. If the CPU clock stops when a program is out of control, the clock can still be supplied to the
watchdog timer.
Table 16.3 lists the Watchdog Timer Specifications (with Count Source Protection Mode Enabled).
NOTES:
1. The WDTON bit cannot be changed by a program. To set the WDTON bit, write 0 to bit 0 of address
0FFFFh with a flash programmer.
2. Even if 0 is written to the CSPROINI bit in the OFS register, the CSPRO bit is set to 1. The CSPROINI
bit cannot be changed by a program. To set the CSPROINI bit, write 0 to bit 7 of address 0FFFFh with
a flash programmer.
Table 16.3 Watchdog Timer Specifications (with Count Source Protection Mode Enabled)
Item Specification
Count source Low-speed on-chip oscillator clock
Count operation Decrement
Period Count value of watchdog timer (4096)
Low-speed on-chip oscillator clock
Example: Period is approximately 32.8 ms when the low-speed on-
chip oscillator clock frequency is 125 kHz
Reset condition of watchdog
timer
• Reset
• Write 00h to the WDTR register before writing FFh
• Underflow
Count start condition The WDTON bit(1) in the OFS register (0FFFFh) selects the operation
of the watchdog timer after a reset.
• When the WDTON bit is set to 1 (watchdog timer is in stop state
after reset)
The watchdog timer and prescaler stop after a reset and the count
starts when the WDTS register is written to
• When the WDTON bit is set to 0 (watchdog timer starts
automatically after reset)
The watchdog timer and prescaler start counting automatically after
a reset
Count stop condition None (The count does not stop in wait mode after the count starts.
The MCU does not enter stop mode.)
Operation at time of underflow Watchdog timer reset (refer to 5.6 Watchdog Timer Reset)
Registers, bits • When setting the CSPPRO bit in the CSPR register to 1 (count
source protection mode is enabled)(2), the following are set
automatically
- Set 0FFFh to the watchdog timer
- Set the CM14 bit in the CM1 register to 0 (low-speed on-chip
oscillator on)
- Set the PM12 bit in the PM1 register to 1 (The watchdog timer is
reset when watchdog timer underflows)
• The following conditions apply in count source protection mode
- Writing to the CM10 bit in the CM1 register is disabled (It remains
unchanged even if it is set to 1. The MCU does not enter stop
mode.)
- Writing to the CM14 bit in the CM1 register is disabled (It remains
unchanged even if it is set to 1. The low-speed on-chip oscillator
does not stop.)
R8C/2G Group 17. Timers
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17. Timers
The MCU has two 8-bit timers with 8-bit prescalers, one 16-bit timer, and a timer with a 4-bit counter and an 8-bit
counter. The two 8-bit timers with 8-bit prescalers are timer RA and timer RB. These timers contain a reload register to
store the default value of the counter. The one 16-bit timer is timer RF and have input capture and output compare
functions. The 4-bit and 8-bit counters are timer RE, and has an output compare function. All the timers operate
independently.
Table 17.1 lists Functional Comparison of Timers.
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NOTE:
1. Rectangular waves are output in these modes. Since the waves are inverted at each overflow, the “H” and “L”
level widths of the pulses are the same.
Table 17.1 Functional Comparison of Timers
Item Timer RA Timer RB Timer RE Timer RF
Configuration 8-bit timer with 8-bit
prescaler (with reload
register)
8-bit timer with 8-bit
prescaler (with reload
register)
4-bit counter
8-bit counter
16-bit timer (with
input capture and
output compare)
Count Decrement Decrement Increment Increment
Count sources • f1
•f2
•f8
•fOCO
•fC32
•f1
•f2
•f8
• Timer RA underflow
•f4
•f8
•f32
•fC4
•f1
•f8
•f32
Function Count of the
internal count
source
Timer mode Timer mode — Output compare
mode
Count of the
external count
source
Event counter mode — — —
External
pulse width/
period
measurement
Pulse width
measurement mode,
pulse period
measurement mode
— — Input capture mode
PWM output Pulse output mode(1),
Event counter mode(1)
Programmable
waveform generation
mode
Output compare
mode(1)
Output compare
mode
One-shot
waveform
output
— Programmable one-
shot generation mode,
Programmable wait
one-shot generation
mode
——
Timer Timer mode (only fC32
count)
— Real-time clock
mode
—
Input pin TRAIO INT0 —TRFI
Output pin TRAO
TRAIO
TRBO TREO TRFO00 to TRFO02,
TRFO10 to TRFO12
Related interrupt Timer RA interrupt,
INT1 interrupt
Timer RB interrupt,
INT0 interrupt
Timer RE interrupt Timer RF interrupt,
Compare 0 interrupt,
Compare 1 interrupt,
Capture interrupt
Timer stop Provided Provided Provided Provided
R8C/2G Group 17. Timers
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17.1 Timer RA
Timer RA is an 8-bit timer with an 8-bit prescaler .
The prescaler and timer each consist of a reload register and counter. The reload register and counter are allocated
at the same address, and can be accessed when accessing registers TRAPRE and TRA (refer to Tables 17.2 to 17.6
the Specifications of Each Mode).
The count source for t im er RA is the operating clock that regulates the timing of timer operations such as counting
and reloading.
Figure 17.1 shows a Block Diagram of Timer RA. Figures 17.2 and 17.3 show the registers associated with timer
RA.
Timer RA has the following five operating modes:
•Timer mode: The timer counts the internal count source.
•Pulse output mode: The timer counts the internal count source and outputs pul ses of which
polarity inverted by underflow of th e timer.
•Event counter mode: The timer counts external pulses.
•Pulse width measurement mode: The timer measures the pulse width of an external pulse.
•Pulse period measurement mode: The timer measures the pulse period of an external pulse.
Figure 17.1 Block Diagram of Ti mer RA
= 000b
= 001b
= 011b
f2
f8
f1
= 010b
fOCO
TCK2 to TCK0
TMOD2 to TMOD0
= other than 010b
Counter
Reload
register
TRAPRE register
(prescaler)
Data bus
Timer RA interrupt
Write to TRAMR register
Write 1 to TSTOP bit
TCSTF, TSTOP: Bits in TRACR register
TEDGSEL, TOPCR, TOENA, TIOSEL, TIPF1, TIPF0: Bits in TRAIOC register
TMOD2 to TMOD0, TCK2 to TCK0, TCKCUT: Bits in TRAMR register
TRAOSEL: Bit in the PINSR2 register
Toggle flip-flop
Q
QCLR
CK
INT1/TRAIO (P1_5) pin
TCSTF
TCKCUT
TMOD2 to TMOD0
= 011b or 100b
TMOD2 to TMOD0
= 010b
Polarity
switching
Digital
filter
Counter
Reload
register
TRA register
(timer)
TIPF1 to TIPF0
= 01b
= 10b
f8
f1
= 11b
f32
TIOSEL = 0
TIOSEL = 1
Count control
circle
TMOD2 to TMOD0 = 001b
TOPCR
Underflow signal
Measurement completion
signal
TIPF1 to TIPF0
= other than
000b
= 00b
INT1/TRAIO (P1_7) pin
TEDGSEL = 1
TEDGSEL = 0
= 100b
fC32
TOENA
TRAO (P3_7) pin
TRAOSEL = 0
TRAOSEL = 1
TRAO (P3_0) pin
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Figure 17.2 Registers TRACR and TRAIOC
Timer RA Control Register(4)
Symbol Address After Reset
TRA CR 0100h 00h
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
4.
5.
Timer RA count start bit(1)
Timer RA count forcible stop
bit(2)
In pulse w idth measurement mode and pulse period measurement mode, use the MOV instruction to set the TRACR
register. If it is necessary to avoid changing the values of bits TEDGF and TUNDF, w rite 1 to them.
Set to 0 in timer mode, pulse output mode, and event counter mode.
Bits TEDGF and TUNDF can be set to 0 by w riting 0 to these bits by a program. How ever, their value remains
unchanged w hen 1 is w ritten.
TUNDF
When the TSTOP bit is set to 1, bits TSTART and TCSTF and registers TRAPRE and TRA are set to the values after a
reset.
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Ref er to 17.1.6 Notes on Timer RA.
—
(b7-b6)
b7 b6 b5 b4 b3 b2
When this bit is set to 1, the count is f orcibly
stopped. When read, its content is 0.
—
(b3)
b1 b0
—
—
RW
TEDGF
0 : Active edge not received
1 : Active edge received
(end of measurement period)
Active edge judgment
flag(3, 5)
Timer RA underflow flag(3, 5) 0 : No underflow
1 : Underflow
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
RW
TCSTF
RW
RW
RO
TSTA RT
0 : Count stops
1 : During count
0 : Count stops
1 : Count starts
Timer RA count status flag(1)
TSTOP
Timer RA I/O Control Registe
r
Symbol Address After Reset
TRA IOC 0101h 00h
Bit Symbol Bit Name Function RW
INT1
_
____ /TRAIO select bit RW
TIPF0 RW
TOENA RW
TRAIO input filter select bits
TIPF1
Function varies depending on operating mode.
—
TEDGSEL RW
TOPCR RW
TRAIO polarity sw itch bit
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
—
(b7-b6)
TRAIO output control bit
TRAO output enable bit
b7 b6 b5 b4 b3 b2
TIOSEL
b1 b0
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Figure 17.3 R egisters TRAMR, TRAPRE, and TRA
Timer RA Mode Register(1)
Symbol Address After Reset
TRA MR 0102h 00h
Bit Symbol Bit Name Function RW
NOTE:
1.
TCKCUT
TCK1
b3 b2
—
(b3)
b1 b0
RW
Timer RA count source
select bits
b6 b5 b4
0 0 0 : f1
0 0 1 : f8
0 1 0 : fOCO
0 1 1 : f2
1 0 0 : fC32
1 0 1 :
1 1 0 : Do not set.
1 1 1 :
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
RW
b7 b6 b5 b4
RW
TMOD1 RW
TMOD0
Timer RA operating mode
select bits
b2 b1 b0
0 0 0 : Timer mode
0 0 1 : Pulse output mode
0 1 0 : Event counter mode
0 1 1 : Pulse w idth measurement mode
1 0 0 : Pulse period measurement mode
1 0 1 :
1 1 0 : Do not set.
1 1 1 :
TMOD2 RW
—
TCK0 RW
When both the TSTART and TCSTF bits in the TRACR register are set to 0 (count stops), rew rite this register.
RW
Timer RA count source
cutoff bit
0 : Provides count source
1 : Cuts off count source
TCK2
Timer RA Prescaler Register
Symbol Address After Reset
TRA PRE 0103h FFh(1)
Mode Function Setting Range RW
NOTE:
1.
RW
Pulse w idth
measurement mode
b0
Time r mode RW
b7
Counts an internal count source 00h to FFh
Pulse output mode RWCounts an internal count source 00h to FFh
Counts internal count source
When the TSTOP bit in the TRACR register is set to 1, the TRAPRE register is set to FFh.
Event counter mode Counts an external count source 00h to FFh RW
00h to FFh RW
Pulse period
measurement mode 00h to FFh
Timer RA Register
Symbol Address After Reset
TRA 0104h FFh(1)
Mode Function Setting Range RW
NOTE:
1.
00h to FFh
b7
When the TSTOP bit in the TRACR register is set to 1, the TRA register is set to FFh.
b0
All modes Counts on underflow of timer RA prescaler
register RW
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17.1.1 T imer Mode
In this mode, the timer counts an internally generated count source (refer to Table 17.2 Timer Mode
Specifications).
Figure 17.4 sh ow s TRAIOC Register in Timer Mode.
Figure 17.4 TRAIOC Register in Timer Mode
Tab le 17.2 Timer Mode Specifications
Item Specification
Count sources f1, f2, f8, fOCO, fC32
Count operations • Decrement
• When the timer underflows, the contents of the reload register are reloaded
and the count is continued.
Divide ratio 1/(n+1)(m+1)
n: Value set in TRAPRE register, m: Value set in TRA register
Count start condition 1 (count starts) is written to the TSTART bit in the TRACR register.
Count stop conditions • 0 (count stops) is written to the TSTART bit in the TRACR register.
• 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register.
Interrupt request
generation timing
When timer RA underflows [timer RA interrupt].
INT1/TRAIO pin
function
Programmable I/O port, or INT1 interrupt input
TRAO pin function Programmable I/O port
Read from timer The count value can be read by reading registers TRA and TRAPRE.
Write to timer • When registers TRAPRE and TRA are written while the count is stopped,
values are written to both the reload register and counter.
• When registers TRAPRE and TRA are written during the count, values are
written to the reload register and counter (refer to 17.1.1.1 Timer Write
Control during Count Operation).
Timer RA I/O Control Registe
r
Symbol Address After Reset
TRA IOC 0101h 00h
Bit Symbol Bit Name Function RW
INT1
_
____ /TRAIO select bit 0 : INT1
_
____ /TRAIO pin (P1_7)
1 : INT1
_
____ /TRAIO pin (P1_5)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
TRAO output enable bit
TRAIO input filter select bits Set to 0 in timer mode.
RW
TRAIO polarity sw itch bit
0
Set to 0 in timer mode.
TRAIO output control bit
—
(b7-b6) —
TOPCR RW
TOENA RW
RW
TIPF0 RW
TIPF1
00
b7 b6 b5 b4 b3 b2
TIOSEL
b1 b0
00
TEDGSEL
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17.1.1.1 Timer Write Control during Count Operation
Timer RA has a pre scaler and a timer (which counts the prescaler underflows). The prescaler and timer each
consist of a reload register and a counter. When writing to the prescaler or timer, values are written to both the
reload register and counter.
However, values are transferred from the reload register to the counter of the prescaler in synchronization with
the count source. In addition, values are transferred from the reload register to the counter of the timer in
synchronization with prescaler underflows. Therefore, if the prescaler or timer is written to when count
operation is in progress, the counter value is not updated immediately after the WR ITE instruction is executed.
Figure 17.5 shows an Operating Example of Timer RA when Counter Value is Rewritten during Count
Operation.
Figure 17.5 Operating Example of Timer RA when Counter Value is Rewritten during Count
Operation
Count source
Reloads register of
timer RA prescaler
IR bit in TRAIC
register 0
Counter of
timer RA prescaler
Reloads register of
timer RA
Counter of timer RA
Set 01h to the TRAPRE register and 25h to
the TRA register by a program.
After writing, the reload register is
written to at the first count source.
Reload at
second count
source
Reload at
underflow
After writing, the reload register is
written to at the first underflow.
Reload at the second underflow
The IR bit remains unchanged until underflow is
generated by a new value.
05h 04h 01h 00h 01h 00h 01h 00h 01h 00h06h
New value (01h)Previous value
New value (25h)Previous value
03h 24h02h 25h
The above applies under the following conditions.
Both bits TSTART and TCSTF in the TRACR register are set to 1 (During count).
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17.1.2 Pulse Output Mode
In pulse output mode, the internally generated count source is counted, and a pulse with i nverted polarity is
output from the TRAIO pin each time the timer underflows (refer to Table 17.3 Pulse Output Mode
Specifications).
Figure 17.6 shows TRAIOC Register in Pulse Output Mode.
NOTE:
1. The level of the output pulse becomes the level when the pulse output starts when the TRAMR
register is written to.
Ta ble 17 .3 Pulse Output Mode Specifications
Item Specification
Count sources f1, f2, f8, fOCO, fC32
Count operations • Decrement
• When the timer underflows, the contents in the reload register is reloaded and
the count is continued.
Divide ratio 1/(n+1)(m+1)
n: Value set in TRAPRE register, m: Value set in TRA register
Count start condition 1 (count starts) is written to the TSTART bit in the TRACR register.
Count stop conditions • 0 (count stops) is written to the TSTART bit in the TRACR register.
• 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register.
Interrupt request
generation timing
When timer RA underflows [timer RA interrupt].
INT1/TRAIO pin
function
Pulse output, programmable output port, or INT1 interrupt(1)
TRAO pin function Programmable I/O port or inverted output of TRAIO(1)
Read from timer The count value can be read by reading registers TRA and TRAPRE.
Write to timer • When registers TRAPRE and TRA are written while the count is stopped, values
are written to both the reload register and counter.
• When registers TRAPRE and TRA are written during the count, values are
written to the reload register and counter (refer to 17.1.1.1 T i mer W ri te Cont rol
during Count Operation).
Select functions • TRAIO output polarity switch function
The TEDGSEL bit in the TRAIOC register selects the level at the start of pulse
output.(1)
• TRAO output function
Pulses inverted from the TRAIO output polarity can be output from the TRAO pin
(selectable by the TOENA bit in the TRAIOC register).
• TRAO pin select function
P3_0 or P3_7 is selected by the TRAOSEL bit in the PINSR2 register.
• Pulse output stop function
Output from the TRAIO pin is stopped by the TOPCR bit in the TRAIOC register.
•INT1
/TRAIO pin select function
P1_7 or P1_5 is selected by the TIOSEL bit in the TRAIOC register.
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Figure 17.6 TRAIOC Register in Pulse Output Mode
Timer RA I/O Control Registe
r
Symbol Address After Reset
TRA IOC 0101h 00h
Bit Symbol Bit Name Function RW
INT1
_
____ /TRAIO select bit 0 : INT1
_
____ /TRAIO pin (P1_7)
1 : INT1
_
____ /TRAIO pin (P1_5)
RW
RW
0 : TRAIO output
1 : Port P1_7 or P1_5
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
TRAO output enable bit
TRAIO input filter select bits Set to 0 in pulse output mode.
TEDGSEL RW
TRAIO polarity sw itch bit
TIPF1
—
(b7-b6) —
TOPCR RW
TOENA RW
RW
TIPF0
TRAIO output control bit
00
b7 b6 b5 b4 b3 b2
0 : Port P3_0 (P3_7)
1 : TRAO output
(inverted TRAIO output from P3_0 (P3_7))
TIOSEL
b1 b0
0 : TRAIO output starts at “H”
1 : TRAIO output starts at “L”
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17.1.3 Event Counter Mode
In event counter mode, external signal inputs to the INT1/TRAIO pin are cou nted (refer to Table 17.4 Event
Counter Mode Specifications).
Figure 17.7 show s TRAIOC Register in Event Counter Mode.
NOTE:
1. The level of the output pulse becomes the level when the pulse output starts when the TRAMR
register is written to.
Table 17.4 Event Counter Mode Specifications
Item Specification
Count source External signal which is input to TRAIO pin (active edge selectable by a program)
Count operations • Decrement
• When the timer underflows, the contents of the reload register are reloaded and
the count is continued.
Divide ratio 1/(n+1)(m+1)
n: setting value of TRAPRE register, m: setting value of TRA register
Count start condition 1 (count starts) is written to the TSTART bit in the TRACR register.
Count stop conditions • 0 (count stops) is written to the TSTART bit in the TRACR register.
• 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register.
Interrupt request
generation timing
• When timer RA underflows [timer RA interrupt].
INT1/TRAIO pin
function
Count source input (INT1 interrupt input)
TRAO pin function Programmable I/O port or pulse output(1)
Read from timer The count value can be read by reading registers TRA and TRAPRE.
Write to timer • When registers TRAPRE and TRA are written while the count is stopped, values
are written to both the reload register and counter.
• When registers TRAPRE and TRA are written during the count, values are
written to the reload register and counter (refer to 17.1.1.1 Timer W rite Control
during Count Operation).
Select functions •NT1
input polarity switch function
The TEDGSEL bit in the TRAIOC register selects the active edge of the count
source.
• Count source input pin select function
P1_7 or P1_5 is selected by the TIOSEL bit in the TRAIOC register.
• Pulse output function
Pulses of inverted polarity can be output from the TRAO pin each time the timer
underflows (selectable by the TOENA bit in the TRAIOC register).(1)
• TRAO pin select function
P3_0 or P3_7 is selected by the TRAOSEL bit in the PINSR2 register.
• Digital filter function
Bits TIPF0 and TIPF1 in the TRAIOC register enable or disable the digital filter
and select the sampling frequency.
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Figure 17.7 TRAIOC Register in Event Counter Mode
Timer RA I/O Control Register
Symbol Address After Reset
TRA IOC 0101h 00h
Bit Symbol Bit Name Function RW
INT1
_
____ /TRAIO select bit 0 : INT1
_
____ /TRAIO pin (P1_7)
1 : INT1
_
____
/TRAIO pin (P1_5)
NOTE:
1.
0 : Port P3_0 (P3_7)
1 : TRAO output
TIOSEL
b1 b0
0 : Starts counting at rising edge of the TRAIO
input or TRAIO starts output at “L”
1 : Starts counting at falling edge of the TRAIO
input or TRAIO starts output at “H”
0
TOENA
b7 b6 b5 b4 b3 b2
—
(b7-b6)
RW
TEDGSEL RW
TRAIO polarity sw itch bit
RW
TIPF0
RW
TOPCR RW
—
When the same value from the TRAIO pin is sampled three times continuously, the input is determined.
TRAIO output control bit Set to 0 in event counter mode.
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
TRAO output enable bit
TRAIO input f ilter select
bits(1)
b5 b4
0 0 : No filter
0 1 : Filter w ith f1 sampling
1 0 : Filter w ith f8 sampling
1 1 : Filter w ith f32 sampling
TIPF1
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17.1.4 Pulse Width Measurement Mode
In pulse width measurement mode, the pulse width of an external signal input to the INT1/TRAIO pin is
measured (refer to Table 17.5 Pulse Width Measurement Mode Specifications).
Figure 17.8 shows TRAIOC Reg ister in Pulse Width Measurement Mode and Figure 17.9 shows an Operating
Example of Pulse Width Measurement Mode.
Table 17.5 Pulse Width Measurement Mode Specifications
Item Specification
Count sources f1, f2, f8, fOCO, fC32
Count operations • Decrement
• Continuously counts the selected signal only when measurement pulse is “H”
level, or conversely only “L” level.
• When the timer underflows, the contents of the reload register are reloaded
and the count is continued.
Count start condition 1 (count starts) is written to the TSTART bit in the TRACR register.
Count stop conditions • 0 (count stops) is written to the TSTART bit in the TRACR register.
• 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register.
Interrupt request
generation timing
• When timer RA underflows [timer RA interrupt].
• Rising or falling of the TRAIO input (end of measurement period) [timer RA
interrupt]
INT1/TRAIO pin function Measured pulse input (INT1 interrupt input)
TRAO pin function Programmable I/O port
Read from timer The count value can be read by reading registers TRA and TRAPRE.
Write to timer • When registers TRAPRE and TRA are written while the count is stopped,
values are written to both the reload register and counter.
• When registers TRAPRE and TRA are written during the count, values are
written to the reload register and counter (refer to 17.1.1.1 Timer Write
Control during Count Operation).
Select functions • Measurement level select
• The TEDGSEL bit in the TRAIOC register selects the “H” or “L” level period.
• Measured pulse input pin select function
P1_7 or P1_5 is selected by the TIOSEL bit in the TRAIOC register.
• Digital filter function
Bits TIPF0 and TIPF1 in the TRAIOC register enable or disable the digital
filter and select the sampling frequency.
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Figure 17.8 TRAIOC Register in Pulse Width Measurement Mode
Timer RA I/O Control Register
Symbol Address After Reset
TRA IOC 0101h 00h
Bit Symbol Bit Name Function RW
INT1
_
____
/TRAIO select bit 0 : INT1
_
____
/TRAIO pin (P1_7)
1 : INT1
_
____ /TRAIO pin (P1_5)
NOTE:
1. When the same value from the TRAIO pin is sampled three times continuously, the input is determined.
b3 b2
TIOSEL
b1 b0
0 : TRAIO input starts at “L”
1 : TRAIO input starts at “H”
00
b7 b6 b5 b4
—
TOPCR RW
TOENA RW
RW
TIPF0
RW
TRAIO output control bit
TEDGSEL RW
TRAIO polarity sw itch bit
TIPF1
—
(b7-b6)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
TRAO output enable bit
TRAIO input f ilter select
bits(1)
b5 b4
0 0 : No filter
0 1 : Filter w ith f1 sampling
1 0 : Filter w ith f8 sampling
1 1 : Filter w ith f32 sampling
Set to 0 in pulse w idth measurement mode.
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Figure 17.9 Operating Example of Pulse Width Measurement Mode
FFFFh
n
0000h
Content of counter (hex)
n = high level: the contents of TRA register, low level: the contents of TRAPRE register
Count start
Count stop
Underflow
Period
TSTART bit in
TRACR register
1
0
Measured pulse
(TRAIO pin input)
1
0
TEDGF bit in
TRACR register
1
0
TUNDF bit in
TRACR register
1
0
• “H” level width of measured pulse is measured. (TEDGSEL = 1)
• TRAPRE = FFh
Set to 1 by program
IR bit in TRAIC
register
1
0
Set to 0 by program
Count stop
Count start
Set to 0 when interrupt request is acknowledged, or set by program
Count start
Set to 0 by program
The above applies under the following conditions.
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17.1.5 Pulse Period Measurement Mode
In pulse period measurement mode, the pulse period of an external signal input to the INT1/TRAIO pin is
measured (refer to Table 17.6 Pulse Period Measurement Mode Specifications).
Figure 17.10 shows TRAIOC Register in Pulse Period Measurement Mode and Figure 17.11 shows an
Operating Example of Pulse Period Measurement Mode.
NOTE:
1. Input a pulse with a period longer than twice the timer RA prescaler period. Input a pulse with a
longer “H” and “L” width than the timer RA prescaler period. If a pulse with a shorter period is input to
the TRAIO pin, the input may be ignored.
Table 17.6 Pulse Period Measurement Mode S pecifications
Item Specification
Count sources f1, f2, f8, fOCO, fC32
Count operations • Decrement
• After the active edge of the measured pulse is input, the contents of the read-
out buffer are retained at the first underflow of timer RA prescaler. Then timer
RA reloads the contents in the reload register at the second underflow of
timer RA prescaler and continues counting.
Count start condition 1 (count starts) is written to the TSTART bit in the TRACR register.
Count stop conditions • 0 (count stops) is written to TSTART bit in the TRACR register.
• 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register.
Interrupt request
generation timing
• When timer RA underflows or reloads [timer RA interrupt].
• Rising or falling of the TRAIO input (end of measurement period) [timer RA
interrupt]
INT1/TRAIO pin function Measured pulse input(1) (INT1 interrupt input)
TRAO pin function Programmable I/O port
Read from timer The count value can be read by reading registers TRA and TRAPRE.
Write to timer • When registers TRAPRE and TRA are written while the count is stopped,
values are written to both the reload register and counter.
• When registers TRAPRE and TRA are written during the count, values are
written to the reload register and counter (refer to 17.1.1.1 Timer Write
Control during Count Operation).
Select functions • Measurement period select
The TEDGSEL bit in the TRAIOC register selects the measurement period of
the input pulse.
• Measured pulse input pin select function
P1_7 or P1_5 is selected by the TIOSEL bit in the TRAIOC register.
• Digital filter function
Bits TIPF0 and TIPF1 in the TRAIOC register enable or disable the digital
filter and select the sampling frequency.
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Figure 17.10 TRAIOC Register in Pulse Period Measurement Mode
Timer RA I/O Control Register
Symbol Address After Reset
TRA IOC 0101h 00h
Bit Symbol Bit Name Function RW
INT1
_
____ /TRAIO select bit 0 : INT1
_
____ /TRAIO pin (P1_7)
1 : INT1
_
____ /TRAIO pin (P1_5)
NOTE:
1.
—
(b7-b6)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
TRAO output enable bit
TRAIO input filter select
bits(1)
b5 b4
0 0 : No f ilter
0 1 : Filter w ith f1 sampling
1 0 : Filter w ith f8 sampling
1 1 : Filter w ith f32 sampling
Set to 0 in pulse period measurement mode.
TEDGSEL RW
TRAIO polarity sw itch bit
—
TOPCR RW
TOENA RW
RW
TIPF0
RW
TRAIO output control bit
TIPF1
b7 b6 b5 b4
When the same value from the TRAIO pin is sampled three times continuously, the input is determined.
b3 b2
TIOSEL
b1 b0
0 : Measures measurement pulse from one
rising edge to next rising edge
1 : Measures measurement pulse from one
f alling edge to next falling edge
00
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Figure 17.11 Operating Example of Pulse Period Measurement Mode
Underflow signal of
timer RA prescaler
NOTES:
1. The contents of the read-out buffer can be read by reading the TRA register in pulse period measurement mode.
2. After an active edge of the measured pulse is input, the TEDGF bit in the TRACR register is set to 1 (active edge found) when the timer
RA prescaler underflows for the second time.
3. The TRA register should be read before the next active edge is input after the TEDGF bit is set to 1 (active edge found).
The contents in the read-out buffer are retained until the TRA register is read. If the TRA register is not read before the next active edge
is input, the measured result of the previous period is retained.
4. To set to 0 by a program, use a MOV instruction to write 0 to the TEDGF bit in the TRACR register. At the same time, write 1 to the
TUNDF bit in the TRACR register.
5. To set to 0 by a program, use a MOV instruction to write 0 to the TUNDF bit. At the same time, write 1 to the TEDGF bit.
6. Bits TUNDF and TEDGF are both set to 1 if timer RA underflows and reloads on an active edge simultaneously.
0Eh 0Dh 0Fh 0Eh 0Dh 0Ch 0Bh 0Ah 09h 0Fh 0Eh 0Dh 01h 00h 0Fh 0Eh0Fh
0Dh
0Fh 0Bh 0Ah 0Dh 01h 00h 0Fh 0Eh09h
TSTART bit in
TRACR register
1
0
1
0
1
0
TEDGF bit in
TRACR register
1
0
Measurement pulse
(TRAIO pin input)
Contents of TRA
1
0
Contents of read-out
buffer(1)
IR bit in TRAIC
register
TUNDF bit in
TRACR register
Set to 1 by program
Starts counting
TRA reloads
TRA read(3)
Retained
(Note 2)
Set to 0 by program
Conditions: The period from one rising edge to the next rising edge of the measured pulse is measured (TEDGSEL = 0) with
the default value of the TRA register as 0Fh.
0Eh
TRA reloads
Retained
Set to 0 when interrupt request is acknowledged, or set by program
Set to 0 by program
Underflow
(Note 2)
(Note 4)
(Note 6)
(Note 5)
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17.1.6 Notes on Timer RA
• Timer RA stops co unting after a reset. Set the values in the timer RA and timer RA p rescalers before the
count starts.
• Even if the prescaler and timer RA are read out in 16-bit units, these registers are read 1 byte at a time by
the MCU. Consequently, the timer value may be updated during the period when these two registers are
being read.
• In pulse period measurement mode, bits TEDGF and TUNDF in the TRACR register can be set to 0 by
writing 0 to these bits by a program. However, these bits remain un changed if 1 is written. When using the
READ-MODIFY-WRITE instruction for the TRACR register, the TEDGF or TUNDF bit may be set to 0
although these bits are set to 1 while the instruction is being executed. In this case, write 1 to the TEDGF or
TUNDF bit which is not supposed to be set to 0 with the MOV instru ction.
• When changing to pulse period measurement mode from another mode, the contents of bits TEDGF and
TUNDF are undefined. Write 0 to bits TEDGF and TUNDF before the count starts.
• The TEDGF bit may be set to 1 by the first timer RA prescaler underflow generated after the count starts.
• When using the pulse period measurement mode, leave two or more periods of the timer RA prescaler
immediately after the count starts, then set the TEDGF bit to 0.
• The TCSTF bit retains 0 (count stops) for 0 to 1 cycle of the count source after setting the TSTAR T bit to 1
(count starts) while the count is stopped.
During this time, do not access registers associated with tim er RA(1) other than the TCSTF bit. Timer RA
starts counting at the first valid edge of the count source after The TCSTF bit is set to 1 (duri ng count).
The TCSTF bit remains 1 for 0 to 1 cycle of the count source after setting the TSTART bit to 0 (count
stops) while the count is in progress. Timer RA counting is stopped when the TCSTF bit is set to 0.
During this time, do not access registers associated with timer RA(1) other than the TCSTF bit.
NOTE:
1. Registers associated with timer RA: TRACR, TRAIOC, TRAMR, TRAPRE, and TRA.
• When the TRAPRE register is continuously wri tten during count operation (TCSTF bit is set to 1), allow
three or more cycles of the count source clock for each write interval.
• When the TRA register is continuously written during count operation (TCSTF bit is set to 1), allow three
or more cycles of the prescaler underflow for each write interval.
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17.2 Timer RB
Timer RB is an 8-bit timer with an 8-bit prescaler.
The prescaler and timer each consist of a reload register and counter (refer to Tables 17.7 to 17.10 the
Specifications of Each Mode).
Timer RB has timer RB primary and timer RB secondary as reload registers.
The count source for timer RB is the operating clock that regulates the timing of timer operations such as counting
and reloading.
Figure 17.12 shows a Block Diagram of Timer RB. Figures 17.13 to 17.15 show the registers associated with timer
RB.
Timer RB has four operation modes listed as follows:
•Timer mode: The timer counts an internal count source (peripheral
function clock or timer RA underflows ).
•Programmable waveform generation mode: The timer outputs pulses of a given width successively.
•Programmable one-shot generation mode: The timer outputs a one-shot pulse.
•Programmable wait one-shot generation mode: The timer outputs a delayed one-shot pulse.
Figure 17.12 Block Diagram of Timer RB
INT0PL
= 00b
= 01b
= 11b
f8
f1
= 10b
Timer RA underflow
TCK1 to TCK0
TSTART
TRBPRE register
(prescaler)
Timer RB interrupt
INT0 interrupt
TCSTF
Toggle
flip-flop
Q
QCLR
CK
TOPL = 1
TOPL = 0
TOCNT = 0
TOCNT = 1
P3_1 bit in P3 register
f2 TMOD1 to TMOD0
= 10b or 11b
TOSSTF
Polarity
select
INOSEG
Input polarity
selected to be one
edge or both edges
Digital filter
INT0 pin
INT0EN
TMOD1 to TMOD0
= 01b, 10b, 11b
TMOD1 to TMOD0
= 01b, 10b, 11b
Counter
Reload
register
Counter (timer RB)
Reload
register
TRBPR
register
Data bus
TRBSC
register
Reload
register
TCKCUT
INOSTG
TSTART, TCSTF: Bits in TRBCR register
TOSSTF: Bit in TRBOCR register
TOPL, TOCNT, INOSTG, INOSEG: Bits in TRBIOC register
TMOD1 to TMOD0, TCK1 to TCK0, TCKCUT: Bits in TRBMR register
TRBOSEL: Bit in PINSR2 register
(Timer)
TRBOSEL = 0
TRBOSEL = 1
TRBO (P1_3) pin
TRBO (P3_1) pin
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Figure 17.13 Registers TRBCR and TRBOCR
Timer RB Control Registe
r
Symbol Address After Reset
TRBCR 0108h 00h
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3. Indicates that count operation is in progress in timer mode or programmable w avef orm mode. In programmable one-
shot generation mode or programmable w ait one-shot generation mode, indicates that a one-shot pulse trigger has
been acknow ledged.
Timer RB count start bit(1)
Timer RB count f orcible stop
bit(1, 2)
Ref er to 17.2.5 Notes on Timer RB f or precautions regarding bits TSTART, TCSTF and TSTOP.
TSTA RT RW
b7 b6 b5 b4 b3 b2
When this bit is set to 1, the count is forcibly
stopped. When read, its content is 0.
b1 b0
0 : Count stops
1 : Count starts
When the TSTOP bit is set to 1, registers TRBPRE, TRBSC, TRBPR, and bits TSTART and TCSTF, and the TOSSTF bit
in the TRBOCR register are set to values after a reset.
0 : Count stops
1 : During count(3)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
RO
—
(b7-b3) —
TCSTF Timer RB count status flag(1)
TSTOP RW
Timer RB One-Shot Control Register(2)
Symbol Address After Reset
TRBOCR 0109h 00h
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Timer RB one-shot status
flag(1)
When 1 is set to the TSTOP bit in the TRBCR register, the TOSSTF bit is set to 0.
This register is enabled w hen bits TMOD1 to TMOD0 in the TRBMR register is set to 10b (programmable one-shot
generation mode) or 11b (programmable w ait one-shot generation mode).
RO
—
(b7-b3) —
RW
RW
Timer RB one-shot start bit When this bit is set to 1, one-shot trigger
generated. When read, its content is 0.
Timer RB one-shot stop bit When this bit is set to 1, counting of one-shot
pulses (including programmable w ait one-shot
pulses) stops. When read, its content is 0.
b7 b6 b5 b4 b3 b2
0 : One-shot stopped
1 : One-shot operating (Including w ait period)
b1 b0
TOSSP
TOSSTF
TOSST
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Figure 17.14 Registers TRBIOC and TRBMR
Timer RB I/O Control Registe
r
Symbol Address After Reset
TRBIOC 010Ah 00h
Bit Symbol Bit Name Function RW
TOPL Timer RB output level select
bit
Timer RB output sw itch bit
b7 b6 b5 b4 b3 b2
INOSEG
b1 b0
INOSTG
TOCNT
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
One-shot trigger polarity
select bit
—
(b7-b4) —
Function varies depending on operating mode. RW
RW
RW
RW
One-shot trigger control bit
Timer RB Mode Register
Symbol Address After Reset
TRBMR 010Bh 00h
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
—
(b6) —
Timer RB count source
select bits(1)
b5 b4
0 0 : f1
0 1 : f8
1 0 : Timer RA underflow
1 1 : f2
TCK1
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
The TWRC bit can be set to either 0 or 1 in timer mode. In programmable w aveform generation mode, programmable
one-shot generation mode, or programmable w ait one-shot generation mode, the TWRC bit must be set to 1 (w rite to
reload register only).
TCK0 RW
Change bits TMOD1 and TMOD0; TCK1 and TCK0; and TCKCUT w hen both the TSTART and TCSTF bits in the TRBCR
register set to 0 (count stops).
RW
Timer RB count source
cutoff bit(1)
0 : Provides count source
1 : Cuts off count source RWTCKCUT
RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Timer RB w rite control bit(2) 0 : Write to reload register and counter
1 : Write to reload register only
—
b7 b6 b5 b4
RW
TMOD1 RW
Timer RB operating mode
select bits(1)
b1 b0
0 0 : Timer mode
0 1 : Programmable w aveform generation mode
1 0 : Programmable one-shot generation mode
1 1 : Programmable w ait one-shot generation mode
b3 b2
TWRC
b1 b0
—
(b2)
TMOD0
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Figure 17.1 5 Registers T RBPRE, TRBSC, and TRBPR
Timer RB Prescaler Register(1)
Symbol Address After Reset
TRBPRE 010Ch FFh
Mode Function Setting Range RW
NOTE:
1. When the TSTOP bit in the TRBCR register is set to 1, the TRBPRE register is set to FFh.
Programmable w aveform
generation mode RW
00h to FFh
Programmable one-shot
generation mode
00h to FFh RW
Programmable w ait one-shot
generation mode
RW
00h to FFhCounts an internal count source or timer RA
underflow s
00h to FFh RW
b7
Time r mode
b0
Timer RB Secondary Register(3, 4)
Symbol Address After Reset
TRBSC 010Dh FFh
Mode Function Setting Range RW
NOTES:
1.
2.
3.
4. To w rite to the TRBSC register, perform the f ollow ing steps.
(1) Write the value to the TRBSC register.
(2) Write the value to the TRBPR register. (If the value does not change, w rite the same value second time.)
The count value can be read out by reading the TRBPR register even w hen the secondary period is being counted.
Programmable w ait one-shot
generation mode
Counts timer RB prescaler underflow s
(one-shot w idth is counted)
00h to FFh WO(2)
The values of registers TRBPR and TRBSC are reloaded to the counter alternately and counted.
When the TSTOP bit in the TRBCR register is set to 1, the TRBSC register is set to FFh.
WO(2)
Counts timer RB prescaler underflow s(1) 00h to FFh
Programmable one-shot
generation mode
Disabled 00h to FFh —
Programmable w aveform
generation mode
b7 b0
Time r mode —
Disabled 00h to FFh
Timer RB Primary Register(2)
Symbol Address After Reset
TRBPR 010Eh FFh
Mode Function Setting Range RW
NOTES:
1.
2.
Programmable w ait one-shot
generation mode
Counts timer RB prescaler underflow s
(w ait period w idth is counted)
00h to FFh RW
b0b7
Time r mode RW
Counts timer RB prescaler underflow s 00h to FFh
When the TSTOP bit in the TRBCR register is set to 1, the TRBPR register is set to FFh.
Programmable w aveform
generation mode RW
Counts timer RB prescaler underflow s(1) 00h to FFh
Programmable one-shot
generation mode
Counts timer RB prescaler underflow s
(one-shot w idth is counted)
00h to FFh RW
The values of registers TRBPR and TRBSC are reloaded to the counter alternately and counted.
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17.2.1 T imer Mode
In timer mode, a count source which is internally generated or timer RA underflows are counted (refer to Table
17.7 Timer Mode Specifications). Registers TRBOCR and TRBSC are not used in timer mode.
Figure 17.16 shows TRBIOC Register in Timer Mode.
Figure 17.16 TRBIOC Register in Timer Mode
Tab le 17.7 Timer Mode Specifications
Item Specification
Count sources f1, f2, f8, timer RA underflow
Count operations • Decrement
• When the timer underflows, it reloads the reload register contents before the
count continues (when timer RB underflows, the contents of timer RB primary
reload register is reloaded).
Divide ratio 1/(n+1)(m+1)
n: setting value in TRBPRE register, m: setting value in TRBPR register
Count start condition 1 (count starts) is written to the TSTART bit in the TRBCR register.
Count stop conditions • 0 (count stops) is written to the TSTART bit in the TRBCR register.
• 1 (count forcibly stop) is written to the TSTOP bit in the TRBCR register.
Interrupt request
generation timing
When timer RB underflows [timer RB interrupt].
TRBO pin function Programmable I/O port
INT0 pin function Programmable I/O port or INT0 interrupt input
Read from timer The count value can be read out by reading registers TRBPR and TRBPRE.
Write to timer • When registers TRBPRE and TRBPR are written while the count is stopped,
values are written to both the reload register and counter.
• When registers TRBPRE and TRBPR are written to while count operation is in
progress:
If the TWRC bit in the TRBMR register is set to 0, the value is written to both
the reload register and the counter.
If the TWRC bit is set to 1, the value is written to the reload register only.
(Refer to 17.2.1.1 Timer Write Control during Count Operation.)
Timer RB I/O Control Registe
r
Symbol Address After Reset
TRBIOC 010Ah 00h
Bit Symbol Bit Name Function RW
RW
RW
One-shot trigger control bit
Set to 0 in timer mode. RW
RW
00
TOPL Timer RB output level select
bit
Timer RB output sw itch bit
b7 b6 b5 b4 b3 b2
INOSEG
b1 b0
00
INOSTG
TOCNT
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
One-shot trigger polarity
select bit
—
(b7-b4) —
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17.2.1.1 Timer Write Control during Count Operation
Timer RB has a prescaler and a timer (which counts the prescaler underflows). The prescaler and timer each
consist of a reload register and a counter. In timer mode, the TWRC bit in the TRBMR register can be used to
select whether writing to the prescaler or timer during count operation is performed to both the reload register
and counter or only to the reload regist er.
However, values are transferred from the reload register to the counter of the prescaler in synchronization with
the count source. In addition, values are transferred from the reload register to the counter of the timer in
synchronization with prescaler underflows. Therefore, even if the TWRC bit is set for writing to both the reload
register and counter, the counter value is not updated immediately after the WRITE instruction is executed. In
addition, if the TWRC bit is set for writing to the reload register only, the synchronization of the writing will be
shifted if the prescaler value changes. Figure 1 7.17 shows an Operating Example of Timer RB when Counter
Value is Rewritten durin g Count Operation.
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Figure 17.17 Operating Example of Timer RB when Co unter Value is Rewritten during Count
Operation
Count source
Reloads register of
timer RB prescaler
IR bit in TRBIC
register 0
Counter of
timer RB prescaler
Reloads register of
timer RB
Counter of timer RB
Set 01h to the TRBPRE register and 25h to
the TRBPR register by a program.
After writing, the reload register is
written with the first count source.
Reload with
the second
count source
Reload on
underflow
After writing, the reload register is
written on the first underflow.
Reload on the second
underflow
The IR bit remains unchanged until underflow
is generated by a new value.
When the TWRC bit is set to 0 (write to reload register and counter)
Count source
Reloads register of
timer RB prescaler
IR bit in TRBIC
register
Counter of
timer RB prescaler
Reloads register of
timer RB
Counter of timer RB
Set 01h to the TRBPRE register and 25h to
the TRBPR register by a program.
After writing, the reload register is
written with the first count source.
Reload on
underflow
After writing, the reload register is
written on the first underflow.
Reload on
underflow
Only the prescaler values are updated,
extending the duration until timer RB underflow.
When the TWRC bit is set to 1 (write to reload register only)
05h 04h 03h 02h 01h 00h 01h 00h 01h 00h06h 01h 00h 01h
03h 00h02h 01h 25h
New value (25h)Previous value
New value (01h)Previous value
New value (01h)Previous value
05h 04h 01h 00h 01h 00h 01h 00h 01h 00h06h
New value (25h)Previous value
03h 24h02h 25h
The above applies under the following conditions.
Both bits TSTART and TCSTF in the TRBCR register are set to 1 (During count).
0
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17.2.2 Programmable Waveform Generation Mode
In programmable waveform generation mode, the signal output from the TRBO pin is inverted each time the
counter underflows, while the values in registers TRBPR and TRBSC a re counted alternately (refer to Table
17.8 Programmable Waveform Generation Mode Specifications). Counting starts by counting the setting
value in the TRBPR register. The TRBOCR register is unused in this mode.
Figure 17.18 shows TRBIOC Register in Programmable Waveform Generation Mode. Figure 17.19 shows an
Operating Example of Timer RB in Programmable Waveform Generation Mode.
NOTES:
1. Even when counting the secondary period, the TRBPR register may be read.
2. The set values are reflected in the waveform output beginning with the following primary period after writing to
the TRBPR register.
3. The value written to the TOCNT bit is enabled by the following.
•When counting starts.
•When a timer RB interrupt request is generated.
The contents after the TOCNT bit is changed are reflected from the output of the following primary period.
Table 17.8 Programmable Waveform Generation Mode Specifications
Item Specification
Count sources f1, f2, f8, timer RA underflow
Count operations • Decrement
• When the timer underflows, it reloads the contents of the primary reload and secondary
reload registers alternately before the count continues.
Width and period of
output waveform
Primary period: (n+1)(m+1)/fi
Secondary period: (n+1)(p+1)/fi
Period: (n+1){(m+1)+(p+1)}/fi
fi: Count source frequency
n: Value set in TRBPRE register
m: Value set in TRBPR register
p: Value set in TRBSC register
Count start condition 1 (count start) is written to the TSTART bit in the TRBCR register.
Count stop conditions • 0 (count stop) is written to the TSTART bit in the TRBCR register.
• 1 (count forcibly stop) is written to the TSTOP bit in the TRBCR register.
Interrupt request
generation timing
In half a cycle of the count source, after timer RB underflows during the secondary period
(at the same time as the TRBO output change) [timer RB interrupt]
TRBO pin function Programmable output port or pulse output
INT0 pin function Programmable I/O port or INT0 interrupt input
Read from timer The count value can be read out by reading registers TRBPR and TRBPRE.(1)
Write to timer • When registers TRBPRE, TRBSC, and TRBPR are written while the count is stopped,
values are written to both the reload register and counter.
• When registers TRBPRE, TRBSC, and TRBPR are written to during count operation,
values are written to the reload registers only.(2)
Select functions • Output level select function
The TOPL bit in the TRBIOC register selects the output level during primary and
secondary periods.
• TRBO pin output switch function
Timer RB pulse output or P3_1 (P1_3) latch output is selected by the TOCNT bit in the
TRBIOC register.(3)
• TRBO pin select function
P3_1 or P1_3 is selected by the TRBOSEL bit in the PINSR2 register.
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Figure 17.18 TRBIOC Register in Programmable Waveform Generation Mode
Timer RB I/O Control Registe
r
Symbol Address After Reset
TRBIOC 010Ah 00h
Bit Symbol Bit Name Function RW
—
(b7-b4) —
RW
RW
One-shot trigger control bit
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
One-shot trigger polarity
select bit
RW
TOCNT RW
00
TOPL
Timer RB output level select
bit
0 : Outputs “H” for primary period
Outputs “L” for secondary period
Outputs “L” w hen the timer is stopped
1 : Outputs “L” for primary period
Outputs “H” for secondary period
Outputs “H” w hen the timer is stopped
Timer RB output sw itch bit 0 : Outputs timer RB w avef orm
1 : Outputs value in P3_1 (P1_3) port register
b7 b6 b5 b4
Set to 0 in programmable w aveform generation
mode.
b3 b2
INOSEG
b1 b0
INOSTG
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Figure 17.19 Operating Example of Timer RB in Programmable Waveform Generation Mode
1
0
1
0
IR bit in TRBIC
register
1
0
Count source
Timer RB prescaler
underflow signal
Counter of timer RB
TRBO pin output
TOPL bit in TRBIO
register
Set to 1 by program
Set to 0 when interrupt
request is acknowledged,
or set by program.
The above applies under the following conditions.
TSTART bit in TRBCR
register
1
0
01h 00h 02h
Timer RB secondary reloads Timer RB primary reloads
Set to 0 by program
TRBPRE = 01h, TRBPR = 01h, TRBSC = 02h
TRBIOC register TOCNT = 0 (timer RB waveform is output from the TRBO pin)
02h 01h 00h 01h 00h
Primary period Primary periodSecondary period
Waveform
output starts Waveform output inverted Waveform output starts
Initial output is the same level
as during secondary period.
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17.2.3 Programmable One-shot Generation Mode
In programmable o ne-shot generat ion mode, a on e-shot pulse is o utput from the TRBO pin by a p rogram or an
external trigger input (input to the INT0 pin) (refer to Table 17.9 Programmable One-Shot Generation Mode
Specifications). When a trigger is generated, the timer starts operating from the point only once for a given
period equal to the set value in the TRBPR register. The TRBSC register is not used in this mo de.
Figure 17.20 shows TRBIO C Register in Programmabl e One-Shot Generation Mode. Figure 17.21 sho ws an
Operating Example of Programmable One-Shot Generation Mode.
NOTES:
1. The set value is reflected at the following one-shot pulse after writing to the TRBPR register.
2. Do not set both the TRBPRE and TRBPR registers to 00h.
Table 17.9 Programmable One-Shot Generation Mode Specifications
Item Specification
Count sources f1, f2, f8, timer RA underflow
Count operations • Decrement the setting value in the TRBPR register
• When the timer underflows, it reloads the contents of the reload register before
the count completes and the TOSSTF bit is set to 0 (one-shot stops).
• When the count stops, the timer reloads the contents of the reload register
before it stops.
One-shot pulse
output time
(n+1)(m+1)/fi
fi: Count source frequency,
n: Setting value in TRBPRE register, m: Setting value in TRBPR register(2)
Count start conditions • The TSTART bit in the TRBCR register is set to 1 (count starts) and the next
trigger is generated
• Set the TOSST bit in the TRBOCR register to 1 (one-shot starts)
• Input trigger to the INT0 pin
Count stop conditions • When reloading completes after timer RB underflows during primary period
• When the TOSSP bit in the TRBOCR register is set to 1 (one-shot stops)
• When the TSTART bit in the TRBCR register is set to 0 (stops counting)
• When the TSTOP bit in the TRBCR register is set to 1 (forcibly stops counting)
Interrupt request
generation timing
In half a cycle of the count source, after the timer underflows (at the same time as
the TRBO output ends) [timer RB interrupt]
TRBO pin function Pulse output
INT0 pin functions • When the INOSTG bit in the TRBIOC register is set to 0 (INT0 one-shot trigger
disabled): programmable I/O port or INT0 interrupt input
• When the INOSTG bit in the TRBIOC register is set to 1 (INT0 one-shot trigger
enabled): external trigger (INT0 interrupt input)
Read from timer The count value can be read out by reading registers TRBPR and TRBPRE.
Write to timer • When registers TRBPRE and TRBPR are written while the count is stopped,
values are written to both the reload register and counter.
• When registers TRBPRE and TRBPR are written during the count, values are
written to the reload register only (the data is transferred to the counter at the
following reload).(1)
Select functions • Output level select function
The TOPL bit in the TRBIOC register selects the output level of the one-shot
pulse waveform.
• One-shot trigger select function
Refer to 17.2.3.1 One-Shot Trigger Selection.
• TRBO pin select function
P3_1 or P1_3 is selected by the TRBOSEL bit in the PINSR2 register.
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Figure 17.20 TRBIOC Register in Programmable One-Shot Generation Mode
Timer RB I/O Control Register
Symbol Address After Reset
TRBIOC 010Ah 00h
Bit Symbol Bit Name Function RW
0 : INT0
_
____
pin one-shot trigger disabled
1 : INT0
_
____ pin one-shot trigger enabled
NOTE:
1. Refer to 17.2.3.1 One-Shot Trigger Selection.
Nothing is assigned. If necessary, set to 0.
When read, its content is 0.
One-Shot Trigger Polarity
Select Bit(1)
—
(b7-b4) —
b3 b2
INOSEG
b1 b0
0
INOSTG
b7 b6 b5 b4
RW
TOCNT RW
TOPL
Timer RB Output Level
Select Bit
0 : Outputs one-shot pulse “H”
Outputs “L” w hen the timer is stopped
1 : Outputs one-shot pulse “L”
Outputs “H” w hen the timer is stopped
Timer RB Output Sw itch Bit Set to 0 in programmable one-shot generation
mode.
RW
RW
One-Shot Trigger Control
Bit(1)
0 : Falling edge trigger
1 : Rising edge trigger
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Figure 17.21 Operating Example of Programmable One-Shot Generation Mode
TOSSTF bit in TRBOCR
register
INT0 pin input
1
0
1
0
IR bit in TRBIC
register
1
0
Count source
Timer RB prescaler
underflow signal
Counter of timer RB
TRBIO pin output
TOPL bit in
TRBIOC register
Set to 1 by program
Set to 1 by program
Set to 0 when interrupt request is
acknowledged, or set by program
The above applies under the following conditions.
TSTART bit in TRBCR
register
1
0
1
0
01h 00h 01h 00h 01h
Count starts Timer RB primary reloads Count starts Timer RB primary reloads
Set to 0 by program
Waveform output starts Waveform output ends Waveform output starts Waveform output ends
Set to 0 when
counting ends
Set to 1 by INT0 pin
input trigger
TRBPRE = 01h, TRBPR = 01h
TRBIOC register TOPL = 0, TOCNT = 0
INOSTG = 1 (INT0 one-shot trigger enabled)
INOSEG = 1 (edge trigger at rising edge)
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17.2.3.1 One-Shot Trigger Selection
In programmable one-shot generation mode and programmable wait one-shot generation mode, operation starts
when a one-shot trigger is generated while the TCSTF bit in the TRBCR register is set to 1 (count starts).
A one-shot trigger can be generated by either of the following causes:
•1 is written to the TOSST bit in the TRBOCR register by a program.
•Trigger input from the IN T0 pin.
When a one-shot trigger occurs, the TOSSTF bit in the TRBOCR register is set to 1 (one-shot operation in
progress) after one or two cycles of the count source have elapsed. Then, in programmable one-shot gen erati on
mode, count operation begins and one-shot waveform output starts. (In programmable wait one-shot generation
mode, count operation starts for the wait period.) If a one-shot trigger occurs w hile the TOSSTF bit is set to 1,
no retriggering occurs.
To use trigger input from the INT0 pin, input the trigger after making the following set tings:
•Set the PD4_5 bit in the PD4 register to 0 (input port).
•Select the INT0 digital filter with bits INT0F1 and INT0F0 in the INTF register.
•Select both edges or one edge with the INT0PL bit in INTEN register. If one edge is selected, further select
falling or rising edge with the INOSEG bit in TRBIOC register.
•Set the INT0EN bit in the INTEN register to 0 (enabled).
•After completing the above, set the INOSTG bit in the TRBIOC register to 1 (INT pin one-shot trigger
enabled).
Note the following points with regard to generating interrupt requests by trigger input from the INT0 pin.
•Processing to handle the interrupts is required. Refer to 13. Interrupts, for details.
•If one edge is selected, use the POL bit in the INT0IC register to select falling or rising edge. (The
INOSEG bit in the TRBIOC register does not affect INT0 interrupts).
•If a one-shot trigger occurs while the TOSSTF bit is set to 1, timer RB operation is not affected, but the
value of the IR bit in the INT0IC register changes.
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17.2.4 Programmable Wait One-Shot Generation Mode
In programmable wait one-shot generation mode, a one-shot pulse is output from the TRBO pin by a program
or an external trigger input (input to the INT0 pin) (refer to Table 17.10 Programmable Wait One-Shot
Generation Mode Specifications). When a trigge r is generated from that point, t he timer outp uts a pulse on ly
once for a given length of time equal to the setting value in the TRBSC register after waiting for a gi ven leng th
of time equal to the setting value in the TRBPR register.
Figure 17.22 shows TRBIOC Register in Pro grammable Wait One-Shot Ge neration Mode. Fig ure 17 .2 3 shows
an Operating Example of Programmable Wait One-Shot Generation Mode.
NOTES:
1. The set value is reflected at the following one-shot pulse after writing to registers TRBSC and TRBPR.
2. Do not set both the TRBPRE and TRBPR registers to 00h.
Table 17.10 Programmable Wait One-Shot Generation Mode Specifications
Item Specification
Count sources f1, f2, f8, timer RA underflow
Count operations • Decrement the timer RB primary setting value.
• When a count of the timer RB primary underflows, the timer reloads the contents of
timer RB secondary before the count continues.
• When a count of the timer RB secondary underflows, the timer reloads the contents
of timer RB primary before the count completes and the TOSSTF bit is set to 0
(one-shot stops).
• When the count stops, the timer reloads the contents of the reload register before it
stops.
Wait time (n+1)(m+1)/fi
fi: Count source frequency
n: Value set in the TRBPRE register, m Value set in the TRBPR register
(2)
One-shot pulse output time (n+1)(p+1)/fi
fi: Count source frequency
n: Value set in the TRBPRE register, p: Value set in the TRBSC register
Count start conditions • The TSTART bit in the TRBCR register is set to 1 (count starts) and the next trigger
is generated.
• Set the TOSST bit in the TRBOCR register to 1 (one-shot starts).
• Input trigger to the INT0 pin
Count stop conditions
• When reloading completes after timer RB underflows during secondary period.
• When the TOSSP bit in the TRBOCR register is set to 1 (one-shot stops).
• When the TSTART bit in the TRBCR register is set to 0 (starts counting).
• When the TSTOP bit in the TRBCR register is set to 1 (forcibly stops counting).
Interrupt request generation
timing
In half a cycle of the count source after timer RB underflows during secondary period
(complete at the same time as waveform output from the TRBO pin) [timer RB
interrupt].
TRBO pin function Pulse output
INT0 pin functions • When the INOSTG bit in the TRBIOC register is set to 0 (INT0 one-shot trigger
disabled): programmable I/O port or INT0 interrupt input
• When the INOSTG bit in the TRBIOC register is set to 1 (INT0 one-shot trigger
enabled): external trigger (INT0 interrupt input)
Read from timer The count value can be read out by reading registers TRBPR and TRBPRE.
Write to timer • When registers TRBPRE, TRBSC, and TRBPR are written while the count stops,
values are written to both the reload register and counter.
• When registers TRBPRE, TRBSC, and TRBPR are written to during count
operation, values are written to the reload registers only.(1)
Select functions • Output level select function
The TOPL bit in the TRBIOC register selects the output level of the one-shot pulse
waveform.
• One-shot trigger select function
Refer to 17.2.3.1 One-Shot Trigger Selection.
• TRBO pin select function
P3_1 or P1_3 is selected by the TRBOSEL bit in the PINSR2 register.
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Figure 17.22 TRBIOC Register in Programmable Wait One-Shot Generation Mode
Timer RB I/O Control Register
Symbol Address After Reset
TRBIOC 010Ah 00h
Bit Symbol Bit Name Function RW
0 : INT0
_
____ pin one-shot trigger disabled
1 : INT0
_
____
pin one-shot trigger enabled
NOTE:
1.
RW
RW
One-shot trigger control bit(1)
0 : Falling edge trigger
1 : Rising edge trigger
RW
TOCNT RW
TOPL
Timer RB output level select
bit
0: Outputs one-shot pulse “H”.
Outputs “L” w hen the timer stops or during
w ait.
1: Outputs one-shot pulse “L”.
Outputs “H” w hen the timer stops or during
w ait.
Timer RB output sw itch bit Set to 0 in programmable w ait one-shot generation
mode.
b7 b6 b5 b4 b3 b2
INOSEG
b1 b0
0
INOSTG
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
One-shot trigger polarity
select bit(1)
—
(b7-b4) —
Ref er to 17.2.3.1 One-Shot Trigger S election.
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Figure 17.23 Operating Example of Programmable Wait One-Shot Generation Mode
TOSSTF bit in TRBOCR
register
INT0 pin input
1
0
1
0
IR bit in TRBIC
register
1
0
Count source
Timer RB prescaler
underflow signal
Counter of timer RB
TRBIO pin output
TOPL bit in
TRBIOC register
Set to 1 by program
Set to 1 by setting 1 to TOSST bit in TRBOCR
register, or INT0 pin input trigger.
Set to 0 when interrupt request is
acknowledged, or set by program.
The above applies under the following conditions.
TSTART bit in TRBCR
register
1
0
1
0
01h 00h 00h 01h
Count starts Timer RB secondary reloads Timer RB primary reloads
Set to 0 by program
Wait starts Waveform output starts Waveform output ends
Set to 0 when
counting ends
TRBPRE = 01h, TRBPR = 01h, TRBSC = 04h
INOSTG = 1 (INT0 one-shot trigger enabled)
INOSEG = 1 (edge trigger at rising edge)
04h 03h 02h 01h
Wait
(primary period)
One-shot pulse
(secondary period)
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17.2.5 Notes on Timer RB
•Timer RB stops counting after a reset. Set the values in the timer RB and timer RB prescalers before the
count starts.
•Even if the prescaler and timer RB is read out in 16-bit units, these registers are read 1 byte at a time by the
MCU. Consequently, the timer value may be updated during the perio d when these two reg isters are being
read.
•In programmable one-shot generation mode and programmable wait one-shot generation mode, when
setting the TSTART bit in the TRBCR register to 0, 0 (stops counting) or setting the TOSSP bit in the
TRBOCR register to 1 (stops one-sh ot), th e timer rel oads the value of reload register and stops. Therefore,
in programmable one-shot generation mode and programmable wait one-shot generation mode, read the
timer count value before the timer stop s.
•The TCSTF bit remains 0 (count stops) for 1 to 2 cycles of the count source after setting the TSTART bit to
1 (count starts) while the count is stopped.
During this time, do not access registers associated with timer RB(1)other than the TCSTF bit. Timer RB
starts counting at the first valid edge of the count source after the TCSTF bit is set to 1 (during count).
The TCSTF bit remains 1 for 1 to 2 cycles of the count source after setting the TSTART bit to 0 (count
stops) while the count is in progress. Timer RB counting is stopped when the TCSTF bi t is set to 0.
During this time, do not access registers associated with timer RB(1) othe r than the TCSTF bit.
NOTE:
1. Registe rs a ssociated with t ime r R B: TRBCR, TRBOCR, TRBIOC, TRBMR, TRBPRE, TRBSC, and
TRBPR.
•If the TSTOP bit in the TRBCR register is set to 1 during timer operation, timer RB stops immediately.
•If 1 is written to the TOSST or TOSSP bit in the TRBOCR register, the value of the TOSSTF bit changes
after one or two cycles of the count source have elap sed. If th e TOSSP bit is written to 1 d uring the peri od
between when the TOSST bit is written to 1 and when the TOSSTF bit is set to 1, the TOSSTF bit may be
set to either 0 or 1 depending on the content state. Likewise, if the TOSST bit is written to 1 during the
period between when the TOSSP bit is written to 1 and when the TOSSTF bit is set to 0, the TOSSTF bit
may be set to either 0 or 1.
17.2.5.1 Timer mode
The following workaround should be performed in timer mode.
To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the following
points:
•When the TRBPRE register is written continuously, allow three or more cycles of the count source for each
write interval.
•When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow
for each write interval.
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17.2.5.2 Programmable waveform generation mode
The following three workarounds should be performe d in programmable waveform generation mode.
(1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the
following points:
•When the TRBPRE register is written continuously, allow three or more cycles of the count source for each
write interval.
•When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow
for each write interval.
(2) To change registers TR BPRE and TRBPR during count operation (TCSTF bit is set to 1), synchronize
the TRBO output cycle using a timer RB interrupt, etc. This operation should be preformed only once in
the same output cycle. Also, make sure that writing to the TRBPR register does not occur during period
A shown in Figures 17.24 and 17.25.
The following shows the detailed workaround examp les.
•Workaround example (a):
As shown in Figure 17.24, write to registers TRBSC and TRBPR in the timer RB interru pt routine. These
write operations must be completed by the beginni ng of period A.
Figure 17.24 Workaround Example (a) When Timer RB interrupt is Used
TRBO pin output
Count source/
prescaler
underflow signal
Primary period
Period A
IR bit in
TRBIC register
Secondary period
(b)
Interrupt
sequence
Instruction in
interrupt routine
Interrupt request is
acknowledged
(a)
Interrupt request
is generated
Ensure sufficient time
Set the secondary and then
the primary register immediately
(a) Period between interrupt request generation and the completion of execution of an instruction. The length of time
varies depending on the instruction being executed.
The DIVX instruction requires the longest time, 30 cycles (assuming no wait states and that a register is set as
the divisor).
(b) 20 cycles. 21 cycles for address match and single-step interrupts.
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•Workaround example (b):
As shown in Figure 17.25 detect the start of the primary period by th e TRBO pin output level and w rite to
registers TRBSC and TRBPR. These write operations must be completed by the beginning of period A.
If the port register’ s bit value is read after the port direction register’s bit corresponding to the TRBO pin is
set to 0 (input mode), the read value indicat es the TRBO pin output value.
Figure 17.25 Workaround Example (b) When TRBO Pin Output Value is Read
(3) To stop the timer counting in the primary period, use the TSTOP bit in the TRBCR register. In this case,
registers TRBPRE and TRBPR are initialized and their values are set to the values after reset.
17.2.5.3 Programmable one-shot generation mode
The following two workarounds should be performe d in programmable one-shot generation mode.
(1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the
following points:
•When the TRBPRE register is written continuousl y during count operatio n (TCSTF bit is set to 1), allow
three or more cycles of the count source for each write interval.
•When the TRBPR register is written continuously during count operation (TCSTF bit is set to 1), allow
three or more cycles of the prescaler underflow for each write interval.
(2) Do not set both the TRBPRE and TRBPR registers to 00h.
TRBO pin output
Count source/
prescaler
underflow signal
Primary period
Period A
Read value of the port register’s
bit corresponding to the TRBO pin
(when the bit in the port direction
register is set to 0)
Secondary period
(i)
The TRBO output inversion
is detected at the end of the
secondary period.
Ensure sufficient time
Upon detecting (i), set the secondary and
then the primary register immediately.
(ii) (iii)
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17.2.5.4 Programmable wait one-shot generation mode
The following three workarounds should be performe d in programmable wait one-shot generation mode.
(1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the
following points:
•When the TRBPRE register is written continuously, allow three or more cycles of the count source for each
write interval.
•When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow
for each write interval.
(2) Do not set both the TRBPRE and TRBPR registers to 00h.
(3) Set registers TRBSC and TRBPR using the following procedure.
(a) To use “INT0 pi n one-shot trigger enabled” as the count start condition
Set the TRBSC register and then the TRBPR register. At this time, after writing to the TRBPR
register, allow an interval of 0.5 or more cycles of the count source before trigger input from the
INT0 pin.
(b) To use “writing 1 to TOSST bit” as the start condition
Set the TRBSC register, the TRBPR register, and then TOSST bit. At this time, after writing to the
TRBPR register, allow an interval of 0.5 or m ore cycles of the count source before writing to the
TOSST bit.
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17.3 Timer RE
Timer RE has the 4-bit counter and 8-bit counter. Timer RE has the following 2 modes:
•Real-time cloc k mode Generate 1-second signal from fC4 and count seconds, m inutes, hours, and days of
the week.
•Output compare mode Count a count source and detect compare matches.
The count source for timer RE is the operating clock that regulates the timing of timer operations.
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17.3.1 Real-Time Clock Mode
In real-time clock mode, a 1-second signal is generated from fC4 using a divide-by-2 frequency divider, 4-bit
counter , and 8-bit counter and used to count seconds, minutes, hours, and days of the week. Figure 17.26 shows
a Block Diagram of Real-Time Clock Mode and Table 17.11 lists the Real-Time Clock Mode Specifications.
Figures 17.27 to 17.31 and 17.33 to 17.35 show the Registers Associated with Real-Time Clock Mode. Ta ble
17.12 lists the Interrupt Sources, Figure 17.32 shows the Definition of Time Representation and Figure 17.36
shows the Operating Example in Real-Time Clock Mode.
Figure 17.26 Block Diagram of Real-Time Clock Mode
TREWK
register
TREHR
register
TREMIN
register
TRESEC
register
H12_H24
bit
PM
bit
MNIE
HRIE
WKIE
000
DYIE
SEIE
Timer RE
interrupt
INT
bit
BSY
bit
Overflow
Timing
control
Data bus
Overflow Overflow
(1s) Overflow
(1/256)
(1/16)
fC4
(8.192kHz)
f2
RCS6 to RCS4
= 000b
= 010b
= 100b
= 011b
TOENA
= 001b
fC
f4
f8
8-bit counter4-bit counter1/2
TOENA, H12_H24, PM, INT: Bits in TRECR1 register
SEIE, MNIE, HRIE, DYIE, WKIE: Bits in TRECR2 register
BSY: Bit in TRESEC, TREMIN, TREHR, TREWK register
RCS4 to RCS6: Bits in TRECSR register
TREOSEL: Bit in PINSR3 register
TREOSEL2: Bit in PINSR4 register
PLUS
MIN US
Data
(D5 to D0)
TREO (P6_0)
pin
TREOSEL=1
TREOSEL=0
TREO (P0_4)
pin
TREOSEL2=0
TREO (P6_5)
pin
TREOSEL2=1
TREOPR
register
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Table 17.11 Real-Time Clock Mode Specifications
Item Specification
Count source fC4
Count operation Increment
Count start condition 1 (count starts) is written to TSTART bit in TRECR1 register
Count stop condition 0 (count stops) is written to TSTART bit in TRECR1 register
Interrupt request generation
timing
Select any one of the following:
• Update second data
• Update minute data
• Update hour data
• Update day of week data
• When day of week data is set to 000b (Sunday)
TREO pin function Programmable I/O ports or output of f2, fC, f4, f8 or, 1Hz
Read from timer When reading TRESEC, TREMIN, TREHR, or TREWK register, the count
value can be read. The values read from registers TRESEC, TREMIN,
and TREHR are represented by the BCD code.
Write to timer When bits TSTART and TCSTF in the TRECR1 register are set to 0 (timer
stops), the value can be written to registers TRESEC, TREMIN, TREHR,
and TREWK. The values written to registers TRESEC, TREMIN, and
TREHR are represented by the BCD codes.
Selectable functions • 12-hour mode/24-hour mode switch function
• Counter precision adjustment function
• TREO pin select function
P0_4, P6_0, or P6_5 is selected by the TREOSEL bit in the PINSR3
register and the TREOSEL2 bit in the PINSR4 register.
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Figure 17.27 TRESEC Register in Real-Time Clock Mode
Figure 17.28 TREMIN Register in Real-Time Clock Mode
Timer RE Second Data Register
Symbol Address Af ter Reset
TRESEC 0118h Undef ined
Bit Symbol Bit Name Function Setting
Range RW
SC02 RW
RW
SC10 RW
SC11
BSY RO
SC12
SC01 RW
Count 0 to 9 every second. When the
digit moves up, 1 is added to the 2nd
digit of second.
0 to 9
(BCD
code)
SC00 RW
b7 b6 b5 b4
RW
b3 b2
SC03
b1 b0
1st digit of second count bits
RW
Timer RE busy flag
2nd digit of second count bits When counting 0 to 5, 60 seconds
are counted.
0 to 5
(BCD
code)
This bit is set to 1 w hile registers TRESEC,
TREMIN, TREHR, and TREWK are updated.
Timer RE Minute Data Register
Symbol Address Af ter Reset
TREMIN 0119h Undefined
Bit Symbol Bit Name Function Setting
Range RW
Timer RE busy flag
2nd digit of minute count bits When counting 0 to 5, 60 minutes are
counted.
0 to 5
(BCD
code)
This bit is set to 1 w hile registers TRESEC,
TREMIN, TREHR, and TREWK are updated.
RW
b3 b2
MN03
b1 b0
RW
b7 b6 b5 b4
MN00 RW1st digit of minute count bits
MN0 1 RW
Count 0 to 9 every minute. When the
digit moves up, 1 is added to the 2nd
digit of minute.
0 to 9
(BCD
code)
MN02 RW
RW
MN10 RW
MN11
BSY RO
MN12
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Figure 17.29 TREHR Register in Real-Time Clock Mode
Figure 17.30 TREWK Register in Real-Time Clock Mode
Timer RE Hour Data Register
Symbol Address Af ter Reset
TREHR 011Ah X0XXXXXXb
Bit Symbol Bit Name Function Setting
Range RW
Timer RE busy flag This bit is set to 1 w hile registers TRESEC,
TREMIN, TREHR, and TREWK are updated.
2nd digit of hour count bits Count 0 to 1 w hen the H12_H24 bit is
set to 0 (12-hour mode).
Count 0 to 2 w hen the H12_H24 bit is
set to 1 (24-hour mode).
0 to 2
(BCD
code)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0. —
b3 b2
HR03
b1 b0
RW
b7 b6 b5 b4
HR00 RW1st digit of hour count bits
HR01 RW
Count 0 to 9 every hour. When the
digit moves up, 1 is added to the 2nd
digit of hour.
0 to 9
(BCD
code)
HR02 RW
RW
HR10 RW
HR11
BSY RO
—
(b6)
Timer RE Day of Week Data Register
Symbol Address Af ter Reset
TREWK 011Bh X0000XXXb
Bit Symbol Bit Name Function RW
WK2 RW
—
BSY RO
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Timer RE busy f lag This bit is set to 1 w hile registers TRESEC,
TREMIN, TREHR, and TREWK are updated.
RW
WK1 RW
Day of w eek count bits b2 b1 b0
0 0 0 : Sunday
0 0 1 : Monday
0 1 0 : Tuesday
0 1 1 : Wednesday
1 0 0 : Thursday
1 0 1 : Friday
1 1 0 : Saturday
1 1 1 : Do not set.
b7 b6 b5 b4 b3 b2
—
(b6-b3)
b1 b0
WK0
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Figure 17.31 TRECR1 Register in Real-Time Clock Mode
Figure 17.32 Definition of Time Representation
Timer RE Control Register 1
Symbol Address Af ter Reset
TRECR1 011Ch XXX0X0X0b
Bit Symbol Bit Name Function RW
NOTE:
1.
b3 b2
INT
b1 b0
—
(b0)
b7 b6 b5 b4
—
TCSTF RO
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Timer RE count status flag 0 : Count stopped
1 : Counting
TREO pin output enable bit 0 : Disable clock output
1 : Enable clock output
This bit is automatically modified w hile timer RE counts.
TOENA RW
RW
TSTA RT Timer RE count start bit 0 : Count stops
1 : Count starts RW
Interrupt request timing bit Set to 1 in real-time clock mode.
PM
A.m./p.m. bit When the H12_H24 bit is set to 0
(12-hour mode)(1)
0 : a.m.
1 : p.m.
When the H12_H24 bit is set to 1 (24-hour
mode), its value is undefined.
TRERST
Timer RE reset bit When setting this bit to 0, after setting it to 1, the
f ollow ings w ill occur.
• Re g is ter s TRESEC, TREMIN, TREHR, TREWK ,
and TRECR2 are set to 00h.
• Bits TCSTF, INT, PM, H12_H24, and TSTART
in the TRECR1 register are set to 0.
• The 8-bit counter is set to 00h and
the 4-bit counter is set to 0h.
RW
RW
H12_H24 Operating mode select bit 0 : 12-hour mode
1 : 24-hour mode RW
Noon
H12_H24 bit = 1
(24-hour mode)
Contents of PM bit 0 (a.m.) 1 (p.m.)
Contents of
TREHR Register H12_H24 bit = 0
(12-hour mode)
Contents in TREWK register 000 (Sunday)
0 1 2 3 4 5 7 9 11 13 15 176 8 10 12 14 16
0 1 2 3 4 5 7 9 11 1356810 024
H12_H24 bit = 1
(24-hour mode)
Contents of PM bit 1 (p.m.)
Contents of
TREHR Register H12_H24 bit = 0
(12-hour mode)
Contents in TREWK register 000 (Sunday)
18 19 20 21 22 23 1 30 2 ⋅⋅⋅
6 7 8 9 10 11 1 30 2
Date changes
⋅⋅⋅
⋅⋅⋅0 (a.m.)
001 (Monday) ⋅⋅⋅
PM bit and H12_H24 bits: Bits in TRECR1 register
The above applies to the case when count starts from a.m. 0 on Sunday.
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Figure 17.33 TRECR2 Register in Real-Time Clock Mode
Table 17.12 Interrupt Sources
Factor Interrupt Source Interrupt Enable Bit
Periodic interrupt
triggered every week
Value in TREWK register is set to 000b (Sunday)
(1-week period)
WKIE
Periodic interrupt
triggered every day
TREWK register is updated (1-day period) DYIE
Periodic interrupt
triggered every hour
TREHR register is updated (1-hour period) HRIE
Periodic interrupt
triggered every minute
TREMIN register is updated (1-minute period) MNIE
Periodic interrupt
triggered every second
TRESEC register is updated (1-second period) SEIE
Timer RE Control Register 2
Symbol Address Af ter Reset
TRECR2 011Dh 00XXXXXXb
Bit Symbol Bit Name Function RW
NOTE:
1.
b3 b2
DY IE
b1 b0
SEIE
b7 b6 b5 b4
0
RW
MNIE RW
Periodic interrupt triggered every
minute enable bit(1)
0 : Disable periodic interrupt triggered
every minute
1 : Enable periodic interrupt triggered
every minute
Periodic interrupt triggered every
second enable bit(1)
0 : Disable periodic interrupt triggered
every second
1 : Enable periodic interrupt triggered
every second
Periodic interrupt triggered every
hour enable bit(1)
0 : Disable periodic interrupt triggered
every hour
1 : Enable periodic interrupt triggered
every hour
Do not set multiple enable bits to 1 (enable interrupt).
HRIE RW
RW
Periodic interrupt triggered every day
enable bit(1)
0 : Disable periodic interrupt triggered
every day
1 : Enable periodic interrupt triggered
every day
COMIE Compare match interrupt enable bit
RW
RW
—
(b7-b6) —
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Set to 0 in real-time clock mode.
WKIE
Periodic interrupt triggered every
w eek enable bit(1)
0 : Disable periodic interrupt triggered
every w eek
1 : Enable periodic interrupt triggered
every w eek
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Figure 17.34 TRECSR Register in Real-Time Clock Mode
Figure 17.35 TREOPR Regist er in Real -Time Clock Mod e
Timer RE Count Source Select Register
Symbol Address Af ter Reset
TRECSR 011Eh 00001000b
Bit Symbol Bit Name Function RW
NOTE:
1.
b3 b2
RCS3
b1 b0
0010
RCS0
b7 b6 b5 b4
RW
RCS1 RW
Count source select bits Set to 00b in real-time clock mode.
4-bit counter select bit Set to 0 in real-time clock mode.
Write to bits RCS4 to RCS6 w hen the TOENA bit in the TRECR1 register is set to 0 (disable clock output).
RCS2 RW
RW
—
(b7) —
Real-time clock mode select bit Set to 1 in real-time clock mode.
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
RW
RW
RCS6 RW
RCS5
RCS4 Clock output select bits(1) b6 b5 b4
0 0 0 : f2
0 0 1 : fC
0 1 0 : f4
0 1 1 : 1Hz
1 0 0 : f8
Other than above : Do not set.
Timer RE Real-Time Clock Precision Adjust Register(1)
Symbol Address Af ter Reset
TREOPR 011Fh 00h
Bit Symbol Bit Name Function Setting
Range RW
8-bit counter subtract bit(2)
8-bit counter add bit(2)
NOTES:
1.
2.
When this bit is set to 1, the correction value set
by D0 to D5 is subtracted from the 8-bit counter
value.
When read, the content is 0.
Use the MOV instruction for setting the TREOPR register.
Allow a period (s) of the XCIN clock × 2064 or more betw een w rites to the TREOPR register.
D2 RW
RW
PLUS RW
RW
RW
MINUS RW
RW
D1 RW
The correction value of the 8-bit
counter is stored.
When read, the content is 000000b.
00h to 3Ch
D5
D4
D0
b7 b6 b5 b4
When this bit is set to 1, the correction value set
by D0 to D5 is added to the 8-bit counter value.
When read, the content is 0.
8-bit counter adjust bit
Write 1 to either the MINUS bit or the PLUS bit only once during each interrupt routine for the
w eek/day/hour/minute/second cycle.
When 00b or 11b is w ritten to bits MINUS and PLUS, the 8-bit counter value is not added or subtracted.
b3 b2
D3
b1 b0
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Figure 17.36 Operating Example in Real-Time Clock Mode
IR bit in TREIC register
03
IR bit in TREIC register
Bits WK2 to WK0 in
TREWK register
(when SEIE bit in TRECR2 register is set
to 1 (enable periodic interrupt triggered
every second))
(when MNIE bit in TRECR2 register is set
to 1 (enable periodic interrupt triggered
every minute))
1
0
PM bit in
TRECR1 register
Bits HR11 to HR00 in
TREHR register (Not changed)
Set to 0 by acknowledgement
of interrupt request
or a program
04
Bits MN12 to MN00 in
TREMIN register
58 59 00
BSY bit
Approx.
62.5 ms
Bits SC12 to SC00 in
TRESEC register
1s
BSY: Bit in registers TRESEC, TREMIN, TREHR, and TREWK
Approx.
62.5 ms
1
0
1
0
(Not changed)
(Not changed)
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17.3.2 Output Compare Mode
In output com pare mode, the inte rnal count so urce divided by 2 is counted using t he 4-bit or 8-bit count er and
compare value match is detected with the 8-bit counter. Figure 17.37 shows a Block Diagram of Output
Compare Mode and Table 17.13 lists the Output Compare Mode Specifications. Figures 17.38 to 17.42 show
the Registers Associated with Output Compare Mode, and Figure 17.43 shows the Operating Example in
Output Compare Mode.
Figure 17.37 Block Diagram of Output Compare Mode
fC4
f32
f4
f8
4-bit
counter 8-bit
counter
TRESEC TREMIN
1/2
RCS2 = 1
RCS2 = 0
COMIE Timer RE interrupt
Match
signal
= 00b
= 01b
= 10b
= 11b
RCS1 to RCS0
TRERST, TOENA: Bits in TRECR1 register
COMIE: Bit in TRECR2 register
RCS0 to RCS2, RCS5 to RCS6: Bits in TRECSR register
TREOSEL: Bit in PINSR3 register
TREOSEL2: Bit in PINSR4 register
TQ
R
Reset
TRERST
Data bus
Comparison
circuit
f2
RCS6 to RCS4
=000b
=010b
=100b
=110b
TOENA
=001b
fC
TREO (P6_0)
pin
TREOSEL=1
TREOSEL=0
TREO (P0_4)
pin
TREOSEL2=0
TREO (P6_5)
pin
TREOSEL2=1
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Table 17.13 Output Compare Mode Specifications
Item Specification
Count sources f4, f8, f32, fC4
Count operations • Increment
• When the 8-bit counter content matches with the TREMIN register
content, the value returns to 00h and count continues.
The count value is held while count stops.
Count period • When RCS2 = 0 (4-bit counter is not used)
1/fi x 2 x (n+1)
• When RCS2 = 1 (4-bit counter is used)
1/fi x 32 x (n+1)
fi: Frequency of count source
n: Setting value of TREMIN register
Count start condition 1 (count starts) is written to the TSTART bit in the TRECR1 register
Count stop condition 0 (count stops) is written to the TSTART bit in the TRECR1 register
Interrupt request generation
timing
When the 8-bit counter content matches with the TREMIN register content
TREO pin function Select any one of the following:
• Programmable I/O ports
• Output f2, fC, f4, or f8
• Compare output
Read from timer When reading the TRESEC register, the 8-bit counter value can be read.
When reading the TREMIN register, the compare value can be read.
Write to timer Writing to the TRESEC register is disabled.
When bits TSTART and TCSTF in the TRECR1 register are set to 0 (timer
stops), writing to the TREMIN register is enabled.
Selectable functions • Select use of 4-bit counter
• Compare output function
Every time the 8-bit counter value matches the TREMIN register value,
TREO output polarity is reversed. The TREO pin outputs “L” after reset
is deasserted and the timer RE is reset by the TRERST bit in the
TRECR1 register. Output level is held by setting the TSTART bit to 0
(count stops).
• TREO pin select function
P0_4, P6_0, or P6_5 is selected by the TREOSEL bit in the PINSR3
register and the TREOSEL2 bit in the PINSR4 register.
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Figure 17.38 TRESEC Register in Output Compare Mode
Figure 17.39 TREMIN Register in Output Compar e Mode
Timer RE Counter Data Register
Symbol Address After Reset
TRESEC 0118h Undefined
RWFunction
8-bit counter data can be read.
Although Timer RE stops counting, the count value is held.
The TRESEC register is set to 00h at the compare match.
b7 b6 b5 b4 b3 b2 b1 b0
RO
Timer RE Compare Data Register
Symbol Address After Reset
TREMIN 0119h Undefined
RWFunction
8-bit compare data is stored.
b7 b6 b5 b4 b3 b2 b1 b0
RW
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Figure 17.40 TRECR1 Register in Output Compare Mode
Figure 17.41 TRECR2 Register in Output Compare Mode
Timer RE Control Register 1
Symbol Address Af ter Reset
TRECR1 011Ch XXX0X0X0b
Bit Symbol Bit Name Function RW
H12_H24 Operating mode select bit RW
Set to 0 in output compare mode.
Timer RE reset bit When setting this bit to 0, after setting it to 1, the
f ollow ing w ill occur.
• Re gis ter s TRESEC, TREMIN, TREHR, TREWK,
and TRECR2 are set to 00h.
• Bits TCSTF, INT, PM, H12_H24, and
TSTART in the TRECR1 register are
set to 0.
• The 8-bit counter is set to 00h and
the 4-bit counter is set to 0h.
RW
RW
TREO pin output enable bit 0 : Disable clock output
1 : Enable clock output
TOENA RW
RW
TSTA RT Timer RE count start bit 0 : Count stops
1 : Count starts RW
Interrupt request timing bit Set to 0 in output compare mode.
PM A.m./p.m. bit
TRERST
—
TCSTF RO
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Timer RE count status flag 0 : Count stopped
1 : Counting
00
b7 b6 b5 b4 b3 b2
INT
b1 b0
0
—
(b0)
Timer RE Control Register 2
Symbol Address Af ter Reset
TRECR2 011Dh 00XXXXXXb
Bit Symbol Bit Name Function RW
b3 b2
DY IE
b1 b0
0000
SEIE
b7 b6 b5 b4
Periodic interrupt triggered every
minute enable bit
Periodic interrupt triggered every
second enable bit
0
HRIE RW
RW
Periodic interrupt triggered every
day enable bit
COMIE Compare match interrupt enable bit
RW
RW
—
(b7-b6) —
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
0 : Disable compare match interrupt
1 : Enable compare match interrupt
WKIE Periodic interrupt triggered every
w eek enable bit
Set to 0 in output compare mode.
Periodic interrupt triggered every
hour enable bit
RW
MNIE RW
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Figure 17.42 TRECSR Register in Output Compare Mode
Timer RE Count Source Select Register
Symbol Address Af ter Reset
TRECSR 011Eh 00001000b
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
Clock output select bits(2) b6 b5 b4
0 0 0 : f2
0 0 1 : fC
0 1 0 : f4
1 0 0 : f8
1 1 0 : Compare output
Other than above : Do not set.
Write to bits RCS0 to RCS1 w hen the TCSTF bit in the TRECR1 register is set to 0 (count stopped).
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
RW
RW
RCS6 RW
RCS5
RCS4
4-bit counter select bit 0 : Not used
1 : Used
Write to bits RCS4 to RCS6 w hen the TOENA bit in the TRECR1 register is set to 0 (disable clock output).
RCS2 RW
RW
—
(b7) —
Real-time clock mode select bit Set to 0 in output compare mode.
RW
RCS1 RW
Count source select bits(1) b1 b0
0 0 : f4
0 1 : f8
1 0 : f32
1 1 : fC4
b7 b6 b5 b4 b3 b2
RCS3
b1 b0
0
RCS0
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Figure 17.43 Operating Example in Output Compare Mode
2 cycles of maximum count source
00h
8-bit counter content
(hexadecimal number)
Count starts
Time
TSTART bit in
TRECR1 register
1
0
IR bit in
TREIC register
1
0
The above applies under the following conditions.
TOENA bit in TRECR1 register = 1 (enable clock output)
COMIE bit in TRECR2 register = 1 (enable compare match interrupt)
RCS6 to RCS5 bits in TRECSR register = 11b (compare output)
Set to 1 by a program
Set to 0 by acknowledgement of interrupt request
or a program
TREMIN register
setting value
Matched
TREO output 1
0
TCSTF bit in
TRECR1 register
1
0
Output polarity is inverted
when the compare matches
Matched Matched
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17.3.3 Notes on Timer RE
17.3.3.1 Starting and Stopping Count
Timer RE has the TSTART bit for instru cting the count to start or stop, and the TCSTF bit, which indicates
count start or stop. Bits TSTART and TCSTF are in the TRECR1 register .
Timer RE starts coun ting and the TCSTF bit is set to 1 (count starts) when the TSTART bit is set to 1 (count
starts). It takes up to 2 cycles of the count source until the TCSTF bit is set to 1 after setting the TSTART bit to
1. During this time, do not access registers associated with timer RE(1) other than the TCSTF bit.
Also, timer RE stops counting when setting the TSTA RT bit to 0 (count stops) and the TCSTF bit is set to 0
(count stops). It takes the tim e for up to 2 cycles of the count source unti l the TCSTF bit is set to 0 afte r setting
the TSTART bit to 0. During this ti me, do not access registers associated with timer RE other than the TCSTF
bit.
NOTE:
1. Registers associated with timer RE:
TRESEC, TRE MIN, TR EHR, TREW K, TRECR 1, TREC R2, TRECSR ,
and TREOPR.
17.3.3.2 Register Setting
Write to the following registers or bits when timer RE is stopped.
•Registers TRESEC, TREMIN, TREHR, TREWK, and TRECR2
•Bits H12_H24, PM, and INT in TRECR1 register
•Bits RCS0 to RCS3 in TRECSR register
Timer RE is stopped when bits TSTART and TCSTF in the TRECR1 register are set to 0 (timer RE stopped).
Also, set all above-mentioned registers and bits (immediately before timer RE count starts) before setting the
TRECR2 register.
Figure 17.44 shows a Setting Example in Real-Time Clock Mode.
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Figure 17.44 Setting Example in Real-Time Clock Mode
Stop timer RE operation
TCSTF in
TRECR1 register = 0?
TSTART in TRECR1 register = 0
Setting of registers TRECSR,
TRESEC, TREMIN, TREHR, TREWK,
and bits H12_H24, PM, and INT in
TRECR1 register
Setting of TRECR2 register
TSTART in TRECR1 register = 1
TCSTF in
TRECR1 register = 1?
TREIC register ← 00h
(disable timer RE interrupt)
Setting of TREIC register (IR bit ← 0,
select interrupt priority level)
Select clock output
Select clock source
Seconds, minutes, hours, days of week, operating mode
Set a.m./p.m., interrupt timing
Select interrupt source
Start timer RE operation
TOENA in TRECR1 register = 0 Disable timer RE clock output
(When it is necessary)
TOENA in TRECR1 register = 1 Enable timer RE clock output
(When it is necessary)
TRERST in TRECR1 register = 1
TRERST in TRECR1 register = 0
Timer RE register
and control circuit reset
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17.3.3.3 Time Reading Procedure of Real-Time Clock Mode
In real-time clock mode, read registers TRESEC, TREMIN, TREHR, and TREWK when time data is updated
and read the PM bit in the TRECR1 register when the BSY bit is set to 0 (not while data is updated).
Also, when reading several registers, an incorrect time will be read if data is updated befo re another register is
read after reading any register.
In order to prevent this, use the reading procedure shown below.
•Using an interrupt
Read necessary contents of registers TRESEC, TREMIN, TREHR, and TREWK and the PM bit in the
TRECR1 register in the timer RE interrupt routine.
•Monitoring with a program 1
Monitor the IR bit in the TREIC register with a program and read necessary contents of registers TRESEC,
TREMIN, TREHR, and TREWK and the PM bit in the TRECR1 register after the IR bit in the TREIC
register is set to 1 (timer RE interrupt request generated).
•Monitoring with a program 2
(1) Monitor the BSY bit.
(2) Monitor until the BSY bit is set to 0 after the BSY bit is set to 1 (approximately 62.5 ms whil e the BSY
bit is set to 1).
(3) Read necessary contents of registers TRESEC, TREMIN, TRE HR, and TREW K and the PM bit in the
TRECR1 register after the BSY bit is set to 0.
•Using read results if they are the same value twice
(1) Read necessary contents of registers TRESEC, TREMIN, TRE HR, and TREW K and the PM bit in the
TRECR1 register.
(2) Read the same register as (1) and compare the contents.
(3) Recognize as the correct value if the contents match. If the contents do not mat ch, repeat u ntil the read
contents match with the previous contents.
Also, when reading several registers, read them as continuously as possible.
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17.4 Timer RF
Timer RF is a 16-bit timer. The count source for timer RF is the operating clock that regulates the timing of timer
operations. Figure 17.45 shows a Block Diagram of Timer RF. Figure 17.46 shows a Block Diagram of CMP
Waveform Generation Unit. Figure 17.47 shows a Block Diagram of CMP Waveform Output Unit.
T imer RF has two modes: input capture mode and output compare mode. Figures 17.48 to 17.51 show the timer RF
associated registers.
Figure 17.45 Block Diagram of Timer RF
TRFM0 register
Data bus
= 00b
= 01b
f8
f1
= 10b
f32
TCK1 to TCK0
TSTART CCLR = 1
CCLR = 0
Capture signal
Timer RF
interrupt
Compare 1
interrupt
Timer RF counter
clear signal
TSTART, TCK0 to TCK1: Bits in TRFCR0 register
TIPF0 to TIPF1, CCLR: Bits in TRFCR1 register
TRFC20: Bit in TRFCR2 register
TRFOSEL: Bit in PINSR4 register
Compare 0
interrupt
TRF register
TRFM1 register
Capture interrupt
Capture, Compare 0 register
Counter
Compare 1 register
Comparator
Comparator
= 01b
= 10b
f8
f1
Digital
filter
= 11b
f32
TIPF1 to TIPF0
= other than
00b
= 00b
TRFI
Sampling clock
TRFC20 = 1
TRFC20 = 0
fC32
Edge
detection
CMP
waveform
generation
unit
TRFO00
TRFO01
TRFO02
TRFO10
TRFO11 (P3_4)
TRFO12
TRFOSEL = 0
TRFOSEL = 1
TRFO11 (P3_7)
CMP waveform
output unit
CMP waveform
output unit
CMP waveform
output unit
CMP waveform
output unit
CMP waveform
output unit
CMP waveform
output unit
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Figure 17.46 Block Diagram of CMP Waveform Generation Unit
Figure 17.47 Block Diagram of CMP Waveform Output Unit
TRFC14
CMP output
(internal signal)
TRFC14 to TRFC17: Bits in TRFC1 register
Latch
DQ
= 11b
= 10b
“L”
“H”
= 01b
Inverted
TRFC17 to TRFC16
= 01b
= 10b
“L”
“H” = 11b
TRFC15 to TRFC14
T
TRFC15
Compare 0 interrupt signal
TRFC16
TRFC17
R
Reset
Compare 1 interrupt signal
Inverted
Inverted
CMP output
(Internal signal)
TRFOUT6 = 0
TRFOUT6 = 1
TRFOUT0 = 1
TRFOUT0 = 0
TRFO00
P1_0 bit
This diagram is a block diagram of the TRFO00 waveform output unit.
The TRFO01 to TRFO02 and TRFO10 to TRFO12 waveform output units have the same configuration.
TRFOUT0 and TRFOUT6: Bits in TRFOUT register
P1_0: Bit in P1 register
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Figure 17.48 Registers TRF, TRFM0, and TRFM1
Compare 1 Register(1)
Symbol Address After Reset
TRFM1 029Fh-029Eh FFFFh
Function Setting Range RW
NOTE:
1.
Mode
Output compare mode
(b8)
b0
(b15)
b7 b0b7
0000h to FFFFh RW
Access the TRFM1 register in 16-bit units.
Store the value compared w ith TRF
register (counter)
Capture and Compare 0 Register(1)
Symbol Address After Reset
TRFM0 029Dh-029Ch 0000h(2)
Function Setting Range RW
NOTES:
1.
2.
3.
Mode
b7
When setting a value in the TRFM0 register, set the TMOD bit in the TRFCR1 register to 1 (output compare mode).
When the TMOD bit is set to 0 (input capture mode), no value can be w ritten.
(b8)
b0
(b15)
b7 b0
―
When the active edge of the measured
pulse is input, store the value in the TRF
register
When the TMOD bit in the TRFCR1 register is set to 1, the value is set to FFFFh.
Access the TRFM0 register in 16-bit units.
Input capture mode
RW
Output compare mode(3) Store the value compared w ith TRF
register (counter)
0000h to FFFFh
RO
Timer RF Register(1)
Symbol Address Af ter Reset
TRF 0291h-0290h 0000h
RW
NOTE:
1. Access the TRF register in 16-bit units.
(b8)
b0
(b15)
b7
Function
Count source increment .
0000h can be read w hen the TSTART bit is set to 0 (count stops).
Count value can be read w hen the TSTART bit is set to 1 (count starts).
RO
b0b7
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Figure 17.49 Registers TRFCR2 and TRFCR0
Timer RF Control Register 2
Symbol Address After Reset
TRFCR2 0299h 00h
Bit Symbol Bit Name Function RW
—
(b6-b5)
—
(b7) —
TRFC20 RW
—
(b4-b1) —
Timer RF capture input select bit 0 : TRFI pin input
1 : fC32
b3 b2 b1 b0
00
b7 b6 b5 b4
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Set to 0. RW
Res er v ed bits
Timer RF Control Register 0
Symbol Address After Reset
TRFCR0 029Ah 00h
Bit Symbol Bit Name Function RW
NOTE:
1.
b4 b3
0 0 : Rising edge
0 1 : Falling edge
1 0 : Both edges
1 1 : Do not set.
RW
RW
TRFC04 RW
TRFC03
0 : TRFC06 bit disabled
Holds output level before count stops
1 : TRFC06 bit enabled
Capture polarity select bits(1)
RW
b7 b6 b5 b4
0
b3 b2 b1 b0
TCK0 RW
Timer RF count start bit 0 : Count stops
1 : Count starts
Timer RF count source select
bits(1)
b2 b1
0 0 : f1
0 1 : f8
1 0 : f32
1 1 : Do not set.
TCK1 RW
TSTA RT RW
Rew rite this bit w hen the TSTART bit is set to 0 (count stops).
CMP output select bit 0 w hen
count stops
TRFC05
TRFC06 CMP output select bit 1 w hen
count stops
0 : “L” output w hen count stops
1 : “H” output w hen count stops
—
(b7)
Reserved bit Set to 0. RW
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Figure 17.5 0 TRFCR1 Regi st er
Figure 17.51 TRFOUT Register
Timer RF Control Register 1
Symbol Address After Reset
TRFCR1 029Bh 00h
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
4.
When the TMOD bit is set to 0 (input capture mode), set bits CCLR, and TRFC14 to TRFC17 to 0.
When the TSTART bit in the TRFCR0 register is set to 0 (count stops), rew rite bits CCLR and TMOD.
RW
TRFC17
TRFC16
Compare 1 output select
bits(2)
b7 b6 CMP output w hen compare 0 is matched
0 0 : Unchanged
0 1 : Inverted
1 0 : “L”
1 1 : “H”
If filter enabled, w hen the same value from the TRFI pin is sampled three times continuously, the input is determined.
b3 b2
0 : Free-running operation
1 : Set TRF register to 0000h w hen compare
1 is matched.
b1 b0
TIPF1
b7 b6 b5 b4
RW
TRFC15
TIPF0
TMOD Timer RF operation mode
select bit(3)
CCLR
TRFC14
TRFI f ilter select bits(1)
When the TMOD bit is set to 0 (input capture mode), set bits ILVL2 to ILVL0 in the CMP1IC register to 000b (level 0)
and set the IR bit to 0 (no interrupt requested).
RW
TRF register count operation
select bit(2, 3)
Compare 0 output select
bits(2)
b5 b4 CMP output w hen compare 0 is matched
0 0 : Unchanged
0 1 : Inverted
1 0 : “L”
1 1 : “H”
RW
b1 b0
0 0 : No filter
0 1 : Filter w ith f1 sampling
1 0 : Filter w ith f8 sampling
1 1 : Filter w ith f32 sampling
0 : Input capture mode(2, 4)
1 : Output compare mode
RW
RW
Timer RF Output Control Register
Symbol Address After Reset
TRFOUT 02FFh 00h
Bit Symbol Bit Name Function RW
TRFOUT3 TRFO10 output enable bit
RW
RW
RW
TRFO00 to TRFO02 output invert
bit RW
0 : Output disabled
1 : Output enabled
0 : Output not inverted
1 : Output inverted
RW
TRFOUT2 RW
RW
TRFO02 output enable bit
TRFO00 output enable bit
TRFO01 output enable bit
b7 b6 b5 b4 b3 b2 b1 b0
TRFOUT1
TRFOUT0
TRFOUT7
TRFOUT6
RW
TRFO12 output enable bitTRFOUT5
TRFO11 output enable bit
TRFO10 to TRFO12 output invert
bit
TRFOUT4
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17.4.1 Input Capture Mode
In input capture mode, the edge of the TRFI pin input signal or fC32 is used as a trigger to latch the timer value
and the width or the period of external sig nal is measured. Th e TRFI input is equi pped with a digital fi lter, and
this prevents errors caused by noise o r the like from oc curring. Ta ble 17.14 shows t he Input Capture Mode
Specification s. Figure 17.52 shows an Operatin g Example in Input Capture Mode.
Table 17.14 Input Capture Mode Specifications
Item Specification
Count sources f1, f8, f32
Count operations • Increment
• Transfer the value in the TRF register to the TRFM0 register at the valid
edge of the measured pulse.
Count period 1/fk × 65536 fk: Frequency of count source
Count start condition The TSTART bit in the TRFCR0 register is set to 1 (count starts).
Count stop condition The TSTART bit in the TRFCR0 register is set to 0 (count stops).
Interrupt request
generation timing
• The valid edge of TRFI input or fC32 [capture interrupt]
• When timer RF overflows [timer RF interrupt]
TRFI pin function Measured pulse input
TRFO00 to TRFO02,
TRFO11 to TRFO12 pin
functions
Programmable I/O port
Counter value reset timing In the following cases, the value in the TRF register is set to 0000h.
• When the TSTART bit in the TRFCR0 register is set to 0 (count stops).
Read from timer • The count value can be read out by reading the TRF register.
• The count value at the measured pulse valid edge input can be read out by
reading the TRFM0 register.
Write to timer Write to the TRF and TRFM0 registers is disabled.
Select functions • TRFI or fC32 polarity selected
Selects the valid edge of the measured pulse.
(Bits TRFC03 to TRFC04 in the TRFCR0 register.)
• Digital filter function
The TRFI input is sampled, and when the sampled input level matches as
three times, the level is determined.
Selects the sampling clock of the digital filter.
(Bits TIPF0 to TIPF1 in the TRFCR1 register.)
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Figure 17.52 Operating Example in Input Capture Mode
FFFFh
0000h
Counter contents (hex)
Count starts
Overflow
Time
TSTART bit in
TRFCR0 register
1
0
Measured pulse
(TRFI pin input)
1
0
The above applies under the following conditions.
Bits TRFC04 to TRFC03 in TRFCR0 register = 01b (Capture input polarity is set for falling edge.)
TRFC20 bit in TRFCR2 register = 0 (TRFI pin input)
← Measurement value 2
Measurement
value 3
Set to 1 by a program
Measured
value 1
TRFM0 register Measured value 2 Measured
value 3
IR bit in
TRFIC register
1
0
IR bit in
CAPIC register
1
0
Set to 0 when interrupt request is acknowledged, or set by a program.
When the count
stops, the value
is set to 0000h.
Set to 0 by
a program
Undefined Undefined
Measurement value 2 -
measurement value 1
(10000h - measurement value 2) +
measurement value 3
Set to 0 when interrupt request is
acknowledged, or set by a program.
The delay caused by digital filter and
one count source cycle delay (max.).
←
← Measurement value 1
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17.4.1.1 Digital Filter
The TRFI input is sampled, and when the sampled input level matches three times, its level is determined.
Select the digital filter function and sam pl ing clock by the TRFCR1 register.
Figure 17.53 Block Diagram of Digital Filter
C
DQ
Latch
C
DQ
Latch
C
DQ
Latch
Match
detection
circuit
Edge
detection
circuit
Sampling clock
TMOD
TRFC04 to TRFC03
TIPF1 to TIPF0
TRFI input
signal
Clock period selected by
bits TIPF1 to TIPF0
Sampling clock
TRFI input signal
Input signal
through digital
filtering
Transmission cannot be performed
without three times match because the
input signal is assumed to be noise.
Signal transmission delayed
up to five sampling clock
Recognition of the
signal change with
three times match
f1
f8
f32
TRFC03 to TRFC04: Bits in TRFCR0 register
TIPF0 to TIPF1 and TMOD: Bits in TRFCR1 register
C
DQ
Latch
C
DQ
Latch
Count source
= 01b
= 10b
= 11b
= 01b, 10b, 11b
= 00b
TIPF1 to TIPF0
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17.4.2 Output Compare Mode
In output compare mode, when the value of the TRF register matches the value of the TRFM0 (compare 0
match) or TRFM1 (compare 1 match) register, a user-set level is output mode from the ou tput-compare output
pin.
Table 17.15 shows the Output Compare Mode Specifications. Table 17.16 shows the Output in Output
Compare Mode (Example of TRFO00 Pin). Figure 17.54 shows an Operating Example in Output Compare
Mode. Figure 17.55 shows an Operating Example in Output Compare Mode (“L” and “H” Held Output in
Count Stops).
Table 17.15 Output Compare Mode Specifications
Item Specification
Count sources f1, f8, f32
Count operations Increment
PWM waveform PWM period: 1/fk × (n + 1)
“L” level width: 1/fk × (m + 1)
“H” level width: 1/fk × (n - m)
fk: Frequency of count source
m: Value set in the TRFM0 register
n: Value set in the TRFM1 register
Count start condition The TSTART bit in the TRFCR0 register is set to 1 (count starts).
Count stop condition The TSTART bit in the TRFCR0 register is set to 0 (count stops).
Interrupt request generation
timing
• When compare 0 match is generated [compare 0 interrupt]
• When compare 1 match is generated [compare 1 interrupt]
• When time RF overflows [timer RF interrupt].
TRFO00 to TRFO12 pin
functions
Programmable I/O port or output-compare output
Counter value reset timing In the following cases, the value in the TRF register is set to 0000h.
• When the TSTART bit in the TRFCR0 register is set to 0 (count stops).
• The CCLR bit in the TRFCR1 register is set to 1 (the TRF register is set to 0000h at
compare 1 match) in the compare 1 matches.
Read from timer • The count value can be read out by reading the TRF register.
• The value in the compare register can be read out by reading registers TRFM0 and
TRFM1.
Write to timer Write to the TRF register is disabled
Select functions • Output-compare output pin selected
Either 1 pin or multiple pins among TRFO00 to TRFO02, or TRFO10 to TRFO12
(bits TRFOUT0 to TRFOUT5 in the TRFOUT register).
• Output level at the compare match
Selects “H”, “L”, inverted, or unchanged (bits TRFC14 to TRFC17 in the TRFCR1
register).
• Output level inverted
Selects output level inverted or not inverted (bits TRFOUT6 to TRFOUT7 in the
TRFOUT register).
• Output level at the count stops
Selects “H”, “L”, or unchanged (bits TRFC05 to TRFC06 in the TRFCR0 register).
• Timing to set the TRF register to 0000h
Overflow or compare 1 match in the TRFM1 register (the CCLR bit in the TRFCR1
register).
• TRFO11 pin select function
P3_4 or P3_7 is selected by the TRFOSEL bit in the PINSR4 register.
It applies under the following conditions.
• CMP output “H” when compare 0 is matched
• CMP output “L” when compare 1 is matched
• CMP output not inverted
n + 1
n - mm + 1
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REJ09B0387-0100
X: 0 or 1
Table 17.16 Output in Outpu t Compare Mode (Example of TRFO00 Pin)
TRFO00 Output
Bit Setting Value
TRFCR0 Register TRFOUT Register P1 Register
TRFC06 TRFC05 TSTART TRFOUT6 TRFOUT0 P1_0
Counting CMP output X X 1 0 1 1
Inverted output of
CMP output
XX1 1 1 1
“L” output X X 1 0 1 0
“H” output X X 1 1 1 0
Count
stops
Holds output level
before count stops
X00 X 1 1
“L” output 0 1 0 X 1 1
“H” output 1 1 0 X 1 1
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Figure 17.54 Operating Example in Output Compare Mode
Value set in
TRFM1 register
0000h
Counter content (hex)
Count starts
Match
Time
TSTART bit in
TRFCR0 register
1
0
IR bit in
CMP0IC register
1
0
Set to 1 by a program
IR bit in
CMP1IC register
1
0
Value set in
TRFM0 register
Match Match
TRFO00 output 1
0
1
0
TRFO10 output
Set to 0 when interrupt request is acknowledged,
or set by a program.
Set to 0 when interrupt request is
acknowledged, or set by a program.
When the count
stops, the value
is set to 0000h.
TRFC05 bit in TRFCR0 register = 1, TRFC06 bit in TRFCR0 register = 0 (“L” output when count stops)
CCLR bit in TRFCR1 register = 1 (TRF register is set to 0000h at compare 1 match occurrence)
TMOD bit in TRFCR1 register = 1 (output compare mode)
Bits TRFC15 to TRFC14 in TRFCR1 register = 11b (CMP output level is set to “H” at compare 0 match)
Bits TRFC17 to TRFC16 in TRFCR1 register = 10b (CMP output level is set to “L” at compare 1 match)
TRFOUT6 bit in TRFOUT register = 0 (not inverted)
TRFOUT7 bit in TRFOUT register = 1 (inverted)
TRFOUT0 bit in TRFOUT register = 1 (TRFO00 output enabled)
TRFOUT3 bit in TRFOUT register = 1 (TRFO10 output enabled)
P1_0 bit in P1 register = 1 (“H”)
P3_3 bit in P3 register = 1 (“H”)
The above applies under the following conditions.
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Figure 17.55 Operating Example in Output Compare Mode (“L” and “H” Held Output in Count
Stops)
In output compare mode, the same PWM waveform is output from all of pins TRFO00 to TRFO02 and
TRFO10 to TRFO12 during coun t operation. Note that the output wavefo rm can be inverted for pi ns TRFO00
to TRFO02 or for pins TRFO10 to TRFO12. The o utput can also be fixed at “L” or “H” for individ ual pins for
a given period.
The behavior when count operation st ops can be selected from the following two options: the output level
before the count stops is maintained, or output is fixed at “L” or “H”.
The values in the compare i register can be read by reading the TRFMi (i = 0 or 1) register. Writ ing to the
TRFMi register causes the values to be stored in the compare i register in the following timing:
• If the TSTART bit is set to 0 (count stops)
Values are stored simultaneously with the write to the TRFMi register.
• If the TSTART bit is set to 1 (count starts) and the CCLR bit in the TRFCR1 register is set to 0 (free running)
Values are stored when the TRF register (counter) overflows.
• If the TSTART bit is set to 1 and the CCLR bit is set to 1 (TRF register set to 0000h at compare 1 match)
Values are stored when the compare 1 and TRF register (counter) values match.
Set to 0 by a program
1
0
1
0
TRFO00 output
Set to 1 by a program
P1_0 bit in
P1 register
TRFO10 output
P3_3 bit in
P3 register
TRFOUT0 bit in TRFOUT register = 1 (TRFO00 output enabled)
TRFOUT3 bit in TRFOUT register = 1 (TRFO10 output enabled)
TRFOUT6 bit in TRFOUT register = 0 (TRFO00 to TRFO02 output not inverted)
TRFOUT7 bit in TRFOUT register = 1 (TRFO10 to TRFO12 output inverted)
TSTART bit in TRFCR0 register = 1 (count starts)
The above applies under the following conditions.
CMP output
(internal signal)
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17.4.3 Notes on Timer RF
• Access registers TRF, TRFM0, and TRFM1 in 16-bit units.
Example of reading timer RF:
MOV.W 0290H,R0 ; Read out timer RF
• In input capture mode, a capture interrupt request is generated by inputting an edge selected by bits
TRFC03 and TRFC04 in the TRFCR0 register even when the TSTART bit in the TRFCR0 register is set to
0 (count stops).
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18. Serial Interface
The serial interface consists of two channels (UART0 or UART2). Each UARTi (i = 0 or 2) has an exclusive timer to
generate the transfer clock and operates independently.
Figure 18.1 shows a UARTi (i = 0 or 2) Block Diagram. Figure 18.2 shows a UARTi Transmit/Receive Unit.
UARTi has two modes: clock synchronous serial I/O mode and clock asynchronous serial I/O mode (UART mode).
Figures 18.3 to 18.5 show the Registers Associated with UARTi.
Figure 18.1 UARTi (i = 0 or 2) Block Diagram
= 01b
f8
f1
= 10b
CLK1 to CLK0 = 00b
RXDi
f32
1/16
1/16
1/2
1/(n0+1)
UART reception
UART transmission
Clock synchronous type
(when internal clock is selected)
Clock
synchronous type
Reception control
circuit
Transmission
control circuit
CKDIR = 0
CKDIR = 1
Receive
clock
Transmit
clock
Transmit/
receive
unit
U0BRG register
CKDIR = 0
Internal
External
CKDIR = 1
UARTi
TXDi
CLK
polarity
switch
circuit
CLKi
Clock
synchronous type
Clock synchronous type
(when external clock is selected)
Clock synchronous type
(when internal clock is selected)
i = 0 or 2
CKDIR: Bit in UiMR register
CLK0 to CLK1: Bits in UiC0 register
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Figure 18.2 UARTi Transmit/Receive Unit
RXDi
1SP
2SP
SP SP PAR
PRYE = 0
PAR
disabled
PAR
enabled
PRYE = 1
UART UART (9 bits)
D7 D6 D5 D4 D3 D2 D1 D0
UARTi receive register
UiRB register
0000000D8
MSB/LSB conversion circuit
Data bus high-order bits
Data bus low-order bits
D7 D6 D5 D4 D3 D2 D1 D0 UiTB register
D8
TXDi
1SP
2SP
SP SP PAR
UARTi transmit register
0
i = 0 or 2
SP: Stop bit
PAR: Parity bit
UART (7 bits)
UART (8 bits)
Clock
synchronous
type
Clock
synchronous
type UART (7 bits)
Clock
synchronous
type
UART (7 bits)
Clock
synchronous
type
UART (8 bits)
UART (9 bits)
UART (7 bits)
UART (8 bits)
Clock
synchronous
type
UART (9 bits)
UART
PRYE = 1
PAR
enabled
PAR
disabled
PRYE = 0
Clock
synchronous
type
MSB/LSB conversion circuit
UART (8 bits)
UART (9 bits)
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Figure 18.3 Registers U0MR, U2MR and U0BRG, U2BRG
UARTi Transmit/Receive Mode Register (i = 0 or 2)
Symbol Address After Reset
U0MR 00A0h 00h
U2MR 0160h 00h
Bit Symbol Bit Name Function RW
RW
b3 b2 b1 b0
SMD0 RW
0
b7 b6 b5 b4
Serial I/O mode select bits b2 b1 b0
0 0 0 : Serial interface disabled
0 0 1 : Clock synchronous serial I/O mode
1 0 0 : UART mode transfer data 7 bits long
1 0 1 : UART mode transfer data 8 bits long
1 1 0 : UART mode transfer data 9 bits long
Other than above : Do not set.
SMD1
SMD2 RW
RW
STPS RW
0 : 1 stop bit
1 : 2 stop bits
CKDIR
RW
Odd/even parity select bit Enable w hen PRYE = 1
0 : Odd parity
1 : Even parity
PRY E Parity enable bit 0 : Parity disabled
1 : Parity enabled RW
Set to 0.
PRY RW
Internal/external clock select bit 0 : Internal clock
1 : External clock
Stop bit length select bit
—
(b7)
Reserved bit
UARTi Bit Rate Register (i = 0 or 2)(1, 2, 3)
Symbol Address Af ter Reset
U0BRG 00A1h Undef ined
U2BRG 0161h Undef ined
Setting Range RW
NOTES:
1.
2.
3.
b7
00h to FFh
Function
Assuming the set value is n, UiBRG divides the count source by n+1
After setting the CLK0 to CLK1 bits of the UiC0 register, w rite to the UiBRG register.
b0
Use the MOV instruction to w rite to this register.
WO
Write to this register w hile the serial I/O is neither transmitting nor receiving.
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Figure 18.4 Registers U0TB, U2TB and U0C0, U2C0
UARTi Transmit/Receive Control Register 0 (i = 0 or 2)
Symbol Address After Reset
U0C0 00A4h 00001000b
U2C0 0164h 00001000b
Bit Symbol Bit Name Function RW
NOTE:
1.
RW
RW
If the BRG count source is sw itched, set the UiBRG register again.
RW
Data output select bit 0 : TXDi pin is for CMOS output
1 : TXDi pin is for N-channel open-drain output
UFORM Transf er format select bit 0 : LSB first
1 : MSB first
NCH
CLK polarity select bit 0 : Transmit data is output at f alling edge of transf er
clock and receive data is input at rising edge
1 : Transmit data is output at rising edge of transfer
clock and receive data is input at falling edge
Set to 0.
Transmit register empty
flag
0 : Data in transmit register (during transmit)
1 : No data in transmit register (transmit completed)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
—
(b2)
CKPOL
CLK1 RW
BRG count source select
bits(1)
b1 b0
0 0 : Selects f1
0 1 : Selects f8
1 0 : Selects f32
1 1 : Do not set.
RW
RW
RO
—
(b4) —
Reserved bit
b7 b6 b5 b4 b3 b2
TXEPT
b1 b0
0
CLK0
UARTi Transmit Buffer Register (i = 0 or 2)(1, 2)
Symbol Address After Reset
U0TB 00A3h-00A2h Undefined
U2TB 0163h-0162h Undef ined
RW
NOTES:
1.
2.
Transmit data
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined.
—
(b8-b0)
—
(b15-b9)
When the transfer data length is 9 bits, w rite data to high byte first, then low byte.
Use the MOV instruction to w rite to this register.
Function
WO
—
b0b7
(b8)
b0
(b15)
b7
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Figure 18.5 Registers U0C1, U2C1 and U0RB, U2RB
UARTi Transmit/Receive Control Register 1 (i = 0 or 2)
Symbol Address After Reset
U0C1 00A5h 00000010b
U2C1 0165h 00000010b
Bit Symbol Bit Name Function RW
NOTES:
1.
2. Set the UiRRM bit to 0 (disables continuous receive mode) in UART mode.
UARTi transmit interrupt cause
select bit
0 : Transmission buffer empty (TI=1)
1 : Transmission completed (TXEPT=1) RW
UiRRM UARTi continuous receive mode
enable bit(2)
0 : Disables continuous receive mode
1 : Enables continuous receive mode RW
The RI bit is set to 0 w hen the higher byte of the UiRB register is read out.
—
(b7)
RO
RW
RI Receive complete flag(1) 0 : No data in UiRB register
1 : Data in UiRB register
RE
RW
TI RO
0 : Data in UiTB register
1 : No data in UiTB register
TE
—
Receive enable bit
b7 b6 b5 b4
0
b3 b2 b1 b0
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Transmit enable bit 0 : Disables transmission
1 : Enables transmission
Transmit buffer empty flag
0 : Disables reception
1 : Enables reception
UiIRS
—
(b6)
Reserved bit Set to 0. RW
UARTi Receive Buffer Register (i = 0 or 2)(1)
Symbol After Reset
U0RB Undefined
U2RB Undefined
RW
NOTES:
1.
2.
—
—
(b7-b0) —
Function
Receive data (D7 to D0) RO
Receive data (D8) RO
—
(b8) —
b0b7
(b15)
b7
(b8)
b0
Bit Symbol Bit Name
Address
00A7h-00A6h
0167h-0166h
OER Overrun error flag(2) 0 : No overrun error
1 : Overrun error RO
0 : No parity error
1 : Parity error RO
FER Framing error flag(2) 0 : No framing error
1 : Framing error RO
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined.
—
(b11-b9)
Read out the UiRB register in 16-bit units.
Bits SUM, PER, FER, and OER are set to 0 (no error) w hen bits SMD2 to SMD0 in the UiMR register are set to 000b
(serial interf ace disabled) or the RE bit in the UiC1 register is set to 0 (receive disabled). The SUM bit is set to 0 (no
error) w hen bits PER, FER, and OER are set to 0 (no error). Bits PER and FER are set to 0 even w hen the higher byte
of the UiRB register is read out.
Also, bits PER and FER are set to 0 w hen reading the high-order byte of the UiRB register.
ROSUM Error sum flag(2) 0 : No error
1 : Error
PER Parity error flag(2)
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18.1 Clock Synchronous Serial I/O Mode
In clock synchronous serial I/O mode, data is transmitted and received using a transfer clock.
Table 18.1 lists the Clock Synchronous Serial I/ O Mode Specifications. Table 18.2 lists the Registers Used and
Settings in Clock Synchronous Serial I/O Mode(1).
i = 0 or 2
NOTES:
1. If an external clock is selected, ensure that the external clock is “H” when the CKPOL bit in the UiC0
register is set to 0 (transmit data output at falling edge and receive data input at rising edge of
transfer clock), and that the external clock is “L” when the CKPOL bit is set to 1 (transmit data output
at rising edge and receive data input at falling edge of transfer clock).
2. If an overrun error occurs, the receive data (b0 to b8) of the UiRB register will be undefined. The IR
bit in the SiRIC register remains unchanged.
Table 18.1 Clock Synchronous Serial I/O Mode Specifications
Item Specification
Transfer data format • Transfer data length: 8 bits
Transfer clocks • CKDIR bit in UiMR register is set to 0 (internal clock): fi/(2(n+1))
fi = f1, f8, f32 n = value set in UiBRG register: 00h to FFh
• The CKDIR bit is set to 1 (external clock): input from CLKi pin
Transmit start conditions • Before transmission starts, the following requirements must be met(1)
- The TE bit in the UiC1 register is set to 1 (transmission enabled)
- The TI bit in the UiC1 register is set to 0 (data in the UiTB register)
Receive start conditions • Before reception starts, the following requirements must be met(1)
- The RE bit in the UiC1 register is set to 1 (reception enabled)
- The TE bit in the UiC1 register is set to 1 (transmission enabled)
- The TI bit in the UiC1 register is set to 0 (data in the UiTB register)
Interrupt request
generation timing
• When transmitting, one of the following conditions can be selected
- The UiIRS bit is set to 0 (transmit buffer empty):
When transferring data from the UiTB register to UARTi transmit register
(when transmission starts).
- The UiIRS bit is set to 1 (transmission completes):
When completing data transmission from UARTi transmit register.
• When receiving
When data transfer from the UARTi receive register to the UiRB register
(when reception completes).
Error detection • Overrun error(2)
This error occurs if the serial interface starts receiving the next data item
before reading the UiRB register and receives the 7th bit of the next data.
Select functions • CLK polarity selection
Transfer data input/output can be selected to occur synchronously with the
rising or the falling edge of the transfer clock.
• LSB first, MSB first selection
Whether transmitting or receiving data begins with bit 0 or begins with bit 7
can be selected.
• Continuous receive mode selection
Receive is enabled immediately by reading the UiRB register.
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i = 0 or 2
NOTE:
1. Set bits which are not in this table to 0 when writing to the above registers in clock synchronous
serial I/O mode.
Ta ble 18.3 lists the I/O Pin Functions in Clock Synchronous Serial I/O Mode. The TXDi pin outputs “H” level
between the operating mode selection of UARTi (i = 0 or 2) and transfer start. (If the NCH bit is set to 1 (N-channel
open-drain output), this pin is in a high-impedance state.)
Table 18.2 Registers Used and Settings in Clock Synchronous Serial I/O Mode(1)
Register Bit Function
UiTB 0 to 7 Set data transmission
UiRB 0 to 7 Data reception can be read
OER Overrun error flag
UiBRG 0 to 7 Set bit rate
UiMR SMD2 to SMD0 Set to 001b
CKDIR Select the internal clock or external clock
UiC0 CLK1 to CLK0 Select the count source in the UiBRG register
TXEPT Transmit register empty flag
NCH Select TXDi pin output mode
CKPOL Select the transfer clock polarity
UFORM Select the LSB first or MSB first
UiC1 TE Set this bit to 1 to enable transmission/reception
TI Transmit buffer empty flag
RE Set this bit to 1 to enable reception
RI Reception complete flag
UiIRS Select the UARTi transmit interrupt source
UiRRM Set this bit to 1 to use continuous receive mode
Table 18.3 I/O Pin Functions in Clock Synchronous Serial I/O Mode
Pin Name Function Selection Method
TXD0 (P1_4) Output serial data (Outputs dummy data when performing reception only)
RXD0 (P1_5) Input serial data PD1_5 bit in PD1 register = 0
(P1_5 can be used as an input port when performing
transmission only)
CLK0 (P1_6) Output transfer clock CKDIR bit in U0MR register = 0
Input transfer clock CKDIR bit in U0MR register = 1
PD1_6 bit in PD1 register = 0
TXD2 (P6_3) Output serial data (Outputs dummy data when performing reception only)
RXD2 (P6_4) Input serial data PD6_4 bit in PD6 register = 0
(P6_4 can be used as an input port when performing
transmission only)
CLK2 (P6_5) Output transfer clock CKDIR bit in U2MR register = 0
Input transfer clock CKDIR bit in U2MR register = 1
PD6_5 bit in PD6 register = 0
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Figure 18.6 Transmit and Receive Timing Example in Clock Synchronous Serial I/O Mode
Transfer clock
D0
TE bit in UiC1
register
TXDi
• Example of transmit timing (when internal clock is selected)
Set data in UiTB register
Transfer from UiTB register to UARTi transmit register
TC
CLKi
TCLK Stop pulsing because the TE bit is set to 0
D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
TC=TCLK=2(n+1)/fi
fi: Frequency of UiBRG count source (f1, f8, f32)
n: Setting value to UiBRG register
The above applies under the following settings:
• CKDIR bit in UiMR register = 0 (internal clock)
• CKPOL bit in UiC0 register = 0 (output transmit data at the falling edge and input receive data at the rising edge of the transfer clock)
• UiIRS bit in UiC1 register = 0 (an interrupt request is generated when the transmit buffer is empty)
D0
Set to 0 when interrupt request is acknowledged, or set by a program
Write dummy data to UiTB register
Transfer from UiTB register to UARTi transmit register
1/fEXT
D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5
Receive data is taken in
Read out from UiRB register
Transfer from UARTi receive register to
UiRB register
TI bit in UiC1
register
1
0
1
0
1
0
1
0
TXEPT bit in
UiC0 register
IR bit in SiTIC
register
Set to 0 when interrupt request is acknowledged, or set by a program
• Example of receive timing (when external clock is selected)
RE bit in UiC1
register
TE bit in UiC1
register
TI bit in UiC1
register
1
0
1
0
1
0
RI bit in UiC1
register
IR bit in SiRIC
register
1
0
1
0
CLKi
RXDi
The above applies under the following settings:
• CKDIR bit in UiMR register = 1 (external clock)
• CKPOL bit in UiC0 register = 0 (output transmit data at the falling edge and input receive data at the rising edge of the transfer clock)
The following conditions are met when “H” is applied to the CLKi pin before receiving data:
• TE bit in UiC1 register = 1 (enables transmit)
• RE bit in UiC1 register = 1 (enables receive)
• Write dummy data to the UiTB register
fEXT: Frequency of external clock
i = 0 or 2
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18.1.1 Polarity Select Function
Figure 18.7 shows the Transfer Clock Polarity. Use the CKPOL bit in the UiC0 (i = 0 or 2) register to select the
transfer clock polarity.
Figure 18.7 Transfer Clock Polarity
18.1.2 LSB First/MSB First Select Function
Figure 18.8 shows the Transfer Format. Use the UFORM bit in the UiC0 (i = 0 or 2) register to select the
transfer format.
Figure 18.8 Transfer Format
CLKi(1)
D0TXDi
• When the CKPOL bit in the UiC0 register = 0 (output transmit data at the falling
edge and input receive data at the rising edge of the transfer clock)
D1 D2
NOTES:
1. When not transferring, the CLKi pin level is “H”.
2. When not transferring, the CLKi pin level is “L”.
D3 D4 D5 D6 D7
D0RXDi D1 D2 D3 D4 D5 D6 D7
CLKi(2)
D0TXDi D1 D2 D3 D4 D5 D6 D7
D0RXDi D1 D2 D3 D4 D5 D6 D7
• When the CKPOL bit in the UiC0 register = 1 (output transmit data at the rising
edge and input receive data at the falling edge of the transfer clock)
i = 0 or 2
CLKi
D0
TXDi
• When UFORM bit in UiC0 register = 0 (LSB first)(1)
D1 D2 D3 D4 D5 D6 D7
D0RXDi D1 D2 D3 D4 D5 D6 D7
CLKi
D7
TXDi D6 D5 D4 D3 D2 D1 D0
RXDi
• When UFORM bit in UiC0 register = 1 (MSB first)(1)
NOTE:
1. The above applies when the CKPOL bit in the UiC0 register is
set to 0 (output transmit data at the falling edge and input receive
data at the rising edge of the transfer clock).
D7 D6 D5 D4 D3 D2 D1 D0
i = 0 or 2
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18.1.3 Continuous Receive Mode
Continuous receive mode is selected by setting the UiRRM (i = 0 or 2) bit in the UiC1 register to 1 (enables
continuous receive mode). In this mode, reading the UiRB register sets the TI bit in the UiC1 register to 0 (data
in the UiTB register). When the UiRRM bit is set to 1, do not write dummy data to the UiTB register by a
program.
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18.2 Clock Asynchron ous Serial I/O (UART) Mode
The UART mode allo ws data transmission and rec eption after setting the desired bit rate and transfer data form at.
Table 18.4 lists the UART Mode Specifications. Table 18.5 lists the Registers Used and Settings for UART Mode.
i = 0 or 2
NOTE:
1. If an overrun error occurs, the receive data (b0 to b8) of the UiRB register will be undefined. The IR
bit in the SiRIC register remains unchanged.
Tab le 18 .4 UART Mode Specifications
Item Specification
Transfer data formats • Character bit (transfer data): Selectable among 7, 8 or 9 bits
• Start bit: 1 bit
• Parity bit: Selectable among odd, even, or none
• Stop bit: Selectable among 1 or 2 bits
Transfer clocks • CKDIR bit in UiMR register is set to 0 (internal clock): fj/(16(n+1))
fj = f1, f8, f32 n = value set in UiBRG register: 00h to FFh
• CKDIR bit is set to 1 (external clock): fEXT/(16(n+1))
fEXT: Input from CLKi pin, n = value set in UiBRG register: 00h to FFh
Transmit start conditions • Before transmission starts, the following are required
- TE bit in UiC1 register is set to 1 (transmission enabled)
- TI bit in UiC1 register is set to 0 (data in UiTB register)
Receive start conditions • Before reception starts, the following are required
- RE bit in UiC1 register is set to 1 (reception enabled)
- Start bit detected
Interrupt request
generation timing
• When transmitting, one of the following conditions can be selected
- UiIRS bit is set to 0 (transmit buffer empty):
When transferring data from the UiTB register to UARTi transmit register
(when transmission starts).
- UiIRS bit is set to 1 (transfer ends):
When serial interfac.e completes transmitting data from the UARTi
transmit register
• When receiving
When transferring data from the UARTi receive register to UiRB register
(when reception ends).
Error detection • Overrun error(1)
This error occurs if the serial interface starts receiving the next data item
before reading the UiRB register and receive the bit preceding the final
stop bit of the next data item.
• Framing error
This error occurs when the set number of stop bits is not detected.
• Parity error
This error occurs when parity is enabled, and the number of 1’s in parity
and character bits do not match the number of 1’s set.
• Error sum flag
This flag is set is set to 1 when an overrun, framing, or parity error is
generated.
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i = 0 or 2
NOTES:
1. The bits used for transmit/receive data are as follows: Bits 0 to 6 when transfer data is 7 bits long; bits 0 to 7
when transfer data is 8 bits long; bits 0 to 8 when transfer data is 9 bits long.
2. The following bits are undefined: Bits 7 and 8 when transfer data is 7 bits long; bit 8 when transfer data is 8 bits
long.
Table 18.6 lists the I/O Pin Functions in UART Mode. After the UARTi (i = 0 or 2) operating mode is selected, the
TXDi pin outputs “H ” level. (If the NCH bit is set to 1 (N-channel open-drain ou tput), this pin is in a high-
impedance state) until transfer starts.)
Table 18.5 Registers Used and Settings for UART Mode
Register Bit Function
UiTB 0 to 8 Set transmit data(1)
UiRB 0 to 8 Receive data can be read(1, 2)
OER,FER,PER,SUM Error flag
UiBRG 0 to 7 Set a bit rate
UiMR SMD2 to SMD0 Set to 100b when transfer data is 7 bits long
Set to 101b when transfer data is 8 bits long
Set to 110b when transfer data is 9 bits long
CKDIR Select the internal clock or external clock
STPS Select the stop bit
PRY, PRYE Select whether parity is included and whether odd or even
UiC0 CLK0, CLK1 Select the count source for the UiBRG register
TXEPT Transmit register empty flag
NCH Select TXDi pin output mode
CKPOL Set to 0
UFORM LSB first or MSB first can be selected when transfer data is 8 bits long.
Set to 0 when transfer data is 7 or 9 bits long.
UiC1 TE Set to 1 to enable transmit
TI Transmit buffer empty flag
RE Set to 1 to enable receive
RI Receive complete flag
UiIRS Select the source of UARTi transmit interrupt
UiRRM Set to 0
Table 18.6 I/O Pin Functions in UART Mode
Pin name Function Selection Method
TXD0 (P1_4) Output serial data (Cannot be used as a port when performing reception only)
RXD0 (P1_5) Input serial data PD1_5 bit in PD1 register = 0
(P1_5 can be used as an input port when performing
transmission only)
CLK0 (P1_6) Programmable I/O Port CKDIR bit in U0MR register = 0
Input transfer clock CKDIR bit in U0MR register = 1
PD1_6 bit in PD1 register = 0
TXD2 (P6_3) Output serial data (Cannot be used as a port when performing reception only)
RXD2 (P6_4) Input serial data PD6_4 bit in PD6 register = 0
(P6_4 can be used as an input port when performing
transmission only)
CLK2 (P6_5) Programmable I/O Port CKDIR bit in U2MR register = 0
Input transfer clock CKDIR bit in U2MR register = 1
PD6_5 bit in PD6 register = 0
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Figure 18.9 Transmit Timing in UART Mode
D0
TC
D1 D2 D3 D4 D5 D6 D7 P SP
ST D0 D1 D2 D3 D4 D5 D6 D7 P SPST D0 D1ST
D0
TC
D1 D2 D3 D4 D5 D6 D7 D8 SP SP
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SPST D0 D1ST
Transfer clock
TE bit in UiC1
register
TXDi
Set to 0 when interrupt request is acknowledged, or set by a program
• Transmit timing when transfer data is 8 bits long (parity enabled, 1 stop bit)
Write data to UiTB register
TC=16 (n + 1) / fj or 16 (n + 1) / fEXT
fj: Frequency of UiBRG count source (f1, f8, f32)
fEXT: Frequency of UiBRG count source (external clock)
n: Setting value to UiBRG register
i = 0 or 2
The above timing diagram applies under the following conditions:
• PRYE bit in UiMR register = 1 (parity enabled)
• STPS bit in UiMR register = 0 (1 stop bit)
• UiIRS bit in UiC1 register = 1 (an interrupt request is generated when transmit completes)
Start
bit Parity
bit
Stop pulsing
because the TE bit is set to 0
TXDi
Write data to UiTB register
Transfer from UiTB register to UARTi transmit register
TI bit in UiC1
register
1
0
1
0
1
0
1
0
TXEPT bit in
UiC0 register
IR bit SiTIC
register
Stop
bit
• Transmit timing when transfer data is 9 bits long (parity disabled, 2 stop bits)
1
0
Stop
bit
Stop
bit
Start
bit
Transfer clock
TE bit in UiC1
register
TI bit in UiC1
register
TXEPT bit in
UiC0 register
IR bit in SiTIC
register
1
0
1
0
1
0
Transfer from UiTB register to UARTi transmit register
TC=16 (n + 1) / fj or 16 (n + 1) / fEXT
fj: Frequency of UiBRG count source (f1, f8, f32)
fEXT: Frequency of UiBRG count source (external clock)
n: Setting value to UiBRG register
i = 0 or 2
Set to 0 when interrupt request is acknowledged, or set by a program
The above timing diagram applies under the following conditions:
• PRYE bit in UiMR register = 0 (parity disabled)
• STPS bit in UiMR register = 1 (2 stop bits)
• UiIRS bit in UiC1 register = 0 (an interrupt request is generated when transmit buffer is empty)
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Figure 18.10 Receive Timing Example in UART Mode
UiBRG output
Set to 0 when interrupt request is accepted, or set by a program
• Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)
The above timing diagram applies when the register bits are set as follows:
• UiMR register PRYE bit = 0 (parity disabled)
• UiMR register STPS bit = 0 (1 stop bit)
i = 0 or 2
UiC1 register
RE bit
Start bit
Stop bit
D0 D1 D7
RXDi
Transfer clock
Determined to be “L” Receive data taken in
Reception triggered when transfer clock
is generated by falling edge of start bit Transferred from UARTi receive
register to UiRB register
UiC1 register
RI bit
SiRIC register
IR bit
1
0
1
0
1
0
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18.2.1 Bit Rate
In UART mode, the bit rate is the frequency divided by the UiBRG (i = 0 or 2) register.
Figure 18.11 Calculation Formula of UiBRG (i = 0 or 2) Register Setting Value
Table 18.7 Bit Rate Setting Example in UART Mode (Internal Clock Selected)
Bit Rate (bps) BRG Count Source System Clock = 8 MHz
UiBRG Setting Value Actual Time (bps) Error (%)
1200 f8 51 (33h) 1201.92 0.16
2400 f8 25 (19h) 2403.85 0.16
4800 f8 12 (0Ch) 4807.69 0.16
9600 f1 51 (33h) 9615.38 0.16
14400 f1 34 (22h) 14285.71 -0.79
19200 f1 25 (19h) 19230.77 0.16
28800 f1 16 (10h) 29411.76 2.12
31250 f1 15 (0Fh) 31250.00 0.00
38400 f1 12 (0Ch) 38461.54 0.16
51200 f1 9 (09h) 50000.00 -2.34
UART mode
• Internal clock selected
UiBRG register setting value = fj
Bit Rate × 16 - 1
Fj: Count source frequency of the UiBRG register (f1, f8, or f32)
• External clock selected
fEXT
Bit Rate × 16 - 1
fEXT: Count source frequency of the UiBRG register (external clock)
UiBRG register setting value =
i = 0 or 2
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18.3 Notes on Serial Interface
•When reading data from the UiRB (i = 0 or 2) register either in the clock synchronous serial I/O mode or in the
clock asynchronous serial I/O mode. Ensure the data is read in 16-bit units. When the high-order byte of the
UiRB register is read, bits PER and FER in the UiRB register and the RI bit in the UiC1 register are set to 0.
To check receive errors, read the UiRB register and then use the read data.
Example (when reading receive buffer register):
MOV.W 00A6H,R0 ; Read the U0RB register
•When writing data to the UiTB register in the clock asynchronous serial I/O mode with 9-bit transfer data
length, write data to the high-order byte first then the low-order byte, in 8-bit units.
Example (when reading transmit buffer register):
MOV.B #XXH,00A3H ; Write the high-order byte of U0TB register
MOV.B #XXH,00A2H ; Write the low-order byte of U0TB register
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19. Hardware LIN
The hardware LIN performs LIN communication in cooperation with timer RA and UART0.
19.1 Features
The hardware LIN has the features listed below.
Figure 19.1 shows a Block Diagram of Hardware LIN.
Master mode
•Generates Synch Break
•Detects bus collision
Slave mode
•Detects Synch Break
•Measures Synch Field
•Controls Synch Break and Synch Field signal inpu ts to UART0
•Detects bus collision
NOTE:1. The WakeUp function is detected by INT1.
Figure 19.1 Block Diagram of Hardware LIN
Timer RA
UART0
Interrupt
control
circuit
Bus collision
detection
circuit
Synch Field
control
circuit
RXD0 input
control
circuit
RXD0 pin
TXD0 pin
LSTART bit
SBE bit
LINE bit Timer RA
interrupt
TIOSEL = 0
Hardware LIN
TIOSEL = 1
RXD data
Timer RA
underflow signal
BCIE, SBIE,
and SFIE bits UART0 transfer clock
UART0 TE bit
Timer RA output pulse
UART0 TXD data
MST bit
LINE, MST, SBE, LSTART, BCIE, SBIE, SFIE: Bits in LINCR register
TIOSEL: Bit in TRAIOC register
TE: Bit in U0C1 register
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19.2 Input/Output Pins
The pin configuration of the hardware LIN is listed in Table 19.1.
Table 19.1 Pin Configuration
Name Abbreviation Input/Output Function
Receive data input RXD0 Input Receive data input pin of the hardware LIN
Transmit data output TXD0 Output Transmit data output pin of the hardware LIN
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19.3 Register Configuration
The hardware LIN contains the registers listed below.
These registers are detailed in Figures 19.2 and 19.3.
•LIN Control Register (LINCR)
•LIN Status Register (LINST)
Figure 19.2 LINCR Register
LIN Control Register
Symbol Address Af ter Reset
LINCR 0106h 00h
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
LIN operation start bit 0 : Causes LIN to stop
1 : Causes LIN to start operating(3) RW
LIN operation mode setting bit(2) 0 : Slave mode
(Synch Break detection circuit actuated)
1 : Master mode
(timer RA output OR’ed w ith TXD0)
0 : Disables Synch Field measurement-
completed interrupt
1 : Enables Synch Field measurement-
completed interrupt
SFIE
Synch Field measurement-
completed interrupt enable bit
b7 b6 b5 b4 b3 b2 b1 b0
0 : RXD0 input enabled
1 : RXD0 input disabled
When this bit is set to 1, timer RA input is
enabled and RXD0 input is disabled.
When read, the content is 0.
RW
RW
RO
RW
RW
RXD0 input status flag
Synch Break detection start bit(1)
Synch Break detection interrupt
enable bit
Bus collision detection interrupt
enable bit
0 : Disables Synch Break detection interrupt
1 : Enables Synch Break detection interrupt
0 : Disables bus collision detection interrupt
1 : Enables bus collision detection interrupt
SBIE
BCIE
RXDSF
LSTART
Inputs to timer RA and UART0 are prohibited immediately af ter this bit is set to 1. (Refer to Figure 19.5 Example of
Header Field Transmission Flowchart (1) and Figure 19.9 Example of Header Field Reception F lowchart
(2).)
Before changing LIN operation modes, temporarily stop the LIN operation (LINE bit = 0).
SBE
After setting the LSTART bit, confirm that the RXDSF flag is set to 1 before Synch Break input starts.
0 : Unmasked after Synch Break is detected
1 : Unmasked after Synch Field measurement
is completed
RW
RXD0 input unmasking timing
select bit (ef fective only in slave
mode )
MST RW
LINE
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Figure 19.3 LINST Register
LIN Status Register
Symbol Address Af ter Reset
LINST 0107h 00h
Bit Symbol Bit Name Function RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
B2CLR
SBDCT
BCDCT
B0CLR
B1CLR
When this bit is set to 1, the BCDCT bit is set to 0.
When read, the content is 0.
Synch Break detection flag
Bus collision detection f lag
SFDCT bit clear bit
RO
SBDCT bit clear bit
BCDCT bit clear bit
1 show s Synch Break detected or Synch Break
generation completed.
1 show s Bus collision detected.
When this bit is set to 1, the SFDCT bit is set to 0.
When read, the content is 0.
When this bit is set to 1, the SBDCT bit is set to 0.
When read, the content is 0.
b7 b6 b5 b4 b3 b2 b1 b0
—
(b7-b6) —
1 show s Synch Field measurement completed.
SFDCT Synch Field measurement-
completed flag RO
RW
RW
RW
RO
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19.4 Functional Description
19.4.1 Master Mode
Figure 19.4 shows typical operation of the hardware LIN when transmitting a header field in master mode.
Figures 19.5 and 19.6 show an Example of Header Field Transmission Flowchart.
When transmitting a header field, the hardware LIN operates as described below.
(1) When the TSTART bit in the TRACR register for timer RA is set by writing 1 in software, the hardware
LIN outputs “L” level from the TXD0 pin for the period that is set in registers TRAPRE and TRA for
timer RA.
(2) When timer RA underflows upon reaching the terminal count, the hardware LIN reverses the output of
the TXD0 pin and sets the SBDCT flag in the LINST register to 1. Furthermore, if the SBIE bit in the
LINCR register is set to 1, it generates a timer RA interrupt.
(3) The hardware LIN transmits 55h via UART0.
(4) The hardware LIN transmits an ID field via UART0 after it finishes sending 55h.
(5) The hardware LIN performs communication for a response field after it finishes sending the ID field.
Figure 19.4 Typical Operation when Sending a Header Field
TXD0 pin
Synch Break
1
0
SBDCT flag in the
LINST register
1
0
IR bit in the TRAIC
register
1
0
Synch Field IDENTIFIER
(1) (2) (3) (4) (5)
Set by writing 1 to the
B1CLR bit in the LINST
register
Cleared to 0 upon
acceptance of interrupt
request or by a program
Shown above is the case where
LINE = 1, MST = 1, SBIE = 1
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Figure 19.5 Example of Header Field Transmission Flowchart (1)
Timer RA Set to timer mode
Bits TMOD0 to TMOD2 in TRAMR register ← 000b
Timer RA Set the pulse output level from low to start
TEDGSEL bit in TRAIOC register ← 1
Timer RA Set the INT1/TRAIO pin to P1_5
TIOSEL bit in TRAIOC register ← 1
Timer RA Set the count source (f1, f2, f8, fOCO)
Bits TCK0 to TCK2 in TRAMR register
Timer RA Set the Synch Break width
TRAPRE register
TRA register
Hardware LIN Set to master mode
MST bit in LINCR register ← 1
Hardware LIN Set the LIN operation to start
LINE bit in LINCR register ← 1
Hardware LIN Set the register to enable interrupts
(Bus collision detection, Synch Break detection,
Synch Field measurement)
Bits BCIE, SBIE, SFIE in LINCR register
Hardware LIN Clear the status flags
(Bus collision detection, Synch Break detection,
Synch Field measurement)
Bits B2CLR, B1CLR, B0CLR in LINST register ← 1
Set the count source and
registers TRA and TRAPRE
as suitable for the Synch
Break period.
During master mode, the
Synch Field measurement-
completed interrupt cannot be
used.
A
For the hardware LIN
function, set the TIOSEL bit
in the TRAIOC register to 1.
UART0 Set to transmit/receive mode
(Transfer data length: 8 bits, Internal clock, 1 stop bit,
Parity disabled)
U0MR register
UART0 Set the BRG count source (f1, f8, f32)
Bits CLK0 to CLK2 in U0C0 register
UART0 Set the bit rate
U0BRG register
Hardware LIN Set the LIN operation to stop
LINCR register LINE bit ← 0
Set the BRG count source
and U0BRG register as
appropriate for the bit rate.
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Figure 19.6 Example of Header Field Transmission Flowchart (2)
Timer RA Set the timer to start counting
TSTART bit in TRACR register ← 1
Timer RA Read the count status flag
TCSTF flag in TRACR register
Hardware LIN Read the Synch Break detection flag
SBDCT flag in LINST register
Timer RA Set the timer to stop counting
TSTART bit in TRACR register ← 0
Timer RA Read the count status flag
TCSTF flag in TRACR register
UART0 Communication via UART0
TE bit in U0C1 register ← 1
U0TB register ← 0055h
The timer RA interrupt may be used
to terminate generation of Synch
Break.
One to two cycles of the CPU clock
are required after Synch Break
generation completes before the
SBDCT flag is set to 1.
Transmit the ID field.
A
TCSTF = 1 ?
SBDCT = 1 ?
YES
TCSTF = 0 ?
YES
UART0 Communication via UART0
U0TB register ← ID field
NO
YES
NO
NO
If registers TRAPRE and TRA for timer
RA do not need to be read or the
register settings do not need to be
changed after writing 0 to the TSTART
bit, the procedure for reading TCSTF
flag = 0 can be omitted.
Zero to one cycle of the timer RA count
source is required after timer RA stops
counting before the TCSTF flag is set
to 0.
Transmit the Synch Field.
After timer RA Synch Break is
generated, the timer should be made
to stop counting.
If registers TRAPRE and TRA for
timer RA do not need to be read or
the register settings do not need to be
changed after writing 1 to the
TSTART bit, the procedure for reading
TCSTF flag = 1 can be omitted.
Zero to one cycle of the timer RA
count source is required after timer
RA starts counting before the TCSTF
flag is set to 1.
Timer RA generates Synch Break.
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19.4.2 Slave Mode
Figure 19.7 shows typical operation of the hardware LIN when receiving a header field in slave mode. Figure
19.8 through Figure 19.10 show an Example of Header Field Reception Flowchart.
When receiving a header field, the hardware LIN operates as described below.
(1) Synch Break detection is enabled by writing 1 to the LSTART bit in the LINCR register of the hardware
LIN.
(2) When “L” level is input for a duration equal to or greater than the period set in timer RA, the hardware
LIN detects it as Synch Break. At this time, the SBDCT flag in the LINST register is set to 1.
Furthermore, if the SBIE bit in the LINCR register is set to 1, the hardware LIN generates a timer RA
interrupt. Then it goes to Synch Field measurement.
(3) The hardware LIN receives a Synch Field (55h). At this time, it measures the period of the start bit and
bits 0 to 6 by using timer RA. In this case, it is possible to select whether to input the Synch Field signal
to RXD0 of UART0 by setting the SBE bit in the LINCR register accordingly.
(4) The hardware LIN sets the SFDCT flag in the LINST regis ter to 1 when it finishes measuring the Synch
Field. Furthermore, if the SFIE bit in the LINCR register is set to 1, it generates a timer RA interrupt.
(5) After it finishes measuring the Synch Field, calculate a transfer rate from th e count value of timer RA
and set to UART0 and registers TRAPRE and TRA of timer RA again. Then it receives an ID field via
UART0.
(6) The hardware LIN performs communication for a response field after it finishes receiving the ID field.
Figure 19.7 Typical Operation when Receiv i ng a He ad e r Fi el d
RXD0 pin
Synch Break
1
0
RXD0 input for
UART0
1
0
RXDSF flag in the
LINCR register
1
0
Synch Field IDENTIFIER
(2) (3) (5) (6)
Shown above is the case where
LINE = 1, MST = 0, SBE = 1, SBIE = 1, SFIE = 1
(4)(1)
SBDCT flag in the
LINST register
1
0
SFDCT flag in the
LINST register
1
0
IR bit in the TRAIC
register
1
0
Set by writing 1 to the
B0CLR bit in the LINST
register
Cleared to 0 when Synch
Field measurement
finishes
Measure this period
Set by writing 1 to
the B1CLR bit in
the LINST register
Cleared to 0 upon
acceptance of
interrupt request or
by a program
Set by writing 1 to
the LSTART bit in
the LINCR register
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Figure 19.8 Example of Header Field Reception Flowchart (1)
Set the count source and registers
TRA and TRAPRE as appropriate
for the Synch Break period.
Select the timing at which to
unmask the RXD0 input for UART0.
If the RXD0 input is chosen to be
unmasked after detection of Synch
Break, the Synch Field signal is
also input to UART0.
A
For the hardware LIN
function, set the TIOSEL bit
in the TRAIOC register to 1.
Timer RA Set to pulse width measurement mode
Bits TMOD0 to TMOD2 in the TRAMR register ← 011b
Timer RA Set the pulse width measurement level low
TEDGSEL bit in the TRAIOC register ← 0
Timer RA Set the INT1/TRAIO pin to P1_5
TIOSEL bit in the TRAIOC register ← 1
Timer RA Set the count source (f1, f2, f8, fOCO)
Bits TCK0 to TCK2 in the TRAMR register
Timer RA Set the Synch Break width
TRAPRE register
TRA register
Hardware LIN Set the LIN operation to stop
LINE bit in the LINCR register ← 0
Hardware LIN Set to slave mode
MST bit in the LINCR register ← 0
Hardware LIN Set the RXD0 input unmasking timing
(After Synch Break detection, or after Synch
Field measurement)
SBE bit in the LINCR register
Hardware LIN Set the register to enable interrupts
(Bus collision detection, Synch Break detection,
Synch Field measurement)
Bits BCIE, SBIE, SFIE in the LINCR register
Hardware LIN Set the LIN operation to start
LINE bit in the LINCR register ← 1
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Figure 19.9 Example of Header Field Reception Flowchart (2)
Timer RA Set to start a pulse width measurement
TSTART bit in the TRACR register ← 1
Timer RA Read the count status flag
TCSTF flag in the TRACR register
Hardware LIN Set to start Synch Break detection
LSTART bit in the LINCR register ← 1
Hardware LIN Read the RXD0 input status flag
RXDSF flag in the LINCR register
A
TCSTF = 1 ?
YES
RXDSF = 1 ?
YES
NO
NO
Hardware LIN Clear the status flags
(Bus collision detection, Synch Break
detection, Synch Field measurement)
Bits B2CLR, B1CLR, B0CLR in the LINST
register ← 1
Hardware LIN Read the Synch Break detection flag
SBDCT flag in the LINST register
SBDCT = 1 ?
YES
NO
B
Timer RA waits until the timer starts
counting.
Hardware LIN detects a Synch Break.
The interrupt of the timer RA may be
used.
When Synch Break is detected, timer
RA is reloaded with the initially set count
value.
Even if the duration of the input “L” level
is shorter than the set period, timer RA
is reloaded with the initially set count
value and waits until the next “L” level is
input.
One to two cycles of the CPU clock are
required after Synch Break detection
before the SBDCT flag is set to 1.
When the SBE bit in the LINCR register
is set to 0 (unmasked after Synch Break
is detected), timer RA can be used in
timer mode after the SBDCT flag in the
LINST register is set to 1 and the
RXDSF flag is set to 0.
Hardware LIN waits until the RXD0
input for UART0 is masked.
Do not apply “L” level to the RXD pin
until the RXDSF flag reads 1 after
writing 1 to the LSTART bit. This is
because the signal applied during this
time is input directly to UART0.
One to two cycles of the CPU clock and
zero to one cycle of the timer RA count
source are required after the LSTART
bit is set to 1 before the RXDSF flag is
set to 1. After this, input to timer RA and
UART0 is enabled.
Zero to one cycle of the timer RA count
source is required after timer RA starts
counting before the TCSTF flag is set to
1.
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Figure 19.10 Example of Header Field Reception Flowchart (3)
Hardware LIN Read the Synch Field measurement-
completed flag
SFDCT flag in the LINST register
UART0 Set the UART0 communication rate
U0BRG register
Communication via UART0
(The SBDCT flag is set when the
timer RA counter underflows upon
reaching the terminal count.)
B
SFDCT = 1 ?
YES
UART0 Communication via UART0
Clock asynchronous serial interface (UART) mode
Transmit ID field
NO
Hardware LIN measures the Synch
Field.
The interrupt of timer RA may be
used (the SBDCT flag is set when
the timer RA counter underflows
upon reaching the terminal count).
When the SBE bit in the LINCR
register is set to 1 (unmasked after
Synch Field measurement is
completed), timer RA may be used
in timer mode after the SFDCT bit
in the LINST register is set to 1.
Set a communication rate based on
the Synch Field measurement
result.
YES
Timer RA Set the Synch Break width again
TRAPRE register
TRA register
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19.4.3 Bus Collision Detection Function
The bus collision detection functio n can be us ed when UART0 i s enabled for transmi ssion (TE bi t in the U 0C1
register = 1).
Figure 19.11 shows the Typical Operation when a Bus Collision is Detected.
Figure 19.11 Typical Operation when a Bus Collision is Detected
TXD0 pin 1
0
RXD0 pin 1
0
Transfer clock 1
0
LINE bit in the
LINCR register
1
0
TE bit in the U0C1
register
1
0
BCDCT flag in the
LINST register
1
0
IR bit in the TRAIC
register
1
0
Cleared to 0 upon
acceptance of interrupt
request or by a program
Set by writing 1 to
the B2CLR bit in the
LINST register
Set to 1 by a program
Set to 1 by a program
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19.4.4 Hardware LIN End Processing
Figure 19.12 shows an Examp le of Hardware LIN Communication Completion Flowchart .
Use the following timing for hardware LIN end processing:
•If the hardware bus collision detection fun c tion is used
Perform hardware LIN end processing after checksum tran smission completes.
•If the bus collision detection function is not used
Perform hardware LIN end processing after header field transmission and reception complete.
Figure 19.12 Example of Hardware LIN Communication Completion Flowchart
Hardware LIN Clear the status flags
(Bus collision detection, Synch Break detection, Synch
Field measurement)
Bits B2CLR, B1CLR, B0CLR in the LINST register ← 1
Timer RA Read the count status flag
TCSTF flag in TRACR register
UART0 Complete transmission via UART0
When the bus collision detection
function is not used, end
processing for the UART0
transmission is not required.
TCSTF = 0 ?
YES
NO
Set the timer to stop counting.
Zero to one cycle of the timer RA
count source is required after timer
RA starts counting before the
TCSTF flag is set to 1.
After clearing hardware LIN
status flag, stop the
hardware LIN operation.
Timer RA Set the timer to stop counting
TSTART bit in TRACR register ← 0
Hardware LIN Set the LIN operation to stop
LINE bit in the LINCR register ← 0
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19.5 Interrupt Requests
There are four interrupt requests that are generated by the hardware LIN: Synch Break detection, Synch Break
generation completed, Synch Field measurement completed, and bus collision detection. These interrupts are
shared with timer RA.
Table 19.2 lists the Interrupt Requests of Hardware LIN.
Table 19.2 Interrupt Requests of Hardware LIN
Interrupt Request Status Flag Cause of Interrupt
Synch Break detection SBDCT Generated when timer RA has underflowed after measuring
the “L” level duration of RXD0 input, or when a “L” level is
input for a duration longer than the Synch Break period
during communication.
Synch Break generation
completed
Generated when “L” level output to TXD0 for the duration set
by timer RA completes.
Synch Field
measurement completed
SFDCT Generated when measurement for 6 bits of the Synch Field
by timer RA is completed.
Bus collision detection BCDCT Generated when the RXD0 input and TXD0 output values
differed at data latch timing while UART0 is enabled for
transmission.
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20. Flash Memory
20.1 Overview
Rewrite operations to the flash memory can be performed in three modes: CPU rewrite, standard serial I/O, and
parallel I/O.
Table 20.1 lists the Flash Memory Performance (refer to Table 1.1 Specifications for R8C/2G Group for items
not listed in Table 20.1).
NOTE:
1. Definition of programming and erasure endurance.
The programming and erasure endurance is defined on a per-block basis.
Ta b le 20 .1 Flash Memory Performance
Item Specification
Flash memory operating mode 3 modes (CPU rewrite, standard serial I/O, and parallel I/O)
Division of erase block Refer to Figure 20.1
Programming method Byte unit
Erase method Block erase
Programming and erasure control method
Program and erase control by software command
Protection method
Program ROM protection by FMR0 register
Number of commands 5 commands
Programming and
erasure endurance(1)
Blocks 0 and 1 (program
ROM)
100 times
Programming and erasure
voltage
VCC = 2.7 to 5.5 V
ID code check function Standard serial I/O mode supported
ROM code protect Parallel I/O mode supported
Table 20.2 Flash Memory Rewrite Modes
Flash Memory
Rewrite Mode CPU Rewrite Mode Standard Serial I/O Mode Parallel I/O Mode
Function User ROM area is rewritten
by executing software
commands from the CPU.
User ROM area is rewritten
by a dedicated serial
programmer.
User ROM area is rewritten
by a dedicated parallel
programmer.
Areas which can
be rewritten
User ROM area User ROM area User ROM area
Rewrite Program User program Standard boot program –
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20.2 Memory Map
The flash memory contains a user ROM area and a boot ROM area (reserved area).
Figure 20.1 shows the Flash Memory Block Diagram for R 8C/2 G Gro up.
The user ROM area contains program ROM.
The user ROM area is divided into several blocks. The user ROM area can be rewritten in CPU rewrite mode and
standard serial I/O and parallel I/O modes.
The rewrite control program (standard boot program) for standard serial I/O mode is stored in the boot ROM area
before shipment. The boot ROM area and the user ROM area share the same address, but have separate memory
areas.
Figure 20.1 Flash Memory Block Diagram for R8C/2G Group
Boot ROM area
(reserved area)(1)
8 Kbytes
0E000h
0FFFFh
Program ROM
User ROM area
08000h
Block 1: 16 Kbytes
Block 0: 16 Kbytes
0BFFFh
0C000h
0FFFFh
32 Kbytes ROM product
User ROM area
Block 0: 16 Kbytes
0C000h
0FFFFh
24 Kbytes ROM product
Block 1: 8 Kbytes
0A000h
0BFFFh
User ROM area
Block 0: 16 Kbytes
0C000h
0FFFFh
16 Kbytes ROM product
NOTE:
1. This area is for storing the standard boot program provided by Renesas Technology.
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20.3 Functions to Prevent Rewriting of Flash Memory
Standard serial I/O mode has an ID code check function, and parallel I/O mode has a ROM code protect function to
prevent the flash memory from being read or rewritten or erasure easily.
20.3.1 ID Code Check Function
The ID code check function is used in standard serial I/O mod e. Unless 3 bytes (addresses from 0FFFCh to
0FFFEh) of the reset vector are set to FFFFFFh, the ID codes sent from the serial programmer or the on-chip
debugging emulator and the 7-byte ID codes written in the flash memory are checked to see if they match. If the
ID codes do not match, the comm ands sent from the serial programmer or the on-chi p debugging emulator are
not acknowledged. For detail s of the ID code check function, refer to 14. ID Code Areas.
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20.3.2 ROM Code Protect Function
The ROM protect function prevents the contents of the flash memory from being read, rewritten, or erased by
means of the OFS register when parallel I/O mode is used.
Figure 20.2 shows the OFS Register. Refer to 15. Option Function Select Area for details of the OFS register.
The ROM code protect function is enabled by writing 0 to the ROMCP1 bit and 1 to the ROMCR bit. It disables
reading or changing the contents of the on-chip flash memory.
Once ROM code protect is enabled, the content in the i nternal flash memory cannot be rewritten in parallel I/O
mode. To disable ROM code protect, erase the block including the OFS register with CPU rewrite mode or
standard serial I/O mode.
Figure 20.2 OFS Register
Option Function Select Register(1)
Symbol Address When Shipping
OFS 0FFFFh FFh(3)
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3. If the block including the OFS register is erased, FFh is set to the OFS register.
—
(b6)
Reserved bit Set to 1. RW
CSPROINI
Count source protect
mode after reset select
bit
0 : Count source protect mode enabled after reset
1 : Count source protect mode disabled after reset RW
Setting the LVD0ON bit is only valid after a hardw are reset. To use the pow er-on reset, set the LVD0ON bit to 0
(voltage monitor 0 reset enabled after hardw are reset).
ROMCP1 ROM code protect bit 0 : ROM code protect enabled
1 : ROM code protect disabled RW
ROMCR ROM code protect
disabled bit
0 : ROM code protect disabled
1 : ROMCP1 enabled RW
—
(b1) RW
Reserved bit Set to 1.
WDTON RW
Watchdog timer start
select bit
0 : Starts w atchdog timer automatically af ter reset
1 : Watchdog timer is inactive after reset
111
b7 b6 b5 b4 b3 b2 b1 b0
—
(b4)
Reserved bit Set to 1. RW
The OFS register is on the flash memory. Write to the OFS register w ith a program. After w riting is completed, do not
w rite additions to the OFS register.
LVD0ON
Voltage detection 0
circuit start bit(2)
0 : Voltage monitor 0 reset enabled after hardw are
reset
1 : Voltage monitor 0 reset disabled after hardw are
reset
RW
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20.4 CPU Rewrite Mode
In CPU rewrite mode, the user ROM area can be rewritten by executing software commands from the CPU.
Therefore, the user ROM area can be rewritten directly while the MCU is mounted on a board without using a
ROM programmer. Execute the software command only to blocks in the user ROM area.
Table 20.3 lists the Differences between EW0 Mode and EW1 Mode.
Table 20.3 Differences between EW0 Mode and EW1 Mode
Item EW0 Mode EW1 Mode
Operating mode Single-chip mode Single-chip mode
Areas in which a rewrite
control program can be
executed
RAM (Rewrite control program is
executed after being transferred)
User ROM or RAM
Areas which can be
rewritten
User ROM User ROM
However, blocks which contain a rewrite
control program are excluded
Software command
restrictions
None • Program and block erase commands
Cannot be run on any block which
contains a rewrite control program
• Read status register command
Cannot be executed
Modes after program or
erase
Read status register mode Read array mode
Modes after read status
register
Read status register mode Do not execute this command
CPU status during auto-
write and auto-erase
Operating Hold state (I/O ports hold state before the
command is executed)
Flash memory status
detection
• Read bits FMR00, FMR06, and FMR07
in the FMR0 register by a program
• Execute the read status register
command and read bits SR7, SR5, and
SR4 in the status register.
Read bits FMR00, FMR06, and FMR07 in
the FMR0 register by a program
CPU clock 5 MHz or below No restriction (on clock frequency to be
used)
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20.4.1 Register Description
The registers used in CPU rewrite mode are described.
20.4.1.1 FMR0 Register (FMR0)
Figure 20.3 shows the FMR0 Register.
Figure 20.3 FMR0 Register
Flash Memory Control Register 0
Symbol Address After Reset
FMR0 01B7h 00000001b
Bit Symbol Bit Name Function RW
RY /BY
_
___
status flag
NOTES:
1.
2.
3.
4.
5.
6. When setting the FMR01 bit to 0 (CPU rew rite mode disabled), the FMR02 bit is set to 0 (disables rew rite).
FMR07
b3 b2 b1 b0
0 : Disables rew rite
1 : Enables rew rite
Flash memory stop bit(3, 5) 0 : Enables f lash memory operation
1 : Stops flash memory
(enters low -pow er consumption state
and f lash memory is reset)
FMR01
Blocks 0, 1 rew rite enable bit(2, 6)
0 : Busy (w riting or erasing in progress)
1 : Ready
CPU rew rite mode select bit(1) 0 : CPU rew rite mode disabled
1 : CPU rew rite mode enabled
00
b7 b6 b5 b4
Reserved bits Set to 0.
RW
FMR02 RW
RW
—
(b5-b4)
FMR00
FMSTP
RW
RO
RO
RO
This bit is set to 0 by executing the clear status command.
This bit is enabled w hen the FMR01 bit is set to 1 (CPU rew rite mode). When the FMR01 bit is set to 0, w riting 1 to the
FMSTP bit causes the FMSTP bit to be set to 1. The flash memory does not enter low -pow er consumption state nor is
it reset.
FMR06
To set this bit to 1, set it to 1 immediately after setting it first to 0. Do not generate an interrupt betw een setting the bit
to 0 and setting it to 1. Enter read array mode and set this bit to 0.
Set this bit to 1 immediately after setting it first to 0 w hile the FMR01 bit is set to 1.
Do not generate an interrupt betw een setting the bit to 0 and setting it to 1.
Set this bit by a program located in a space other than the flash memory.
Program status flag(4) 0 : Completed successfully
1 : Terminated by error
Erase status flag(4) 0 : Completed successfully
1 : Terminated by error
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•FMR00 Bit
This bit indicates the operating status of the flash memory. The bits value is 0 during programming,
erasure, or erase-suspend mode; otherwise, it is 1.
•FMR01 Bit
The MCU is made ready to accept commands by setting the FMR01 bit to 1 (CPU rewrite mode).
•FMR02 Bit
Rewriting of blocks 0 and 1 does not accept program or block erase commands if the FMR02 bit is set to 0
(rewrite disabled).
Rewriting of blocks 0 and 1 is controlled by bits FMR15 and FMR16 if the FMR02 bit is set to 1 (rewrite
enabled).
•FMSTP Bit
This bit is used to initialize the f lash memory control cir cuits, and also to reduce the amount of current
consumed by the flash memory. Access to the flash memory is disabled by setting the FMSTP bit to 1.
Therefore, the FMSTP bit must be written to by a program transferred to the RAM.
In the following cases, set the FMSTP bit to 1:
- When flash memory access resulted in an error while erasing or programming in EW0 mode (FMR00 bit
not reset to 1 (ready))
- To provi de lower consum pti on in low-speed on-chip oscillator mode and low-speed clock mode.
Note that when going to stop or wait mode while the CPU rewrite mode is disabled, the FMR0 register
does not need to be set because the power for the flash memory is automaticall y turned off and is turned
back on again after returning from stop or wait mode.
•FMR06 Bit
This is a read-only bit indicating the status of an auto-program operation. The bit is set to 1 when a
program error occurs; otherwise, it is set to 0. For details, refer to the description in Table 20.4 Errors and
FMR0 Register Status.
•FMR07 Bit
This is a read-only bit ind icating the status of an auto-erase operation. The bit is set to 1 when an erase
error occurs; otherwise, it is set to 0. Refer to Table 20.4 Errors and FMR0 Register Status for details.
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NOTE:
1. When FFh is written in the 2nd byte of the block erase command, the MCU enters read array mode,
and the command code written in the 1st byte is disabled.
Tab le 20 .4 Errors and FMR0 Regist er Status
FMR0 Register (Status
Register) Status Error Error Occurrence Condition
FMR07(SR5) FMR06(SR4)
1 1 Command sequence
error
• When a command is not written correctly.
• When D0h or FFh is not written in the 2nd byte
of the block erase command.(1)
• When the program command or block erase
command is executed while rewriting is
disabled by the FMR02 bit in the FMR0 register,
or the FMR15 or FMR16 bit in the FMR1
register.
• When an address not allocated in flash memory
is input during erase command input
• When attempting to erase the block for which
rewriting is disabled during erase command
input.
• When an address not allocated in flash memory
is input during write command input.
• When attempting to write to a block for which
rewriting is disabled during write command
input.
1 0 Erase error • When the block erase command is executed
but auto-erasure does not complete correctly
0 1 Program error • When the program command is executed but
not auto-programming does not complete.
0 0 Completed successfully –
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20.4.1.2 FMR1 Register (FMR1)
Figure 20.4 shows the FMR1 Register.
Figure 20.4 FMR1 Register
•FMR11 Bit
Setting this bit to 1 (EW1 mode) places the MCU in EW1 mode.
•FMR15 Bit
When the FMR02 bit is set to 1 (rewrite enabled) and the FMR15 bit is set to 0 (rewrite enabled), block 0
accepts program and block erase commands.
•FMR16 Bit
When the FMR02 bit is set to 1 (rewrite enabled) and the FMR16 bit is set to 0 (rewrite enabled), block 1
accepts program and block erase commands.
Flash Memory Control Register 1
Symbol Address Af ter Reset
FMR1 01B5h 1000000Xb
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
b3 b2
Set to 0.
0
b1 b0
FMR11
—
(b4-b2)
10
b7 b6 b5 b4
RW
FMR15
—
(b0)
Reserved bits
When read, the content is undefined.
EW1 mode select bit(1, 2) 0 : EW0 mode
1 : EW1 mode
Block 0 rew rite disable bit(2,3) 0 : Enables rew rite
1 : Disables rew rite
While the FMR01 bit is set to 1 (CPU rew rite mode enabled), bits FMR15 and FMR16 can be w ritten to.
To set this bit to 0, set it to 0 immediately after setting it first to 1.
To set this bit to 1, set it to 1.
—
(b7)
0
RW
RW
RW
RO
RW
Reserved bit
0 : Enables rew rite
1 : Disables rew rite
FMR16 Block 1 rew rite disable bit(2,3)
To set this bit to 1, set it to 1 immediately after setting it first to 0 w hile the FMR01 bit is set to 1 (CPU rew rite mode
enable). Do not generate an interrupt betw een setting the bit to 0 and setting it to 1.
This bit is set to 0 by setting the FMR01 bit in the FMR0 register to 0 (CPU rew rite mode disabled).
Reserved bit Set to 1.
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20.4.1.3 FMR4 Register (FMR4)
Figure 20.5 shows the FMR4 Register.
Figure 20.5 FMR4 Register
•FMR43 Bit
When the auto-erase operation starts, the FMR43 bit is set to 1 (erase execution in progress).
When the auto-erase operation ends, the FMR43 bit is set to 0 (erase not executed).
•FMR44 Bit
When the auto-program operation starts, the FMR44 bit is set to 1 (program execution in progress).
When the auto-program operation ends, the FMR44 bit is set to 0 (program not executed).
•FMR46 Bit
The FMR46 bit is set to 0 (reading disabled) during auto-program or auto-erase execution. Do not access
the flash memory w hile this bit is set to 0.
•FMR47 Bit
Current consumption when reading the flash memory can be reduced by setting the FMR47 bit to 1
(enabled) in low-speed clock mode and low-speed on-chip oscillator mode.
Refer to 21.2.10 Low-Current-Consumption Read Mode for details of the handling procedure.
Flash Memory Control Register 4
Symbol Address After Reset
FMR4 01B3h 01000000b
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
In high-speed on-chip oscillator mode, set the FMR47 bit to 0 (disabled).
FMR47 RW
Low -current-consumption
read mode enable bit (1, 2, 3)
0 : Disable
1 : Enable
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
RW
Reserved bits Set to 0.
—
Erase command f lag 0 : Erase not executed
1 : Erase execution in progress
—
(b2-b0)
FMR43
b7 b6 b5 b4
Set the FMR01 bit to 0 (CPU rew rite mode disabled) in low -current-consumption read mode.
To set this bit to 1, set it to 1 immediately after setting it first to 0. Do not generate an interrupt betw een setting the bit
to 0 and setting it to 1.
b3 b2
0
b1 b0
00
—
(b5)
RO
FMR44 Program command f lag 0 : Program not executed
1 : Program execution in progress RO
FMR46 Read status flag 0 : Disables reading
1 : Enables reading RO
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20.4.2 Status Check Procedure
When an error occurs, bits FMR06 to FMR07 in the FMR0 register are set to 1, indicating the occurrence of an
error. Therefore, checking these status bits (full status check) can be used to determine the execution result.
Figure 20.6 shows the Full Status Check and Handling Procedure for In dividual Errors.
Figure 20.6 Full Status Check and Handling Procedure for Individual Erro rs
NOTE:
1. To rewrite to the address where the program error occurs, check if the full
status check is complete normally and write to the address after the block
erase command is executed.
Full status check
FMR06 = 1
and
FMR07 = 1?
FMR07 = 1?
FMR06 = 1?
Full status check completed
No
Yes
Yes
No
Yes
No
Command sequence error
Erase error
Program error
Command sequence error
Execute the clear status register command
(set these status flags to 0)
Check if command is properly input
Re-execute the command
Erase error
Execute the clear status register command
(set these status flags to 0)
Erase command
re-execution times ≤ 3 times?
Re-execute block erase command
Program error
Execute the clear status register
command
(set these status flags to 0)
Specify the other address besides the
write address where the error occurs for
the program address(1)
Re-execute program command
Block targeting for erasure
cannot be used
No
Yes
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20.4.3 EW0 Mode
The MCU enters CPU rewrite mode and software commands can be acknowledged by setting the FMR01 bit in
the FMR0 register to 1 (CPU rewrite mode enabled). In this case, since the FMR11 bit in the FMR1 register is
set to 0, EW0 mode is selected.
Use software commands to control program and erase operations. The FMR0 register or the status register can
be used to determine when program and erase operations complete.
Figure 20.7 shows How to Set and Exit EW0 Mode.
Figure 20.7 How to Set and Exit EW0 Mode
Set registers(1) CM0 and CM1
Transfer a rewrite control program which uses CPU
rewrite mode to the RAM.
Jump to the rewrite control program which has been
transferred to the RAM.
(The subsequent process is executed by the rewrite
control program in the RAM.)
Write 0 to the FMR01 bit before writing 1
(CPU rewrite mode enabled)(2)
Execute the read array command(3)
Execute software commands
Write 0 to the FMR01 bit
(CPU rewrite mode disabled)
Jump to a specified address in the flash memory
Rewrite control program
NOTES:
1. Select 5 MHz or below for the CPU clock by the CM06 bit in the CM0 register and bits CM16 to CM17 in the CM1 register.
2. To set the FMR01 bit to 1, write 0 to the FMR01 bit before writing 1. Do not generate an interrupt between writing 0 and 1.
Write to the FMR01 bit in the RAM.
3. Disable the CPU rewrite mode after executing the read array command.
EW0 Mode Operating Procedure
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20.4.3.1 Software Commands
There are five types of software commands:
•Read array
•Read status register
•Clear status register
•Program
•Block erase
Figure 20.8 shows Software Command Status Transition Diagram in EW0 Mode.
Figure 20.8 Software Command Status Transition Diagram in EW0 Mode
Read array mode
(FMR46 = 1 Reading enabled)
Program
Read status
register mode Block erase Clear status
register
Auto-erasure completed
Non-D0h
and
non-FFh
Write 1 to the FMR01 bit immediately after writing 0.
FMR01 = 0 CPU rewrite mode (EW0 mode)
Read array mode
(FMR46 = 1 Reading enabled)
No command required
Reading only available
Auto-programming completed
50h
(Clear status
register command)
20h
(Block erase
command)
FFh
(Read array
command)
70h
(Read status
register
command)
40h
(Program command)
Write data
(Programming starts)
FFh
(Read array
command)
D0h
(Block erasure starts)
Auto-erase
(FMR46 = 0 Reading disabled)
Auto-program
(FMR46 = 0 Reading disabled)
Clear ends
ResetCPU rewrite disabled
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•Read Array Command
The read array command reads the flash memory.
When FFh is written to an address in the user ROM area, the MCU enters read array mode. In this mode,
the contents of the specified address can be read.
Read array mode continues un til other commands are written. The MCU enters this m ode after a reset is
deasserted.
•Read Status Register Command
The read status register command is used to read the status register. Figure 20.9 shows Status Register.
The status register indicates the operating status of the flash memory and whether an erase or program
operation has completed normally or in er ror (refer to Table 20.4 Errors and FMR0 Register Status).
When 70h is written to an address in the user ROM area, the MCU enters read status register mode. When
the address in the user ROM area is read subsequently, the status register can be read.
The MCU remains in read status register mode until the next read array command is written.
The status of the status register can be determined by reading bits FMR00, FMR06, and FMR07 in the
FMR0 register.
Figure 20.9 Status Register
•Clear Status Register Command
The clear status register command sets the status register to 0.
When 50h is written to an address in the user ROM area, bits FMR07 and FMR06 in the FMR0 register and
bits SR5 and SR4 in the status register are set to 00b.
SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 Status register
D0D1D2D3D4D5D6D7
FMR0 register
FMR06 bit
FMR07 bit
FMR00 bit
D0 to D7: These indicate the read data buses when the read status command is executed.
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•Program Command
The program command writes data to the flash memory in 1-byte units.
When 40h is written and then data is written to the write address, an auto-program operation (data program
and verify) starts.
The FMR00 bit in the FMR0 register can be used to determine whether auto-programming has completed .
The FMR00 bit is set to 0 during auto-programming and set to 1 when auto-programming completes.
The FMR06 bit in the FMR0 register can be used to determin e the result of auto-programming after it has
been finished (refer to 20.4.2 Status Check Procedure).
Do not write additions to the already programmed addresses.
Also, when the FMR02 bit i n the FMR0 register is set to 0 (rewri te disabled), or the FMR02 bit is set to 1
(rewrite enabled) and the FMR15 bit in the FMR1 register is set to 1 (rewrite disabled), program
commands targeting block 0 are not acknowledged. When the FMR 16 bit is set to 1 (rewrite disabled),
program commands targeting block 1 are not acknowledged.
Figure 20.10 shows the Program Command in EW0 Mode.
In EW0 mode, the MCU enters read status register mode at the same time auto-programming starts and the
status register can be read. In this case, t he MCU re mains in read status register mode until the next read
array command is written.
Figure 20.10 Program Command in EW0 Mode
Start
Write the command code 40h to
the write address
Write data to the write address
FMR00 = 1?
Full status check
Program completed
No
Yes
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•Block Erase
When 20h is first written and then D0h is written to a given block address, an auto-erase operation (erase
and verify) of the specified block starts.
The FMR00 bit in the FMR0 register can be used to determine whether auto-erasure has completed.
The FMR00 bit is set to 0 during auto-erasure and set to 1 when auto-erasure completes.
The FMR07 bit in the FMR0 register can be used to determine the result of auto-er asure after auto-er asure
has completed (refer to 20.4.2 Status Check Procedure).
Also, when the FMR02 bit i n the FMR0 register is set to 0 (rewri te disabled), or the FMR02 bit is set to 1
(rewrite enabled) and the FMR15 bit in the FMR1 register is set to 1 (rewrite disabled), block erase
commands targeting block 0 are not acknowledged. W hen the FMR16 bit is set to 1 (rewrite disabled) ,
block erase commands targeting block 1 are not acknowledged.
In EW0 mode, the MCU enters read status register mode at the same time auto-erasure starts and the status
register can be read. In this case, the MCU remains in read status re gister mode until th e next read array
command is written.
Figure 20.11 shows the Block Erase Comm and in EW0 Mode.
If the programming and erasure endurance is n (n = 100, 1000, or 10,000), each block can be erased n
times. For example, if 1,024 1-byte writes are performed to block A, a 1-Kbyte block, and then the block is
erased, the erase count stands at one. When performing 100 or more rewrites, the actual erase count can be
reduced by executing programming operations in such a way that all blank areas are used before
performing an erase operation. Avoid rewriting only particular blocks and try to average out the
programming and erasure endurance of the blocks. It is also advisable to retain data on the erase count of
each block and limit the number of erase operations to a certain number.
Figure 20.11 Block Erase Command in EW0 Mode
Start
Write the command code 20h
Write D0h to any block
address
FMR00 = 1?
Full status check
Block erase completed
No
Yes
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20.4.3.2 EW0 Mode Interrupts
In EW0 mode, maskable interrupts can be used by allocatin g a vector in RAM. Table 20.5 lists the EW0 Mode
Interrupts. Refer to 20.7.1.3 Non-Maskable Interrupts for details of the non-maskable interrupt.
Table 20.5 EW0 Mode Interrupts
Status When Maskable Interrupt Request is Acknowledged
During auto-erasure Interrupt handling is executed.
Auto-programming
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20.4.4 EW1 Mode
The MCU is switched to EW1 mode by settin g the FMR11 bit to 1 (EW1 mode) after set ting the FMR01 bit to
1 (CPU rewrite mode enabled).
The FMR0 register can be used to determine when program and erase operations complete. Figure 20.12 shows
How to Set and Exit EW1 Mode.
Figure 20.12 How to Set and Exit EW1 Mode
Write 0 to the FMR01 bit before writing 1 (CPU
rewrite mode enabled)(1)
Write 0 to the FMR11 bit before writing 1 (EW1
mode)
Execute software commands
Write 0 to the FMR01 bit
(CPU rewrite mode disabled)
NOTE:
1. To set the FMR01 bit to 1, write 0 to the FMR01 bit before writing 1.
Do not generate an interrupt between writing 0 and 1.
EW1 Mode Operating Procedure
Program in ROM
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20.4.4.1 Software Commands
There are four types of software commands:
•Read array
•Clear status register
•Program
•Block erase
Do not execute read status register command in EW1 mode.
Figure 20.13 shows Softw a re Com mand Status Transition Diagram in EW1 Mod e .
Figure 20.13 Software Command Status Transition Diagram in EW1 Mode
•Read Array Command
The read array command reads the flash memory.
When FFh is written to an address in the user ROM area, the MCU enters read array mode. In this mode,
the contents of the specified address can be read.
Read array mode continues un til other commands are written. The MCU enters this m ode after a reset is
deasserted.
•Clear Status Register Command
The clear status register command sets the status register to 0.
When 50h is written to an address in the user ROM area, bits FMR07 and FMR06 in the FMR0 register and
bits SR5 and SR4 in the status register are set to 00b.
Read array mode
(FMR46 = 1 Reading enabled)
Program
Block erase Clear status
register
Auto-erasure
completed
Write 1 to the FMR01 bit immediately after writing 0, and
write 1 to the FMR11 bit immediately after writing 0.
FMR01 = 0
Read array mode
(FMR46 = 1 Reading enabled)
No command required
Reading only available
Auto-programming
completed
50h
(Clear status
register
command)
20h
(Block erase
command)
40h
(Program command)
Write data
(Programming starts)
FFh
(Read array
command)
D0h
(Block erasure starts)
CPU stops
Auto-erase
(FMR46 = 0 Reading disabled)
Auto-program
(FMR46 = 0 Reading disabled)
Clear ends
CPU rewrite mode (EW1 mode)
Reset
CPU rewrite disabled
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•Program Command
The program command writes data to the flash memory in 1-byte unit s.
When 40h is written and then data is written to the write address, an auto-program operation (data program
and verify) starts.
The FMR00 bit in the FMR0 register can be used to determine whether auto-programming has completed .
The FMR00 bit is set to 0 during auto-programming and set to 1 when auto-programming completes.
The FMR06 bit in the FMR0 register can be used to determin e the result of auto-programming after it has
been finished (refer to 20.4.2 Status Check Procedure).
Do not write additions to the already programmed addresses.
Also, when the FMR02 bit i n the FMR0 register is set to 0 (rewri te disabled), or the FMR02 bit is set to 1
(rewrite enabled) and the FMR15 bit in the FMR1 register is set to 1 (rewrite disabled), program
commands targeting block 0 are not acknowledged. When the FMR 16 bit is set to 1 (rewrite disabled),
program commands targeting block 1 are not acknowledged.
In EW1 mode, do not execute this command for any address wh ich a rewrite control program is allocated.
Figure 20.14 shows the Program Command in EW1 Mode.
Figure 20.14 Program Command in EW1 Mode
Start
Write the command code 40h to
the write address
Write data to the write address
FMR00 = 1?
Full status check
Program completed
No
Yes
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•Block Erase
When 20h is first written and then D0h is written to a given block address, an auto-erase operation (erase
and verify) of the specified block starts.
The FMR00 bit in the FMR0 register can be used to determine whether auto-erasure has completed.
The FMR00 bit is set to 0 during auto-erasure and set to 1 when auto-erasure completes.
The FMR07 bit in the FMR0 register can be used to determine the result of auto-er asure after auto-er asure
has completed (refer to 20.4.2 Status Check Procedure).
Also, when the FMR02 bit i n the FMR0 register is set to 0 (rewri te disabled), or the FMR02 bit is set to 1
(rewrite enabled) and the FMR15 bit in the FMR1 register is set to 1 (rewrite disabled), block erase
commands targeting block 0 are not acknowledged. W hen the FMR16 bit is set to 1 (rewrite disabled) ,
block erase commands targeting block 1 are not acknowledged.
Do not execute this command for any address to which a rewrite control program is allocated.
Figure 20.15 shows the Block Erase Command in EW1 Mode.
If the programming and erasure endurance is n (n = 100, 1000, or 10,000), each block can be erased n
times. For example, if 1,024 1-byte writes are performed to block A, a 1-Kbyte block, and then the block is
erased, the erase count stands at one. When performing 100 or more rewrites, the actual erase count can be
reduced by executing programming operations in such a way that all blank areas are used before
performing an erase operation. Avoid rewriting only particular blocks and try to average out the
programming and erasure endurance of the blocks.
It is also advisable to retain data on the erase count of each block and limit the number of erase operations
to a certain number.
Figure 20.15 Block Erase Command in EW1 Mode
Start
Write the command code 20h
Write D0h to any block
address
FMR00 = 1?
Full status check
Block erase completed
No
Yes
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20.4.4.2 EW1 Mode Interrupts
In EW1 mode, maskable interrupts can be used.
Table 20.6 lists the EW1 Mode Interrupts. Refer to 20.7.1.3 Non-Maskable Interrupts for details of the no n-
maskable interrupt.
Table 20.6 EW1 Mode Interrupts
Status When Maskable Interrupt Request is Acknowledged
During auto-erasure Auto-erasure has priority and the interrupt request acknowledgement is put on
standby. Interrupt handling is executed after auto-erasure completes.
During auto- programming Auto-programming has priority and the interrupt request acknowledgement is put on
standby. Interrupt handling is executed after auto-programming completes.
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20.5 Standard Serial I/O Mode
In standard serial I/O mode, the user ROM area can be rewritten while the MCU is mounted on-board by using a
serial programmer which is suitable for the MCU.
There are three types of standard serial I/O modes:
•Standard serial I/O mode 1 ............Clock synchronous serial I/O used to connect with a serial programmer
•Standard serial I/O mode 2 ............Clock asynchronous serial I/O used to connect with a serial programmer
•Standard serial I/O mode 3 ............Special clock asynchronous serial I/O used to connect with a serial
programmer
This MCU uses Standard serial I/O mode 3.
Refer to Appendix 2. Connection Examples with On-Chip Debugging Emulator. Contact the manufacturer of
your serial programmer for details. Refer to the user’s manual of your serial programmer for instructions on how to
use it.
Table 20.7 lists the Pin Functions (Flash Memory Standard Serial I/O Mode 3), and Figure 20.16 shows an
Example of Pin Processing in Standard Serial I/O Mode 3.
After processing the pins sh own in Table 20.7 and rewriting the flash memory using the programmer, apply “H” to
the MODE pin and reset the hardware to run a program in the flash memory in single-chip mode.
20.5.1 ID Code Check Function
The ID code check function determines whether the ID codes sent from the serial programmer and those written
in the flash memory match.
Refer to 14. ID Code Areas for details of the ID code check.
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Figure 20.16 Example of Pin Processing in Standard Serial I/O Mode 3
Table 20.7 Pin Functions (Flash Memory Standard Serial I/O Mode 3)
Pin Name I/O Description
VCC,VSS Power input Apply the voltage guaranteed for programming and
erasure to the VCC pin and 0 V to the VSS pin.
RESET Reset input I Reset input pin.
P4_3/XCIN P4_3 input/clock input I Connect crystal oscillator between pins XCIN and
XCOUT when connecting external oscillator.
To use P4_3 as an input port, input a “H” or “L” level
signal or leave the pin open.
To use P4_4 as an output port, leave the pin open.
P4_4/XCOUT P4_4 output/clock
output
O
P0_4 to P0_7 Input port P0 I Input a “H” or “L” level signal or leave the pin open.
P1_0 to P1_7 Input port P1 I
P3_0 to P3_7 Input port P3 I
P4_5 Input port P4 I
P6_0, P6_3 to P6_6 Input port P6 I
MODE MODE I/O Serial data I/O pin. Connect to the flash programmer.
NOTES:
1. Controlled pins and external circuits vary depending on the programmer.
Refer to the programmer manual for details.
2. In this example, modes are switched between single-chip mode and
standard serial I/O mode by connecting a programmer.
3. When operating with the on-chip oscillator clock, it is not necessary to
connect an oscillating circuit.
MCU
MODE
RESET
User reset signal
MODE I/O
Reset input
VSS
VCC
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20.6 Parallel I/O Mode
Parallel I/O mode is used to input and output software commands, addresses and data necessary to control (read,
program, and erase) the on-chip flash memory. Use a parallel programmer which supports this MCU. Contact the
manufacturer of the parallel programmer for more information, and refer to the user ’s manual of the parallel
programmer for details on how to use it.
ROM areas shown in Figure 20.1 can be rewritten in parallel I/O mode.
20.6.1 ROM Code Protect Function
The ROM code protect function disables the reading and rewriting of the flash memory. (Refer to 20.3.2 RO M
Code Protect Function.)
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20.7 Notes on Flash Memory
20.7.1 CPU Rewrite Mode
20.7.1.1 Operating Speed
Before entering CPU rewrite mode (EW0 mode), select 5 MHz or below for the CPU clock using the CM06 bit
in the CM0 register and bits CM16 to CM17 in the CM1 register. This does not apply to EW1 mode.
20.7.1.2 Prohibited Instructions
The following instructions cannot be used in EW0 mode because they reference data in the flash memory:
UND, INTO, and BRK.
20.7.1.3 Non-Maskable Interrupts
•EW0 Mode
Once a watchdog timer, voltage monitor1, voltage monitor 2, comparator 1, or comp arator 2 interrupt
request is acknowledged, auto-erasure or auto-programming is forcibly stopped immed iately and the flash
memory is reset. Interrupt handling starts after a fixed period and the flash memory restarts.
As the block during auto-erasure or the address during auto-programming is forcibly stopped, the normal
value may not be readable. Execute auto-erasure again and ensure it completes normally.
The watchdog timer does not st op durin g comman d operation, so that in terrupt requ est s may be gene rated.
Initialize the watchdog timer regularly.
Do not use the address match interrupt while a command is being executed because the vector of the
address match interrupt is allocated in ROM.
Do not use a non-maskable interrupt while block 0 is being automatically erased because the fixed vector is
allocated in block 0.
•EW1 Mode
Once a watchdog timer, voltage monitor1, voltage monitor 2, comparator 1, or comp arator 2 interrupt
request is acknowledged, auto-erasure or auto-programming is forcibly stopped immed iately and the flash
memory is reset. Interrupt handling starts after a fixed period and the flash memory restarts.
As the block during auto-erasure or the address during auto-programming is forcibly stopped, the normal
value may not be readable. Execute auto-erasure again and ensure it completes normally.
The watchdog timer does not stop even during command operation, so that interrupt requests may be
generated. Initialize the watchdog timer by using the erase-suspend function.
Do not use the address match interrupt while a command is being executed because the vector of the
address match interrupt is allocated in ROM.
Do not use a non-maskable interrupt while block 0 is being automatically erased because the fixed vector is
allocated in block 0.
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20.7.1.4 How to Access
Write 0 before writing 1 when setting Bits FMR01, FMR02 in the FMR0 register, or FMR11 bit in the FMR1
register to 1. Do not generate an interrup t between writing 0 and 1.
20.7.1.5 Rewriting User ROM Area
In EW0 Mode, if the supply voltage drops while rewriting any block in which a rewrite control program is
stored, it may not be possible to rewrite the flash memory because the rewrite control program cannot be
rewritten correctly. In this case, use standard serial I/O mode.
20.7.1.6 Program
Do not write additions to the already programmed address.
20.7.1.7 Program and Erase Voltage for Flash Memory
To perform programming and erasure, use VCC = 2.7 V to 5.5 V as the supply voltage. Do not perform
programming and erasure at less than 2.7 V.
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21. Reducing Power Consumption
21.1 Overview
This chapter describes key points and processing methods for reducing power consumption.
21.2 Key Points and Processing Methods for Reducing Power Consumption
Key points for reducing power consumption are shown below. They should be referred to when designing a system
or creating a program.
21.2.1 Voltage Detection Circuit
When voltage monitor 1 and comparator 1 are not used, set the VCA26 bit in the VCA2 register to 0 (voltage
detection 1 circuit disabled). When voltage monitor 2 and comparator 2 are not used, set the VCA27 bit in the
VCA2 register to 0 (voltage detection 2 circuit disabled).
If the power-on reset and voltage monitor 0 reset are not used, set the VCA25 bit in the VCA2 register to 0
(voltage detection 0 circuit disabled).
21.2.2 Ports
Even after the MCU enters wait mode or stop mode, the states of the I/O ports are retained. Current flows into
the output ports in the active state, and shoot-through current flows into the input ports in the high-impedance
state. Unnecessary ports should be set to input and fixed to a stable electric potential before the MCU enters
wait mode or stop mode.
21.2.3 Clocks
Power consumption gen erally depends on the n umber of the operating clocks and their frequencies. The fewer
the number of operating clocks or the lower their frequencies, the more power consumption decreases.
Unnecessary clocks should be stopped accordingly.
Stopping low-speed on-chip oscillator oscillation: CM14 bit in CM1 register
Stopping high-speed on-chip oscillator oscillation: HRA00 bit in HRA0 register
21.2.4 Selecting Oscillation Drive Capacity
Set the drive capacity of the XCIN clock oscillation circuit to “LOW”. Confirm that th e circuit oscillates stably
while it is in the “LOW” state.
Selecting XCIN-XCOUT drive capacity: CM03 bit in CM0 register
21.2.5 Wait Mode, Stop Mode
Power consumption can be reduced in wait mode and stop mode. Refer to 11.4 Power Control for details.
21.2.6 Stopping Peripheral Function Clocks
If the peripheral function f1, f2, f4, f8, and f32 clocks are not necessary in wait mode, set the CM02 bit in the
CM0 register to 1 (peripheral function clock stops in wait mode). This will stop the f1, f2, f4, f8, and f32 clocks
in wait mode.
21.2.7 Timers
If timer RA is not used, set the TCKCUT bit in the TRAMR register to 1 (count source cutoff).
If timer RB is not used, set the TCKCUT bit in the TRBMR register to 1 (count source cutoff).
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21.2.8 Reducing Internal Power Consumption
When the MCU enters wait mode using low-speed clock mode or low-speed on-chip oscillator mode, internal
power consumption can be reduced by using the VCA20 bit in the VCA2 register. Figure 21.1 shows the
Handling Procedure of Internal Power Low Consumption Using VCA20 Bit. To enable internal power low
consumption by the VCA20 bit, follow Figure 21.1 Handling Procedure of Internal Power Low Consumption
Using VCA20 Bit.
Figure 21.1 Handling Procedure of Internal Power Low Consumption Using VCA20 Bit
NOTES:
1. Execute this routine to handle all interrupts generated in wait mode.
However, this does not apply if it is not necessary to start high-speed on-chip oscillator during the interrupt routine.
2. Do not set the VCA20 bit to 0 with the instruction immediately after setting the VCA20 bit to 1. Also, do not do the opposite.
3. When entering wait mode, follow 11.5.2 Wait Mode.
Handling procedure of internal power
low consumption enabled by VCA20 bit
Enter low-speed clock mode or low-speed
on-chip oscillator mode
Stop high-speed on-chip oscillator clock
VCA20 ← 1 (internal power low consumption
enabled)(2)
Enter wait mode(3)
VCA20 ← 0 (internal power low consumption
disabled)(2)
Start high-speed on-chip oscillator clock
(Wait until high-speed on-chip oscillator clock
oscillation stabilizes)
In interrupt routine
VCA20 ← 0 (internal power low consumption
disabled)(2)
Start high-speed on-chip oscillator clock
Enter high-speed on-chip oscillator mode
Enter low-speed clock mode or
low-speed on-chip oscillator mode
Exit wait mode by interrupt
Stop high-speed on-chip oscillator clock
VCA20 ← 1 (internal power low consumption
enabled)(2, 3)
Interrupt handling completed
Step (1)
Step (2)
Step (3)
Step (4)
Step (5)
Step (6)
Step (7)
Step (5)
Step (6)
Step (7) (Wait until high-speed on-chip oscillator clock
oscillation stabilizes)
Step (1)
Step (2)
Step (3)
If it is necessary to start
the high-speed on-chip
oscillator in the interrupt
routine, execute steps (5)
to (8) in the interrupt
routine.
If high-speed on-chip
oscillator is started in the
interrupt routine, execute
steps (1) to (3) at the last of
the interrupt routine.
(Note 1)
Interrupt handling
VCA20: Bit in VCA2 register
Step (8)
Enter high-speed on-chip oscillator modeStep (8)
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21.2.9 Stopping Flash Memory
In low-speed on-chip oscillator mode and low-speed clock mode, power consumption can be further reduced by
stopping the flash memory using the FMSTP bit in the FMR0 register.
Access to the flash memory is disabled by setting the FMSTP bit to 1 (flash memory stops). The FMSTP bit
must be written to by a program transferred to RAM.
When the MUC enters stop mode or wait mode while CPU rewrite mode is disabled, the power for the flash
memory is automatically turned off. It is turned back on again after the MCU exit stop mode or wait mode. This
eliminates the need to set the FMR0 register.
Figure 21.2 shows the Handling Procedure Example of Low Power Consumption Using FMSTP Bit.
Figure 21.2 Handling Procedure Example of Low Power Consumption Using FMSTP Bit
FMSTP bit setting program
Transfer FMSTP bit setting program to RAM
Jump to FMSTP bit setting program
(The subsequent processing is executed by
the program in the RAM)
After writing 0 to FMR01 bit, write 1 (CPU
rewrite mode enabled)
Enter low-speed clock mode or low-speed on-
chip oscillator mode
Process in low-speed clock mode, low-
speed on-chip oscillator mode
Write 0 to FMR01 bit (CPU rewrite mode
disabled)
Jump to specified address in flash memory
NOTES:
1. After setting the FMR01 bit to 1 (CPU rewrite mode enabled),
set the FMSTP bit to 1 (flash memory stops).
2. Before switching the CPU clock source, make sure the designated
clock is stable.
3. Insert a 30 µs wait time by a program.
Do not access to the flash memory during this wait time.
Write 1 to FMSTP bit (flash memory stops. low
power consumption state)(1)
Wait until flash memory circuit stabilizes
(30 µs)(3)
Write 0 to FMSTP bit (flash memory operates)
Switch clock source for CPU clock(2)
FMR01, FMSTP: Bits in FMR0 register
Stop high-speed on-chip oscillator
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21.2.10 Low-Current-Consumption Read Mode
In low-speed clock mode and low-speed on-chip oscillator mode, the current consumption when reading the
flash memory can be reduced by setting the FMR47 bi t in the FMR4 regi ster to 1 (enabled).
Figure 21.3 shows the Handling Procedure Example of Low-Current-Consumption Read Mode.
Figure 21.3 Handling Procedure Example of Low-Current- Consumption Read Mode
NOTES:
1. To set the FMR47 bit to 1, first write 0 and then write 1 immediately.
After writing 0, do not generate an interrupt before writing 1.
2. In low-current-consumption read mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled).
Handling procedure of
low-current-consumption read mode
enabled by FMR47 bit
Enter low-speed clock mode or
low-speed on-chip oscillator mode
Stop high-speed on-chip oscillator clock
FMR47 ← 1 (low-current-consumption read
mode enabled)(1)
Enter low-current-consumption read mode(2)
FMR47 ← 0 (low-current-consumption read
mode disabled)
Start high-speed on-chip oscillator clock
(Wait until high-speed on-chip oscillator clock
oscillation stabilizes)
Enter high-speed on-chip oscillator mode
Step (1)
Step (2)
Step (3)
Step (4)
Step (5)
Step (6)
Step (7)
Step (8)
FMR47: Bit in FMR4 register
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22. Electrical Characteristics
NOTES:
1. VCC = 2.2 to 5.5 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
2. The average output current indicates the average value of current measured during 100 ms.
Figure 22.1 Ports P0, P1, P3, P4, and P6 Ti ming Measurement Circuit
Table 22.1 Absolute Maximum Ratings
Symbol Parameter Condition Rated Value Unit
VCC Supply voltage −0.3 to 6.5 V
VIInput voltage −0.3 to VCC + 0.3 V
VOOutput voltage −0.3 to VCC + 0.3 V
PdPower dissipation Topr = 25°C500mW
Topr Operating ambient temperature −20 to 85 (N version) /
−40 to 85 (D version)
°C
Tstg Storage temperature −65 to 150 °C
Table 22.2 Recommended Operating Conditions
Symbol Parameter Conditions Standard Unit
Min. Typ. Max.
VCC Supply voltage 2.2 −5.5 V
VSS Supply voltage −0−V
VIH Input “H” voltage 0.8 VCC −VCC V
VIL Input “L” voltage 0 −0.2 VCC V
IOH(sum) Peak sum output “H”
current
Sum of all pins IOH(peak) −−−160 mA
IOH(sum) Average sum output “H”
current
Sum of all pins IOH(avg) −−−80 mA
IOH(peak) Peak output “H” current All pins −−−10 mA
IOH(avg) Average output “H”
current
All pins −−−5mA
IOL(sum) Peak sum output “L”
currents
Sum of all pins IOL(peak) −−160 mA
IOL(sum) Average sum output “L”
currents
Sum of all pins IOL(avg) −−80 mA
IOL(peak) Peak output “L” currents All pins −−10 mA
IOL(avg) Average output “L” current All pins −−5mA
f(XCIN) XCIN clock input oscillation frequency 2.2 V ≤ VCC ≤ 5.5 V 0 −70 kHz
−System clock OCD2 = 0
XClN clock selected
2.2 V ≤ VCC ≤ 5.5 V 0 −70 kHz
OCD2 = 1
On-chip oscillator clock
selected
HRA01 = 0
Low-speed on-chip
oscillator selected
−125 −kHz
HRA01 = 1
High-speed on-chip
oscillator selected
2.7 V ≤ VCC ≤ 5.5 V
−−8MHz
HRA01 = 1
High-speed on-chip
oscillator selected
2.2 V ≤ VCC ≤ 5.5 V
−−4MHz
P0
P1
P3
P4
P6
30pF
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NOTES:
1. VCC = 2.7 to 5.5 V at Topr = 0 to 60°C, unless otherwise specified.
2. Definition of programming/erasure endurance
The programming and erasure endurance is defined on a per-block basis.
If the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. For example, if 1,024
1-byte writes are performed to block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance
still stands at one.
However, the same address must not be programmed more than once per erase operation (overwriting prohibited).
3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
4. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential
addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,
when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups
before erasing them all in one operation. It is also advisable to retain data on the erase count of each block and limit the
number of erase operations to a certain number.
5. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase
command at least three times until the erase error does not occur.
6. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.
7. The data hold time includes time that the power supply is off or the clock is not supplied.
Table 22.3 Flash Memory (Program ROM) Electrical Characteristics
Symbol Parameter Conditions Standard Unit
Min. Typ. Max.
−Program/erase endurance(2) 100(3) −−times
−Byte program time −50 400 µs
−Block erase time −0.4 9 s
−Program, erase voltage 2.7 −5.5 V
−Read voltage 2.2 −5.5 V
−Program, erase temperature 0 −60 °C
−Data hold time(7) Ambient temperature = 55°C20 −−year
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NOTES:
1. The measurement condition is VCC = 2.2 to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version).
2. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA25 bit in the VCA2
register to 0.
NOTES:
1. The measurement condition is VCC = 2.2 to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version).
2. Time until the voltage monitor 1 interrupt request is generated after the voltage passes Vdet1.
3. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA26 bit in the VCA2
register to 0.
4. This parameter shows the voltage detection level when the power supply drops.
The voltage detection level when the power supply rises is higher than the voltage detection level when the power supply
drops by approximately 0.1 V.
NOTES:
1. The measurement condition is VCC = 2.2 to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version).
2. Time until the voltage monitor 2 interrupt request is generated after the voltage passes Vdet2.
3. Necessary time until the voltage detection circuit operates after setting to 1 again after setting the VCA27 bit in the VCA2
register to 0.
Table 22.4 Voltage Detection 0 Circuit Electrical Characteristics
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
Vdet0 Voltage detection level 2.2 2.3 2.4 V
−Voltage detection circuit self power consumption VCA25 = 1, VCC = 5.0 V −0.9 −µA
td(E-A) Waiting time until voltage detection circuit operation
starts(2)
−−300 µs
Vccmin MCU operating voltage minimum value 2.2 −−V
Table 22.5 Voltage Detection 1 Circuit Electrical Characteristics
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
Vdet1 Voltage detection level(4) 2.70 2.85 3.00 V
−Voltage monitor 1 interrupt request generation time(2) −40 −µs
−Voltage detection circuit self power consumption VCA26 = 1, VCC = 5.0 V −0.6 −µA
td(E-A) Waiting time until voltage detection circuit operation
starts(3)
−−100 µs
Table 22.6 Voltage Detection 2 Circuit Electrical Characteristics
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
Vdet2 Voltage detection level 3.3 3.6 3.9 V
−Voltage monitor 2 interrupt request generation time(2) −40 −µs
−Voltage detection circuit self power consumption VCA27 = 1, VCC = 5.0 V −0.6 −µA
td(E-A) Waiting time until voltage detection circuit operation
starts(3)
−−100 µs
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NOTES:
1. The measurement condition is Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
2. This condition (external power VCC rise gradient) does not apply if VCC ≥ 1.0 V.
3. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVD0ON bit in the OFS register to 0, the
VW0C0 and VW0C6 bits in the VW0C register to 1 respectively, and the VCA25 bit in the VCA2 register to 1.
4. tw(por1) indicates the duration the external power VCC must be held below the effective voltage (Vpor1) to enable a power on
reset. When turning on the power for the first time, maintain tw(por1) for 30 s or more if −20°C ≤ Topr ≤ 85°C, maintain tw(por1) for
3,000 s or more if −40°C ≤ Topr < −20°C.
Figure 22.2 Reset Circuit Electrical Characteristics
Table 22.7 Power-on Reset Circuit, Voltage Monitor 0 Reset Electrical Characteristics(3)
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
Vpor1 Power-on reset valid voltage(4) −−0.1 V
Vpor2 Power-on reset or voltage monitor 0 reset valid
voltage
0−Vdet0 V
trth External power VCC rise gradient(2) 20 −−mV/msec
NOTES:
1. When using the voltage monitor 0 digital filter, ensure that the voltage is within the MCU operation voltage
range (2.2 V or above) during the sampling time.
2. The sampling clock can be selected. Refer to 6. Voltage De tection Circuit for details.
3. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit. Refer to 6. Voltage Detection
Circuit for details.
Vdet0(3)
Vpor1
Internal
reset signal
(“L” valid)
tw(por1) Sampling time(1, 2)
Vdet0(3)
1
fOCO-S × 32 1
fOCO-S × 32
Vpor2
External
Power VCC
trth
trth
2.2 V
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NOTE:
1. The measurement condition is Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
NOTES:
1. The measurement condition is Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
2. These standard values show when the HRA1 register is set to the value before shipment and the HRA2 register is set to 00h.
3. These standard values show when the correction value in the FRA6 register is written into the HRA1 register.
NOTE:
1. VCC = 2.2 to 5.5 V, Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
NOTES:
1. The measurement condition is VCC = 2.2 to 5.5 V and Topr = 25°C.
2. Waiting time until the internal power supply generation circuit stabilizes during power-on.
3. Time until system clock supply starts after the interrupt is acknowledged to exit stop mode.
Table 22.8 Comparator Electrical Characteristics
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
Vref Internal reference voltage VCC = 2.2 V to 5.5 V, Topr = 25°C 1.15 1.25 1.35 V
VCC = 2.2 V to 5.5 V,
Topr = −40 to 85°C
−1.25 −V
Vcref External input reference voltage VCC = 2.2 V to 4.0 V 0.5 −VCC − 1.1 V
VCC = 4.0 V to 5.5 V 0.5 −VCC − 1.5
Vcin External comparison voltage input
range
−0.3 −VCC + 0.3 V
Vofs Input offset voltage −20 120 mV
Tcrsp Response time −4−µs
Table 22.9 High-speed On-Chip Oscillator Circuit Electrical Characteristics
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
fOCO-F High-speed on-chip oscillator frequency
temperature • supply voltage dependence
VCC = 4.75 V to 5.25 V
Topr = 0 to 60°C(2)
7.76 8 8.24 MHz
VCC = 2.7 V to 5.5 V
Topr = −20 to 85°C(2)
7.68 8 8.32 MHz
VCC = 2.7 V to 5.5 V
Topr = −40 to 85°C(2)
7.44 8 8.32 MHz
VCC = 2.2 V to 5.5 V
Topr = −20 to 85°C(3)
7.04 8 8.96 MHz
VCC = 2.2 V to 5.5 V
Topr = −40 to 85°C(3)
6.8 8 9.2 MHz
Table 22.10 Low-speed On-Chip Oscillator Circuit Electrical Characteristics
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
fOCO-S Low-speed on-chip oscillator frequency 30 125 250 kHz
−Oscillation stability time −10 100 µs
−Self power consumption at oscillation VCC = 5.0 V, Topr = 25°C−15 −µA
Table 22.11 Power Supply Circuit Timing Characteristics
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
td(P-R) Time for internal power supply stabilization during
power-on(2)
1−2000 µs
td(R-S) STOP exit time(3) −−150 µs
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NOTE:
1. VCC = 4.2 to 5.5 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
Table 22.12 Electrical Characteristics (1) [VCC = 5 V]
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
VOH Output “H” voltage IOH = −5 mA VCC − 2.0 −VCC V
IOH = −200 µAVCC − 0.5 −VCC V
VOL Output “L” voltage IOL = 5 mA −−2.0 V
IOL = 200 µA−−0.45 V
VT+-VT- Hysteresis INT0, INT1, INT2, INT4,
KI0, KI1, KI2, KI3,
RXD0, RXD2,
CLK0, CLK2
0.1 0.5 −V
RESET 0.1 1.0 −V
IIH Input “H” current VI = 5 V, VCC = 5 V −−5.0 µA
IIL Input “L” current VI = 0 V, VCC = 5 V −−−5.0 µA
RPULLUP Pull-up resistance VI = 0 V, VCC = 5 V 30 50 167 kΩ
RfXCIN Feedback resistance XCIN −18 −MΩ
VRAM RAM hold voltage During stop mode 2.0 −−V
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Table 22.13 Electrical Characteristics (2) [Vcc = 5 V]
(Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.)
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
ICC Power supply current
(VCC = 3.3 to 5.5 V)
Single-chip mode,
output pins are open,
other pins are VSS
High-speed
on-chip oscillator mode
High-speed on-chip oscillator on = 8 MHz
Low-speed on-chip oscillator on = 125 kHz
No division
−58mA
High-speed on-chip oscillator on = 8 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
−2−mA
Low-speed
on-chip oscillator mode
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8, FMR47 = 1
−130 300 µA
Low-speed clock mode High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (low drive)
FMR47 = 1
−130 300 µA
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (low drive)
Program operation on RAM
Flash memory off, FMSTP = 1
−30 −µA
Wait mode High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock operation
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
−25 75 µA
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
−23 60 µA
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (high drive)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
BGR trimming circuit disabled (BGRCR0 = 1)
−4−µA
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (low drive)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
BGR trimming circuit disabled (BGRCR0 = 1)
−2.2 −µA
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (high drive)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
BGR trimming circuit enabled (BGRCR0 = 0)
−8−µA
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (low drive)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
BGR trimming circuit enabled (BGRCR0 = 0)
−6−µA
Stop mode XCIN clock off, Topr = 25°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
BGR trimming circuit disabled (BGRCR0 = 1)
−0.8 3 µA
XCIN clock off, Topr = 85°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
BGR trimming circuit disabled (BGRCR0 = 1)
−1.2 −µA
XCIN clock off, Topr = 25°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
BGR trimming circuit enabled (BGRCR0 = 0)
−58µA
XCIN clock off, Topr = 85°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
BGR trimming circuit enabled (BGRCR0 = 0)
−5.5 −µA
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Timing Requirements
(Unless Otherwise Specified: VCC = 5 V, VSS = 0 V at Topr = 25°C) [VCC = 5 V]
Figure 22.3 XCIN Input Timing Diagram when VCC = 5 V
Figure 22.4 TRAIO Input Timing Diagram when VCC = 5 V
Ta b le 22 .1 4 XCIN Input
Symbol Parameter Standard Unit
Min. Max.
tc(XCIN) XCIN input cycle time 14 −µs
tWH(XCIN) XCIN input “H” width 7 −µs
tWL(XCIN) XCIN input “L” width 7 −µs
Table 22.15 T RAIO Input
Symbol Parameter Standard Unit
Min. Max.
tc(TRAIO) TRAIO input cycle time 100 −ns
tWH(TRAIO) TRAIO input “H” width 40 −ns
tWL(TRAIO) TRAIO input “L” width 40 −ns
XCIN input
tWH(XCIN)
tC(XCIN)
tWL(XCIN)
VCC = 5 V
TRAIO input
VCC = 5 V
tC(TRAIO)
tWL(TRAIO)
tWH(TRAIO)
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i = 0 or 2
Figure 22.5 Serial Interface Timing Diagram when VCC = 5 V
NOTES:
1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
Figure 22.6 External Interrupt INTi Input Timing Diagram when VCC = 5 V
Table 22.16 Serial Interface
Symbol Parameter Standard Unit
Min. Max.
tc(CK) CLKi input cycle time 200 −ns
tW(CKH) CLKi input “H” width 100 −ns
tW(CKL) CLKi input “L” width 100 −ns
td(C-Q) TXDi output delay time −50 ns
th(C-Q) TXDi hold time 0 −ns
tsu(D-C) RXDi input setup time 50 −ns
th(C-D) RXDi input hold time 90 −ns
Table 22.17 External Interrupt INTi (i = 0, 1, 2, 4) Input
Symbol Parameter Standard Unit
Min. Max.
tW(INH) INTi input “H” width 250(1) −ns
tW(INL) INTi input “L” width 250(2) −ns
tW(CKH)
tC(CK)
tW(CKL)
th(C-Q)
th(C-D)
tsu(D-C)td(C-Q)
CLKi
TXDi
RXDi
i = 0 or 2
VCC = 5 V
INTi input
tW(INL)
tW(INH)
i = 0, 1, 2, 4
VCC = 5 V
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NOTE:
1. VCC =2.7 to 3.3 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
Table 22.18 Electrical Characteristics (3) [VCC = 3 V]
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
VOH Output “H” voltage IOH = −1 mA VCC − 0.5 −VCC V
VOL Output “L” voltage IOL = 1 mA −−0.5 V
VT+-VT- Hysteresis INT0, INT1, INT2, INT4,
KI0, KI1, KI2, KI3,
RXD0, RXD2,
CLK0, CLK2
0.1 0.3 −V
RESET 0.1 0.4 −V
IIH Input “H” current VI = 3 V, VCC = 3 V −−4.0 µA
IIL Input “L” current VI = 0 V, VCC = 3 V −−−4.0 µA
RPULLUP Pull-up resistance VI = 0 V, VCC = 3 V 66 160 500 kΩ
RfXCIN Feedback resistance XCIN −18 −MΩ
VRAM RAM hold voltage During stop mode 1.8 −−V
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Table 22.19 Electrical Characteristics (4) [Vcc = 3 V]
(Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.)
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
ICC Power supply current
(VCC = 2.7 to 3.3 V)
Single-chip mode,
output pins are open,
other pins are VSS
High-speed
on-chip oscillator mode
High-speed on-chip oscillator on = 8 MHz
Low-speed on-chip oscillator on = 125 kHz
No division
−5−mA
High-speed on-chip oscillator on = 8 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
−2−mA
Low-speed
on-chip oscillator mode
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8, FMR47 = 1
−130 300 µA
Low-speed clock mode High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (low drive)
FMR47 = 1
−130 300 µA
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (low drive)
Program operation on RAM
Flash memory off, FMSTP = 1
−30 −µA
Wait mode High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock operation
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
−25 70 µA
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
−23 55 µA
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (high drive)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
BGR trimming circuit disabled (BGRCR0 = 1)
−3.8 −µA
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (low drive)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
BGR trimming circuit disabled (BGRCR0 = 1)
−2−µA
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (high drive)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
BGR trimming circuit enabled (BGRCR0 = 0)
−8−µA
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (low drive)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
BGR trimming circuit enabled (BGRCR0 = 0)
−6−µA
Stop mode XCIN clock off, Topr = 25°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
BGR trimming circuit disabled (BGRCR0 = 1)
−0.7 3 µA
XCIN clock off, Topr = 85°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
BGR trimming circuit disabled (BGRCR0 = 1)
−1.1 −µA
XCIN clock off, Topr = 25°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
BGR trimming circuit enabled (BGRCR0 = 0)
−57µA
XCIN clock off, Topr = 85°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
BGR trimming circuit enabled (BGRCR0 = 0)
−5.5 −µA
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Timing requirements
(Unless Otherwise Specified: VCC = 3 V, VSS = 0 V at Topr = 25°C) [VCC = 3 V]
Figure 22.7 XCIN Input Timing Diagram when VCC = 3 V
Figure 22.8 TRAIO Input Timing Diagram when VCC = 3 V
Ta b le 22 .2 0 XCIN Input
Symbol Parameter Standard Unit
Min. Max.
tc(XCIN) XCIN input cycle time 14 −µs
tWH(XCIN) XCIN input “H” width 7 −µs
tWL(XCIN) XCIN input “L” width 7 −µs
Table 22.21 T RAIO Input
Symbol Parameter Standard Unit
Min. Max.
tc(TRAIO) TRAIO input cycle time 300 −ns
tWH(TRAIO) TRAIO input “H” width 120 −ns
tWL(TRAIO) TRAIO input “L” width 120 −ns
XCIN input
tWH(XCIN)
tC(XCIN)
tWL(XCIN)
VCC = 3 V
TRAIO input
VCC = 3 V
tC(TRAIO)
tWL(TRAIO)
tWH(TRAIO)
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i = 0 or 2
Figure 22.9 Serial Interface Timing Diagram when VCC = 3 V
NOTES:
1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
Figure 22.10 External Interrupt INTi Input Timing Diagram when VCC = 3 V
Table 22.22 Serial Interface
Symbol Parameter Standard Unit
Min. Max.
tc(CK) CLKi input cycle time 300 −ns
tW(CKH) CLKi input “H” width 150 −ns
tW(CKL) CLKi Input “L” width 150 −ns
td(C-Q) TXDi output delay time −80 ns
th(C-Q) TXDi hold time 0 −ns
tsu(D-C) RXDi input setup time 70 −ns
th(C-D) RXDi input hold time 90 −ns
Table 22.23 External Interrupt INTi (i = 0, 1, 2, 4) Input
Symbol Parameter Standard Unit
Min. Max.
tW(INH) INTi input “H” width 380(1) −ns
tW(INL) INTi input “L” width 380(2) −ns
tW(CKH)
tC(CK)
tW(CKL)
th(C-Q)
th(C-D)
tsu(D-C)td(C-Q)
CLKi
TXDi
RXDi
VCC = 3 V
i = 0 or 2
INTi input
tW(INL)
tW(INH)
VCC = 3 V
i = 0, 1, 2, 4
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NOTE:
1. VCC = 2.2 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
Table 22.24 Electrical Characteristics (5) [VCC = 2.2 V]
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
VOH Output “H” voltage IOH = −1 mA VCC − 0.5 −VCC V
VOL Output “L” voltage IOL = 1 mA −−0.5 V
VT+-VT- Hysteresis INT0, INT1, INT2, INT4,
KI0, KI1, KI2, KI3,
RXD0, RXD2,
CLK0, CLK2
0.05 0.3 −V
RESET 0.05 0.15 −V
IIH Input “H” current VI = 2.2 V −−4.0 µA
IIL Input “L” current VI = 0 V −−−4.0 µA
RPULLUP Pull-up resistance VI = 0 V 100 200 600 kΩ
RfXCIN Feedback resistance XCIN −35 −MΩ
VRAM RAM hold voltage During stop mode 1.8 −−V
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Table 22.25 Electrical Characteristics (6) [Vcc = 2.2 V]
(Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.)
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
ICC Power supply current
(VCC = 2.2 to 2.7 V)
Single-chip mode,
output pins are open,
other pins are VSS
High-speed
on-chip oscillator mode
High-speed on-chip oscillator on = 4 MHz
Low-speed on-chip oscillator on = 125 kHz
No division
−3.5 −mA
High-speed on-chip oscillator on = 4 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
−1.5 −mA
Low-speed
on-chip oscillator mode
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8, FMR47 = 1
−100 230 µA
Low-speed clock mode High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (low drive)
FMR47 = 1
−100 230 µA
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (low drive)
Program operation on RAM
Flash memory off, FMSTP = 1
−25 −µA
Wait mode High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock operation
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
−22 60 µA
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
−20 55 µA
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (high drive)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
BGR trimming circuit disabled (BGRCR0 = 1)
−3−µA
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (low drive)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
BGR trimming circuit disabled (BGRCR0 = 1)
−1.8 −µA
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (high drive)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
BGR trimming circuit enabled (BGRCR0 = 0)
−7−µA
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (low drive)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
BGR trimming circuit enabled (BGRCR0 = 0)
−6−µA
Stop mode XCIN clock off, Topr = 25°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
BGR trimming circuit disabled (BGRCR0 = 1)
−0.7 3 µA
XCIN clock off, Topr = 85°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
BGR trimming circuit disabled (BGRCR0 = 1)
−1.1 −µA
XCIN clock off, Topr = 25°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
BGR trimming circuit enabled (BGRCR0 = 0)
−57µA
XCIN clock off, Topr = 85°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
BGR trimming circuit enabled (BGRCR0 = 0)
−5.5 −µA
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Timing requirements
(Unless Otherwise Specified: VCC = 2.2 V, VSS = 0 V at Topr = 25°C) [VCC = 2.2 V]
Figure 22.11 XCIN Input Timing Diagram when VCC = 2.2 V
Figure 22.12 TRAIO Input Timing Diagram when VCC = 2.2 V
Ta b le 22 .2 6 XCIN Input
Symbol Parameter Standard Unit
Min. Max.
tc(XCIN) XCIN input cycle time 14 −µs
tWH(XCIN) XCIN input “H” width 7 −µs
tWL(XCIN) XCIN input “L” width 7 −µs
Table 22.27 T RAIO Input
Symbol Parameter Standard Unit
Min. Max.
tc(TRAIO) TRAIO input cycle time 500 −ns
tWH(TRAIO) TRAIO input “H” width 200 −ns
tWL(TRAIO) TRAIO input “L” width 200 −ns
XCIN input
tWH(XCIN)
tC(XCIN)
tWL(XCIN)
VCC = 2.2 V
TRAIO input
tC(TRAIO)
tWL(TRAIO)
tWH(TRAIO)
VCC = 2.2 V
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i = 0 or 2
Figure 22.13 Serial Interface Timing Diagram when VCC = 2.2 V
NOTES:
1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
Figure 22.14 External Interrupt INTi Input Timing Diagram when VCC = 2.2 V
Table 22.28 Serial Interface
Symbol Parameter Standard Unit
Min. Max.
tc(CK) CLKi input cycle time 800 −ns
tW(CKH) CLKi input “H” width 400 −ns
tW(CKL) CLKi input “L” width 400 −ns
td(C-Q) TXDi output delay time −200 ns
th(C-Q) TXDi hold time 0 −ns
tsu(D-C) RXDi input setup time 150 −ns
th(C-D) RXDi input hold time 90 −ns
Table 22.29 External Interrupt INTi (i = 0, 1, 2, 4) Input
Symbol Parameter Standard Unit
Min. Max.
tW(INH) INTi input “H” width 1000(1) −ns
tW(INL) INTi input “L” width 1000(2) −ns
tW(CKH)
tC(CK)
tW(CKL)
th(C-Q)
th(C-D)
tsu(D-C)td(C-Q)
CLKi
TXDi
RXDi
VCC = 2.2 V
i = 0 or 2
INTi input
tW(INL)
tW(INH)
VCC = 2.2 V
i = 0, 1, 2, 4
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23. Usage Notes
23.1 Notes on I/O Ports
23.1.1 Port P4_3, P4_4
Ports P4_3 and P4_4 are also used as the XCIN function and the XCOUT function, respectively. During a reset
period and after a reset release, these ports are set to the XCIN and XCOUT functions. Pins P4_3 and P4_4 can
be switched to the po rt functions by setti ng the CM04 bit in the CM0 register to 0 (p orts P4_3 and P4_4) by a
program.
To use port s P4_3 and P4_4 as ports, note the following:
•Port P4_3
After a reset until the CM 04 bit is set to 0 (por ts P4_3 and P4_4) by a p rogram, a typical 1 0 MΩ impedance is
connected between the P4_3 pin and the MCU power supply or GND. If the XCIN is set to intermediate-level
input or left floating, a shoot-through cu rrent flows into the oscillation driver.
•Port P4_4
Use port P4_4 as an output port by setting the PD4_4 bit in the PD4 register to 1 (output mode). After a reset
until the CM04 bit is set to 0 (ports P4_3 and P4_4) by a program, the P4_4 pin may output an intermediate
potential of about 2.0 V.
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23.2 Notes on Clock Generation Circuit
23.2.1 Stop Mode
When entering stop mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and the
CM10 bit in the CM1 register to 1 (stop mode). An instruction queue pre-reads 4 bytes from the instr uction
which sets the CM10 bit to 1 (stop mode) and the program stops.
Insert at least 4 NOP instructions following the JMP.B instruction after the instruction which sets th e CM10 b it
to 1.
• Program example to enter stop mode
BCLR 1,FMR0 ; CPU rewrite mode disabled
BSET 0,PRCR ; Protect disabled
FSET I ; Enable interrupt
BSET 0,CM1 ; Stop mode
JMP.B LABEL_001
LABEL_001 :
NOP
NOP
NOP
NOP
23.2.2 Wait Mode
When entering wait m ode, set the FMR01 bit in the FMR0 regist er to 0 (CPU rewrite mode disabled) and
execute the WAIT instruction. An instruct ion queue pre-reads 4 bytes from the WAIT instruction and the
program stops. Insert at least 4 NOP instructions after the WAIT instruction.
• Program example to execute the WAIT instru ction
BCLR 1,FMR0 ; CPU rewrite mode disabled
FSET I ; Enable interrupt
WAIT ; Wait mo de
NOP
NOP
NOP
NOP
23.2.3 Oscillation Circuit Constants
Ask the manufacturer of the oscillator to specify the best oscillation circuit constants for your system.
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23.3 Notes on Interrupts
23.3.1 Reading Address 00000h
Do not read address 0000 0h by a program. When a maskable interrupt requ est is acknowledged, the CPU reads
interrupt information (interrupt number and interrupt request level) from 00000h in the interrupt sequence. At
this time, the acknowledged interrupt IR bit is set to 0.
If address 00000h is read by a program, the IR bit for the interrupt which has the highest priority among the
enabled interrupts is set to 0. This may cause the interrupt to be canceled, or an unexpected interrupt to be
generated.
23.3.2 SP Setting
Set any value in the SP before an interrupt is acknowl edged. The SP i s set to 000 0h after reset. Therefore, if an
interrupt is acknowledged before setting a value in the SP, the program ma y ru n out of control.
23.3.3 External Interrupt and Key Input Interrupt
Either “L” level or an “H” level of width shown in the Electrical Characteristics is ne cessary for the signal input
to pins INT0, INT1, INT2, INT4 and pins KI0 to KI3, regardless of the CPU clock.
For details, refer to Table 22.17 (VCC = 5V), Table 22.23 (VCC = 3V), and Table 22.29 (VCC = 2.2V)
External Interrupt INTi (i = 0, 1, 2, 4) Input.
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23.3.4 Changing Interrupt Sources
The IR bit in the interrupt control register may be set to 1 (interrupt requested) when the interrupt source
changes. When using an interrupt, set the IR bit to 0 (no interrupt requested) after changing the interrupt source.
In addition, changes of interrupt sources include all factors that change the interrupt sources assigned to
individual software interrupt numbers, polarities, and timing. Therefore, if a mode change of a peripher al
function involve s interrupt so urces, edge polarities, an d timing, set t he IR bit to 0 (no i nterrupt requested) after
the change. Refer to the individual peripheral function for its related interrupts.
Figure 23.1 shows an Example of Procedure for Changing In terrup t Sources.
Figure 23.1 Example of Procedure for Changing Interrupt Sources
NOTES:
1. Execute the above settings individually. Do not execute two
or more settings at once (by one instruction).
2. To prevent interrupt requests from being generated, disable
the peripheral function before changing the interrupt
source. In this case, use the I flag if all maskable interrupts
can be disabled. If all maskable interrupts cannot be
disabled, use bits ILVL0 to ILVL2 of the interrupt whose
source is changed.
3. Refer to 13.5.5 Changing Interrupt Control Register
Contents for the instructions to be used and usage notes.
Interrupt source change
Disable interrupts(2, 3)
Set the IR bit to 0 (interrupt not requested)
using the MOV instruction(3)
Change interrupt source (including mode
of peripheral function)
Enable interrupts(2, 3)
Change completed
IR bit: The interrupt control register bit of an
interrupt whose source is changed.
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23.3.5 Changing Interrupt Control Register Contents
(a) The contents of an interrupt control register can only be changed while no interrupt requests
corresponding to that register are gen erated. If interrupt requests may be generated, disable interrupts
before changing the interrupt control register contents.
(b) When changing the contents of an interrupt control register after disabling interrupts, be careful to
choose appropriate instructions.
Changing any bit other than IR bit
If an interrupt request corresponding to a register is generated while executing the instruction, the IR bit
may not be set to 1 (interrupt req uested), and the interrupt request may be ignored. If this causes a
problem, use the following instructions to change the register: AND, OR, BCLR, BSET
Changing IR bit
If the IR bit is set to 0 (interrupt not requested), it may not be set to 0 depending on the instruction used.
Therefore, use the MOV instruction to set the IR bit to 0.
(c) When di sabling interrupts using the I flag, set the I flag as shown in the sample programs b elow. Refer
to (b) regarding changing the contents of interrupt control registers by the sample programs.
Sample programs 1 to 3 are for preventing the I flag from being set to 1 (interrupts enabled) before the interrupt
control register is changed for reasons of the internal bus or the instruction queue buffer.
Example 1: Use NOP instructions to prevent I flag from being set to 1 before interrupt control register
is changed
INT_SWITCH1:
FCLR I ; Disable interrupts
AND.B #00H,0056H ; Set TRAIC register to 00h
NOP ;
NOP
FSET I ; Enable interrupts
Example 2: Use dummy read to delay FSET instruction
INT_SWITCH2:
FCLR I ; Disable interrupts
AND.B #00H,0056H ; Set TRAIC register to 00h
MOV.W MEM,R0 ; Dummy read
FSET I ; Enable interrupts
Example 3: Use POPC instruction to change I flag
INT_SWITCH3:
PUSHC FLG
FCLR I ; Disable interrupts
AND.B #00H,0056H ; Set TRAIC register to 00h
POPC FLG ; Enable interrupts
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23.4 Notes on ID Code Areas
23.4.1 Setting Example of ID Code Areas
As the ID code areas are allocated in the flash memory (not in the SFRs), they cannot be rewritten by executing
an instruction. Write appropriate values when creating a program . The following shows a setting example.
•To set 55h in all of the ID code areas
.org 00FFDCH
.lword dummy | (55000000h) ; UND
.lword dummy | (55000000h) ; INTO
.lword dummy ; BREAK
.lword dummy | (55000000h) ; ADDRESS MATCH
.lword dummy | (55000000h) ; SET SINGLE STEP
.lword dummy | (55000000h) ; WDT
.lword dummy | (55000000h) ; ADDRESS BREAK
.lword dummy | (55000000h) ; RESERVE
(Programming form ats vary depending on the compiler. Check the compiler manual.)
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23.5 Notes on Option Function Select Area
23.5.1 Setting Example of Option Function Select Area
As the option function select area is allocated in the flash memory (not in the SFRs), they cannot be rewritten by
executing an instruction. Write appropriate value s when creating a program. The following shows a setting
example.
•To set FFh in the OFS register
.org 00FFFCH
.lword reset | (0FF000000h) ; RESET
(Programming form ats vary depending on the compiler. Check the compiler manual.)
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23.6 Notes on Timers
23.6.1 Notes on Timer RA
•Timer RA stops counting after a reset. Set th e values in the timer RA and timer RA prescalers before the
count starts.
•Even if the prescaler and timer RA are read out in 16-bit units, these registers are read 1 byte at a time by
the MCU. Consequently, the timer value may be updated during the period when these two registers are
being read.
•In pulse period measurement mode, bits TEDGF and TUNDF in the TRACR register can be set to 0 by
writing 0 to these bits by a program. However, these bits remain un changed if 1 is written. When using the
READ-MODIFY-WRITE instruction for the TRACR register, the TEDGF or TUNDF bit may be set to 0
although these bits are set to 1 while the instruction is being executed. In this case, write 1 to the TEDGF or
TUNDF bit which is not supposed to be set to 0 with the MOV instru ction.
•When changing to pulse period measurement mode from another mode, the contents of bits TEDGF and
TUNDF are undefined. Write 0 to bits TEDGF and TUNDF before the count starts.
•The TEDGF bit may be set to 1 by the first timer RA prescaler underflow generated after the count starts.
•When using the pulse period measurement mode, leave two or more periods of the timer RA prescaler
immediately after the count starts, then set the TEDGF bit to 0.
•The TCSTF bit retains 0 (count stops) for 0 to 1 cycle of the count source after setting the TSTART bit to 1
(count starts) while the count is stopped.
During this time, do not access registers associated with tim er RA(1) other than the TCSTF bit. Timer RA
starts counting at the first valid edge of the count source after The TCSTF bit is set to 1 (duri ng count).
The TCSTF bit remains 1 for 0 to 1 cycle of the count source after setting the TSTART bit to 0 (count
stops) while the count is in progress. Timer RA counting is stopped when the TCSTF bit is set to 0.
During this time, do not access registers associated with timer RA(1) other than the TCSTF bit.
NOTE:
1. Registers associated with timer RA: TRACR, TRAIOC, TRAMR, TRAPRE, and TRA.
•When the TRAPRE register is continuously wri tten during count operation (TCSTF bit is set to 1), allow
three or more cycles of the count source clock for each write interval.
•When the TRA register is continuously written during count operation (TCSTF bit is set to 1), allow three
or more cycles of the prescaler underflow for each write interval.
R8C/2G Group 23. Usage Notes
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23.6.2 Notes on Timer RB
•Timer RB stops counting after a reset. Set the values in the timer RB and timer RB prescalers before the
count starts.
•Even if the prescaler and timer RB is read out in 16-bit units, these registers are read 1 byte at a time by the
MCU. Consequently, the timer value may be updated during the perio d when these two reg isters are being
read.
•In programmable one-shot generation mode and programmable wait one-shot generation mode, when
setting the TSTART bit in the TRBCR register to 0, 0 (stops counting) or setting the TOSSP bit in the
TRBOCR register to 1 (stops one-sh ot), th e timer rel oads the value of reload register and stops. Therefore,
in programmable one-shot generation mode and programmable wait one-shot generation mode, read the
timer count value before the timer stop s.
•The TCSTF bit remains 0 (count stops) for 1 to 2 cycles of the count source after setting the TSTART bit to
1 (count starts) while the count is stopped.
During this time, do not access registers associated with timer RB(1)other than the TCSTF bit. Timer RB
starts counting at the first valid edge of the count source after the TCSTF bit is set to 1 (during count).
The TCSTF bit remains 1 for 1 to 2 cycles of the count source after setting the TSTART bit to 0 (count
stops) while the count is in progress. Timer RB counting is stopped when the TCSTF bi t is set to 0.
During this time, do not access registers associated with timer RB(1) othe r than the TCSTF bit.
NOTE:
1. Registe rs a ssociated with t ime r R B: TRBCR, TRBOCR, TRBIOC, TRBMR, TRBPRE, TRBSC, and
TRBPR.
•If the TSTOP bit in the TRBCR register is set to 1 during timer operation, timer RB stops immediately.
•If 1 is written to the TOSST or TOSSP bit in the TRBOCR register, the value of the TOSSTF bit changes
after one or two cycles of the count source have elap sed. If th e TOSSP bit is written to 1 d uring the peri od
between when the TOSST bit is written to 1 and when the TOSSTF bit is set to 1, the TOSSTF bit may be
set to either 0 or 1 depending on the content state. Likewise, if the TOSST bit is written to 1 during the
period between when the TOSSP bit is written to 1 and when the TOSSTF bit is set to 0, the TOSSTF bit
may be set to either 0 or 1.
23.6.2.1 Timer mode
The following workaround should be performed in timer mode.
To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the following
points:
•When the TRBPRE register is written continuously, allow three or more cycles of the count source for each
write interval.
•When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow
for each write interval.
R8C/2G Group 23. Usage Notes
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23.6.2.2 Programmable waveform generation mode
The following three workarounds should be performe d in programmable waveform generation mode.
(1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the
following points:
•When the TRBPRE register is written continuously, allow three or more cycles of the count source for each
write interval.
•When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow
for each write interval.
(2) To change registers TR BPRE and TRBPR during count operation (TCSTF bit is set to 1), synchronize
the TRBO output cycle using a timer RB interrupt, etc. This operation should be preformed only once in
the same output cycle. Also, make sure that writing to the TRBPR register does not occur during period
A shown in Figures 23.2 and 23.3.
The following shows the detailed workaround examp les.
•Workaround example (a):
As shown in Figure 23.2, writ e to registers TRBSC and TRBPR in the timer RB interrupt routine. These
write operations must be completed by the beginni ng of period A.
Figure 23.2 Workaround Example (a) When Timer RB interrupt is Used
TRBO pin output
Count source/
prescaler
underflow signal
Primary period
Period A
IR bit in
TRBIC register
Secondary period
(b)
Interrupt
sequence
Instruction in
interrupt routine
Interrupt request is
acknowledged
(a)
Interrupt request
is generated
Ensure sufficient time
Set the secondary and then
the primary register immediately
(a) Period between interrupt request generation and the completion of execution of an instruction. The length of time
varies depending on the instruction being executed.
The DIVX instruction requires the longest time, 30 cycles (assuming no wait states and that a register is set as
the divisor).
(b) 20 cycles. 21 cycles for address match and single-step interrupts.
R8C/2G Group 23. Usage Notes
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•Workaround example (b):
As shown in Figure 23.3 detect the start of the primary period by the TRBO pin output level and write to
registers TRBSC and TRBPR. These write operations must be completed by the beginning of period A.
If the port register’ s bit value is read after the port direction register’s bit corresponding to the TRBO pin is
set to 0 (input mode), the read value indicat es the TRBO pin output value.
Figure 23.3 Workaround Example (b) When TRBO Pin Output Value is Read
(3) To stop the timer counting in the primary period, use the TSTOP bit in the TRBCR register. In this case,
registers TRBPRE and TRBPR are initialized and their values are set to the values after reset.
23.6.2.3 Programmable one-shot generation mode
The following two workarounds should be performe d in programmable one-shot generation mode.
(1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the
following points:
•When the TRBPRE register is written continuousl y during count operatio n (TCSTF bit is set to 1), allow
three or more cycles of the count source for each write interval.
•When the TRBPR register is written continuously during count operation (TCSTF bit is set to 1), allow
three or more cycles of the prescaler underflow for each write interval.
(2) Do not set both the TRBPRE and TRBPR registers to 00h.
TRBO pin output
Count source/
prescaler
underflow signal
Primary period
Period A
Read value of the port register’s
bit corresponding to the TRBO pin
(when the bit in the port direction
register is set to 0)
Secondary period
(i)
The TRBO output inversion
is detected at the end of the
secondary period.
Ensure sufficient time
Upon detecting (i), set the secondary and
then the primary register immediately.
(ii) (iii)
R8C/2G Group 23. Usage Notes
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23.6.2.4 Programmable wait one-shot generation mode
The following three workarounds should be performe d in programmable wait one-shot generation mode.
(1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the
following points:
•When the TRBPRE register is written continuously, allow three or more cycles of the count source for each
write interval.
•When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow
for each write interval.
(2) Do not set both the TRBPRE and TRBPR registers to 00h.
(3) Set registers TRBSC and TRBPR using the following procedure.
(a) To use “INT0 pi n one-shot trigger enabled” as the count start condition
Set the TRBSC register and then the TRBPR register. At this time, after writing to the TRBPR
register, allow an interval of 0.5 or more cycles of the count source before trigger input from the
INT0 pin.
(b) To use “writing 1 to TOSST bit” as the start condition
Set the TRBSC register, the TRBPR register, and then TOSST bit. At this time, after writing to the
TRBPR register, allow an interval of 0.5 or m ore cycles of the count source before writing to the
TOSST bit.
R8C/2G Group 23. Usage Notes
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23.6.3 Notes on Timer RE
23.6.3.1 Starting and Stopping Count
Timer RE has the TSTART bit for instru cting the count to start or stop, and the TCSTF bit, which indicates
count start or stop. Bits TSTART and TCSTF are in the TRECR1 register .
Timer RE starts coun ting and the TCSTF bit is set to 1 (count starts) when the TSTART bit is set to 1 (count
starts). It takes up to 2 cycles of the count source until the TCSTF bit is set to 1 after setting the TSTART bit to
1. During this time, do not access registers associated with timer RE(1) other than the TCSTF bit.
Also, timer RE stops counting when setting the TSTA RT bit to 0 (count stops) and the TCSTF bit is set to 0
(count stops). It takes the tim e for up to 2 cycles of the count source unti l the TCSTF bit is set to 0 afte r setting
the TSTART bit to 0. During this ti me, do not access registers associated with timer RE other than the TCSTF
bit.
NOTE:
1. Registers associated with timer RE:
TRESEC, TRE MIN, TR EHR, TREW K, TRECR 1, TREC R2, TRECSR ,
and TREOPR.
23.6.3.2 Register Setting
Write to the following registers or bits when timer RE is stopped.
•Registers TRESEC, TREMIN, TREHR, TREWK, and TRECR2
•Bits H12_H24, PM, and INT in TRECR1 register
•Bits RCS0 to RCS3 in TRECSR register
Timer RE is stopped when bits TSTART and TCSTF in the TRECR1 register are set to 0 (timer RE stopped).
Also, set all above-mentioned registers and bits (immediately before timer RE count starts) before setting the
TRECR2 register.
Figure 23.4 shows a Setting Example in Real-Time Clock Mode.
R8C/2G Group 23. Usage Notes
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REJ09B0387-0100
Figure 23.4 Setting Example in Real-Time Clock Mode
Stop timer RE operation
TCSTF in
TRECR1 register = 0?
TSTART in TRECR1 register = 0
Setting of registers TRECSR,
TRESEC, TREMIN, TREHR, TREWK,
and bits H12_H24, PM, and INT in
TRECR1 register
Setting of TRECR2 register
TSTART in TRECR1 register = 1
TCSTF in
TRECR1 register = 1?
TREIC register ← 00h
(disable timer RE interrupt)
Setting of TREIC register (IR bit ← 0,
select interrupt priority level)
Select clock output
Select clock source
Seconds, minutes, hours, days of week, operating mode
Set a.m./p.m., interrupt timing
Select interrupt source
Start timer RE operation
TOENA in TRECR1 register = 0 Disable timer RE clock output
(When it is necessary)
TOENA in TRECR1 register = 1 Enable timer RE clock output
(When it is necessary)
TRERST in TRECR1 register = 1
TRERST in TRECR1 register = 0
Timer RE register
and control circuit reset
R8C/2G Group 23. Usage Notes
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23.6.3.3 Time Reading Procedure of Real-Time Clock Mode
In real-time clock mode, read registers TRESEC, TREMIN, TREHR, and TREWK when time data is updated
and read the PM bit in the TRECR1 register when the BSY bit is set to 0 (not while data is updated).
Also, when reading several registers, an incorrect time will be read if data is updated befo re another register is
read after reading any register.
In order to prevent this, use the reading procedure shown below.
•Using an interrupt
Read necessary contents of registers TRESEC, TREMIN, TREHR, and TREWK and the PM bit in the
TRECR1 register in the timer RE interrupt routine.
•Monitoring with a program 1
Monitor the IR bit in the TREIC register with a program and read necessary contents of registers TRESEC,
TREMIN, TREHR, and TREWK and the PM bit in the TRECR1 register after the IR bit in the TREIC
register is set to 1 (timer RE interrupt request generated).
•Monitoring with a program 2
(1) Monitor the BSY bit.
(2) Monitor until the BSY bit is set to 0 after the BSY bit is set to 1 (approximately 62.5 ms whil e the BSY
bit is set to 1).
(3) Read necessary contents of registers TRESEC, TREMIN, TRE HR, and TREW K and the PM bit in the
TRECR1 register after the BSY bit is set to 0.
•Using read results if they are the same value twice
(1) Read necessary contents of registers TRESEC, TREMIN, TRE HR, and TREW K and the PM bit in the
TRECR1 register.
(2) Read the same register as (1) and compare the contents.
(3) Recognize as the correct value if the contents match. If the contents do not mat ch, repeat u ntil the read
contents match with the previous contents.
Also, when reading several registers, read them as continuously as possible.
R8C/2G Group 23. Usage Notes
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REJ09B0387-0100
23.6.4 Notes on Timer RF
•Access registers TRF, TRFM0, and TRFM1 in 16-bit units.
Example of reading timer RF:
MOV.W 0290H,R0 ; Read out timer RF
•In input capture mode, a capture interrupt request is generated by inputting an edge selected by bits
TRFC03 and TRFC04 in the TRFCR0 register even when the TSTART bit in the TRFCR0 register is set to
0 (count stops).
R8C/2G Group 23. Usage Notes
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23.7 Notes on Serial Interface
•When reading data from the UiRB (i = 0 or 2) register either in the clock synchronous serial I/O mode or in the
clock asynchronous serial I/O mode. Ensure the data is read in 16-bit units. When the high-order byte of the
UiRB register is read, bits PER and FER in the UiRB register and the RI bit in the UiC1 register are set to 0.
To check receive errors, read the UiRB register and then use the read data.
Example (when reading receive buffer register):
MOV.W 00A6H,R0 ; Read the U0RB register
•When writing data to the UiTB register in the clock asynchronous serial I/O mode with 9-bit transfer data
length, write data to the high-order byte first then the low-order byte, in 8-bit units.
Example (when reading transmit buffer register):
MOV.B #XXH,00A3H ; Write the high-order byte of U0TB register
MOV.B #XXH,00A2H ; Write the low-order byte of U0TB register
R8C/2G Group 23. Usage Notes
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23.9 Notes on Flash Memory
23.9.1 CPU Rewrite Mode
23.9.1.1 Operating Speed
Before entering CPU rewrite mode (EW0 mode), select 5 MHz or below for the CPU clock using the CM06 bit
in the CM0 register and bits CM16 to CM17 in the CM1 register. This does not apply to EW1 mode.
23.9.1.2 Prohibited Instructions
The following instructions cannot be used in EW0 mode because they reference data in the flash memory:
UND, INTO, and BRK.
23.9.1.3 Non-Maskable Interrupts
•EW0 Mode
Once a watchdog timer, voltage monitor1, voltage monitor 2, comparator 1, or comp arator 2 interrupt
request is acknowledged, auto-erasure or auto-programming is forcibly stopped immed iately and the flash
memory is reset. Interrupt handling starts after a fixed period and the flash memory restarts.
As the block during auto-erasure or the address during auto-programming is forcibly stopped, the normal
value may not be readable. Execute auto-erasure again and ensure it completes normally.
The watchdog timer does not st op durin g comman d operation, so that in terrupt requ est s may be gene rated.
Initialize the watchdog timer regularly.
Do not use the address match interrupt while a command is being executed because the vector of the
address match interrupt is allocated in ROM.
Do not use a non-maskable interrupt while block 0 is being automatically erased because the fixed vector is
allocated in block 0.
•EW1 Mode
Once a watchdog timer, voltage monitor1, voltage monitor 2, comparator 1, or comp arator 2 interrupt
request is acknowledged, auto-erasure or auto-programming is forcibly stopped immed iately and the flash
memory is reset. Interrupt handling starts after a fixed period and the flash memory restarts.
As the block during auto-erasure or the address during auto-programming is forcibly stopped, the normal
value may not be readable. Execute auto-erasure again and ensure it completes normally.
The watchdog timer does not stop even during command operation, so that interrupt requests may be
generated. Initialize the watchdog timer by using the erase-suspend function.
Do not use the address match interrupt while a command is being executed because the vector of the
address match interrupt is allocated in ROM.
Do not use a non-maskable interrupt while block 0 is being automatically erased because the fixed vector is
allocated in block 0.
R8C/2G Group 23. Usage Notes
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REJ09B0387-0100
23.9.1.4 How to Access
Write 0 before writing 1 when setting Bits FMR01, FMR02 in the FMR0 register, or FMR11 bit in the FMR1
register to 1. Do not generate an interrup t between writing 0 and 1.
23.9.1.5 Rewriting User ROM Area
In EW0 Mode, if the supply voltage drops while rewriting any block in which a rewrite control program is
stored, it may not be possible to rewrite the flash memory because the rewrite control program cannot be
rewritten correctly. In this case, use standard serial I/O mode.
23.9.1.6 Program
Do not write additions to the already programmed address.
23.9.1.7 Program and Erase Voltage for Flash Memory
To perform programming and erasure, use VCC = 2.7 V to 5.5 V as the supply voltage. Do not perform
programming and erasure at less than 2.7 V.
R8C/2G Group 23. Usage Notes
Rev.1.00 Apr 04, 2008 Page 312 of 318
REJ09B0387-0100
23.10 Notes on Noise
23.10.1
Inserting a Byp ass Cap acitor between VCC and VSS Pins as a Countermeasure
against Noise and Latch-up
Connect a bypass capacitor (at least 0.1 µF) using the shortest and thickest write possible.
23.10.2 Countermeasures against Noise Error of Port Control Registers
During rigorous noise testing or the like, external noise (mainly power supply system noise) can exceed the
capacity of the MCU's internal noise control circuitry. In such cases the contents of the port related registers
may be changed.
As a firmware countermeasure, it is recommended that the port registers, port direction registers, and p ull-up
control registers be reset periodically. However, examine the control processing fully before introducing the
reset routine as conflicts may be created between the reset routine and interrupt routines.
R8C/2G Group 24. Notes for On-Chip Debugger
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REJ09B0387-0100
24. Notes for On-Chip Debugger
When using the on-chip debugger to develop and debug programs for the R8C/2G Group take note of the following.
(1) Some of the user flash memory and RAM areas are used by the on-ship debugger. These areas cannot be
accessed by the user.
Refer to the on-chip debugger manual for which areas are used.
(2) Do not set the address match interrupt (registers AIER, RMAD0, and RMAD1 and fixed vector tables) in a
user system.
(3) Do not use the BRK instruction in a user system.
(4) Debugging is available under the condition of supply voltage VCC = 2.7 to 5.5 V. Debugging with the on-chip
debugger under less than 2.7 V is not allowed.
Connecting and usin g the on-chip debugger has so me special restrictions. Refer to the on-chip deb ugger manual for
details.
R8C/2G Group Appendix 1. Package Dimensions
Rev.1.00 Apr 04, 2008 Page 314 of 318
REJ09B0387-0100
Appendix 1. Package Dimensions
Diagrams showing the latest package dimensions and mounting information are available in the “Packages” section of
the Renesas Technology website.
2.
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
NOTE)
DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
y
Index mark
*3
F
32
25
24 17
16
9
81
*1
*2
x
b
p
e
H
E
E
D
H
D
Z
D
Z
E
Detail F
L
1
L
A
c
A
2
A
1
Previous CodeJEITA Package Code RENESAS Code
PLQP0032GB-A 32P6U-A
MASS[Typ.]
0.2gP-LQFP32-7x7-0.80
1.0
0.125
0.35
0.7
0.7
0.20
0.20
0.145
0.09
0.420.370.32
MaxNomMin
Dimension in Millimeters
Symbol
Reference
7.17.06.9
D
7.17.06.9
E
1.4
A
2
9.29.08.8
9.29.08.8
1.7
A
0.20.1
0
0.70.50.3
L
x
8°0°
c
0.8
e
0.10
y
H
D
H
E
A
1
b
p
b
1
c
1
Z
D
Z
E
L
1
Terminal cross section
b
1
c
1
bp
c
R8C/2G Group Appendix 2. Connection Examples with On-Chip Debugging Emulator
Rev.1.00 Apr 04, 2008 Page 315 of 318
REJ09B0387-0100
Appendix 2.
Connection Examples with On-Chip Debugging Emulator
Appendix Figure 2.1 shows a Connection Example with E8 Emulator (R0E000080KCE00).
Appendix Figure 2.1 Connection Example with E8 Emulator (R 0E000080KCE00)
NOTE:
1. It is not necessary to connect an oscillation circuit when
operating with the on-chip oscillator clock.
MODE
4.7kΩ ±10%
E8 emulator
(R0E000080KCE00)
RESET
12
10
8
6
4
2
VSS
13
7 MODE
VCC
14
VSS
VCC
Connect oscillation circuit(1)
29
28
27
26
25
32
31
30
9
10
11
12
13
14
15
16
5
7
8
1
2
3
4
6
24
23
22
21
20
19
18
17
R8C/2G Group
4.7kΩ or more
Open collector buffer
User logic
R8C/2G Group Appendix 3. Example of Oscillation Evaluation Circuit
Rev.1.00 Apr 04, 2008 Page 316 of 318
REJ09B0387-0100
Appendix 3. Example of Oscillation Evaluation Circuit
Appendix Figure 3.1 shows an Example of Oscillation Evaluation Circuit.
Appendix Figure 3.1 Example of Oscillation Evaluation Circuit
Connect
oscillation
circuit
NOTE:
1. After reset, the XCIN clock stop.
Write a program to oscillate the XCIN clock.
VSS
VCC
RESET
29
28
27
26
25
32
31
30
9
10
11
12
13
14
15
16
5
7
8
1
2
3
4
6
24
23
22
21
20
19
18
17
R8C/2G Group
Rev.1.00 Apr 04, 2008 Page 317 of 318
REJ09B0387-0100
R8C/2G Group Index
[ A ]
AIER .................................................................................... 128
ALCMR .................................................................................. 52
[ B ]
BGRCR ................................................................................. 53
BGRTRM ............................................................................... 54
BGRTRMA ............................................................................ 48
BGRTRMB ............................................................................ 48
[ C ]
CAPIC ................................................................................. 113
CM0 ....................................................................................... 89
CM1 ....................................................................................... 90
CMP0IC ............................................................................... 113
CMP1IC ............................................................................... 113
CPSRF .................................................................................. 93
CSPR .................................................................................. 140
[ F ]
FMR0 .................................................................................. 249
FMR1 .................................................................................. 252
FMR4 .................................................................................. 253
FRA4 ..................................................................................... 93
FRA6 ..................................................................................... 93
[ H ]
HRA0 ..................................................................................... 92
HRA1 ..................................................................................... 92
HRA2 ..................................................................................... 92
[ I ]
INT0IC ................................................................................. 114
INT1IC ................................................................................. 114
INT2IC ................................................................................. 114
INT4IC ................................................................................. 114
INTEN ................................................................................. 121
INTEN2 ............................................................................... 122
INTF .................................................................................... 122
INTF2 .................................................................................. 123
[ K ]
KIEN .................................................................................... 126
KUPIC ................................................................................. 113
[ L ]
LINCR ................................................................................. 231
LINST .................................................................................. 232
[ O ]
OCD ...................................................................................... 91
OFS ............................................................... 26, 135, 140, 247
[ P ]
PDi (i = 0, 1, 3, 4, or 6) .......................................................... 71
Pi (i = 0, 1, 3, 4, or 6) ............................................................. 72
PINSR2 ................................................................................. 73
PINSR3 ................................................................................. 73
PINSR4 ..................................................................... 39, 54, 73
PM0 ....................................................................................... 85
PM1 ....................................................................................... 85
PMR ....................................................................................... 74
PRCR .................................................................................. 107
PUR0 ..................................................................................... 74
PUR1 ..................................................................................... 74
[ R ]
RMAD0 ................................................................................ 128
RMAD1 ................................................................................ 128
[ S ]
S0RIC .................................................................................. 113
S0TIC .................................................................................. 113
S2RIC .................................................................................. 113
S2TIC .................................................................................. 113
[ T ]
TRA ..................................................................................... 147
TRACR ................................................................................ 146
TRAIC .................................................................................. 113
TRAIOC ....................................... 146, 148, 151, 153, 155, 158
TRAMR ................................................................................ 147
TRAPRE .............................................................................. 147
TRBCR ................................................................................ 162
TRBIC .................................................................................. 113
TRBIOC ............................................... 163, 165, 169, 172, 176
TRBMR ................................................................................ 163
TRBOCR ............................................................................. 162
TRBPR ................................................................................ 164
TRBPRE .............................................................................. 164
TRBSC ................................................................................ 164
TRECR1 ...................................................................... 187, 194
TRECR2 ...................................................................... 188, 194
TRECSR ...................................................................... 189, 195
TREHR ................................................................................ 186
TREIC .................................................................................. 113
TREMIN ....................................................................... 185, 193
TREOPR .............................................................................. 189
TRESEC ...................................................................... 185, 193
TREWK ................................................................................ 186
TRF ...................................................................................... 202
TRFCR0 .............................................................................. 203
TRFCR1 .............................................................................. 204
TRFCR2 .............................................................................. 203
TRFIC .................................................................................. 113
TRFM0 ................................................................................. 202
TRFM1 ................................................................................. 202
TRFOUT .............................................................................. 204
[ U ]
U0BRG ................................................................................ 215
U0C0 ................................................................................... 216
U0C1 ................................................................................... 217
U0MR .................................................................................. 215
U0RB ................................................................................... 217
U0TB ................................................................................... 216
U2BRG ................................................................................ 215
U2C0 ................................................................................... 216
U2C1 ................................................................................... 217
U2MR .................................................................................. 215
U2RB ................................................................................... 217
U2TB ................................................................................... 216
Index
Rev.1.00 Apr 04, 2008 Page 318 of 318
REJ09B0387-0100
R8C/2G Group Index
[ V ]
VCA1 ............................................................................... 35, 49
VCA2 ......................................................................... 35, 49, 94
VCAB .................................................................................... 52
VCAC .............................................................................. 39, 53
VCMP1IC ............................................................................ 113
VCMP2IC ............................................................................ 113
VW0C .................................................................................... 36
VW1C .............................................................................. 37, 50
VW2C .............................................................................. 38, 51
[ W ]
WDC .................................................................................... 139
WDTR ................................................................................. 139
WDTS .................................................................................. 139
C - 1
REVISION HISTORY R8C/2G Group Hardware Manual
Rev. Date Description
Page Summary
0.01 Mar 30, 2007 −First Edition issued
0.10 Jul 20, 2007 −“RENESAS TECHNICAL UPDATE” reflected:
TN-16C-A164A/E, TN-16C-A167A/E
−Register/bit symbols revised:
“CM1POR” → “LCM1POR”, “CM2POR” → “LCM2POR”,
“ACMR” → “ALCMR”
2 Table 1.1: Clock; “Real-time clock (timer RE)” added
5Figure 1.3 “P4_4/(XCOUT)(1)” → “P4_4/XCOUT”,
“P4_3/(XCIN)(1)” → “P4_3/XCIN”
6Table 1.3 “(XCOUT)(1)” → “XCOUT”, “(XCIN)(1)” → “XCIN”
13, 36 Table 4.2, Figure 6.6: 0038h After reset;
“0000X010b” → “1000X010b”, “0100X011b” → “1100X011b”
25 Figure 5.3 revised
26, 130,
135, 242
Figure 5.4, Figure 15.2, Figure 16.3, Figure 20.2:
OFS Register; NOTE1 revised
83 Figure 11.1 revised
139 Table 17.1: Timer RE; “• fC32” deleted
144 Figure 17.5 revised
156 17.2 “The reload register .... same address” added
159 Figure 17.15 “Programmable one-shot mode” → “Programmable one-
shot generation mode”
162 Figure 17.17 revised
173 NOTE: “TRBIOC” added
229 Figure 19.5 revised
230 Figure 19.6 revised
231 Figure 19.7: SFDCT flag in the LINST register;
“Set by ....the B1CLR bit in the LINST register” →
“Set by ....the B0CLR bit in the LINST register”
233 Figure 19.9 revised
236 Figure 19.12 revised
268 Figure 20.23: Title is revised
270 Figure 20.24: Title is revised
276 Figure 21.2 NOTE4 deleted
282 Table 22.9 Parameter: “High-speed on-chip oscillator temperature
supply voltage dependence” → “High-speed on-chip oscillator frequency
temperature • supply voltage dependence”
317 Appendix Figure 2.1 revised
0.20 Nov 12, 2007 2 Table 1.1 I/O Ports: “• Output-only: 1” added
“• CMOS I/O ports: 28” → “• CMOS I/O ports: 27”
4 Figure 1.2 revised
R8C/2G Group Hardware Manual
REVISION HISTORY
C - 2
REVISION HISTORY R8C/2G Group Hardware Manual
0.20 Nov 12, 2007 5 Figure 1.3 revised
6 Table 1.3 Pin Number: 4, 6, 20 revised
7 Table 1.4 I/O port: “P4_3 to P4_5” → “P4_3, P4_5”
Output port added
12 Table 4.1 0006h “01001000b” → “01011000b”
16 Table 4.5 0118h to 011Dh: After reset revised
011Fh “Timer RE Real-Time Clock Precision Adjust Register”
added
45 Figure 6.13 revised
61 8. “There are 28 I/O ports ...... oscillation circuit is not used.”
→ “There are 27 I/O ports ...... used as an output port.”
Table 8.1 revised, NOTE3 added
65 Figure 8.3 revised
67 Figure 8.5 NOTE3 “To use port P4_4 as ... an input port.” added
69 Figure 8.7 b7 revised
70 Figure 8.9 PUR1: b1 revised
71 Table 8.4 revised
77 Table 8.26 NOTE2 added, Table 8.27 revised
78 Table 8.29, Table 8.32 revised
80 8.6 added
83 Table 11.1 Oscillator status after reset: XCIN Clock Oscillation Circuit
“Stop” → “Oscillate”
85 Figure 11.2 revised
93 11.2 “During and after reset, the XCIN clock stops.” → “During and after
reset, the XCIN clock oscillates.”
141 Figure 17.1 “TSTART” → “TCSTF”
179 Figure 17.26 revised
180 Table 17.11 Select function revised
181 Figure 17.27, Figure 17.28 After Reset “00h” → “Undefined”
182 Figure 17.29 After Reset “00h” → “X0XXXXXXb”
Figure 17.30 After Reset “00h” → “X0000XXXb”
183 Figure 17.31 After Reset “00h” → “XXX0X0X0b”
184 Figure 17.33 After Reset “00h” → “00XXXXXXb”
185 Figure 17.35 added
187 Figure 17.37 revised
188 Table 17.13 Select functions: Specification revised
189 Figure 17.38, Figure 17.39 After Reset “00h” → “Undefined”
190 Figure 17.40 After Reset “00h” → “XXX0X0X0b”
Figure 17.41 After Reset “00h” → “00XXXXXXb”
193 17.3.3.1 NOTE revised
Rev. Date Description
Page Summary
C - 3
REVISION HISTORY R8C/2G Group Hardware Manual
0.20 Nov 12, 2007 194 Figure 17.44 revised
200 Figure 17.50 NOTE4 added
234 Figure 19.9 revised
279 Table 22.2 NOTE2 revised
309 Figure 23.4 revised
1.00 Apr 04, 2008 All pages “Under development” deleted
2 Table 1.1 revised
3 Table 1.2 “(D): Under development” deleted
11 Figure 3.1 “Expanded area” deleted
12 Table 4.1 “002Eh” “002Fh” revised
13 Table 4.2 “003Eh” “003Fh” revised
24 Figure 5.1 NOTE1 added
25 Table 5.2 revised
38, 51 Figure 6.8, Figure 7.5; “7. The VW2C7 ... 1.” → “7. The VW2C7 ... 0.”
48 Figure 7.2 added
53, 54 Figure 7.9, Figure 7.10 added
63, 64 7.6, Figure 7.16, Figure 7.17 added
107 12, Figure 12.1; “BGRCR, and BGRTRM” added
144 Table 17.1 Timer RF “Capture interrupt” added
161 Figure 17.12 “TSTRAT” → “TSTART”
171 Table 17.9 “TRBP pin function” → “TRBO pin function”
235 Figure 19.6 “Three to five ...” → “One to two ...”
238 Figure 19.9 revised
244 Table 20.1 “Suspend function” deleted
248 20.4 “The flash module ... (EW1 mode).” deleted
Table 20.3 “... to erase-suspend” “... to program-suspend” deleted
250 • FMR00 Bit “(including suspend periods)” deleted
251 Table 20.4 “FRM0 Register ...” → “FMR0 Register ...”
253 Figure 20.5 revised
• FMR40 Bit, • FMR41 Bit, • FMR42 Bit, • FMR43 Bit, • FMR44 Bit,
• FMR46 Bit; deleted
256 Figure 20.8 revised
258 • Program Command; revised
Old Figure 20.11 deleted
259 • Block Erase; revised
Old Figure 20.13, Old 20.4.3.2, Old Figure 20.14, Old Figure 20.15;
deleted
262 Figure 20.13 revised
263 • Program Command; revised
Old Figure 20.19 deleted
Rev. Date Description
Page Summary
C - 4
REVISION HISTORY R8C/2G Group Hardware Manual
1.00 Apr 04, 2008 264 • Block Erase; revised
Old Figure 20.21, Old 20.4.4.2, Old Figure 20.22, Old Figure 20.23;
deleted
265 Table 20.6 revised
267 Table 20.7 “P4_4 input/clock output” → “P4_4 output/clock output”
270 Old 20.7.1.7, Old 20.7.1.8 deleted
276 Table 22.3 revised
Figure 22.2 deleted
279 Table 22.8, Table 22.11 revised
Table 22.9 revised, NOTE3 added
281 Table 22.13 revised
285 Table 22.19 revised
289 Table 22.25 revised
311 Old 23.9.1.7, Old 23.9.1.8 deleted
Rev. Date Description
Page Summary
R8C/2G Group Hardware Manual
Publication Date: Rev.0.01 Mar 30, 2007
Rev.1.00 Apr 04, 2008
Published by: Sales Strategic Planning Div.
Renesas Technology Corp.
© 2008. Renesas Technology Corp., All rights reserved. Printed in Japan
1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8668 Japan
R8C/2G Group
REJ09B0387-0100
Hardware Manual
