Signal Name Description
PWRGOOD PWRGOOD is a processor input. The processor requires this signal to be a
clean indication that all processor clocks and power supplies are stable and
within their specifications.
"Clean" implies that the signal will remain low (capable of sinking leakage
current), without glitches, from the time that the power supplies are turned
on until they come within specification. The signal must then transition
monotonically to a high state.
PWRGOOD can be driven inactive at any time, but clocks and power must
again be stable before a subsequent rising edge of PWRGOOD. PWRGOOD
transitions from inactive to active when all supplies except VCCIN are
stable.
The signal must be supplied to the processor; it is used to protect internal
circuits against voltage sequencing issues. It should be driven high
throughout boundary scan operation.
RESET_N Global reset signal. Asserting the RESET_N signal resets the processor to a
known state and invalidates its internal caches without writing back any of
their contents. Note some PLL, Intel QuickPath Interconnect and error
states are not affected by reset and only PWRGOOD forces them to a
known state.
THERMTRIP_N Assertion of THERMTRIP_N (Thermal Trip) indicates one of two possible
critical over-temperature conditions: One, the processor junction
temperature has reached a level beyond which permanent silicon damage
may occur and Two, the system memory interface has exceeded a critical
temperature limit set by BIOS. Measurement of the processor junction
temperature is accomplished through multiple internal thermal sensors that
are monitored by the Digital Thermal Sensor (DTS). Simultaneously, the
Power Control Unit (PCU) monitors external memory temperatures via the
dedicated SMBus interface to the DIMMs.
If any of the DIMMs exceed the BIOS defined limits, the PCU will signal
THERMTRIP_N to prevent damage to the DIMMs.
Once activated, the processor will stop all execution and shut down all
PLLs. To further protect the processor, its core voltage (VCCIN), VCCD,
VCCIO_IN, VCCPECI supplies must be removed following the assertion of
THERMTRIP_N.
Once activated, THERMTRIP_N remains latched until RESET_N is asserted.
While the assertion of the RESET_N signal may de-assert THERMTRIP_N, if
the processor's junction temperature remains at or above the trip level,
THERMTRIP_N will again be asserted after RESET_N is de-asserted. This
signal can also be asserted if the system memory interface has exceeded a
critical temperature limit set by BIOS.
Table 32. Miscellaneous Signals
Signal Name Description
BIST_ENABLE BIST Enable Strap. Input which allows the platform to enable or disable
built-in self test (BIST) on the processor. This signal is pulled up on the die.
Rrefer to Table 8 on page 26 for details.
BMCINIT BMC Initialization Strap. Indicates whether Service Processor Boot Mode
should be used. Used in combination with FRMAGENT and SOCKET_ID
inputs.
• 0: Service Processor Boot Mode Disabled. Example boot modes: Local
PCH (this processor hosts a legacy PCH with firmware behind it), Intel
QPI Link Boot (for processors one hop away from the FW agent), or
Intel QPI Link Init (for processors more than one hop away from the
firmware agent).
• 1: Service Processor Boot Mode Enabled. In this mode of operation, the
processor performs the absolute minimum internal configuration and
then waits for the Service Processor to complete its initialization. The
socket boots after receiving a "GO" handshake signal via a firmware
scratchpad register.
continued...
Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families—Signal Descriptions
Intel® Xeon® Processor E5-1600, E5-2600, and E5-4600 v3 Product Families, Volume 1 of 2, Electrical
Datasheet June 2015
56 Order No.: 330783-002