SN55LBC176, SN65LBC176, SN65LBC176Q, SN75LBC176
DIFFERENTIAL BUS TRANSCEIVERS
SLLS067H − AUGUST 1990 − REVISED DECEMBER 2010
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DBidirectional Transceiver
DMeets or Exceeds the Requirements of
ANSI Standard TIA/EIA−485−A and
ISO 8482:1987(E)
DHigh-Speed Low-Power LinBiCMOS™
Circuitry
DDesigned for High-Speed Operation in Both
Serial and Parallel Applications
DLow Skew
DDesigned for Multipoint Transmission on
Long Bus Lines in Noisy Environments
DVery Low Disabled Supply Current ...200
μA Maximum
DWide Positive and Negative Input/Output
Bus Voltage Ranges
DThermal-Shutdown Protection
DDriver Positive-and Negative-Current
Limiting
DOpen-Circuit Failsafe Receiver Design
DReceiver Input Sensitivity . . . ±200 mV Max
DReceiver Input Hysteresis . . . 50 mV Typ
DOperates From a Single 5-V Supply
DGlitch-Free Power-Up and Power-Down
Protection
DAvailable in Q-Temp Automotive
HighRel Automotive Applications
Configuration Control / Print Support
Qualification to Automotive Standards
description
The SN55LBC176, SN65LBC176,
SN65LBC176Q, and SN75LBC176 differential
bus transceivers are monolithic, integrated
circuits designed for bidirectional data communi-
cation on multipoint bus-transmission lines. They
are designed for balanced transmission lines and
meet ANSI Standard TIA/EIA−485−A (RS-485)
and ISO 8482:1987(E).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
8
7
6
5
R
RE
DE
D
VCC
B
A
GND
D, JG, OR P PACKAGE
(TOP VIEW)
3212019
910111213
4
5
6
7
8
18
17
16
15
14
NC
B
NC
A
NC
NC
RE
NC
DE
NC
FK PACKAGE
(TOP VIEW)
NC
R
NC
GND
NC
V
NC
NC
D
NC
NC−No internal connection
CC
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 2000−2006, Texas Instruments Incorporated
LinBiCMOS and LinASIC are trademarks of Texas Instruments Incorporated.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
INPUT
D
H
L
X
ENABLE
DE
H
H
L
OUTPUTS
A B
H L
L H
Z Z
DRIVER
DIFFERENTIAL INPUTS
VID = VIA −VIB
VID ≥ 0.2 V
−0.2 V < VID < 0.2 V
VID ≤ −0.2 V
X
Open
ENABLE
RE
L
L
L
H
L
OUTPUT
R
H
?
L
Z
H
RECEIVER
H = high level, L = low level, ? = indeterminate,
X = irrelevant, Z = high impedance (off)
Function Tables
SN55LBC176, SN65LBC176, SN65LBC176Q, SN75LBC176
DIFFERENTIAL BUS TRANSCEIVERS
SLLS067H − AUGUST 1990 − REVISED DECEMBER 2010
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
The SN55LBC176, SN65LBC176, SN65LBC176Q, and SN75LBC176 combine a 3-state, differential line driver
and a differential input line receiver, both of which operate from a single 5-V power supply. The driver and
receiver have active-high and active-low enables, respectively, which can externally connect together to
function as a direction control. The driver differential outputs and the receiver differential inputs connect
internally to form a differential input/output (I/O) bus port that is designed to offer minimum loading to the bus
whenever the driver is disabled or VCC = 0. This port features wide positive and negative common-mode voltage
ranges, making the device suitable for party-line applications. Very low device supply current can be achieved
by disabling the driver and the receiver.
These transceivers are suitable for ANSI Standard TIA/EIA−485 (RS-485) and ISO 8482 applications to the
extent that they are specified in the operating conditions and characteristics section of this data sheet. Certain
limits contained in TIA/EIA−485−A and ISO 8482:1987 (E) are not met or cannot be tested over the entire military
temperature range.
The SN55LBC176 is characterized for operation from −55°C to 125°C. The SN65LBC176 is characterized for
operation from −40°C to 85°C, and the SN65LBC176Q is characterized for operation from −40°C to 125°C.
The SN75LBC176 is characterized for operation from 0°C to 70°C.
logic symbol†logic diagram (positive logic)
2
EN1
B
A
1
4
2
R
D
RE
7
6
D
RE
R7
6
4
1
2
B
ABus
3
EN2
1
1
DE
3
DE
†This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
AVAILABLE OPTIONS
TAPACKAGE PART NUMBER PART MARKING
0°C to 70°C
SOP SN75LBC176D 7LB176
0°C to 70°CPDIP SN75LBC176P 75LBC176
40°C to 85°C
SOP SN65LBC176D 6LB176
−40°C to 85°CPDIP SN65LBC176P 65LBC176
40°C to 125°C
SOP SN65LBC176QD LB176Q
−40°C to 125°CSOP SN65LBC176QDR LB176Q
55°C to 125°C
LCCC SNJ55LBC176FK SNJ55LBC176FK
−55°C to 125°CCDIP SNJ55LBC176JG SNJ55LBC176
SN55LBC176, SN65LBC176, SN65LBC176Q, SN75LBC176
DIFFERENTIAL BUS TRANSCEIVERS
SLLS067H − AUGUST 1990 − REVISED DECEMBER 2010
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
schematics of inputs and outputs
Input
VCC
EQUIVALENT OF D, RE, and
DE INPUTS
TYPICAL OF RECEIVER OUTPUT
Output
VCC
VCC
100 kΩ NOM
A Port Only
18 kΩ
NOM
3 kΩ
NOM
A or B
100 kΩ NOM
B Port Only 1.1 kΩ
NOM
TYPICAL OF A AND B I/O PORTS
absolute maximum ratings†
Supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range at any bus terminal −10 V to 15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, VI (D, DE, R, or RE) −0.3 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receiver output current, IO $10 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values, except differential I/O bus voltage, are with respect to network ground terminal.
DISSIPATION RATING TABLE
PACKAGE THERMAL
MODEL
TA < 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
TA = 110°C
POWER RATING
D
Low K†526 mW 5.0 mW/°C301 mW 226 mW —
DHigh K‡882 mW 8.4 mW/°C 504 mW 378 mW —
P840 mW 8.0 mW/°C480 mW 360 mW —
JG 1050 mW 8.4 mW/°C672 mW 546 mW 210 mW
FK 1375 mW 11.0 mW/°C880 mW 715 mW 440 mW
†In accordance with the low effective thermal conductivity metric definitions of EIA/JESD 51−3.
‡In accordance with the high effective thermal conductivity metric definitions of EIA/JESD 51−7.
SN55LBC176, SN65LBC176, SN65LBC176Q, SN75LBC176
DIFFERENTIAL BUS TRANSCEIVERS
SLLS067H − AUGUST 1990 − REVISED DECEMBER 2010
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, VCC 4.75 5 5.25 V
Voltage at any bus terminal (separately or common mode), VI or VIC −7 12 V
High-level input voltage, VIH D, DE, and RE 2 V
Low-level input voltage, VIL D, DE, and RE 0.8 V
Differential input voltage, VID (see Note 2) −12 12 V
High level output current I
Driver −60 mA
High-level output current, IOH Receiver −400 μA
Low level output current I
Driver 60
mA
Low-level output current, IOL Receiver 8 mA
Junction temperature, TJ140 °C
SN55LBC176 −55 125
Operating free air temperature T
SN65LBC176 −40 85
°C
Operating free-air temperature, TASN65LBC176Q −40 125 °C
SN75LBC176 0 70
NOTE 2: Differential input/output bus voltage is measured at the noninverting terminal A with respect to the inverting terminal B.
SN55LBC176, SN65LBC176, SN65LBC176Q, SN75LBC176
DIFFERENTIAL BUS TRANSCEIVERS
SLLS067H − AUGUST 1990 − REVISED DECEMBER 2010
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DRIVER SECTION
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
VIK Input clamp voltage II = −18 mA −1.5 V
VOOutput voltage IO = 0 0 6 V
| VOD1 | Differential output voltage IO = 0 1.5 6 V
55LBC176
,
| V |
Diff ti l t t lt
R
L
= 54 Ω
,
See Fi
ure 1
55LBC176
,
65LBC176, 1.1
V
| VOD2 | Differential output voltage
RL = 54 Ω
,
See Note 3
,
65LBC176
,
65LBC176Q
1
.
1
V
See Note 3
75LBC176 1.5 5
55LCB176,
65LCB176
11
VOD3 Differential output voltage Vtest = −7 V to 12 V,
See Note 3
See Figure 2, 65LCB176,
65LBC176Q
1.1 V
See Note 3
75LBC176 1.5 5
Δ| VOD | Change in magnitude of differential
output voltage†−0.2 0.2 V
VOC Common-mode output voltage RL = 54 Ω or 100 Ω,See Figure 1 −1 3 V
Δ| VOC | Change in magnitude of
common-mode output voltage†
RL 54 Ω or 100 Ω,
−0.2 0.2 V
I
Output current
Output disabled, VO = 12 V 1
mA
IOOutput current
Output disabled
,
See Note 4 VO = −7 V −0.8 mA
IIH High-level input current VI = 2.4 V −100 μA
IIL Low-level input current VI = 0.4 V −100 μA
VO = −7 V −250
I
Short circuit output current
VO = 0 −150
mA
IOS Short-circuit output current VO = VCC
250
mA
VO = 12 V 250
Receiver disabled
55LBC176,
65LBC176Q 1.75
I
Supply current
VI = 0 or V
CC
,
and driver enabled 65LBC176,
75LBC176 1.5
mA
ICC Supply current
VI = 0 or VCC
,
No load
Receiver and driver
55LBC176,
65LBC176Q 0.25
mA
disabled 65LBC176,
75LBC176 0.2
†Δ | VOD | and Δ | VOC | are the changes in magnitude of VOD and VOC, respectively, that occur when the input changes from a high level to a
low level.
NOTES: 3. This device meets the VOD requirements of TIA/EIA−485−A above 0°C only.
4. This applies for both power on and off; refer to TIA/EIA−485−A for exact conditions.
SN55LBC176, SN65LBC176, SN65LBC176Q, SN75LBC176
DIFFERENTIAL BUS TRANSCEIVERS
SLLS067H − AUGUST 1990 − REVISED DECEMBER 2010
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER TEST CONDITIONS
SN55LBC176
SN65LBC176Q
SN65LBC176
SN75LBC176 UNIT
PARAMETER
TEST CONDITIONS
MIN TYP MAX MIN TYP†MAX
UNIT
td(OD) Differential output delay time
R 54 Ω
C 50 F
8 31 8 25 ns
tt(OD) Differential output transition time RL = 54 Ω,
See Figure 3
CL = 50 pF, 12 12 ns
tsk(p) Pulse skew (| td(ODH) − td(ODL) |)
S
ee
Fi
gure
3
6 0 6 ns
tPZH Output enable time to high level RL = 110 Ω,See Figure 4 65 35 ns
tPZL Output enable time to low level RL = 110 Ω,See Figure 5 65 35 ns
tPHZ Output disable time from high level RL = 110 Ω,See Figure 4 105 60 ns
tPLZ Output disable time from low level RL = 110 Ω,See Figure 5 105 35 ns
†All typical values are at VCC = 5 V, TA = 25°C.
SYMBOL EQUIVALENTS
DATA SHEET PARAMETER RS-485
VOVoa, Vob
| VOD1 | Vo
| VOD2 | Vt (RL = 54 Ω)
| VOD3 | Vt (test termination
measurement 2)
Δ | VOD | || Vt | − | Vt ||
VOC | Vos |
Δ | VOC | | Vos − Vos |
IOS None
IOIia, Iib
SN55LBC176, SN65LBC176, SN65LBC176Q, SN75LBC176
DIFFERENTIAL BUS TRANSCEIVERS
SLLS067H − AUGUST 1990 − REVISED DECEMBER 2010
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
RECEIVER SECTION
electrical characteristics over recommended ranges of common-mode input voltage, supply
voltage, and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
VIT + Positive-going input threshold
voltage VO = 2.7 V, IO = −0.4 mA 0.2 V
VIT −Negative-going input threshold
voltage VO = 0.5 V, IO = 8 mA −0.2‡V
Vhys Hysteresis voltage (VIT + − VIT −)
(see Figure 4) 50 mV
VIK Enable-input clamp voltage II = −18 mA −1.5 V
V
High level output voltage
VID = 200 mV, I
O
H = −400
μ
A,
27
V
VOH High-level output voltage
VID = 200 mV
,
See Figure 6
IOH = 400 μA
,2.7 V
V
Low level output voltage
VID = −200 mV, I
O
L = 8 mA,
045
V
VOL Low-level output voltage
VID = 200 mV
,
See Figure 6
IOL = 8 mA
,0.45 V
IOZ High-impedance-state output
current VO = 0.4 V to 2.4 V −20 20 μA
I
Line input current
Other input = 0 V, VI = 12 V 1
mA
IILine input current
Other input = 0 V
,
See Note 5 VI = −7 V −0.8 mA
IIH High-level enable-input current VIH = 2.7 V −100 μA
IIL Low-level enable-input current VIL = 0.4 V −100 μA
rIInput resistance 12 kΩ
Receiver enabled
and driver disabled 3.9 mA
I
CC
Suppl
y
current VI = 0 or VCC,
No load
Ri d
SN55LBC176,
SN65LBC176
025
ICC
Supply current
No load Receiver and
driver disabled
SN65LBC176,
SN65LBC176Q
0.25 mA
driver disabled
SN75LBC176 0.2
†All typical values are at VCC = 5 V, TA = 25°C.
‡The algebraic convention, in which the less-positive (more-negative) limit is designated minimum, is used in this data sheet.
NOTE 5: This applies for both power on and power off. Refer to ANSI Standard RS-485 for exact conditions.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 15 pF
PARAMETER TEST CONDITIONS
SN55LBC176
SN65LBC176Q
SN65LBC176
SN75LBC176 UNIT
PARAMETER
TEST CONDITIONS
MIN MAX MIN TYP†MAX
UNIT
tPLH Propagation delay time, low- to high-level
single-ended output
V 15 V t 15 V
11 37 11 33 ns
tPHL Propagation delay time, high- to low-level
single-ended output
VID = −1.5 V to 1.5 V,
See Figure 7 11 37 11 33 ns
tsk(p) Pulse skew (| tPLH − tPHL |) 10 3 6 ns
tPZH Output enable time to high level
See Figure 8
35 35 ns
tPZL Output enable time to low level See Figure 8 35 30 ns
tPHZ Output disable time from high level
See Figure 8
35 35 ns
tPLZ Output disable time from low level See Figure 8 35 30 ns
†All typical values are at VCC = 5 V, TA = 25°C.
SN55LBC176, SN65LBC176, SN65LBC176Q, SN75LBC176
DIFFERENTIAL BUS TRANSCEIVERS
SLLS067H − AUGUST 1990 − REVISED DECEMBER 2010
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VOC
2
RL
VOD2
Vtest
VOD3 60 Ω
375 Ω
375 Ω
2
RL
Figure 1. Driver VOD and VOC Figure 2. Driver VOD3
VOLTAGE WAVEFORMS
50%
tt(OD)
td(ODL)
10%
tt(OD)
≈ 2.5 V
≈− 2.5 V
90%
50%
Output
td(ODH)
0 V
3 V
1.5 V
Input
TEST CIRCUIT
Output
CL = 50 pF
(see Note B)
RL = 54 Ω
50 Ω
3 V
Generator
(see Note A)
1.5 V
Figure 3. Driver Test Circuit and Voltage Waveforms
VOLTAGE WAVEFORMS
tPHZ
1.5 V
2.3 V
0.5 V
0 V
3 V
tPZH
Output
Input 1.5 V
S1
0 V or 3 V
Output
TEST CIRCUIT
50 Ω
VOH
Voff ≈ 0 V
RL = 110 Ω
Generator
(see Note A)
CL = 50 pF
(see Note B)
Figure 4. Driver Test Circuit and Voltage Waveforms
TEST CIRCUIT
Output
RL = 110 Ω
5 V
S1
50 Ω
3 V or 0 V
VOLTAGE WAVEFORMS
5 V
VOL
0.5 V
tPZL
3 V
0 V
tPLZ
2.3 V
1.5 V
Output
Input
CL = 50 pF
(see Note B)
Generator
(see Note A)
1.5 V
Figure 5. Driver Test Circuit and Voltage Waveforms
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO=50Ω.
B. CL includes probe and jig capacitance.
SN55LBC176, SN65LBC176, SN65LBC176Q, SN75LBC176
DIFFERENTIAL BUS TRANSCEIVERS
SLLS067H − AUGUST 1990 − REVISED DECEMBER 2010
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
−IOH
+IOL
VOL
VID
VOH
Figure 6. Receiver VOH and VOL
51 Ω
CL = 15 pF
(see Note B)
Output
1.5 V
0 V
TEST CIRCUIT VOLTAGE WAVEFORMS
1.5 V
3 V
0 V
Input
Output 1.3 V
VOH
VOL
tPHL
tPLH
Generator
(see Note A)
1.5 V
1.3 V
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO=50Ω.
B. CL includes probe and jig capacitance.
Figure 7. Receiver Test Circuit and Voltage Waveforms
THERMAL CHARACTERISTICS − D PACKAGE
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Junction to ambient thermal reisistance θ†
Low-K board, no air flow 199.4
Junction−to−ambient thermal reisistance, θJA†
High-K board, no air flow 119
°C/W
Junction−to−board thermal reisistance, θJB High-K board, no air flow 67 °C/W
Junction−to−case thermal reisistance, θJC 46.6
Average power dissipation, P(AVG)
RL = 54 Ω, input to D is 10 Mbps 50% duty
cycle square wave, VCC = 5.25 V,
TJ = 130 °C.
330 mW
Thermal shutdown junction temperature, TSD 165 °C
†See TI application note literature number SZZA003, Package Thermal Characterization Methodologies, for an explanation of this parameter.
SN55LBC176, SN65LBC176, SN65LBC176Q, SN75LBC176
DIFFERENTIAL BUS TRANSCEIVERS
SLLS067H − AUGUST 1990 − REVISED DECEMBER 2010
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
Input
3 V
tPZH
1.5 V
1.5 V
0 V
VOH
0 V
0 V
1.5 V
3 V
Input
≈ 1.3 V
VOH
0.5 V
Output
tPHZ
Output
0 V
1.5 V
3 V
Input
tPLZ
Input
3 V
1.5 V
0 V
Output 1.5 V
Output
VOL
≈ 1.3 V
tPZL
≈ 4.5 V
VOL
0.5 V
S1 to 1.5 V
S2 Open
S3 Closed S3 Opened
S2 Closed
S1 to −1.5 V
S1 to 1.5 V
S2 Closed
S3 Closed S3 Closed
S2 Closed
S1 to −1.5 V
VOLTAGE WAVEFORMS
TEST CIRCUIT
50 Ω
S3
5 V
S2
2 kΩ
5 kΩ
S1
−1.5 V
1.5 V
1N916 or Equivalent
Generator
(see Note A)
CL = 15 pF
(see Note B)
Figure 8. Receiver Test Circuit and Voltage Waveforms
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO=50Ω.
B. CL includes probe and jig capacitance.
SN55LBC176, SN65LBC176, SN65LBC176Q, SN75LBC176
DIFFERENTIAL BUS TRANSCEIVERS
SLLS067H − AUGUST 1990 − REVISED DECEMBER 2010
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THERMAL CHARACTERISTICS OF IC PACKAGES
ΘJA (Junction-to-Ambient Thermal Resistance) is defined as the difference in junction temperature to ambient temperature
divided by the operating power
ΘJA is NOT a constant and is a strong function of
Dthe PCB design (50% variation)
Daltitude (20% variation)
Ddevice power (5% variation)
ΘJA can be used to compare the thermal performance of packages if the specific test conditions are defined and used.
Standardized testing includes specification of PCB construction, test chamber volume, sensor locations, and the thermal
characteristics of holding fixtures. ΘJA is often misused when it is used to calculate junction temperatures for other
installations.
TI uses two test PCBs as defined by JEDEC specifications. The low-k board gives average in-use condition thermal
performance and consists of a single trace layer 25 mm long and 2-oz thick copper. The high-k board gives best case in−use
condition and consists of two 1-oz buried power planes with a single trace layer 25 mm long with 2-oz thick copper. A 4%
to 50% difference in ΘJA can be measured between these two test cards
ΘJC (Junction-to-Case Thermal Resistance) is defined as difference in junction temperature to case divided by the
operating power. It is measured by putting the mounted package up against a copper block cold plate to force heat to flow
from die, through the mold compound into the copper block.
ΘJC is a useful thermal characteristic when a heatsink is applied to package. It is NOT a useful characteristic to predict
junction temperature as it provides pessimistic numbers if the case temperature is measured in a non-standard system and
junction temperatures are backed out. It can be used with ΘJB in 1-dimensional thermal simulation of a package system.
ΘJB (Junction-to-Board Thermal Resistance) is defined to be the difference in the junction temperature and the PCB
temperature at the center of the package (closest to the die) when the PCB is clamped in a cold−plate structure. ΘJB is only
defined for the high-k test card.
ΘJB provides an overall thermal resistance between the die and the PCB. It includes a bit of the PCB thermal resistance
(especially for BGA’s with thermal balls) and can be used for simple 1-dimensional network analysis of package system
(see Figure 1).
Surface Node
qJC Calculated/Measured
Junction
qJB Calculated/Measured
PC Board
qCA Calculated
Ambient Node
Figure 1. Thermal Resistance
SN55LBC176, SN65LBC176, SN65LBC176Q, SN75LBC176
DIFFERENTIAL BUS TRANSCEIVERS
SLLS067H − AUGUST 1990 − REVISED DECEMBER 2010
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL INFORMATION
D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
4040047/ D 10/96
0.228 (5,80)
0.244 (6,20)
0.069 (1,75) MAX 0.010 (0,25)
0.004 (0,10)
1
14
0.014 (0,35)
0.020 (0,51)
A
0.157 (4,00)
0.150 (3,81)
7
8
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.010 (0,25)
PINS **
0.008 (0,20) NOM
A MIN
A MAX
DIM
Gage Plane
0.189
(4,80)
(5,00)
0.197
8
(8,55)
(8,75)
0.337
14
0.344
(9,80)
16
0.394
(10,00)
0.386
0.004 (0,10)
M
0.010 (0,25)
0.050 (1,27)
0°−8°
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
SN55LBC176, SN65LBC176, SN65LBC176Q, SN75LBC176
DIFFERENTIAL BUS TRANSCEIVERS
SLLS067H − AUGUST 1990 − REVISED DECEMBER 2010
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL INFORMATION
FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER
4040140/ C 11/95
28 TERMINALS SHOWN
B
0.358
(9,09)
MAX
(11,63)
0.560
(14,22)
0.560
0.458
0.858
(21,8)
1.063
(27,0)
(14,22)
A
NO. OF
MINMAX
0.358
0.660
0.761
0.458
0.342
(8,69)
MIN
(11,23)
(16,26)
0.640
0.740
0.442
(9,09)
(11,63)
(16,76)
0.962
1.165
(23,83)
0.938
(28,99)
1.141
(24,43)
(29,59)
(19,32)(18,78)
**
20
28
52
44
68
84
0.020 (0,51)
TERMINALS
0.080 (2,03)
0.064 (1,63)
(7,80)
0.307
(10,31)
0.406
(12,58)
0.495
(12,58)
0.495
(21,6)
0.850
(26,6)
1.047
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.035 (0,89)
0.010 (0,25)
121314151618 17
11
10
8
9
7
5
432
0.020 (0,51)
0.010 (0,25)
6
12826 27
19
21
B SQ
A SQ
22
23
24
25
20
0.055 (1,40)
0.045 (1,14)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold-plated.
E. Falls within JEDEC MS-004
SN55LBC176, SN65LBC176, SN65LBC176Q, SN75LBC176
DIFFERENTIAL BUS TRANSCEIVERS
SLLS067H − AUGUST 1990 − REVISED DECEMBER 2010
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL INFORMATION
JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE PACKAGE
0.310 (7,87)
0.290 (7,37)
0.014 (0,36)
0.008 (0,20)
Seating Plane
4040107/C 08/96
5
4
0.065 (1,65)
0.045 (1,14)
8
1
0.020 (0,51) MIN
0.400 (10,20)
0.355 (9,00)
0.015 (0,38)
0.023 (0,58)
0.063 (1,60)
0.015 (0,38)
0.200 (5,08) MAX
0.130 (3,30) MIN
0.245 (6,22)
0.280 (7,11)
0.100 (2,54)
0°−15°
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only.
E. Falls within MIL-STD-1835 GDIP1-T8
MECHANICAL DATA
MPDI001A − JANUARY 1995 − REVISED JUNE 1999
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL INFORMATION
P (R-PDIP-T8) PLASTIC DUAL-IN-LINE
8
4
0.015 (0,38)
Gage Plane
0.325 (8,26)
0.300 (7,62)
0.010 (0,25) NOM
MAX
0.430 (10,92)
4040082/D 05/98
0.200 (5,08) MAX
0.125 (3,18) MIN
5
0.355 (9,02)
0.020 (0,51) MIN
0.070 (1,78) MAX
0.240 (6,10)
0.260 (6,60)
0.400 (10,60)
1
0.015 (0,38)
0.021 (0,53)
Seating Plane
M
0.010 (0,25)
0.100 (2,54)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
PACKAGE OPTION ADDENDUM
www.ti.com 23-May-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
5962-9318301Q2A ACTIVE LCCC FK 20 1 TBD Call TI Call TI
5962-9318301QPA ACTIVE CDIP JG 8 1 TBD Call TI Call TI
SN65LBC176D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LBC176DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LBC176DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LBC176DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LBC176P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
SN65LBC176PE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
SN65LBC176QD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LBC176QDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LBC176QDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LBC176QDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75LBC176D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75LBC176DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75LBC176DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75LBC176DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75LBC176P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
SN75LBC176PE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
SNJ55LBC176FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
SNJ55LBC176JG ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type
PACKAGE OPTION ADDENDUM
www.ti.com 23-May-2012
Addendum-Page 2
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN55LBC176, SN65LBC176, SN75LBC176 :
•Catalog: SN75LBC176
•Automotive: SN65LBC176-Q1
•Military: SN55LBC176
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
PACKAGE OPTION ADDENDUM
www.ti.com 23-May-2012
Addendum-Page 3
•Military - QML certified for Military and Defense Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN65LBC176DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN65LBC176QDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN75LBC176DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN65LBC176DR SOIC D 8 2500 340.5 338.1 20.6
SN65LBC176QDR SOIC D 8 2500 367.0 367.0 35.0
SN75LBC176DR SOIC D 8 2500 340.5 338.1 20.6
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MCER001A – JANUARY 1995 – REVISED JANUAR Y 1997
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE
0.310 (7,87)
0.290 (7,37)
0.014 (0,36)
0.008 (0,20)
Seating Plane
4040107/C 08/96
5
4
0.065 (1,65)
0.045 (1,14)
8
1
0.020 (0,51) MIN
0.400 (10,16)
0.355 (9,00)
0.015 (0,38)
0.023 (0,58)
0.063 (1,60)
0.015 (0,38)
0.200 (5,08) MAX
0.130 (3,30) MIN
0.245 (6,22)
0.280 (7,11)
0.100 (2,54)
0°–15°
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP1-T8
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