Low Voltage Controller for Touch Screens AD7879/AD7889 FEATURES Personal digital assistants Smart handheld devices Touch screen monitors Point-of-sale terminals Medical devices Cell phones VCC/REF X- Y- X+ Y+ X+ X- REF- REF- REF+ TEMPERATURE SENSOR 12-BIT SAR ADC AD7879/ AD7879-1/ AD7889/ AD7889-1 SERIAL PORT RESULT REGISTERS CONTROL REGISTERS PENIRQ/INT/DAV GND FILTERING Y- 6-TO-1 MUX Y+ SEQUENCER AND TIMER TO RESULT REGISTERS CS/ DIN/ DOUT/ SCL ADD0 ADD1 SDA 07667-001 APPLICATIONS FUNCTIONAL BLOCK DIAGRAM AUX/VBAT/GPIO 4-wire touch screen interface 1.6 V to 3.6 V operation Median and averaging filter to reduce noise Automatic conversion sequencer and timer User-programmable conversion parameters Auxiliary analog input/battery monitor (0.5 V to 5 V) 1 optional GPIO Interrupt outputs (INT, PENIRQ) Touch-pressure measurement Wake-up on touch function Shutdown mode: 6 A maximum 12-ball, 1.6 mm x 2 mm WLCSP 16-lead, 4 mm x 4 mm LFCSP Figure 1. GENERAL DESCRIPTION The AD7879/AD7889 are 12-bit successive approximation analog-to-digital converters (SAR ADCs) with a synchronous serial interface and low on-resistance switches for driving 4-wire resistive touch screens. The AD7879/AD7889 work with a very low power supply--a single 1.6 V to 3.6 V supply--and feature throughput rates of 105 kSPS. The devices include a shutdown mode that reduces current consumption to less than 6 A. To reduce the effects of noise from LCDs and other sources, the AD7879/AD7889 contain a preprocessing block. The preprocessing function consists of a median filter and an averaging filter. The combination of these two filters provides a more robust solution, discarding the spurious noise in the signal and keeping only the data of interest. The size of both filters is programmable. Other user-programmable conversion controls include variable acquisition time and first conversion delay; up to 16 averages can be taken per conversion. The AD7879/AD7889 can run in slave mode or standalone (master) mode, using an automatic conversion sequencer and timer. The AD7879/AD7889 have a programmable pin that can operate as an auxiliary input to the ADC, as a battery monitor, or as a GPIO. In addition, a programmable interrupt output can operate in three modes: as a general-purpose interrupt to signal when new data is available (DAV), as an interrupt to indicate when limits are exceeded (INT), or as a pen-down interrupt when the screen is touched (PENIRQ). The AD7879/AD7889 offer temperature measurement and touch-pressure measurement. The AD7879 is available in a 12-ball, 1.6 mm x 2 mm WLCSP and in a 16-lead, 4 mm x 4 mm LFCSP. The AD7889 is available in a backside-coated version of the WLCSP. Both parts support an SPI interface (AD7879/AD7889) or an I2C interface (AD7879-1/AD7889-1). Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2008-2010 Analog Devices, Inc. All rights reserved. AD7879/AD7889 TABLE OF CONTENTS Features .............................................................................................. 1 Auxiliary Input ........................................................................... 18 Applications ....................................................................................... 1 Battery Input ............................................................................... 18 Functional Block Diagram .............................................................. 1 Limit Comparison ...................................................................... 18 General Description ......................................................................... 1 GPIO ............................................................................................ 18 Revision History ............................................................................... 2 Conversion Timing ........................................................................ 20 Specifications..................................................................................... 3 Register Map ................................................................................... 21 SPI Timing Specifications (AD7879/AD7889)......................... 4 Detailed Register Descriptions ..................................................... 22 I C Timing Specifications (AD7879-1/AD7889-1).................. 5 Control Registers ............................................................................ 26 Absolute Maximum Ratings............................................................ 6 Control Register 1 ...................................................................... 26 Thermal Resistance ...................................................................... 6 Control Register 2 ...................................................................... 28 ESD Caution .................................................................................. 6 Control Register 3 ...................................................................... 29 Pin Configurations and Function Descriptions ........................... 7 Interrupts ..................................................................................... 30 Typical Performance Characteristics ............................................. 9 Synchronizing the AD7879/AD7889 to the Host CPU ........ 31 Terminology .................................................................................... 12 Serial Interface ................................................................................ 32 Theory of Operation ...................................................................... 13 SPI Interface ................................................................................ 32 Touch Screen Principles ............................................................ 13 I2C-Compatible Interface .......................................................... 34 Measuring Touch Screen Inputs ............................................... 14 Grounding and Layout .................................................................. 37 Touch-Pressure Measurement .................................................. 15 Lead Frame Chip Scale Packages ............................................. 37 Temperature Measurement ....................................................... 15 WLCSP Assembly Considerations ........................................... 37 Median and Averaging Filters ....................................................... 17 Outline Dimensions ....................................................................... 38 AUX/VBAT/GPIO Pin ................................................................... 18 Ordering Guide .......................................................................... 39 2 REVISION HISTORY 11/10--Rev. B to Rev. C Changes to Table 2 ............................................................................ 3 Added Conversion Timing Section .............................................. 20 Added Figure 34.............................................................................. 29 1/10--Rev. A to Rev. B Updated Outline Dimensions ....................................................... 37 Changes to Ordering Guide .......................................................... 38 3/09--Rev. 0 to Rev. A Added AD7889 and Backside-Coated WLCSP ......... Throughout Change to Battery Monitor, Input Voltage Range Parameter ..... 3 Changes to Table 4 ............................................................................ 6 Added Thermal Resistance Section and Table 5; Renumbered Sequentially ................................................................ 6 Changes to Pin Configurations and Function Descriptions Section ................................................................................................ 7 Added Table 7.................................................................................... 8 Changes to First Method Section ................................................. 15 Changes to Median and Averaging Filters Section .................... 17 Changes to GPIO Interrupt Enable (Bit 12, Control Register 3, Address 0x03) Section ................................................................... 19 Changes to Table 13 ....................................................................... 22 Changes to ADC Channel (Control Register 1, Bits[14:12]) Section.............................................................................................. 26 Changes to Power Management (Control Register 2, Bits[15:14]) Section ........................................................................ 27 Changes to DAV--Data Available Interrupt Section................. 29 Changes to INT--Out-of-Limit Interrupt Section .................... 29 Changes to Writing Data Section ................................................. 31 Changes to Reading Data Section and Figure 40 ....................... 32 Changes to Figure 41...................................................................... 33 Changes to Writing Data over the I2C Bus Section.................... 34 Changes to Figure 44...................................................................... 35 Updated Outline Dimensions ....................................................... 37 Changes to Ordering Guide. ......................................................... 38 10/08--Revision 0: Initial Version Rev. C | Page 2 of 40 AD7879/AD7889 SPECIFICATIONS VCC = 1.6 V to 3.6 V, TA = -40C to +85C, unless otherwise noted. Table 1. Parameter DC ACCURACY Resolution No Missing Codes Integral Nonlinearity (INL)1 Differential Nonlinearity (DNL)1 Negative DNL Positive DNL Offset Error1, 2 Gain Error1, 2 Noise3 Power Supply Rejection3 Internal Clock Frequency Internal Clock Accuracy SWITCH DRIVERS On Resistance1 Y+, X+ Y-, X- ANALOG INPUTS Input Voltage Range DC Leakage Current Input Capacitance Accuracy TEMPERATURE MEASUREMENT Temperature Range Resolution Accuracy2 BATTERY MONITOR Input Voltage Range Input Impedance3 Accuracy LOGIC INPUTS (DIN, SCL, CS, SDA, GPIO) Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN3 LOGIC OUTPUTS (DOUT, GPIO, SCL, SDA, INT) Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance2 CONVERSION RATE3 Conversion Time Throughput Rate Min Typ 12 11 12 2 Max Unit 3 Bits Bits LSB -0.99 2 6 4 70 60 2 1.8 2.2 6 5 Test Conditions/Comments LSB size = 390 V. LSB size = 390 V. LSB LSB LSB LSB V rms dB MHz MHz 0 VCC V A pF % +85 C C C Calibrated at 25C. V k % Uncalibrated accuracy. 0.1 30 0.3 -40 0.3 2 0.5 5 16 2 5 0.7 x VCC 0.3 x VCC 0.01 10 VCC - 0.2 V V A pF 0.1 5 V V A pF 9.5 s 105 kSPS 0.4 Rev. C | Page 3 of 40 VIN = 0 V or VCC. Including 2 s of acquisition time, MAV filter off. 2 s of additional time is required if MAV filter is on. AD7879/AD7889 Parameter POWER REQUIREMENTS VCC ICC Converting Mode Static Min Typ Max Unit Test Conditions/Comments 1.6 2.6 3.6 V 480 406 650 A A 0.5 6 A Specified performance. Digital inputs = 0 V or VCC. ADC on, PM = 10. ADC and temperature sensor are off; the reference and oscillator are on; PM = 01 or 11. PM = 00. Shutdown Mode 1 2 3 See the Terminology section. Guaranteed by characterization; not production tested. Sample tested at 25C to ensure compliance. SPI TIMING SPECIFICATIONS (AD7879/AD7889) VCC = 1.6 V to 3.6 V, TA = -40C to +85C, unless otherwise noted. Sample tested at 25C to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VCC) and timed from a voltage level of 1.4 V. Table 2. Parameter 1 fSCL t1 t2 t3 t4 t5 t6 t7 t8 Unit MHz max ns min ns min ns min ns min ns min ns max ns max ns min Description CS falling edge to first SCL falling edge SCL high pulse width SCL low pulse width DIN setup time DIN hold time DOUT access time after SCL falling edge CS rising edge to DOUT high impedance SCL rising edge to CS high Guaranteed by design; not production tested. CS t1 t2 1 SCL t8 t3 2 3 15 16 1 2 15 16 t4 t5 DIN LSB MSB t6 DOUT MSB Figure 2. Detailed SPI Timing Diagram Rev. C | Page 4 of 40 t7 LSB 07667-002 1 Limit 5 5 20 20 15 15 20 16 15 AD7879/AD7889 I2C TIMING SPECIFICATIONS (AD7879-1/AD7889-1) VCC = 1.6 V to 3.6 V, TA = -40C to +85C, unless otherwise noted. Sample tested at 25C to ensure compliance. All input signals are timed from a voltage level of 1.4 V. Table 3. Parameter1 fSCL t1 t2 t3 t4 t5 t6 t7 t8 tR tF Unit kHz max s min s min s min ns min ns min s min s min s min ns max ns max Description Start condition hold time, tHD; STA Clock low period, tLOW Clock high period, tHIGH Data setup time, tSU; DAT Data hold time, tHD; DAT Stop condition setup time, tSU; STO Start condition setup time, tSU; STA Bus-free time between stop and start conditions, tBUF Clock/data rise time Clock/data fall time Guaranteed by design; not production tested. tR t2 tF t1 SCL t3 t1 t5 t7 t6 t4 SDA t8 STOP START START Figure 3. Detailed I2C Timing Diagram Rev. C | Page 5 of 40 STOP 07667-003 1 Limit 400 0.6 1.3 0.6 100 300 0.6 0.6 1.3 300 300 AD7879/AD7889 ABSOLUTE MAXIMUM RATINGS TA = 25C, unless otherwise noted. THERMAL RESISTANCE Table 4. JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. 1 Rating -0.3 V to +3.6 V -0.3 V to VCC + 0.3 V -0.3 V to +5 V -0.3 V to VCC + 0.3 V -0.3 V to VCC + 0.3 V 10 mA Table 5. Thermal Resistance Package Type1 12-Ball WLCSP 16-Lead LFCSP 1 JA 75 30.4 Unit C/W C/W 4-layer board. 15 kV 10 kV 200A TO OUTPUT PIN 4 kV 1 kV 0.2 kV -40C to +85C -65C to +150C 150C IOL 1.4V CL 50pF 200A IOH Figure 4. Circuit Used for Digital Timing ESD CAUTION 866 mW 2.138 W 260C (0.5C) 300C Transient currents of up to 100 mA do not cause SCR latch-up. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. C | Page 6 of 40 07667-004 Parameter VCC to GND Analog Input Voltage to GND AUX/VBAT to GND Digital Input Voltage to GND Digital Output Voltage to GND Input Current to Any Pin Except Supplies1 ESD Rating (X+, Y+, X-, Y-) Air Discharge Human Body Model Contact Human Body Model ESD Rating (All Other Pins) Human Body Discharge Field-Induced Charged Device Model Machine Model Operating Temperature Range Storage Temperature Range Junction Temperature Power Dissipation WLCSP (4-Layer Board) LFCSP (4-Layer Board) IR Reflow Peak Temperature Lead Temperature (Soldering 10 sec) AD7879/AD7889 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS BALL A1 INDICATOR 1 2 AUX/ VBAT/ GPIO VCC/REF BALL A1 INDICATOR 1 2 3 AUX/ VBAT/ GPIO VCC/REF X+ A 3 X+ A PENIRQ/ INT/DAV CS PENIRQ/ INT/DAV ADD0 Y+ B Y+ B DOUT DIN X- C SDA ADD1 X- SCL GND Y- C SCL GND Y- D TOP VIEW (BALL SIDE DOWN) Not to Scale Figure 5. AD7879/AD7889 WLCSP Pin Configuration 07667-006 TOP VIEW (BALL SIDE DOWN) Not to Scale 07667-005 D Figure 6. AD7879-1/AD7889-1 WLCSP Pin Configuration Table 6. Pin Function Descriptions, WLCSP Ball No. AD7879/ AD7879-1/ AD7889 AD7889-1 1A 1A Mnemonic AUX/VBAT/GPIO 1B 1B PENIRQ/INT/DAV 1C N/A 1D 2A 2B N/A N/A 1C 1D 2A N/A 2B DOUT SDA SCL VCC/REF CS ADD0 2C N/A N/A 2C DIN ADD1 2D 2D GND 3A 3B 3C 3D 3A 3B 3C 3D X+ Y+ X- Y- Description This pin can be programmed as an auxiliary input to the ADC (AUX), as a battery measurement input to the ADC (VBAT), or as a general-purpose digital input/output (GPIO). Interrupt Output. This pin is asserted when the screen is touched (PENIRQ), when a measurement exceeds the preprogrammed limits (INT), or when new data is available in the registers (DAV). Active low, internal 50 k pull-up resistor. SPI Serial Data Output for the AD7879/AD7889. I2C Serial Data Input and Output for the AD7879-1/AD7889-1. Serial Interface Clock Input. Power Supply Input and ADC Reference. Chip Select for the SPI Serial Interface on the AD7879/AD7889. Active low. I2C Address Bit 0 for the AD7879-1/AD7889-1. This pin can be tied high or low to determine an address for the AD7879-1/AD7889-1 (see Table 25). SPI Serial Data Input to the AD7879/AD7889. I2C Address Bit 1 for the AD7879-1/AD7889-1. This pin can be tied high or low to determine an address for the AD7879-1/AD7889-1 (see Table 25). Ground. Ground reference point for all circuitry on the AD7879/AD7889. All analog input signals and any external reference signal should be referred to this voltage. Touch Screen Input Channel. Touch Screen Input Channel. Touch Screen Input Channel. Touch Screen Input Channel. Rev. C | Page 7 of 40 14 ADD0 13 AUX/VBAT/GPIO 12 PENIRQ/INT/DAV Y+ 1 PIN 1 INDICATOR 12 PENIRQ/INT/DAV AD7879-1 11 NC NC 3 TOP VIEW (Not to Scale) 10 NC NC 3 10 NC 9 X- 4 TOP VIEW (Not to Scale) Y- 5 SDA NOTES 1. NC = NO CONNECT 2. THE EXPOSED PAD IS NOT CONNECTED INTERNALLY. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED THAT THE PAD BE SOLDERED TO THE GROUND PLANE. 07667-007 NOTES 1. NC = NO CONNECT 2. THE EXPOSED PAD IS NOT CONNECTED INTERNALLY. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED THAT THE PAD BE SOLDERED TO THE GROUND PLANE. 9 SCL 8 DOUT SCL 8 Y- 5 X- 4 GND 7 NC 2 ADD1 6 11 NC GND 7 AD7879 DIN 6 NC 2 Figure 7. AD7879 LFCSP Pin Configuration 07667-008 PIN 1 INDICATOR Y+ 1 16 X+ 15 VCC/REF 14 CS 13 AUX/VBAT/GPIO 16 X+ 15 VCC/REF AD7879/AD7889 Figure 8. AD7879-1 LFCSP Pin Configuration Table 7. Pin Function Descriptions, LFCSP Pin No. AD7879 AD7879-1 1 1 2, 3, 10, 11 2, 3, 10, 11 4 4 5 5 6 N/A N/A 6 Mnemonic Y+ NC X- Y- DIN ADD1 7 7 GND 8 9 N/A 12 8 N/A 9 12 SCL DOUT SDA PENIRQ/INT/DAV 13 13 AUX/VBAT/GPIO 14 N/A N/A 14 CS ADD0 15 16 15 16 VCC/REF X+ EP Description Touch Screen Input Channel. No Connect. Touch Screen Input Channel. Touch Screen Input Channel. SPI Serial Data Input to the AD7879. I2C Address Bit 1 for the AD7879-1. This pin can be tied high or low to determine an address for the AD7879-1 (see Table 25). Ground. Ground reference point for all circuitry on the AD7879. All analog input signals and any external reference signal should be referred to this voltage. Serial Interface Clock Input. SPI Serial Data Output for the AD7879. I2C Serial Data Input and Output for the AD7879-1. Interrupt Output. This pin is asserted when the screen is touched (PENIRQ), when a measurement exceeds the preprogrammed limits (INT), or when new data is available in the registers (DAV). Active low, internal 50 k pull-up resistor. This pin can be programmed as an auxiliary input to the ADC (AUX), as a battery measurement input to the ADC (VBAT), or as a general-purpose digital input/output (GPIO). Chip Select for the SPI Serial Interface on the AD7879. Active low. I2C Address Bit 0 for the AD7879-1. This pin can be tied high or low to determine an address for the AD7879-1 (see Table 25). Power Supply Input and ADC Reference. Touch Screen Input Channel. Exposed Pad. The exposed pad is not connected internally. For increased reliability of the solder joints and maximum thermal capability, it is recommended that the pad be soldered to the ground plane. Rev. C | Page 8 of 40 AD7879/AD7889 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25C, VCC = 2.6 V, fSCL = 2 MHz, unless otherwise noted. 1.0 470 0.8 465 0.6 GAIN ERROR VARIATION (LSB) 475 455 450 445 440 435 430 0.4 0.2 2.6V 0 3.6V -0.2 -0.4 1.6V -0.6 -0.8 -40 -25 -10 10 25 40 TEMPERATURE (C) 55 70 85 -1.0 07667-009 425 Figure 9. Supply Current vs. Temperature -40 -25 -10 10 25 40 TEMPERATURE (C) 55 70 85 07667-011 CURRENT (A) 460 Figure 12. Change in ADC Gain vs. Temperature 1.0 700 0.8 600 OFFSET VARIATION (LSB) 0.6 CURRENT (A) 500 400 300 200 0.4 1.6V 0.2 2.6V 0 -0.2 3.6V -0.4 -0.6 100 1.8 2.0 2.2 2.4 2.6 2.8 VCC (V) 3.0 3.2 3.4 3.6 -1.0 3.5 1.5 3.0 1.0 2.5 0.5 INL (LSB) 2.0 2.0 -0.5 1.0 -1.0 0.5 -1.5 0 -10 10 25 50 TEMPERATURE (C) -10 10 25 40 TEMPERATURE (C) 55 70 85 0 1.5 75 100 -2.0 07667-012 CURRENT (A) 4.0 -25 -25 Figure 13. Change in ADC Offset vs. Temperature Figure 10. Supply Current vs. VCC -40 -40 0 Figure 11. Full Power-Down IDD vs. Temperature 512 1024 1536 2048 CODE 2560 Figure 14. ADC INL Rev. C | Page 9 of 40 3072 3584 4096 07667-014 1.6 07667-010 0 07667-013 -0.8 AD7879/AD7889 1.0 6.0 0.8 5.5 0.6 5.0 0.2 RON () 0 4.5 -0.2 4.0 -0.4 -0.6 X+ TO VCC Y+ TO VCC X- TO GND Y- TO GND 3.5 -0.8 1 501 1001 1501 2001 2501 CODE 3001 3501 4001 3.0 07667-015 -1.0 -40 Figure 15. ADC DNL -25 -10 10 25 40 TEMPERATURE (C) 55 70 85 07667-017 DNL (LSB) 0.4 Figure 17. Switch On Resistance vs. Temperature (X+, Y+: Pin to VCC; X-, Y-: Pin to GND) 7 2370 2369 6 2368 ADC CODE (Decimal) 4 3 X+ TO VCC Y+ TO VCC X- TO GND Y- TO GND 2 2367 2366 2365 2364 2363 2362 1 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 VCC (V) 3.0 3.2 3.4 3.6 2360 -40 -25 -15 -5 Figure 16. Switch On Resistance vs. VCC (X+, Y+: Pin to VCC; X-, Y-: Pin to GND) 5 15 25 35 45 TEMPERATURE (C) 55 65 75 85 Figure 18. ADC Code vs. Temperature (Fixed Analog Input) Rev. C | Page 10 of 40 07667-018 2361 07667-016 RON () 5 AD7879/AD7889 1400 MEAN: -1.98893 SD: 0.475534 250 1000 NUMBER OF UNITS TEMPERATURE (Code) 1200 800 600 200 150 100 400 50 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 VCC (V) 0 07667-019 0 INPUT TONE AMPLITUDE (dB) SNR = 61.58dB THD = 72.34dB -40 -60 -80 -100 -120 07667-020 0 1603 3206 4809 6412 8015 9618 11221 12824 14427 16030 17633 19236 20839 22442 24045 25648 27251 28854 30457 32060 33663 35266 36869 -140 FREQUENCY (Hz) -2 -1 0 Figure 21. Typical Uncalibrated Accuracy for the Battery Channel (25C) 0 -160 -3 ERROR (%) Figure 19. Temperature Code vs. VCC for 25C -20 -4 07667-021 200 Figure 20. Typical FFT Plot for the Auxiliary Channels at 25 kHz Sampling Rate and 1 kHz Input Frequency Rev. C | Page 11 of 40 AD7879/AD7889 TERMINOLOGY Differential Nonlinearity (DNL) DNL is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Integral Nonlinearity (INL) INL is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale at 1 LSB below the first code transition and full scale at 1 LSB above the last code transition. Gain Error Gain error is the deviation of the last code transition (111 ... 110 to 111 ... 111) from the ideal (VREF - 1 LSB) after the offset error has been calibrated out. Offset Error Offset error is the deviation of the first code transition (00 ... 000 to 00 ... 001) from the ideal (AGND + 1 LSB). On Resistance On resistance is a measure of the ohmic resistance between the drain and the source of the switch drivers. Rev. C | Page 12 of 40 AD7879/AD7889 THEORY OF OPERATION CONDUCTIVE ELECTRODE ON BOTTOM SIDE Y+ The core of the AD7879/AD7889 is a high speed, low power, 12-bit analog-to-digital converter (ADC) with an input multiplexer, on-chip track-and-hold, and on-chip clock. Conversion results are stored in on-chip result registers. The results from the auxiliary input or the battery input can be compared with high and low limits stored in limit registers to generate an outof-limit interrupt (INT). The AD7879/AD7889 also contain low resistance analog switches to switch the X and Y excitation voltages to the touch screen and to the on-chip temperature sensor. The high speed SPI serial bus provides control of the devices, as well as communication with the devices. The AD7879-1/AD7889-1 are available with an I2C interface. Operating from a single supply from 1.6 V to 3.6 V, the AD7879/ AD7889 offer a throughput rate of 105 kHz. The device is available in a 1.6 mm x 2 mm, 12-ball wafer level chip scale package (WLCSP) and in a 4 mm x 4 mm, 16-lead lead frame chip scale package (LFCSP). The AD7879/AD7889 have an on-chip sequencer that schedules a sequence of preprogrammed conversions. The conversion sequence starts automatically when the screen is touched or at preset intervals, using the on-board timer. To ensure that the AD7879/AD7889 work well with different touch screens, the user can select the acquisition time. A programmable delay ensures that the voltage on the touch screen settles before a measurement is taken. To help reduce noise in the system, the ADC takes up to 16 conversion results from each channel and writes the average of the results to the register. To further improve the performance of the AD7879/AD7889, the median filter can also be used if there is noise present in the system. PLASTIC FILM WITH TRANSPARENT, RESISTIVE COATING ON BOTTOM SIDE X- Y- X+ CONDUCTIVE ELECTRODE ON TOP SIDE PLASTIC FILM WITH TRANSPARENT, RESISTIVE COATING ON TOP SIDE LCD SCREEN 07667-022 The AD7879/AD7889 are a complete 12-bit data acquisition system for digitizing positional inputs from a 4-wire resistive touch screen. To support this function, data acquisition on the AD7879/AD7889 is highly programmable to ensure accurate and noise-free results from the touch screen. Figure 22. Basic Construction of a Touch Screen The Y layer has conductive electrodes running along the top and bottom edges, allowing the application of an excitation voltage down the Y layer from top to bottom. Provided that the layers are of uniform resistivity, the voltage at any point between the two electrodes is proportional to the horizontal position for the X layer and the vertical position for the Y layer. When the screen is touched, the two layers make contact. If only the X layer is excited, the voltage at the point of contact and, therefore, the horizontal position, can be sensed at one of the Y layer electrodes. Similarly, if only the Y layer is excited, the voltage and, therefore, the vertical position, can be sensed at one of the X layer electrodes. By switching alternately between X and Y excitation and measuring the voltages, the X and Y coordinates of the contact point can be determined. In addition to measuring the X and Y coordinates, it is also possible to estimate the touch pressure by measuring the contact resistance between the X and Y layers. The AD7879/ AD7889 are designed to facilitate this measurement. TOUCH SCREEN PRINCIPLES A 4-wire touch screen consists of two flexible, transparent, resistive-coated layers that are normally separated by a small air gap (see Figure 22). The X layer has conductive electrodes running down the left and right edges, allowing the application of an excitation voltage across the X layer from left to right. Rev. C | Page 13 of 40 AD7879/AD7889 Figure 23 shows an equivalent circuit of the analog input structure of the AD7879/AD7889, showing the touch screen switches, the main analog multiplexer, the ADC, and the dual 3-to-1 multiplexer that selects the reference source for the ADC. VCC X+ X- Y+ Y- X- Y- GND X+ Y+ VCC DUAL 3-TO-1 MUX AUX/VBAT/GPIO REF- TEMPERATURE SENSOR REF+ 12-BIT SUCCESSIVE APPROXIMATION ADC WITH TRACK-AND-HOLD 07667-023 IN+ Figure 23. Analog Input Structure The AD7879/AD7889 can be set up to automatically convert either specific input channels or a sequence of channels. The results of the ADC conversions are stored in the result registers. When measuring the ancillary analog inputs (AUX, TEMP, or VBAT), the ADC uses a VCC reference and the measurement is referred to GND. VIN = VCC x RY - The advantage of the single-ended method is that the touch screen excitation voltage is switched off when the signal is acquired. Because a screen can draw over 1 mA, this is a significant consideration for a battery-powered system. The disadvantage of the single-ended method is that voltage drops across the switches can introduce errors. Touch screens can have a total end-to-end resistance ranging from 200 to 900 . By taking the lowest screen resistance of 200 and a typical switch resistance of 14 , the user can reduce the apparent excitation voltage to 200/228 x 100 = 87% of its actual value. In addition, the voltage drop across the low-side switch adds to the ADC input voltage. This introduces an offset into the input voltage; thus, it can never reach 0. Ratiometric Method The ratiometric method illustrated in Figure 25 shows the negative input of the ADC reference connected to Y- and the positive input connected to Y+. Thus, the screen excitation voltage provides the reference for the ADC. The input of the ADC is connected to X+ to determine the Y position. VCC Y+ MEASURING TOUCH SCREEN INPUTS When measuring the touch screen inputs, it is possible to use VCC as a reference or instead to use the touch screen excitation voltage as the reference and to perform a ratiometric, differential measurement. The differential method is the default method and is selected by clearing the SER/DFR bit (Bit 9 in Control Register 2) to 0. The single-ended method is selected by setting this bit to 1. Single-Ended Method Figure 24 illustrates the single-ended method for the Y position. For the X position, the excitation voltage is applied to X+ and X- and the voltage is measured at Y+. VCC Y+ X+ VREF INPUT (VIA MUX) X+ REF+ ADC TOUCH SCREEN REF- Y- GND Figure 25. Ratiometric Conversion of Touch Screen Inputs For greater accuracy, the ratiometric method has two significant advantages. One is that the reference to the ADC is provided from the actual voltage across the screen; therefore, any voltage dropped across the switches has no effect. The other advantage is that because the measurement is ratiometric, it does not matter if the voltage across the screen varies in the long term. However, it must not change after the signal has been acquired. REF- 07667-024 Y- GND INPUT (VIA MUX) The disadvantage of the ratiometric method is that the screen must be powered up at all times because it provides the reference voltage for the ADC. REF+ ADC TOUCH SCREEN (1) RYTOTAL 07667-025 INPUT MUX The voltage seen at the input to the ADC in Figure 24 is Figure 24. Single-Ended Conversion of Touch Screen Inputs Rev. C | Page 14 of 40 AD7879/AD7889 TOUCH-PRESSURE MEASUREMENT Second Method The pressure applied to the touch screen by a pen or finger can also be measured with the AD7879/AD7889 using some simple calculations. The contact resistance between the X and Y plates is measured, providing a good indication of the size of the depressed area and, therefore, the applied pressure. The area of the spot that is touched is proportional to the size of the object touching it. The size of this resistance (RTOUCH) can be calculated using two different methods. The second method requires the user to know the resistance of the X-plate and Y-plate tablets. Three touch screen conversions are required: a measurement of the X position (XPOSITION), the Y position (YPOSITION), and the Z1 position. The following equation also calculates the touch resistance (RTOUCH): RTOUCH = RXPLATE x (XPOSITION/4096) x [(4096/Z1) - 1] - RYPLATE x [1 - (YPOSITION/4096)] First Method The first method requires the user to know the total resistance of the X-plate tablet (RX). Three touch screen conversions are required: measurement of the X position, XPOSITION (Y+ input); measurement of the X+ input with the excitation voltage applied to Y+ and X- (Z1 measurement); and measurement of the Y- input with the excitation voltage applied to Y+ and X- (Z2 measurement). These three measurements are illustrated in Figure 26. The AD7879/AD7889 have two special ADC channel settings that configure the X and Y switches for the Z1 and Z2 measurements and store the results in the Z1 and Z2 result registers. The Z1 measurement is selected by setting the CHNL ADD[2:0] bits to 101 in Control Register 1 (Address 0x01); the result is stored in the X+ (Z1) result register (Address 0x0A). The Z2 measurement is selected by setting the CHNL ADD[2:0] bits to 100 in Control Register 1 (Address 0x01); the result is stored in the Y- (Z2) result register (Address 0x0B). The touch resistance (RTOUCH) can then be calculated using the following equation: RTOUCH = (RXPLATE) x (XPOSITION/4096) x [(Z2/Z1) - 1] MEASURE X POSITION X+ TOUCH RESISTANCE Y- Y+ X+ TEMPERATURE MEASUREMENT A temperature measurement option called the single-conversion method is available on the AD7879/AD7889. The conversion method requires only a single measurement on ADC Channel 001. The results are stored in the temperature conversion result register (Address 0x0D). The AD7879/AD7889 do not provide an explicit output of the temperature reading; the system must perform some external calculations. This method is based on an on-chip diode measurement. The acquisition time is fixed at 16 ms for temperature measurement. Conversion Method The conversion method makes use of the fact that the temperature coefficient of a silicon diode is approximately -2.1 mV/C. However, this small change is superimposed on the diode forward voltage, which can have a wide tolerance. Therefore, it is necessary to calibrate by measuring the diode voltage at a known temperature to provide a baseline from which the change in forward voltage with temperature can be measured. This method provides a resolution of approximately 0.3C and a predicted accuracy of 2C. The temperature limit comparison is performed on the result in the temperature conversion result register (Address 0x0D), which is the measurement of the diode forward voltage. The values programmed into the high and low limits should be referenced to the calibrated diode forward voltage to make accurate limit comparisons. Y+ X- (2) MEASURE Z1 POSITION TOUCH RESISTANCE Y- X- Y+ X+ TOUCH RESISTANCE X- MEASURE Z2 POSITION 07667-026 Y- (3) Figure 26. Three Measurements Required for Touch Pressure Rev. C | Page 15 of 40 AD7879/AD7889 Temperature Calculations Example If an explicit temperature reading in degrees Celsius is required, calculate for the single-measurement method as follows: Using VCC = 2.5 V as reference, 1. Calculate the scale factor of the ADC in degrees per LSB. Degrees per LSB = ADC LSB size/-2.1 mV = (VCC/4096)/-2.1 mV 2. 3. 4. Degrees per LSB = (2.5/4096)/-2.1 x 10-3 = -0.291 The ADC output is 983 decimal at 25C, equivalent to a diode forward voltage of 0.6 V. The ADC output at TAMB is 880. Save the ADC output, DCAL, at the calibration temperature, TCAL. Take the ADC reading, DAMB, at the temperature to be measured, TAMB. Calculate the difference in degrees between TCAL and TAMB by T = (DAMB - DCAL) x degrees per LSB 5. Add T to TCAL. Rev. C | Page 16 of 40 T = (880 - 983) x -0.291 = 30C TAMB = 25 + 30 = 55C AD7879/AD7889 MEDIAN AND AVERAGING FILTERS As explained in the Touch Screen Principles section, touch screens are composed of two resistive layers, normally placed over an LCD screen. Because these layers are in close proximity to the LCD screen, noise can be coupled from the screen onto these resistive layers, causing errors in the touch screen positional measurements. The AD7879/AD7889 contain a filtering block to process the data and discard the spurious noise before sending the information to the host. The purpose of this block is not only the suppression of noise; the on-chip filtering also greatly reduces the host processing loading. The processing function consists of two filters that are applied to the converted results: the median filter and the averaging filter. The median filter suppresses the isolated out-of-range noise and sets the number of measurements to be taken. These measurements are arranged in a temporary array, where the first value is the smallest measurement and the last value is the largest measurement. Bit 6 and Bit 5 in Control Register 2 (MED1, MED0) set the window of the median filter and, therefore, the number of measurements taken. Table 10. Median Averaging Filters (MAVF) Settings Setting M=A M>A M<A Example In this example, MED1, MED0 = 11 and AVG1, AVG0 = 10; the median filter has a window size of 16. This means that 16 measurements are taken and arranged in descending order in a temporary array. Number of Measurements Median filter disabled 4 8 16 The averaging filter size determines the number of values to average. Bit 8 and Bit 7 in Control Register 2 (AVG1, AVG0) set the average to 2, 4, 8, or 16 samples. Only the final averaged result is written into the result register. Table 9. Averaging Filter Size AVG1 0 0 1 1 AVG0 0 1 0 1 Function Median filter is disabled; output is the average of A converted results Output is the average of the middle A values from the array of M measurements Not possible because the median filter size is always larger than the averaging window size Filter Size Average of 2 middle samples Average of 4 middle samples Average of 8 middle samples Average of 16 samples 12-BIT SAR ADC MEDIAN FILTER AVERAGING FILTER CONVERTED RESULTS 16 MEASUREMENTS ARRANGED AVERAGE OF MIDDLE 8 VALUES 6 2 13 4 16 5 15 10 9 3 11 8 1 12 14 7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 M = 16 A=8 07667-027 MED0 0 1 0 1 The number specified with the MED1 and MED0 settings must be greater than or equal to the number specified with the AVG1 and AVG0 settings. If both settings specify the same number, the median filter is switched off. The averaging window size in this example is 8. The output is the average of the middle eight values of the 16 measurements taken with the median filter. Table 8. Median Filter Size MED1 0 0 1 1 When both filter values are 00, only one measurement is transferred to the register map. Figure 27. Median and Averaging Filter Example It takes approximately 2 s to sort the data in the rank filter (tSORT in Figure 34); tSORT adds to the update rate of the AD7879. Rev. C | Page 17 of 40 AD7879/AD7889 AUX/VBAT/GPIO PIN The AUX/VBAT/GPIO pin on the AD7879/AD7889 can be programmed as an auxiliary input to the ADC, as a battery monitoring input, or as a general-purpose digital input/output. To select the auxiliary measurement, set the ADC channel address to 011 (Bits[14:12] in Control Register 1, Address 0x01). To select a battery measurement, set the ADC channel address to 010. To select the GPIO function, set Bit 13 in Control Register 2 (Address 0x02) to 1. AUXILIARY INPUT The AD7879/AD7889 have an auxiliary analog input, AUX. When the auxiliary input function is selected, the signal on the AUX pin (AUX/VBAT/GPIO) is connected directly to the ADC input. This channel has a full-scale input range from 0 V to VCC. The ADC channel address for AUX is 011 (Bits[14:12] in Control Register 1, Address 0x01), and the result is stored in the AUX/VBAT result register (Address 0x0C). BATTERY INPUT The AD7879/AD7889 can monitor battery voltages from 0.5 V to 5 V when the BAT measurement is selected. Figure 28 shows a block diagram of a battery voltage monitored through the VBAT pin. The voltage to the VCC pin (VCC/REF) of the AD7879/AD7889 is maintained at the desired supply voltage via the dc-to-dc converter, and the input to the converter is monitored. This voltage on VBAT is divided by 4 internally, so that a 5 V battery voltage is presented to the ADC as 1.25 V. To conserve power, the divider circuit is on only during the sampling of a voltage on VBAT. Note that the possible maximum input is 5 V. The ADC channel address for VBAT is 010 (Bits[14:12] in Control Register 1, Address 0x01), and the result is stored in the AUX/VBAT result register (Address 0x0C). DC-TO-DC CONVERTER After a measurement from either AUX or VBAT is taken, it is compared with the high and low limits. The out-of-limit comparison sets a status bit in Control Register 3. Separate status bits for the high limit and the low limit indicate which limit was exceeded. The interrupt sources can be masked by clearing the corresponding enable bit in Control Register 3. GPIO The AD7879/AD7889 have one general-purpose logic input/ output pin, GPIO (AUX/VBAT/GPIO). To enable GPIO, set Bit 13 in Control Register 2 to 1. If this bit is set to 0, the AUX/VBAT function is active on the pin. If the GPIO is not enabled, the other GPIO configuration bits have no effect. The GPIO data bit is Bit 12 in Control Register 2. Direction (Bit 11, Control Register 2, Address 0x02) Bit 11 sets the direction of the GPIO pin (AUX/VBAT/GPIO). When GPIO DIR = 0, the pin is an output. Setting or clearing the GPIO data bit (Bit 12 in Control Register 2) outputs a value on the GPIO pin. Polarity (Bit 10, Control Register 2, Address 0x02) When GPIO POL = 0, the GPIO pin is active low. When GPIO POL = 1, the GPIO pin is active high. How this bit affects the GPIO operation also depends on the GPIO DIR bit. VCC 12k The AUX measurement and the battery measurement can be compared with high and low limits stored on chip. An out-of-limit result generates an alarm output at the INT pin (PENIRQ/INT/DAV) when the INT function is enabled. The high limit for both channels is stored in the AUX/VBAT high limit register (Address 0x04), and the low limit is stored in the AUX/VBAT low limit register (Address 0x05). When GPIO DIR = 1, the pin is an input. An input value on the GPIO pin sets or clears the GPIO data bit (Bit 12 in Control Register 2). GPIO data register bits are read-only when GPIO DIR = 1. BATTERY 0.5V TO 5V VBAT LIMIT COMPARISON SW 0.125V TO 1.25V ADC If GPIO POL = 1 and GPIO DIR = 1, a 1 at the input pin sets the corresponding GPIO data register bit to 1. A 0 at the input pin clears the corresponding GPIO data bit to 0. 07667-028 4k Figure 28. Block Diagram of Battery Measurement Circuit The maximum battery voltage that the AD7879/AD7889 can measure changes when a different reference voltage is used. The maximum voltage that is measurable is VCC x 4 because this voltage gives a full-scale output from the ADC. The battery voltage can be calculated using the following formula: VBAT (V) = [(Register Value) x VCC x 4]/4095 If GPIO POL = 1 and GPIO DIR = 0, a 1 in the GPIO data register bit puts a 1 on the corresponding GPIO output pin. A 0 in the GPIO data register bit puts a 0 on the GPIO output pin. If GPIO POL = 0 and GPIO DIR = 1, a 1 at the input pin sets the corresponding GPIO data bit to 0. A 0 at the input pin clears the corresponding GPIO data bit to 1. If GPIO POL = 0 and GPIO DIR = 0, a 1 in the GPIO data register bit puts a 0 on the corresponding GPIO output pin. A 0 in the GPIO data register bit puts a 1 on the GPIO output pin. Rev. C | Page 18 of 40 AD7879/AD7889 GPIO Interrupt Enable (Bit 12, Control Register 3, Address 0x03) The GPIO pin can operate as an interrupt source to trigger the INT output. This is controlled by Bit 12 in Control Register 3. INT is asserted if the GPIO data register bit is set when the GPIO is configured as an input, provided that INT is enabled. INT is triggered only when the GPIO is configured as an input, that is, when GPIO DIR = 1. If the GPIO ALERT interrupt enable bit is set to 0, the GPIO can trigger INT. If this bit is set to 1, the GPIO cannot trigger INT. INT is cleared only when the GPIO signal or the GPIO enable bit changes. Rev. C | Page 19 of 40 AD7879/AD7889 CONVERSION TIMING Conversion timing or update rate is the rate at which the AD7879 provides converted values from the ADC so that the XY positions in the touch screen can be updated. In other words, the update rate is the timing required to give valid measurements in the sequencer. Conversion time per channel depends on the number of samples to be converted. The number of samples is programmed using the following median filter settings: TCHANNEL = TMEASURE x MED TCHANNEL_MIN =9.5 s (ACQ = 2 s, MED = 0) Figure 29 shows conversion timing for a conversion sequence. X+ Y+ Z1 VBAT/AUX Z2 TCHANNEL_MAX = 376 s (ACQ = 16 s, MED = 16) TEMP Update Rate = [FCD + (TMEASURE x MED)] x N + FCD + TMR xM xM xM xM xM 07667-046 F F F F F C TMEASURE C TMEASURE C TMEASURE C TMEASURE TMEASURE TMEASURE C D D D D D xM where: N = number of channels to be measured (1 to 6). MED = median filter setting (1, 4, 8, 16). Figure 29. Conversion Timing Sequence FCD is required before each touch screen measurement (X+, Y+, Z1, and Z2). This time is required to allow the screen inputs to settle before converting. If the sequence does not contain any screen channel (VBAT, AUX, or TEMP), only one FCD is added at start of the sequence. At the end of the sequence, there is always another FCD. TMEASURE is the time required to perform one measurement in the conversion sequence. TMR = timer setting (0 s to 9.4 ms). The total update rate depends on the median filter settings and the number of channels in the conversion sequence. The timer setting (TMR) allows the user more flexibility to program the update rate. For example, if ACQ = 4 us TMEASURE = [ACQ (2 s, 4 s, 8 s, 16 s) + TCONV (7.5 s) + TSORT (2 s)] MED = 8 where: ACQ is the acquisition time which is programmable in Control Register 1. For temperature measurements, ACQ is fixed at 16 s. TCONV (typical ADC conversion time) is specified at 7.5 s. TSORT is the time needed to sort the new sample within the median filter array. The TSORT value is approximately 2 s. If a median filter is not used (MED =0), the TSORT value is 0. FCD = 1.024 ms TMEASURE_MIN = 9.5 s (ACQ = 2 s, no median filter) N=2 TMR = 620 s TMEASURE = 4 + 7.5 + 2 = 13.5 s TCHANNEL = (13.5 x 8) = 108 s Then Update rate = [1024 + 108] x 2 + 1024 + 620 = 3.9 ms Rev. C | Page 20 of 40 AD7879/AD7889 REGISTER MAP Table 11. Register Table Address1 0x00 0x01 Register Name Unused Control Register 1 0x02 Control Register 2 0x03 Control Register 3 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E AUX/VBAT high limit AUX/VBAT low limit TEMP high limit TEMP low limit X+ Y+ X+ (Z1) Y- (Z2) AUX/VBAT TEMP Revision and device ID 1 Description Unused Pen interrupt enable, channel selection for manual conversion, ADC mode, acquisition time, and conversion timer ADC power management, GPIO control, pen interrupt mode, averaging, median filter, software reset, and FCD Status of high/low limit comparisons for TEMP and AUX/VBAT, and enable bits to allow them to become interrupts; channel selection for slave/master mode AUX/VBAT high limit for comparison AUX/VBAT low limit for comparison TEMP high limit for comparison TEMP low limit for comparison X+ measurement for Y position Y+ measurement for X position X+ measurement for touch-pressure calculation (Z1) Y- measurement for touch-pressure calculation (Z2) AUX/VBAT voltage measurement Temperature conversion measurement Revision and device ID Do not write to addresses outside the register map. Rev. C | Page 21 of 40 Default Value 0x0000 0x0000 Type R/W R/W 0x4040 R/W 0x0000 R/W 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0379 (AD7879-1/AD7889-1) 0x037A (AD7879/AD7889) R/W R/W R/W R/W R R R R R R R R AD7879/AD7889 DETAILED REGISTER DESCRIPTIONS All addresses and default values are expressed in hexadecimal. Table 12. Control Register 1 Address 0x01 Bit Name Disable PENIRQ Data Bit 15 Description Pen interrupt enable. 0 = PENIRQ is enabled. Default Value 0x0000 1 = PENIRQ is disabled and INT is enabled. 1 2 CHNL ADD[2:0] [14:12] ADC MODE[1:0] [11:10] ACQ[1:0] [9:8] TMR[7:0] [7:0] ADC channel address for manual conversion (ADC mode = 01). 111 = X+ input (Y position). 110 = Y+ input (X position). 101 = X+ (Z1) input for touch-pressure calculation. 100 = Y- (Z2) input (used for touch-pressure measurement). 011 = AUX input.1 010 = VBAT input.1 001 = temperature measurement. 000 = not applicable. ADC mode. 00 = no conversion. 01 = single conversion.2 10 = conversion sequence (slave mode).2 11 = conversion sequence (master mode). ADC acquisition time. 00 = 4 clock periods (2 s). 01 = 8 clock periods (4 s). 10 = 16 clock periods (8 s). 11 = 32 clock periods (16 s). Note that the acquisition time does not apply to the temperature sensor channels; the temperature channel has a constant settling time of 16 s. Conversion interval timer. Starts at 550 s (00000001) and continues to 9.440 ms (11111111) in steps of 35 s (see Table 18). Note that, in slave mode, the conversion interval timer starts to count as soon as the conversion sequence is finished; in master mode, it starts to count again only if the screen remains touched. If the screen is released, the timer stops counting and, on the next screen touch, a conversion starts immediately. If GPIO is enabled in Control Register 2 (Bit 13), AUX and VBAT are both ignored. If AUX and VBAT are both selected in Control Register 3 and GPIO is disabled, AUX is ignored and VBAT is measured. Note that these bits are cleared to 00 at the end of the conversion sequence if the conversion interval timer bits in Control Register 1 (Address 0x01) Bits[7:0] = 0x00 at the end of the conversion sequence. Rev. C | Page 22 of 40 AD7879/AD7889 Table 13. Control Register 2 Address 0x02 1 Bit Name PM[1:0] Data Bit [15:14] GPIO EN 13 GPIO DAT GPIO DIR 12 11 GPIO POL 10 SER/DFR 9 AVG[1:0] [8:7] MED[1:0] [6:5] SW/RST FCD[3:0] 4 [3:0] Description ADC power management. 00 = full shutdown; the ADC, oscillator, bias, and temperature sensor are all powered down. 01 = analog blocks to be powered down depend on the ADC mode. If ADC mode is master mode, the ADC, oscillator, bias, and temperature sensor are powered down and must wake up when the user touches the screen. If ADC mode is slave mode, the ADC and temperature sensor are powered down when not being used. They wake up automatically when required. The oscillator and bias are powered up because they are needed to measure time. This also applies to the single-conversion mode. 10 = ADC, bias, and oscillator are powered up continuously, irrespective of ADC mode. 11 = same as 01. GPIO enable. 0 = AUX/VBAT channel active. 1 = GPIO enabled on AUX/VBAT/GPIO pin. GPIO data bit. GPIO direction. 0 = output. 1 = input. GPIO polarity. 0 = GPIO pin is active low. 1 = GPIO pin is active high. Selects normal (single-ended) or ratiometric (differential) conversion. 0 = ratiometric (differential). 1 = normal (single-ended). ADC averaging. Default Value 0x4040 00 = 2 middle values averaged (one measurement when median filter is disabled). 01 = 4 middle values averaged. 10 = 8 middle values averaged. 11 = 16 values averaged. Median filter size. 00 = median filter disabled. 01 = 4 measurements. 10 = 8 measurements. 11 = 16 measurements. Software reset; digital logic is reset when this bit is set. ADC first conversion delay.1 Starts at 128 s (default) and continues to 4.096 ms in steps of 128 s (see Table 22). This delay occurs before conversion of the X and Y coordinate channels (including Z1 and Z2) to allow for screen settling and before the first conversion to allow the ADC to power up. Rev. C | Page 23 of 40 AD7879/AD7889 Table 14. Control Register 3 Address 0x03 Bit Name TEMP MASK Data Bit 15 AUX/VBAT MASK 14 INT MODE 13 Description TEMP mask bit. 0 = temperature measurement is allowed to cause interrupt. 1 = temperature measurement is not allowed to cause interrupt. AUX/VBAT mask bit. 0 = AUX/VBAT measurement is allowed to cause interrupt. 1 = AUX/VBAT measurement is not allowed to cause interrupt. DAV/INT mode select. Default Value 0x0000 0 = enable DAV mode. 1 = enable INT mode. GPIO ALERT 12 Note that this bit overrides any mask bits associated with individual channels. GPIO interrupt enable. 0 = GPIO can cause an alert on the INT output. 1 = mask GPIO from causing an alert on the INT output. AUX/VBAT LOW AUX/VBAT HIGH TEMP LOW TEMP HIGH X+ Y+ Z1 Z2 AUX VBAT TEMP Not used 1 11 10 9 8 7 6 5 4 3 2 1 0 1 = AUX/VBAT below low limit. 1 = AUX/VBAT above high limit. 1 = TEMP below low limit. 1 = TEMP above high limit. 1 = include measurement of Y position (X+ input). 1 = include measurement of X position (Y+ input). 1 = include Z1 touch-pressure measurement (X+ input). 1 = include measurement of Z2 touch-pressure measurement (Y- input). 1 = include measurement of AUX channel.1 1 = include measurement of battery monitor (VBAT).1 1 = include temperature measurement. Unused. If GPIO is enabled in Control Register 2 (Bit 13), AUX and VBAT are both ignored. If AUX and VBAT are both selected and GPIO is disabled, AUX is ignored and VBAT is measured. Table 15. Limit Registers Address 0x04 0x05 0x06 0x07 Register Name AUX/VBAT high limit AUX/VBAT low limit TEMP high limit TEMP low limit Data Bit [15:0] [15:0] [15:0] [15:0] Description User-programmable AUX/VBAT high limit register User-programmable AUX/VBAT low limit register User-programmable TEMP high limit register User-programmable TEMP low limit register Rev. C | Page 24 of 40 Default Value 0x0000 0x0000 0x0000 0x0000 AD7879/AD7889 Table 16. Measurement Result Registers (Read Only) Address 0x08 0x09 0x0A 0x0B 0x0C 0x0D Register Name X+ Y+ X+ (Z1) Y- (Z2) AUX/VBAT TEMP Data Bits [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Description Measured X+ input with Y excitation (Y position) Measured Y+ input with X excitation (X position) Measured X+ input with X - and Y+ excitation (touch-pressure calculation Z1) Measured Y - input with X- and Y+ excitation (touch-pressure calculation Z2) AUX/VBAT voltage measurement Temperature conversion measurement Default Value 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 Table 17. Revision and Device ID Register (Read Only) Address 0x0E Data Bits [15:12] [11:8] [7:0] Description Unused Revision and device ID bits Device ID Rev. C | Page 25 of 40 Default Value 0x0379 (AD7879-1/AD7889-1) 0x037A (AD7879/AD7889) AD7879/AD7889 CONTROL REGISTERS 0 DISABLE CHNL CHNL CHNL ADC ADC ACQ1 ACQ0 TMR7 TMR6 TMR5 TMR4 TMR3 TMR2 TMR1 TMR0 PENIRQ ADD2 ADD1 ADD0 MODE1 MODE0 07667-029 15 Figure 30. Control Register 1 CONTROL REGISTER 1 ADC Mode (Control Register 1, Bits[11:10]) Control Register 1 (Address 0x01) contains the ADC channel address and the ADC mode bits. It sets the acquisition time and the timer. It also contains a bit to disable the pen interrupt. Control Register 1 should always be the last register programmed prior to starting conversions. Its power-on default value is 0x0000. To change any parameter after conversion has begun, the part must first be put into ADC Mode 00. Make the changes, and then reprogram Control Register 1, ensuring that it is always the last register programmed before conversions begin. The mode bits select the operating mode of the ADC. The AD7879/AD7889 have three operating modes. These modes are selected by writing to the mode bits in Control Register 1. If the mode bits are set to 00, no conversion is performed. Timer (Control Register 1, Bits[7:0]) The TMR bits in Control Register 1 set the conversion interval timer, which enables the ADC to perform a conversion sequence at regular intervals from 550 s (00000001) up to 9.440 ms (11111111) in increments of 35 s (see Table 18). The default value of these bits is 00000000, which enables the ADC to perform one conversion only. In slave mode, the timer starts as soon as the conversion sequence is finished. In master mode, the timer starts at the end of a conversion sequence only if the screen remains touched. If the touch is released at any stage, the timer stops. The next time that the screen is touched, a conversion sequence begins immediately. Table 18. Timer Selection TMR[7:0] 00000000 00000001 00000010 00000011 ... 11111101 11111110 11111111 The ACQ bits in Control Register 1 allow the selection of acquisition times for the ADC of 2 s (default), 4 s, 8 s, or 16 s. The user can program the ADC with an acquisition time suitable for the type of signal being sampled. For example, signals with large RC time constants can require longer acquisition times. Table 19. Acquisition Time Selection ACQ0 0 1 0 1 Acquisition Time 4 clock periods (2 s) 8 clock periods (4 s) 16 clock periods (8 s) 32 clock periods (16 s) ADC MODE0 0 1 1 1 0 1 Function Do not convert (default) Single-channel conversion; the device is in slave mode Sequence 0; the device is in slave mode Sequence 1; the device is in master mode If the mode bits are set to 01, a single conversion is performed on the channel selected by writing to the channel bits of Control Register 1 (Bits[14:12]). At the end of the conversion, if the TMR bits in Control Register 1 are set to 00000000, the mode bits revert to 00 and the ADC returns to no convert mode until a new conversion is initiated by the host. Setting the TMR bits to a value other than 00000000 causes the conversion to be repeated. The AD7879/AD7889 can also be programmed to automatically convert a sequence of selected channels. The two modes for this type of conversion are slave mode and master mode. For slave mode operation, the channels to be digitized are selected by setting the corresponding bits in Control Register 3. Conversion is initiated by writing 10 to the mode bits of Control Register 1. The ADC then digitizes the selected channels and stores the results in the corresponding result registers. At the end of the conversion, if the TMR bits in Control Register 1 are set to 00000000, the mode bits revert to 00 and the ADC returns to no convert mode until a new conversion is initiated by the host. Setting the TMR bits to a value other than 00000000 causes the conversion sequence to be repeated. Conversion Interval Convert one time only (default) Every 550 s Every 585 s Every 620 s ... Every 9.370 ms Every 9.405 ms Every 9.440 ms Acquisition Time (Control Register 1, Bits[9:8]) ACQ1 0 0 1 1 Table 20. Mode Selection ADC MODE1 0 0 For master mode operation, the channels to be digitized are written to Control Register 3. Master mode is then selected by writing 11 to the mode bits in Control Register 1. In this mode, the wake-up on touch feature is active; therefore, conversion does not begin immediately. The AD7879/AD7889 wait until the screen is touched before beginning the sequence of conversions. The ADC then digitizes the selected channels, and the results are written to the result registers. Before beginning another sequence of conversions, the AD7879/AD7889 wait for the screen to be touched again or for a timer event if the screen remains touched. Rev. C | Page 26 of 40 AD7879/AD7889 ADC Channel (Control Register 1, Bits[14:12]) The ADC channel address is selected by Bits[14:12] of Control Register 1 (CHNL ADD2 to CHNL ADD0). A complete list of channel addresses is given in Table 21. For single-channel conversion, the channel address is selected by writing the appropriate code to the CHNL ADD2 to CHNL ADD0 bits in Control Register 1. For sequential channel conversion, the channels to be converted are selected by setting the bits corresponding to the channel number in Control Register 3 for slave and master mode sequencing. For both single-channel and sequential conversion, a normal conversion (single-ended) is selected by setting the SER/DFR bit in Control Register 2 (Bit 9). Ratiometric (differential) conversion is selected by clearing the SER/DFR bit. PENIRQ Enable (Control Register 1, Bit 15) The AD7879/AD7889 have a dual function output that performs as PENIRQ or INT depending on the pen interrupt enable bit (Bit 15 of Control Register 1). When this bit is set to 0, the pin functions as a pen interrupt and goes low whenever the screen is touched. When the pen interrupt enable bit is set to 1, the pen interrupt request is disabled and the pin functions as an interrupt when a measurement exceeds a preprogrammed limit (INT). Table 21. Codes for Selecting Input Channel and Normal or Ratiometric Conversion Channel 0 1 2 3 4 5 6 7 8 9 12 13 14 15 SER/DFR 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 CHNL ADD[2:0] 111 110 101 100 011 010 001 000 111 110 101 100 011 010 001 000 Analog Input X+ (Y position) Y+ (X position) X+ (Z1 touch pressure) Y- (Z2 touch pressure) AUX VBAT TEMP X+ (Y position) Y+ (X position) X+ (Z1 touch pressure) Y- (Z2 touch pressure) AUX VBAT TEMP X Switches Y Switches Off On On Off X+ off, X- on Y+ on, Y- off X+ off, X- on Y+ on, Y- off Off Off Off Off Off Off Invalid address Off On On Off Off Off Off Off Off Off Off Off Off Off Invalid address Rev. C | Page 27 of 40 REF+ Y+ X+ Y+ Y+ VCC VCC VCC REF- Y- X- X- X- GND GND GND VCC VCC VCC VCC VCC VCC VCC GND GND GND GND GND GND GND AD7879/AD7889 PM1 0 PM0 GPIO EN GPIO DAT GPIO GPIO DIR POL SER/ DFR AVG1 AVG0 MED1 MED0 SW/ RST FCD3 FCD2 FCD1 FCD0 07667-030 15 Figure 31. Control Register 2 CONTROL REGISTER 2 Power Management (Control Register 2, Bits[15:14]) Control Register 2 (Address 0x02) contains the ADC power management bits, the GPIO settings, the SER/DFR bit (to choose the single-ended or differential method of touch screen measurement), the averaging and median filter settings, a bit that allows resetting of the part, and the first conversion delay bits. Its power-on default value is 0x4040. See the Detailed Register Descriptions section for more information about the control registers. For information about the averaging and median filter settings, see the Median and Averaging Filters section. For information about the GPIO settings, see the GPIO section. The power management (PM) bits in Control Register 2 allow the power management features of the ADC to be programmed (see Table 23). If the PM bits are set to 00, the ADC is in full shutdown. This setting overrides any setting of the mode bits in Control Register 1. Power management overrides the ADC modes. Table 23. Power Management Selection PM1 0 PM0 0 0 1 1 0 1 1 First Conversion Delay (Control Register 2, Bits[3:0]) The first conversion delay (FCD) bits in Control Register 2 program a delay from 128 s (default) up to 4.096 ms before the first conversion to allow the ADC time to power up. This delay also occurs before conversion of the X and Y coordinate channels to allow extra time for screen settling, and after the last conversion in a sequence to precharge PENIRQ. Table 22. First Conversion Delay Selection FCD[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Delay 128 s 256 s 384 s 512 s 640 s 768 s 896 s 1.024 ms 1.152 ms 1.280 ms 1.536 ms 1.792 ms 2.048 ms 2.560 ms 3.584 ms 4.096 ms Rev. C | Page 28 of 40 Function Full shutdown; ADC, oscillator, bias, and temperature sensor are turned off. The only way to exit this mode is to write to the part over the serial interface and change the PM bits. This setting overrides any other setting on the part, including the ADC mode bits. The analog blocks to be powered down depend on the ADC mode setting. In master mode, the ADC, bias, temperature sensor, and oscillator are powered down and must wake up when the user touches the screen. In slave mode, the ADC and temperature sensor are powered down when not being used. They wake up automatically when required. The oscillator and bias are powered up because they are needed to measure time. This setting also applies to the single-conversion mode. The ADC, bias, and oscillator are powered up continuously, irrespective of ADC mode. Same as 01. AD7879/AD7889 0 AUX/ AUX/ AUX/ TEMP TEMP TEMP INT GPIO VBAT VBAT VBAT MASK LOW HIGH MODE ALERT MASK LOW HIGH X+ Y+ Z1 Z2 NOT VBAT TEMP USED AUX 07667-031 15 Figure 32. Control Register 3 CONTROL REGISTER 3 Control Register 3 (Address 0x03) includes the interrupt register (Bits[15:8]) and the sequencer bits (Bits[7:0]). START OF CONVERSION SEQUENCE Sequencer (Control Register 3, Bits[7:0]) SET CHANNEL YES The sequencer bits control which channels are converted during a conversion sequence in both slave mode and master mode. NO FCD To include a measurement in a sequence, the relevant bit must be set in the sequence. Setting Bit 7 includes a measurement on the X+ channel (Y position). Setting Bit 6 includes a measurement on the Y+ channel (X position), and so on (see Table 14). WAIT FOR ACQUISITION ACQ CONVERT DATA Figure 32 illustrates the correspondence between the bits in Control Register 3 and the various measurements. Bit 0 is not used. YES RANK NEW DATA (WAIT tSORT) YES NO 11 10 SLAVE MODE CONVERSION SEQUENCE YES MEDIAN # OF SAMPLES TAKEN? 1 MASTER MODE TRANSFER DATA TO REGISTERS AVERAGE DATA WAIT FOR FIRST TOUCH SET ALERT AND INTERRUPT CONVERSION SEQUENCE YES TIMER = 00? OUT-OFLIMIT? NO NO SCREEN TOUCHED? START TIMER END OF SEQUENCE ? NO YES YES 1MEDIAN # MEANS MEDIAN WAIT FOR TIMER TIMER = 00? YES FILTER SIZE. Figure 34. Conversion Sequence NO START TIMER WAIT FOR TIMER YES NO 07667-032 SCREEN TOUCHED? FCD Figure 33. Conversion Modes Rev. C | Page 29 of 40 NO 07667-033 SINGLE CONVERSION MAV FILTER ENABLED ? NO 00 IDLE ADC MODE? 01 FCD REQ'D? AD7879/AD7889 INTERRUPTS PENIRQ--Pen Interrupt The AD7879/AD7889 have a dual function interrupt output, INT, as well as a pen-down interrupt, PENIRQ. The INT output can be configured as a data available interrupt (DAV), as an out-of-limit interrupt (INT), or as a GPIO interrupt. The pen interrupt request output (PENIRQ) goes low whenever the screen is touched and the PENIRQ enable bit is set to 0 (Control Register 1, Bit 15). When PENIRQ enable is set to 1, the pen interrupt request output is disabled. DAV--Data Available Interrupt The pen interrupt equivalent output circuitry is shown in Figure 36. This digital logic output has an internal 50 k pullup resistor, so it does not need an external pull-up. The PENIRQ output idles high, and the PENIRQ circuitry is always enabled in master mode (ADC mode = 11), except during conversions. The behavior of the interrupt output is controlled by Bit 13 in Control Register 3. In default mode (Bit 13 = 0), INT operates as a data available interrupt (DAV). When the AD7879/AD7889 finish a conversion or a conversion sequence, the interrupt is asserted to let the host know that new ADC data is available in the result registers. X- TOUCH SCREEN Y- Figure 36. PENIRQ Output Equivalent Circuit NEW DATA HOST READS AVAILABLE RESULTS IDLE When the screen is touched, PENIRQ goes low. This generates an interrupt request to the host. When the screen touch ends, PENIRQ immediately goes high if the ADC is idle. If the ADC is converting, PENIRQ goes high when the ADC becomes idle. The PENIRQ operation for these two conditions is shown in Figure 37. NOT SCREEN TOUCHED Figure 35. Operation of DAV Output When the on-board timer is programmed to perform automatic conversions, limited time is available to the host to read the result registers before another sequence of conversions begins. The DAV signal is reset high when the timer expires, and the host should not access the result registers while DAV is high. PENIRQ DETECTS TOUCH PENIRQ ADC STATUS The INT pin operates as an alarm or interrupt output when Bit 13 in Control Register 3 (Address 0x03) is set to 1. The output goes low if any one of the interrupt sources is asserted. The results of high and low limit comparisons on the AUX, VBAT, and TEMP channels are interrupt sources. An out-oflimit comparison sets a status bit in the interrupt register. A separate status bit for the high limit and the low limit on each channel indicates which limit was exceeded. The interrupt sources can be masked by setting the corresponding enable bit in this register to 1. There is one enable bit per channel. Rev. C | Page 30 of 40 TOUCHED RELEASE NOT DETECTED PENIRQ DETECTS TOUCH PENIRQ ADC STATUS PENIRQ DETECTS RELEASE ADC IDLE NOT SCREEN TOUCHED INT--Out-of-Limit Interrupt NOT TOUCHED TOUCHED ADC IDLE NOT TOUCHED PENIRQ DETECTS RELEASE ADC CONVERTING ADC IDLE Figure 37. PENIRQ Operation for ADC Idle and ADC Converting 07667-036 ADC CONVERTING 07667-035 PENIRQ ENABLE 07667-034 STATUS IDLE tCONV PENIRQ X+ DAV SETUP BY HOST VCC VCC 50k While the ADC is idle or is converting, DAV is high. When the ADC has finished converting and new data has been written to the result registers, DAV goes low. Reading the result registers resets DAV to a high condition. DAV is also reset if a new conversion is started by the AD7879/AD7889 because the timer expired. The host should read the result registers only when DAV is low. To ensure correct operation of the DAV mode when using the SPI interface, it is necessary to write 0x0000 to Register 0x81 after a set of register reads. This clears the internal data read signal. AD7879/ AD7889 Y+ AD7879/AD7889 SYNCHRONIZING THE AD7879/AD7889 TO THE HOST CPU and enable INT or DAV using Bit 15 in Control Register 1 and Bit 13 in Control Register 3. The host can then enter sleep mode to conserve power. The wake-up on touch feature of the AD7879/AD7889 is active in this mode; therefore, when the screen is touched, the programmed sequence of conversions automatically begins. When the INT or DAV signal is asserted, the host reads the new data available in the AD7879/AD7889 result registers and returns to sleep mode. This method can significantly reduce the load on the host. The two methods for synchronizing the AD7879/AD7889 to its host CPU are slave mode (in which the mode bits are set to 01 or 10) and master mode (in which the mode bits set to 11). In master mode (ADC mode bits = 11), PENIRQ can be used as an interrupt to the host. When PENIRQ goes low to indicate that the screen has been touched, the host is awakened. The host can then program the AD7879/AD7889 to convert in any mode and read the results after the conversions are completed. Figure 38 shows how the PENIRQ circuit is enabled. The wake-up on touch circuit and the PENIRQ circuit are enabled only in master mode (ADC mode = 11). In slave mode, the PENIRQ/INT/DAV pin can output only INT or DAV signals. In master mode, INT or DAV can also be used as an interrupt to the host. The host should first define a conversion sequence in Control Register 3, initialize the AD7879/AD7889 in Mode 11, ENABLE PENIRQ DETECTION CIRCUIT ADC MODE = 11? MASTER MODE YES TOUCH SCREEN TOUCHED DAV (END OF CONVERSION SEQUENCE) INT (GPIO ALERT/OUT OF LIMITS) ENABLE WAKE-UP ON TOUCH TOUCH SCREEN TOUCHED 0 TO THE DIGITAL CORE 0 PENIRQ/INT/DAV PIN INT/DAV/GPIO ALERT 1 1 CONTROL REGISTER 1 BIT 15 CONTROL REGISTER 3 BIT 13 Figure 38. Master Mode Operation Rev. C | Page 31 of 40 07667-037 YES AD7879/AD7889 SERIAL INTERFACE The AD7879 and AD7879-1 (and the AD7889 and AD7889-1) differ only in the serial interface provided on the part. The AD7879 and the AD7889 are available with a serial peripheral interface (SPI). The AD7879-1 and the AD7889-1 are available with an I2C-compatible interface. It is recommended that addresses outside the register map not be written to. Bits[15:11] of the command word must be set to 11100 to successfully begin a bus transaction. Bit 10 is the read/write bit; 1 indicates a read, and 0 indicates a write. Bits[9:0] contain the target register address. When reading or writing to more than one register, this address indicates the address of the first register to be written to or read from. SPI INTERFACE The AD7879/AD7889 have a 4-wire SPI. The SPI has a data input pin (DIN) for inputting data to the device, a data output pin (DOUT) for reading data back from the device, and a data clock pin (SCL) for clocking data into and out of the device. A chip select pin (CS) enables or disables the serial interface. CS is required for correct operation of the SPI interface. Data is clocked out of the AD7879/AD7889 on the falling edge of SCL, and data is clocked into the device on the rising edge of SCL. Writing Data SPI Command Word Data is written to the AD7879/AD7889 in 16-bit words. The first word written to the device is the command word, with the read/write bit set to 0. The master then supplies the 16-bit input data-word on the DIN line. The AD7879/AD7889 clock the data into the register addressed in the command word. If there is more than one word of data to be clocked in, the AD7879/ AD7889 automatically increment the address pointer and clock the next data-word into the following register. All data transactions on the SPI bus begin with the master taking CS from high to low and sending out the command word. This indicates to the AD7879/AD7889 whether the transaction is a read or a write and gives the address of the register from which to begin the data transfer. The bit map in Table 24 shows the SPI command word. The AD7879/AD7889 continue to clock in data on the DIN line until the master ends the write transition by pulling CS high or until the address pointer reaches its maximum value. The AD7879/ AD7889 address pointer does not wrap. When the address pointer reaches its maximum value, any data provided by the master on the DIN line is ignored by the AD7879/AD7889. Table 24. SPI Command Word LSB 14 1 13 1 12 0 11 0 10 R/W [9:0] Register address 16-BIT COMMAND WORD ENABLE WORD DIN CW 15 CW 14 CW 13 CW 12 R/W CW 11 t2 SCL CW 10 CW 8 t4 1 t1 2 3 4 5 16-BIT DATA REGISTER ADDRESS CW 9 CW 7 CW 6 CW 5 CW 4 CW 3 CW 2 CW 1 CW 0 D15 D14 D13 D2 D1 D0 t5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 30 31 32 t8 t3 CS NOTES 1. DATA BITS ARE LATCHED ON SCL RISING EDGES. SCL CAN IDLE HIGH OR LOW BETWEEN WRITE OPERATIONS. 2. ALL 32 BITS MUST BE WRITTEN: 16 BITS FOR THE COMMAND WORD AND 16 BITS FOR DATA. 3. 16-BIT COMMAND WORD SETTINGS FOR SINGLE WRITE OPERATION: CW[15:11] = 11100 (ENABLE WORD) CW[10] = 0 (R/W) CW[9:0] = [AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (10-BIT MSB JUSTIFIED REGISTER ADDRESS) Figure 39. Single Register Write, SPI Timing Rev. C | Page 32 of 40 07667-038 MSB 15 1 AD7879/AD7889 16-BIT COMMAND WORD R/W ENABLE WORD DIN SCL CW 15 CW 14 1 2 CW 13 CW 12 CW 11 4 5 3 CW 10 DATA FOR STARTING REGISTER ADDRESS STARTING REGISTER ADDRESS CW 9 6 CW 8 7 CW 7 8 CW 6 9 CW 5 CW 4 11 10 CW 3 12 CW 2 13 CW 1 14 CW 0 15 D15 16 D14 17 DATA FOR NEXT REGISTER ADDRESS D1 18 D0 31 32 D15 33 D1 D14 34 47 D0 D15 48 49 CS 07667-039 NOTES 1. MULTIPLE SEQUENTIAL REGISTERS CAN BE LOADED CONTINUOUSLY. 2. THE FIRST (LOWEST ADDRESS) REGISTER ADDRESS IS WRITTEN, FOLLOWED BY MULTIPLE 16-BIT DATA-WORDS. 3. THE ADDRESS AUTOMATICALLY INCREMENTS WITH EACH 16-BIT DATA-WORD (ALL 16 BITS MUST BE WRITTEN). 4. CS IS HELD LOW UNTIL THE LAST DESIRED REGISTER HAS BEEN LOADED. 5. 16-BIT COMMAND WORD SETTINGS FOR SEQUENTIAL WRITE OPERATION: CW[15:11] = 11100 (ENABLE WORD) CW[10] = 0 (R/W) CW[9:0] = [AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (STARTING MSB JUSTIFIED REGISTER ADDRESS) Figure 40. Sequential Register Write, SPI Timing 16-BIT COMMAND WORD ENABLE WORD DIN CW 15 CW 14 CW 13 CW 12 R/W CW 11 REGISTER ADDRESS CW 9 CW 8 t4 t2 SCL CW 10 1 2 t1 3 4 5 CW 7 CW 6 CW 5 CW 4 CW 3 CW 2 CW 1 CW 0 X X X X X X t5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 30 31 32 t8 t3 CS t6 DOUT XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX D15 D14 t7 D13 D2 D1 D0 XXX 16-BIT READBACK DATA 07667-040 NOTES 1. DATA BITS ARE LATCHED ON SCL RISING EDGES. SCL CAN IDLE HIGH OR LOW BETWEEN WRITE OPERATIONS. 2. THE 16-BIT COMMAND WORD MUST BE WRITTEN ON DIN: 5 BITS FOR ENABLE WORD, 1 BIT FOR R/W, AND 10 BITS FOR REGISTER ADDRESS. 3. THE REGISTER DATA IS READ BACK ON THE DOUT PIN. 4. X DENOTES DON'T CARE. 5. XXX DENOTES HIGH IMPEDANCE THREE-STATE OUTPUT. 6. CS IS HELD LOW UNTIL ALL REGISTER BITS HAVE BEEN READ BACK. 7. 16-BIT COMMAND WORD SETTINGS FOR SINGLE READBACK OPERATION: CW[15:11] = 11100 (ENABLE WORD) CW[10] = 1 (R/W) CW[9:0] = [AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (10-BIT MSB JUSTIFIED REGISTER ADDRESS) Figure 41. Single Register Readback, SPI Timing Reading Data A read transaction begins when the master writes the command word to the AD7879/AD7889 with the read/write bit set to 1. The master then supplies 16 clock pulses per data-word to be read, and the AD7879/AD7889 clock out data from the addressed register on the DOUT line. The first data-word is clocked out on the first falling edge of SCL following the command word, as shown in Figure 41. The AD7879/AD7889 continue to clock out data on the DOUT line provided that the master continues to supply the clock signal on SCL. The read transaction ends when the master takes CS high. If the AD7879/AD7889 address pointer reaches its maximum value, the AD7879/AD7889 repeatedly clock out data from the addressed register. The address pointer does not wrap. Rev. C | Page 33 of 40 AD7879/AD7889 16-BIT COMMAND WORD ENABLE WORD R/W STARTING REGISTER ADDRESS DIN CW 15 CW 14 CW 13 CW 12 CW 11 CW 10 CW 9 CW 8 CW 7 SCL 1 2 3 4 5 6 7 8 9 CW 6 10 CW 5 11 CW 4 CW 3 12 13 CW 2 14 CW 1 15 CW 0 X X 16 17 18 XXX XXX XXX D15 D14 X X 31 32 X 33 X 34 X 47 X 48 X 49 CS XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX D1 D0 READBACK DATA FOR STARTING REGISTER ADDRESS D15 D14 D1 D0 D15 READBACK DATA FOR NEXT REGISTER ADDRESS NOTES 1. MULTIPLE SEQUENTIAL REGISTERS CAN BE READ BACK CONTINUOUSLY. 2. THE 16-BIT COMMAND WORD MUST BE WRITTEN ON DIN: 5 BITS FOR ENABLE WORD, 1 BIT FOR R/W, AND 10 BITS FOR REGISTER ADDRESS. 3. THE ADDRESS AUTOMATICALLY INCREMENTS WITH EACH 16-BIT DATA-WORD BEING READ BACK ON THE DOUT PIN. 4. CS IS HELD LOW UNTIL ALL REGISTER BITS HAVE BEEN READ BACK. 5. X DENOTES DON'T CARE. 6. XXX DENOTES HIGH IMPEDANCE THREE-STATE OUTPUT. 7. 16-BIT COMMAND WORD SETTINGS FOR SEQUENTIAL READBACK OPERATION: CW[15:11] = 11100 (ENABLE WORD) CW[10] = 1 (R/W) CW[9:0] = [AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (STARTING MSB JUSTIFIED REGISTER ADDRESS) 07667-041 DOUT Figure 42. Sequential Register Readback, SPI Timing I2C-COMPATIBLE INTERFACE The AD7879-1/AD7889-1 support the industry standard 2-wire I2C serial interface protocol. The two wires associated with the I2C timing are the SCL and SDA inputs. SDA is an I/O pin that allows both register write and register readback operations. The AD7879-1/AD7889-1 are always slave devices on the I2C serial interface bus. The devices have a 7-bit device address, Address 0101 1XX. The lower two bits are set by tying the ADD0 and ADD1 pins high or low. The AD7879-1/AD7889-1 respond when the master device sends its device address over the bus. The AD7879-1/AD7889-1 cannot initiate data transfers on the bus. Table 25. I2C Device Addresses for the AD7879-1/AD7889-1 ADD1 0 0 1 1 ADD0 0 1 0 1 I2C Address 0101 100 0101 101 0101 110 0101 111 Data Transfer Data is transferred over the I2C serial interface in 8-bit bytes. The master initiates a data transfer by establishing a start condition, defined as a high-to-low transition on the serial data line, SDA, while the serial clock line, SCL, remains high. This indicates that an address/data stream follows. All slave peripherals connected to the serial bus respond to the start condition and shift in the next eight bits, consisting of a 7-bit address (MSB first) plus a R/W bit that determines the direction of the data transfer. The peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the ninth clock pulse. This is known as the acknowledge bit. All other devices on the bus then remain idle while the selected device waits for data to be read from or written to it. If the R/W bit is a 0, the master writes to the slave device. If the R/W bit is a 1, the master reads from the slave device. Data is sent over the serial bus in a sequence of nine clock pulses (eight bits of data followed by an acknowledge bit from the slave device). Transitions on the data line must occur during the low period of the clock signal and remain stable during the high period because a low-to-high transition when the clock is high can be interpreted as a stop signal. The number of data bytes transmitted over the serial bus in a single read or write operation is limited only by what the master and slave devices can handle. When all data bytes are read or written, a stop condition is established. A stop condition is defined by a low-to-high transition on SDA while SCL remains high. If the AD7879-1/ AD7889-1 encounter a stop condition, they return to the idle condition. Rev. C | Page 34 of 40 AD7879/AD7889 START AD7879-1/AD7889-1 DEVICE ADDRESS REGISTER ADDRESS[A7:A0] SDA DEV A6 DEV A5 DEV A4 1 2 3 DEV DEV DEV A3 A2 A1 t1 DEV A0 R/W ACK 7 8 9 A7 A6 A1 A0 t3 SCL 4 5 6 10 11 16 17 t2 STOP ACK D15 D14 D9 REGISTER DATA[D7:D0] D8 ACK D7 t4 18 19 20 25 26 D1 D6 D0 28 DEV A6 t6 29 34 AD7879-1/AD7889-1 DEVICE ADDRESS ACK t5 27 START t8 35 36 DEV A5 DEV A4 t7 37 1 2 NOTES 1. A START CONDITION AT THE BEGINNING IS DEFINED AS A HIGH-TO-LOW TRANSITION ON SDA WHILE SCL REMAINS HIGH. 2. A STOP CONDITION AT THE END IS DEFINED AS A LOW-TO-HIGH TRANSITION ON SDA WHILE SCL REMAINS HIGH. 3. 7-BIT DEVICE ADDRESS [DEV A6:DEV A0] = [01011XX], WHERE THE Xs ARE DON'T CARE BITS. 4. REGISTER DATA [D15:D8] AND REGISTER DATA [D7:D0] ARE ALWAYS SEPARATED BY A LOW ACK BIT. 3 07667-042 REGISTER DATA[D15:D8] Figure 43. Example of I2C Timing for Single Register Write Operation Writing Data over the I2C Bus The process of writing to the AD7879-1/AD7889-1 over the I C bus is shown in Figure 43 and Figure 45. The device address is sent over the bus followed by the R/W bit set to 0. This is followed by one byte of data that contains the 8-bit address of the internal data register to be written. The bit map in Table 26 shows the register address byte. 2 6 LSB Bit 7 Bit 6 5 4 3 2 Register Address Bit 5 Bit 4 Bit 3 Bit 2 To end the transaction, the master generates a stop condition on SDA, or it generates a repeat start condition if the master is to maintain control of the bus. Reading Data over the I2C Bus Table 26. I2C Register Address Byte MSB 7 All registers on the AD7879-1/AD7889-1 have 16 bits. Two consecutive 8-bit data bytes are combined and written to the 16-bit registers. To avoid errors, all writes to the device must contain an even number of data bytes. 1 0 Bit 1 Bit 0 The third data byte contains the eight MSBs of the data to be written to the internal register. The fourth data byte contains the eight LSBs of data to be written to the internal register. The AD7879-1/AD7889-1 address pointer register automatically increments after each write. This allows the master to sequentially write to all registers on the AD7879-1/AD7889-1 in the same write transaction. However, the address pointer register does not wrap after the last address. Any data written to the AD7879-1/AD7889-1 after the address pointer has reached its maximum value is discarded. To read from the AD7879-1/AD7889-1, the address pointer register must first be set to the address of the required internal register. The master performs a write transaction and writes to the AD7879-1/AD7889-1 to set the address pointer. The master then outputs a repeat start condition to keep control of the bus or, if this is not possible, the master ends the write transaction with a stop condition. A read transaction is initiated, with the R/W bit set to 1. The AD7879-1/AD7889-1 supply the upper eight bits of data from the addressed register in the first readback byte, followed by the lower eight bits in the next byte. This is shown in Figure 44 and Figure 45. Because the address pointer automatically increments after each read, the AD7879-1/AD7889-1 continue to output readback data until the master puts a no acknowledge and a stop condition on the bus. If the address pointer reaches its maximum value and the master continues to read from the part, the AD7879-1/ AD7889-1 repeatedly send data from the last register addressed. Rev. C | Page 35 of 40 AD7879/AD7889 START AD7879-1/AD7889-1 DEVICE ADDRESS REGISTER ADDRESS[A7:A0] SDA DEV A6 DEV A5 DEV DEV DEV A3 A2 A1 DEV A4 DEV A0 t1 R/W ACK A7 A1 A6 A0 ACK t3 SCL 1 2 3 5 4 6 7 9 8 10 11 17 16 18 t2 DEV A6 USING REPEATED START P AD7879-1/AD7889-1 DEVICE ADDRESS SR DEV A5 DEV A1 REGISTER DATA[D7:D0] DEV A0 ACK R/W D7 20 19 P 25 21 DEV A6 DEV A5 20 ACK 26 27 28 29 35 30 REGISTER DATA[D7:D0] DEV A1 DEV A0 25 21 37 36 R/W D7 ACK 26 D1 D6 DEV A6 DEV A5 DEV A4 1 2 3 t7 t6 P D0 ACK t5 t4 19 D0 t5 AD7879-1/AD7889-1 DEVICE ADDRESS S SEPARATE READ AND WRITE TRANSACTIONS D1 D6 t4 AD7879-1/AD7889-1 DEVICE ADDRESS t8 27 28 29 35 30 36 37 07667-043 NOTES 1. A START CONDITION AT THE BEGINNING IS DEFINED AS A HIGH-TO-LOW TRANSITION ON SDA WHILE SCL REMAINS HIGH. 2. A STOP CONDITION AT THE END IS DEFINED AS A LOW-TO-HIGH TRANSITION ON SDA WHILE SCL REMAINS HIGH. 3. THE MASTER GENERATES THE ACK AT THE END OF THE READBACK TO SIGNAL THAT IT DOES NOT WANT ADDITIONAL DATA. 4. 7-BIT DEVICE ADDRESS [DEV A6:DEV A0] = [01011XX], WHERE THE TWO LSB Xs ARE DON'T CARE BITS. 5. REGISTER DATA [D15:D8] AND REGISTER DATA [D7:D0] ARE ALWAYS SEPARATED BY A LOW ACK BIT. 6. THE R/W BIT IS SET TO 1 TO INDICATE A READBACK OPERATION. Figure 44. Example of I2C Timing for Single Register Readback Operation WRITE DATA LOW BYTE [7:0] ... WRITE DATA HIGH BYTE [15:8] WRITE DATA LOW BYTE [7:0] ACK WRITE DATA HIGH BYTE [15:8] ACK REGISTER ADDR [7:0] ACK 7-BIT DEVICE ADDRESS W ACK S ACK WRITE P READ DATA LOW BYTE [7:0] ... READ DATA HIGH BYTE [15:8] READ DATA LOW BYTE [7:0] ACK READ DATA HIGH BYTE [15:8] ACK 7-BIT DEVICE R ADDRESS ACK REGISTER ADDR [7:0] ACK 7-BIT DEVICE ADDRESS W ACK SR S ACK READ (USING REPEATED START) P OUTPUT FROM AD7879-1/AD7889-1 S = START BIT P = STOP BIT SR = REPEATED START BIT R = READ BIT READ DATA HIGH BYTE [15:8] READ DATA . LOW BYTE [7:0] READ DATA . . HIGH BYTE [15:8] W = WRITE BIT ACK = ACKNOWLEDGE BIT ACK = NO ACKNOWLEDGE BIT Figure 45. Example of Sequential I2C Write and Readback Operation Rev. C | Page 36 of 40 READ DATA LOW BYTE [7:0] ACK 7-BIT DEVICE R ADDRESS ACK S P 07667-044 OUTPUT FROM MASTER P ACK REGISTER ADDR [7:0] ACK 7-BIT DEVICE ADDRESS W ACK S ACK READ (WRITE TRANSACTION SETS UP REGISTER ADDRESS) AD7879/AD7889 GROUNDING AND LAYOUT of at least 0.25 mm between the thermal pad and the inner edges of the land pattern on the PCB. Thermal vias can be used on the PCB thermal pad to improve the thermal performance of the package. If vias are used, incorporate them into the thermal pad at a 1.2 mm pitch grid. The via diameter should be between 0.3 mm and 0.33 mm, and the via barrel should be plated with 1 oz. of copper to plug the via. For detailed information on grounding and layout considerations for the AD7879/AD7889, refer to the AN-577 Application Note, Layout and Grounding Recommendations for Touch Screen Digitizers. LEAD FRAME CHIP SCALE PACKAGES The lands on the lead frame chip scale package (CP-16-10) are rectangular. The printed circuit board (PCB) pad for these lands should be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. Center the land on the pad to maximize the solder joint size. Connect the PCB thermal pad to GND. WLCSP ASSEMBLY CONSIDERATIONS For detailed information on the WLCSP PCB assembly and reliability, see the AN-617 Application Note, MicroCSPTM Wafer Level Chip Scale Package. The bottom of the lead frame chip scale package has a central thermal pad. The thermal pad on the PCB should be at least as large as this exposed pad. To avoid shorting, provide a clearance VOLTAGE REGULATOR 0.1F NC X- Y- TOUCH SCREEN DOUT NC = NO CONNECT 5 6 7 SCLK 10 MISO 9 MOSI 8 Figure 46. Typical Application Circuit Rev. C | Page 37 of 40 07667-045 NC INT 11 SPI INTERFACE AD7879/ AD7889 12 SCL 4 NC NC GND 3 HOST CS PENIRQ/INT/DAV DIN 2 Y+ CS VCC/REF X+ 1 13 14 AUX/ VBAT/ GPIO 15 16 MAIN BATTERY 0.1F TO 10F (OPTIONAL) AD7879/AD7889 OUTLINE DIMENSIONS 0.65 0.59 0.53 1.67 1.61 1.55 0.17 0.15 0.13 SEATING PLANE 3 2 1 A BALL 1 IDENTIFIER 2.07 2.01 1.95 0.36 0.32 0.28 B 1.50 REF C D 0.10 MAX COPLANARITY 0.37 0.35 0.33 BOTTOM VIEW (BALL SIDE UP) 0.28 0.24 0.20 120808-A TOP VIEW (BALL SIDE DOWN) 0.50 REF Figure 47. 12-Ball Wafer Level Chip Scale Package [WLCSP] (CB-12-1) Dimensions shown in millimeters 0.650 0.595 0.540 1.555 1.505 1.455 0.040 MAX 0.020 MIN SEATING PLANE 3 2 1 A BALL 1 IDENTIFIER 2.055 2.005 1.955 0.340 0.320 0.300 B 1.50 REF C D 0.10 MAX COPLANARITY 0.380 0.355 0.330 BOTTOM VIEW (BALL SIDE UP) 1.00 REF 0.270 0.240 0.210 010410-A TOP VIEW (BALL SIDE DOWN) 0.50 REF Figure 48. 12-Ball, Backside-Coated Wafer Level Chip Scale Package [WLCSP] (CB-12-5) Dimensions shown in millimeters 4.00 BSC SQ 0.60 MAX 0.60 MAX 13 12 MAX 1.00 0.85 0.80 0.65 BSC TOP VIEW 12 0.50 0.40 0.30 0.80 MAX 0.65 TYP 0.35 0.30 0.25 2.50 2.35 SQ 2.20 EXPOSED PAD 3.75 BSC SQ (BOTTOM VIEW) 9 8 5 4 0.25 MIN 1.95 BSC 0.05 MAX 0.02 NOM SEATING PLANE PIN 1 INDICATOR 1 0.20 REF COPLANARITY 0.08 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VGGC Figure 49. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm x 4 mm, Very Thin Quad (CP-16-10) Dimensions shown in millimeters Rev. C | Page 38 of 40 082008-A PIN 1 INDICATOR 16 AD7879/AD7889 ORDERING GUIDE Model1 AD7879ACBZ-RL AD7879ACBZ-500R7 AD7879ACPZ-RL AD7879ACPZ-500R7 AD7879-1ACBZ-RL AD7879-1ACBZ-500R7 AD7879-1ACPZ-RL AD7879-1ACPZ-500R7 AD7889ACBZ-RL AD7889ACBZ-500R7 AD7889-1ACBZ-RL AD7889-1ACBZ-RL7 AD7889-1ACBZ-500R7 EVAL-AD7879EBZ EVAL-AD7879-1EBZ 1 Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C Serial Interface Description SPI Interface SPI Interface SPI Interface SPI Interface I2C Interface I2C Interface I2C Interface I2C Interface SPI Interface SPI Interface I2C Interface I2C Interface I2C Interface SPI Interface I2C Interface Package Description 12-Ball WLCSP 12-Ball WLCSP 16-Lead LFCSP_VQ 16-Lead LFCSP_VQ 12-Ball WLCSP 12-Ball WLCSP 16-Lead LFCSP_VQ 16-Lead LFCSP_VQ 12-Ball, Backside-Coated WLCSP 12-Ball, Backside-Coated WLCSP 12-Ball, Backside-Coated WLCSP 12-Ball, Backside-Coated WLCSP 12-Ball, Backside-Coated WLCSP Evaluation Board Evaluation Board Z = RoHS Compliant Part. Rev. C | Page 39 of 40 Package Option CB-12-1 CB-12-1 CP-16-10 CP-16-10 CB-12-1 CB-12-1 CP-16-10 CP-16-10 CB-12-5 CB-12-5 CB-12-5 CB-12-5 CB-12-5 Branding T2Y T2Y T0Q T0Q T3R T3R T3Q T3Q T3Q AD7879/AD7889 NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). (c)2008-2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07667-0-11/10(C) Rev. C | Page 40 of 40