Low Voltage Controller for Touch Screens
AD7879/AD7889
Rev. C
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FEATURES
4-wire touch screen interface
1.6 V to 3.6 V operation
Median and averaging filter to reduce noise
Automatic conversion sequencer and timer
User-programmable conversion parameters
Auxiliary analog input/battery monitor (0.5 V to 5 V)
1 optional GPIO
Interrupt outputs (INT, PENIRQ)
Touch-pressure measurement
Wake-up on touch function
Shutdown mode: 6 μA maximum
12-ball, 1.6 mm × 2 mm WLCSP
16-lead, 4 mm × 4 mm LFCSP
APPLICATIONS
Personal digital assistants
Smart handheld devices
Touch screen monitors
Point-of-sale terminals
Medical devices
Cell phones
FUNCTIONAL BLOCK DIAGRAM
REF+
X– Y– X+ Y+
FILTERING
RESULT
REGISTERS
CONTROL
REGISTERS
SEQUENCER
AND TI M E R
REF–
TEMPERATURE
SENSOR
TO
RESULT
REGISTERS
6-TO- 1 MUX
AD7879/
AD7879-1/
AD7889/
AD7889-1
V
CC
/
RE
F
X+
X–
Y+
Y–
GND
AUX/VBAT/GPIO
PENIRQ/INT/DAV
SERIAL PORT
DIN/
ADD1 DOUT/
SDA SCLCS/
ADD0
12-BIT
SAR ADC
REF–
07667-001
Figure 1.
GENERAL DESCRIPTION
The AD7879/AD7889 are 12-bit successive approximation
analog-to-digital converters (SAR ADCs) with a synchronous
serial interface and low on-resistance switches for driving 4-wire
resistive touch screens. The AD7879/AD7889 work with a very
low power supply—a single 1.6 V to 3.6 V supply—and feature
throughput rates of 105 kSPS. The devices include a shutdown
mode that reduces current consumption to less than 6 μA.
To reduce the effects of noise from LCDs and other sources, the
AD7879/AD7889 contain a preprocessing block. The prepro-
cessing function consists of a median filter and an averaging
filter. The combination of these two filters provides a more robust
solution, discarding the spurious noise in the signal and keeping
only the data of interest. The size of both filters is programmable.
Other user-programmable conversion controls include variable
acquisition time and first conversion delay; up to 16 averages
can be taken per conversion. The AD7879/AD7889 can run in
slave mode or standalone (master) mode, using an automatic
conversion sequencer and timer.
The AD7879/AD7889 have a programmable pin that can operate
as an auxiliary input to the ADC, as a battery monitor, or as a
GPIO. In addition, a programmable interrupt output can operate
in three modes: as a general-purpose interrupt to signal when
new data is available (DAV), as an interrupt to indicate when
limits are exceeded (INT), or as a pen-down interrupt when the
screen is touched (PENIRQ). The AD7879/AD7889 offer temp-
erature measurement and touch-pressure measurement.
The AD7879 is available in a 12-ball, 1.6 mm × 2 mm WLCSP
and in a 16-lead, 4 mm × 4 mm LFCSP. The AD7889 is available
in a backside-coated version of the WLCSP. Both parts support
an SPI interface (AD7879/AD7889) or an I2C interface
(AD7879-1/AD7889-1).
AD7879/AD7889
Rev. C | Page 2 of 40
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
SPI Timing Specifications (AD7879/AD7889)......................... 4
I2C Timing Specifications (AD7879-1/AD7889-1).................. 5
Absolute Maximum Ratings ............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution .................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ............................................. 9
Terminology .................................................................................... 12
Theory of Operation ...................................................................... 13
Touch Screen Principles ............................................................ 13
Measuring Touch Screen Inputs ............................................... 14
Touch-Pressure Measurement .................................................. 15
Temperature Measurement ....................................................... 15
Median and Averaging Filters ....................................................... 17
AUX/VBAT/GPIO Pin ................................................................... 18
Auxiliary Input ........................................................................... 18
Battery Input ............................................................................... 18
Limit Comparison ...................................................................... 18
GPIO ............................................................................................ 18
Conversion Timing ........................................................................ 20
Register Map ................................................................................... 21
Detailed Register Descriptions ..................................................... 22
Control Registers ............................................................................ 26
Control Register 1 ...................................................................... 26
Control Register 2 ...................................................................... 28
Control Register 3 ...................................................................... 29
Interrupts ..................................................................................... 30
Synchronizing the AD7879/AD7889 to the Host CPU ........ 31
Serial Interface ................................................................................ 32
SPI Interface ................................................................................ 32
I2C-Compatible Interface .......................................................... 34
Grounding and Layout .................................................................. 37
Lead Frame Chip Scale Packages ............................................. 37
WLCSP Assembly Considerations ........................................... 37
Outline Dimensions ....................................................................... 38
Ordering Guide .......................................................................... 39
REVISION HISTORY
11/10—Rev. B to Rev. C
Changes to Table 2 ............................................................................ 3
Added Conversion Timing Section .............................................. 20
Added Figure 34 .............................................................................. 29
1/10—Rev. A to Rev. B
Updated Outline Dimensions ....................................................... 37
Changes to Ordering Guide .......................................................... 38
3/09—Rev. 0 to Rev. A
Added AD7889 and Backside-Coated WLCSP ......... Throughout
Change to Battery Monitor, Input Voltage Range Parameter ..... 3
Changes to Table 4 ............................................................................ 6
Added Thermal Resistance Section and Table 5;
Renumbered Sequentially ................................................................ 6
Changes to Pin Configurations and Function Descriptions
Section ................................................................................................ 7
Added Table 7 .................................................................................... 8
Changes to First Method Section ................................................. 15
Changes to Median and Averaging Filters Section .................... 17
Changes to GPIO Interrupt Enable (Bit 12, Control Register 3,
Address 0x03) Section ................................................................... 19
Changes to Table 13 ....................................................................... 22
Changes to ADC Channel (Control Register 1, Bits[14:12])
Section .............................................................................................. 26
Changes to Power Management (Control Register 2,
Bits[15:14]) Section ........................................................................ 27
Changes to DAV —Data Available Interrupt Section ................. 29
Changes to
INT—Out-of-Limit Interrupt Section .................... 29
Changes to Writing Data Section ................................................. 31
Changes to Reading Data Section and Figure 40 ....................... 32
Changes to Figure 41 ...................................................................... 33
Changes to Writing Data over the I2C Bus Section .................... 34
Changes to Figure 44 ...................................................................... 35
Updated Outline Dimensions ....................................................... 37
Changes to Ordering Guide. ......................................................... 38
10/08—Revision 0: Initial Version
AD7879/AD7889
Rev. C | Page 3 of 40
SPECIFICATIONS
VCC = 1.6 V to 3.6 V, TA = −40°C to +85°C, unless otherwise noted.
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
DC ACCURACY
Resolution 12 Bits
No Missing Codes 11 12 Bits
Integral Nonlinearity (INL)1 ±3 LSB LSB size = 390 µV.
Differential Nonlinearity (DNL)1 LSB size = 390 µV.
Negative DNL −0.99 LSB
Positive DNL 2 LSB
Offset Error1, 2 ±2 ±6 LSB
Gain Error1, 2 ±4 LSB
Noise3 70 µV rms
Power Supply Rejection3 60 dB
Internal Clock Frequency 2 MHz
Internal Clock Accuracy 1.8 2.2 MHz
SWITCH DRIVERS
On Resistance1
Y+, X+ 6 Ω
Y−, X− 5 Ω
ANALOG INPUTS
Input Voltage Range 0 VCC V
DC Leakage Current ±0.1 µA
Input Capacitance 30 pF
Accuracy 0.3 %
TEMPERATURE MEASUREMENT
Temperature Range −40 +85 °C
Resolution 0.3 °C
Accuracy2 ±2 °C Calibrated at 25°C.
BATTERY MONITOR
Input Voltage Range 0.5 5 V
Input Impedance3 16 kΩ
Accuracy 2 5 % Uncalibrated accuracy.
LOGIC INPUTS (DIN, SCL, CS, SDA, GPIO)
Input High Voltage, VINH 0.7 × VCC V
Input Low Voltage, VINL 0.3 × VCC V
Input Current, IIN 0.01 µA VIN = 0 V or VCC.
Input Capacitance, CIN3 10 pF
LOGIC OUTPUTS (DOUT, GPIO, SCL, SDA, INT)
Output High Voltage, VOH VCC − 0.2 V
Output Low Voltage, VOL 0.4 V
Floating-State Leakage Current ±0.1 µA
Floating-State Output Capacitance2 5 pF
CONVERSION RATE3
Conversion Time 9.5 µs Including 2 µs of acquisition time, MAV
filter off. 2 µs of additional time is required
if MAV filter is on.
Throughput Rate 105 kSPS
AD7879/AD7889
Rev. C | Page 4 of 40
Parameter Min Typ Max Unit Test Conditions/Comments
POWER REQUIREMENTS
VCC 1.6 2.6 3.6 V Specified performance.
ICC Digital inputs = 0 V or VCC.
Converting Mode 480 650 µA ADC on, PM = 10.
Static 406 µA ADC and temperature sensor are off; the
reference and oscillator are on; PM = 01
or 11.
Shutdown Mode 0.5 6 µA PM = 00.
1 See the Terminology section.
2 Guaranteed by characterization; not production tested.
3 Sample tested at 25°C to ensure compliance.
SPI TIMING SPECIFICATIONS (AD7879/AD7889)
VCC = 1.6 V to 3.6 V, TA = −40°C to +85°C, unless otherwise noted. Sample tested at 25°C to ensure compliance. All input signals are
specified with tR = tF = 5 ns (10% to 90% of VCC) and timed from a voltage level of 1.4 V.
Table 2.
Parameter1Limit Unit Description
fSCL 5 MHz max
t1 5 ns min CS falling edge to first SCL falling edge
t2 20 ns min SCL high pulse width
t3 20 ns min SCL low pulse width
t4 15 ns min DIN setup time
t5 15 ns min DIN hold time
t6 20 ns max DOUT access time after SCL falling edge
t7 16 ns max CS rising edge to DOUT high impedance
t8 15 ns min SCL rising edge to CS high
1 Guaranteed by design; not production tested.
CS
SCL
DIN
DOUT
t1
116
15
MSB LSB
2 3
MSB LSB
1 2 15 16
t2
t4t5
t3
t6t7
t8
07667-002
Figure 2. Detailed SPI Timing Diagram
AD7879/AD7889
Rev. C | Page 5 of 40
I2C TIMING SPECIFICATIONS (AD7879-1/AD7889-1)
VCC = 1.6 V to 3.6 V, TA = −40°C to +85°C, unless otherwise noted. Sample tested at 25°C to ensure compliance. All input signals are
timed from a voltage level of 1.4 V.
Table 3.
Parameter1 Limit Unit Description
fSCL 400 kHz max
t1 0.6 µs min Start condition hold time, tHD; STA
t2 1.3 µs min Clock low period, tLOW
t3 0.6 µs min Clock high period, tHIGH
t4 100 ns min Data setup time, tSU; DAT
t5 300 ns min Data hold time, tHD; DAT
t6 0.6 µs min Stop condition setup time, tSU; STO
t7 0.6 µs min Start condition setup time, tSU; STA
t8 1.3 µs min Bus-free time between stop and start conditions, tBUF
tR 300 ns max Clock/data rise time
tF 300 ns max Clock/data fall time
1 Guaranteed by design; not production tested.
07667-003
SCL
SDA
t
R
t
F
t
2
t
5
t
1
t
3
t
4
STOP START STOPSTART
t
7
t
6
t
1
t
8
Figure 3. Detailed I2C Timing Diagram
AD7879/AD7889
Rev. C | Page 6 of 40
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 4.
Parameter Rating
VCC to GND −0.3 V to +3.6 V
Analog Input Voltage to GND −0.3 V to VCC + 0.3 V
AUX/VBAT to GND −0.3 V to +5 V
Digital Input Voltage to GND −0.3 V to VCC + 0.3 V
Digital Output Voltage to GND −0.3 V to VCC + 0.3 V
Input Current to Any Pin Except Supplies1 10 mA
ESD Rating (X+, Y+, X−, Y−)
Air Discharge Human Body Model 15 kV
Contact Human Body Model 10 kV
ESD Rating (All Other Pins)
Human Body Discharge 4 kV
Field-Induced Charged Device Model 1 kV
Machine Model 0.2 kV
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
Power Dissipation
WLCSP (4-Layer Board) 866 mW
LFCSP (4-Layer Board) 2.138 W
IR Reflow Peak Temperature 260°C (±0.5°C)
Lead Temperature (Soldering 10 sec) 300°C
1 Transient currents of up to 100 mA do not cause SCR latch-up.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 5. Thermal Resistance
Package Type1 θJA Unit
12-Ball WLCSP 75 °C/W
16-Lead LFCSP 30.4 °C/W
1 4-layer board.
200µA IOL
200µA IOH
1.4V
TO OUTPUT
PIN CL
50pF
07667-004
Figure 4. Circuit Used for Digital Timing
ESD CAUTION
AD7879/AD7889
Rev. C | Page 7 of 40
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
07667-005
TOP VIEW
(BALL SIDE DOWN)
Not t o Scal e
AUX/
VBAT/
GPIO VCC/REF X+
Y+
DOUT DIN X–
SCLGND Y–
1
A
B
C
D
2 3
BALLA1
INDICATOR
PENIRQ/
INT/DAV CS
Figure 5. AD7879/AD7889 WLCSP Pin Configuration
07667-006
TOP VIEW
(BALL SIDE DOWN)
Not t o Scal e
AUX/
VBAT/
GPIO VCC/REF X+
Y+
SDAADD1 X–
SCLGND Y–
1
A
B
C
D
2 3
BALLA1
INDICATOR
PENIRQ/
INT/DAV ADD0
Figure 6. AD7879-1/AD7889-1 WLCSP Pin Configuration
Table 6. Pin Function Descriptions, WLCSP
Ball No.
Mnemonic Description
AD7879/
AD7889
AD7879-1/
AD7889-1
1A 1A AUX/VBAT/GPIO This pin can be programmed as an auxiliary input to the ADC (AUX), as a battery measure-
ment input to the ADC ( V BAT ), or as a general-purpose digital input/output (GPIO).
1B 1B PENIRQ/INT/DAV Interrupt Output. This pin is asserted when the screen is touched (PENIRQ), when a measure-
ment exceeds the preprogrammed limits (INT), or when new data is available in the registers
(DAV). Active low, internal 50 kΩ pull-up resistor.
1C N/A DOUT SPI Serial Data Output for the AD7879/AD7889.
N/A 1C SDA I2C Serial Data Input and Output for the AD7879-1/AD7889-1.
1D 1D SCL Serial Interface Clock Input.
2A 2A VCC/REF Power Supply Input and ADC Reference.
2B N/A CS Chip Select for the SPI Serial Interface on the AD7879/AD7889. Active low.
N/A 2B ADD0 I2C Address Bit 0 for the AD7879-1/AD7889-1. This pin can be tied high or low to determine
an address for the AD7879-1/AD7889-1 (see Table 25).
2C N/A DIN SPI Serial Data Input to the AD7879/AD7889.
N/A 2C ADD1 I2C Address Bit 1 for the AD7879-1/AD7889-1. This pin can be tied high or low to determine
an address for the AD7879-1/AD7889-1 (see Table 25).
2D 2D GND Ground. Ground reference point for all circuitry on the AD7879/AD7889. All analog input
signals and any external reference signal should be referred to this voltage.
3A 3A X+ Touch Screen Input Channel.
3B 3B Y+ Touch Screen Input Channel.
3C 3C X− Touch Screen Input Channel.
3D 3D Y− Touch Screen Input Channel.
AD7879/AD7889
Rev. C | Page 8 of 40
Figure 7. AD7879 LFCSP Pin Configuration
07667-008
PIN 1
INDICATOR
1Y+
2NC 3NC 4X–
11 NC
12
10 NC
9 SDA
5
Y–
6
ADD1 7
GND 8
SCL
15 VCC/REF
16 X+
14
13 AUX/VBAT/GPIO
AD7879-1
TOP VIEW
(No t t o Scal e)
PENIRQ/INT/DAV
ADD0
NOTES
1. NC = NO CO NNE CT
2. THE EXPOSED PAD IS NOT CONNECTED INTE RNALLY.
FOR INCRE AS E D RE LI ABILITY OF THE SOLDER JOINTS
AND MAXIMUM THERM AL CAPABILITY, I T I S RECOMMENDED
THAT THE PAD BE SOL DE RE D TO T HE GROUND P LANE.
Figure 8. AD7879-1 LFCSP Pin Configuration
Table 7. Pin Function Descriptions, LFCSP
Pin No.
Mnemonic Description
AD7879 AD7879-1
1 1 Y+ Touch Screen Input Channel.
2, 3, 10, 11 2, 3, 10, 11 NC No Connect.
4 4 X− Touch Screen Input Channel.
5 5 Y− Touch Screen Input Channel.
6 N/A DIN SPI Serial Data Input to the AD7879.
N/A 6 ADD1 I2C Address Bit 1 for the AD7879-1. This pin can be tied high or low to determine an address
for the AD7879-1 (see Table 25).
7 7 GND Ground. Ground reference point for all circuitry on the AD7879. All analog input signals and
any external reference signal should be referred to this voltage.
8 8 SCL Serial Interface Clock Input.
9 N/A DOUT SPI Serial Data Output for the AD7879.
N/A 9 SDA I2C Serial Data Input and Output for the AD7879-1.
12 12 PENIRQ/INT/DAV Interrupt Output. This pin is asserted when the screen is touched (PENIRQ), when a measure-
ment exceeds the preprogrammed limits (INT), or when new data is available in the registers
(DAV). Active low, internal 50 kΩ pull-up resistor.
13 13 AUX/VBAT/GPIO This pin can be programmed as an auxiliary input to the ADC (AUX), as a battery measure-
ment input to the ADC ( V BAT ), or as a general-purpose digital input/output (GPIO).
14 N/A CS Chip Select for the SPI Serial Interface on the AD7879. Active low.
N/A 14 ADD0 I2C Address Bit 0 for the AD7879-1. This pin can be tied high or low to determine an address
for the AD7879-1 (see Table 25).
15 15 VCC/REF Power Supply Input and ADC Reference.
16 16 X+ Touch Screen Input Channel.
EP Exposed Pad. The exposed pad is not connected internally. For increased reliability of the
solder joints and maximum thermal capability, it is recommended that the pad be soldered
to the ground plane.
AD7879/AD7889
Rev. C | Page 9 of 40
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VCC = 2.6 V, fSCL = 2 MHz, unless otherwise noted.
475
470
465
460
455
450
445
440
435
430
425 –40 –25 –10 10 25 40 55 70 85
TEMPERATURE (°C)
CURRENT ( µ A)
07667-009
Figure 9. Supply Current vs. Temperature
700
600
500
400
300
200
100
01.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
VCC (V)
CURRENT ( µ A)
07667-010
Figure 10. Supply Current vs. VCC
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0–40 –25 –10 10 25 50 75 100
TEMPERATURE (°C)
CURRENT ( µ A)
07667-012
Figure 11. Full Power-Down IDD vs. Temperature
1.0
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
TEMPERATURE (°C)
GAIN ERRO R V ARIAT ION ( LSB)
07667-011
2.6V
3.6V
1.6V
85–40 –25 –10 10 25 40 55 70
Figure 12. Change in ADC Gain vs. Temperature
07667-013
1.0
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
TEMPERATURE (°C)
OFFSET VARIATION (LSB)
2.6V
3.6V
1.6V
85
–40 –25 –10 10 25 40 55 70
Figure 13. Change in ADC Offset vs. Temperature
2.0
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
04096358430722560204815361024512 CODE
INL (LSB)
07667-014
Figure 14. ADC INL
AD7879/AD7889
Rev. C | Page 10 of 40
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.01501 1001 1501 2001 2501 3001 3501 4001
CODE
DNL ( LSB)
07667-015
Figure 15. ADC DNL
7
6
5
4
3
2
1
01.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
V
CC
(V)
R
ON
(Ω)
07667-016
X+ TO V
CC
Y+ TO V
CC
X– TO GND
Y– TO GND
Figure 16. Switch On Resistance vs. VCC
(X+, Y+: Pin to VCC; X−, Y−: Pin to GND)
6.0
5.5
5.0
4.5
4.0
3.5
3.0 –40 –25 –10 10 25 40 55 70 85
TEMPERATURE (°C)
R
ON
(Ω)
07667-017
X+ TO V
CC
Y+ TO V
CC
X– TO GND
Y– TO GND
Figure 17. Switch On Resistance vs. Temperature
(X+, Y+: Pin to VCC; X−, Y−: Pin to GND)
2370
2369
2368
2367
2366
2365
2364
2363
2362
2361
2360 –40 –25 –15 –5 515 25 35 45 55 65
TEMPERATURE (°C)
ADC CODE ( Decimal)
07667-018
75 85
Figure 18. ADC Code vs. Temperature (Fixed Analog Input)
AD7879/AD7889
Rev. C | Page 11 of 40
1400
1200
1000
800
600
400
200
02.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
V
CC
(V)
TE M P E RATURE (Cod e)
07667-019
Figure 19. Temperature Code vs. VCC for 25°C
0
–20
–40
–60
–80
–100
–120
–140
–160
0
1603
3206
4809
6412
8015
9618
11221
12824
14427
16030
17633
19236
20839
22442
24045
25648
27251
28854
30457
32060
33663
35266
36869
FRE QUENCY ( Hz )
INPUT TONE AMPLITUDE (dB)
07667-020
SNR = 61. 58dB
THD = 72.34d B
Figure 20. Typical FFT Plot for the Auxiliary Channels at 25 kHz Sampling
Rate and 1 kHz Input Frequency
250
200
150
100
50
0
NUMBER OF UNIT S
–4 –3 –2 –1 0
ERRO R ( %)
MEAN: –1.98893
SD: 0.475534
07667-021
Figure 21. Typical Uncalibrated Accuracy for the Battery Channel (25°C)
AD7879/AD7889
Rev. C | Page 12 of 40
TERMINOLOGY
Differential Nonlinearity (DNL)
DNL is the difference between the measured and the ideal
1 LSB change between any two adjacent codes in the ADC.
Integral Nonlinearity (INL)
INL is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The
endpoints of the transfer function are zero scale at 1 LSB below
the first code transition and full scale at 1 LSB above the last
code transition.
Gain Error
Gain error is the deviation of the last code transition
(111 … 110 to 111 … 111) from the ideal (VREF − 1 LSB)
after the offset error has been calibrated out.
Offset Error
Offset error is the deviation of the first code transition
(00 … 000 to 00 … 001) from the ideal (AGND + 1 LSB).
On Resistance
On resistance is a measure of the ohmic resistance between the
drain and the source of the switch drivers.
AD7879/AD7889
Rev. C | Page 13 of 40
THEORY OF OPERATION
The AD7879/AD7889 are a complete 12-bit data acquisition
system for digitizing positional inputs from a 4-wire resistive
touch screen. To support this function, data acquisition on the
AD7879/AD7889 is highly programmable to ensure accurate
and noise-free results from the touch screen.
The core of the AD7879/AD7889 is a high speed, low power,
12-bit analog-to-digital converter (ADC) with an input multi-
plexer, on-chip track-and-hold, and on-chip clock. Conversion
results are stored in on-chip result registers. The results from
the auxiliary input or the battery input can be compared with
high and low limits stored in limit registers to generate an out-
of-limit interrupt (INT).
The AD7879/AD7889 also contain low resistance analog
switches to switch the X and Y excitation voltages to the touch
screen and to the on-chip temperature sensor. The high speed
SPI serial bus provides control of the devices, as well as com-
munication with the devices. The AD7879-1/AD7889-1 are
available with an I2C interface.
Operating from a single supply from 1.6 V to 3.6 V, the AD7879/
AD7889 offer a throughput rate of 105 kHz. The device is avail-
able in a 1.6 mm × 2 mm, 12-ball wafer level chip scale package
(WLCSP) and in a 4 mm × 4 mm, 16-lead lead frame chip scale
package (LFCSP).
The AD7879/AD7889 have an on-chip sequencer that schedules
a sequence of preprogrammed conversions. The conversion
sequence starts automatically when the screen is touched or
at preset intervals, using the on-board timer.
To ensure that the AD7879/AD7889 work well with different
touch screens, the user can select the acquisition time. A
programmable delay ensures that the voltage on the touch
screen settles before a measurement is taken.
To help re duce noise in the system, the ADC takes up to 16
conversion results from each channel and writes the average of
the results to the register. To further improve the performance
of the AD7879/AD7889, the median filter can also be used if
there is noise present in the system.
TOUCH SCREEN PRINCIPLES
A 4-wire touch screen consists of two flexible, transparent,
resistive-coated layers that are normally separated by a small
air gap (see Figure 22). The X layer has conductive electrodes
running down the left and right edges, allowing the application
of an excitation voltage across the X layer from left to right.
07667-022
X+
X–
Y–
Y+
CONDUCTIV E E LECTRODE
ON BOTTOM SIDE
PLASTIC FILM WITH
TRANSPARENT, RESIST I VE
COATING ON BOTTOM SIDE
PLASTIC FILM WITH
TRANSPARENT, RESIST I VE
COATING ONTOP SIDE
LCD S CRE E N
CONDUCTIV E E LECTRODE
ON TOP SIDE
Figure 22. Basic Construction of a Touch Screen
The Y layer has conductive electrodes running along the top
and bottom edges, allowing the application of an excitation
voltage down the Y layer from top to bottom.
Provided that the layers are of uniform resistivity, the voltage
at any point between the two electrodes is proportional to the
horizontal position for the X layer and the vertical position for
the Y layer.
When the screen is touched, the two layers make contact. If
only the X layer is excited, the voltage at the point of contact
and, therefore, the horizontal position, can be sensed at one of
the Y layer electrodes. Similarly, if only the Y layer is excited,
the voltage and, therefore, the vertical position, can be sensed
at one of the X layer electrodes. By switching alternately
between X and Y excitation and measuring the voltages, the
X and Y coordinates of the contact point can be determined.
In addition to measuring the X and Y coordinates, it is also
possible to estimate the touch pressure by measuring the
contact resistance between the X and Y layers. The AD7879/
AD7889 are designed to facilitate this measurement.
AD7879/AD7889
Rev. C | Page 14 of 40
Figure 23 shows an equivalent circuit of the analog input structure
of the AD7879/AD7889, showing the touch screen switches, the
main analog multiplexer, the ADC, and the dual 3-to-1 multi-
plexer that selects the reference source for the ADC.
AUX/VBAT/GPIO
12-BIT SUCCE S S IVE
APPRO X IMATION ADC
WI TH T RACK- AND- HOLD
INPUT
MUX
TEMPERATURE
SENSOR
Y–
Y+
X–
X+
VCC
REF–
IN+
REF+
DUAL 3-TO - 1 M UX
X– Y– GND X+ Y+ VCC
07667-023
Figure 23. Analog Input Structure
The AD7879/AD7889 can be set up to automatically convert
either specific input channels or a sequence of channels. The
results of the ADC conversions are stored in the result registers.
When measuring the ancillary analog inputs (AUX, TEMP, or
VBAT), the ADC uses a VCC reference and the measurement is
referred to GND.
MEASURING TOUCH SCREEN INPUTS
When measuring the touch screen inputs, it is possible to use
VCC as a reference or instead to use the touch screen excitation
voltage as the reference and to perform a ratiometric, differential
measurement. The differential method is the default method
and is selected by clearing the SER/DFR bit (Bit 9 in Control
Register 2) to 0. The single-ended method is selected by setting
this bit to 1.
Single-Ended Method
Figure 24 illustrates the single-ended method for the Y position.
For the X position, the excitation voltage is applied to X+ and
X− and the voltage is measured at Y+.
ADC
REF+
INPUT
(VIA MUX)
X+
REF–
TOUCH
SCREEN
Y+
Y–
GND
V
REF
V
CC
07667-024
Figure 24. Single-Ended Conversion of Touch Screen Inputs
The voltage seen at the input to the ADC in Figure 24 is
YTOTAL
Y
CC
IN R
R
VV −
×= (1)
The advantage of the single-ended method is that the touch
screen excitation voltage is switched off when the signal is
acquired. Because a screen can draw over 1 mA, this is a
significant consideration for a battery-powered system.
The disadvantage of the single-ended method is that voltage
drops across the switches can introduce errors. Touch screens
can have a total end-to-end resistance ranging from 200 Ω to
900 Ω. By taking the lowest screen resistance of 200 Ω and a
typical switch resistance of 14 Ω, the user can reduce the apparent
excitation voltage to 200/228 × 100 = 87% of its actual value. In
addition, the voltage drop across the low-side switch adds to the
ADC input voltage. This introduces an offset into the input
voltage; thus, it can never reach 0.
Ratiometric Method
The ratiometric method illustrated in Figure 25 shows the
negative input of the ADC reference connected to Y− and the
positive input connected to Y+. Thus, the screen excitation
voltage provides the reference for the ADC. The input of the
ADC is connected to X+ to determine the Y position.
ADC
REF+
INPUT
(VIA MUX)
REF–
VCC
X+
TOUCH
SCREEN
Y+
Y–
GND
07667-025
Figure 25. Ratiometric Conversion of Touch Screen Inputs
For greater accuracy, the ratiometric method has two significant
advantages. One is that the reference to the ADC is provided
from the actual voltage across the screen; therefore, any voltage
dropped across the switches has no effect. The other advantage
is that because the measurement is ratiometric, it does not
matter if the voltage across the screen varies in the long term.
However, it must not change after the signal has been acquired.
The disadvantage of the ratiometric method is that the screen
must be powered up at all times because it provides the reference
voltage for the ADC.
AD7879/AD7889
Rev. C | Page 15 of 40
TOUCH-PRESSURE MEASUREMENT
The pressure applied to the touch screen by a pen or finger can
also be measured with the AD7879/AD7889 using some simple
calculations. The contact resistance between the X and Y plates
is measured, providing a good indication of the size of the
depressed area and, therefore, the applied pressure. The area of
the spot that is touched is proportional to the size of the object
touching it. The size of this resistance (RTOUCH) can be calculated
using two different methods.
First Method
The first method requires the user to know the total resistance
of the X-plate tablet (RX). Three touch screen conversions are
required: measurement of the X position, XPOSITION (Y+ input);
measurement of the X+ input with the excitation voltage applied
to Y+ and X− (Z1 measurement); and measurement of the Y−
input with the excitation voltage applied to Y+ and X− (Z2
measurement). These three measurements are illustrated in
Figure 26.
The AD7879/AD7889 have two special ADC channel settings
that configure the X and Y switches for the Z1 and Z2 measure-
ments and store the results in the Z1 and Z2 result registers. The
Z1 measurement is selected by setting the CHNL ADD[2:0] bits
to 101 in Control Register 1 (Address 0x01); the result is stored
in the X+ (Z1) result register (Address 0x0A). The Z2 measurement
is selected by setting the CHNL ADD[2:0] bits to 100 in Control
Register 1 (Address 0x01); the result is stored in the Y− (Z2)
result register (Address 0x0B).
The touch resistance (RTOUCH) can then be calculated using the
following equation:
RTOUCH = (RXPLATE) × (XPOSITION/4096) × [(Z2/Z1) − 1] (2)
07667-026
Y–
Y+
X–
X+
TOUCH
RESISTANCE
MEASURE
Z1 POSITION
X–
X+
Y–
Y+
TOUCH
RESISTANCE
MEASURE
X POSITION
Y–
Y+
X–
X+
TOUCH
RESISTANCE
MEASURE
Z2 POSITION
Figure 26. Three Measurements Required for Touch Pressure
Second Method
The second method requires the user to know the resistance of
the X-plate and Y-plate tablets. Three touch screen conversions
are required: a measurement of the X position (XPOSITION), the
Y position (YPOSITION), and the Z1 position.
The following equation also calculates the touch resistance
(RTOUCH):
RTOUCH = RXPLATE × (XPOSITION/4096) × [(4096/Z1) − 1] −
RYPLATE × [1 − (YPOSITION/4096)] (3)
TEMPERATURE MEASUREMENT
A temperature measurement option called the single-conversion
method is available on the AD7879/AD7889. The conversion
method requires only a single measurement on ADC Channel
001. The results are stored in the temperature conversion result
register (Address 0x0D). The AD7879/AD7889 do not provide
an explicit output of the temperature reading; the system must
perform some external calculations. This method is based on
an on-chip diode measurement.
The acquisition time is fixed at 16 ms for temperature
measurement.
Conversion Method
The conversion method makes use of the fact that the tempera-
ture coefficient of a silicon diode is approximately −2.1 mV/°C.
However, this small change is superimposed on the diode forward
voltage, which can have a wide tolerance. Therefore, it is necessary
to calibrate by measuring the diode voltage at a known temperature
to provide a baseline from which the change in forward voltage
with temperature can be measured. This method provides a
resolution of approximately 0.3°C and a predicted accuracy
of ±2°C.
The temperature limit comparison is performed on the result
in the temperature conversion result register (Address 0x0D),
which is the measurement of the diode forward voltage. The
values programmed into the high and low limits should be
referenced to the calibrated diode forward voltage to make
accurate limit comparisons.
AD7879/AD7889
Rev. C | Page 16 of 40
Temperature Calculations
If an explicit temperature reading in degrees Celsius is required,
calculate for the single-measurement method as follows:
1. Calculate the scale factor of the ADC in degrees per LSB.
Degrees per LSB = ADC LSB size/−2.1 mV =
(VCC/4096)/−2.1 mV
2. Save the ADC output, DCAL, at the calibration temperature,
TCAL.
3. Take the ADC reading, DAMB, at the temperature to be
measured, TAMB.
4. Calculate the difference in degrees between TCAL and TAMB by
∆T = (DAMB − DCAL) × degrees per LSB
5. Add ∆T to TCAL.
Example
Using VCC = 2.5 V as reference,
Degrees per LSB = (2.5/4096)/−2.1 × 10−3 = −0.291
The ADC output is 983 decimal at 25°C, equivalent to a diode
forward voltage of 0.6 V.
The ADC output at TAMB is 880.
∆T = (880 − 983) × −0.291 = 30°C
TAMB = 25 + 30 = 55°C
AD7879/AD7889
Rev. C | Page 17 of 40
MEDIAN AND AVERAGING FILTERS
As explained in the Touch Screen Principles section, touch
screens are composed of two resistive layers, normally placed
over an LCD screen. Because these layers are in close proximity
to the LCD screen, noise can be coupled from the screen onto
these resistive layers, causing errors in the touch screen
positional measurements.
The AD7879/AD7889 contain a filtering block to process the
data and discard the spurious noise before sending the infor-
mation to the host. The purpose of this block is not only the
suppression of noise; the on-chip filtering also greatly reduces
the host processing loading.
The processing function consists of two filters that are applied
to the converted results: the median filter and the averaging filter.
The median filter suppresses the isolated out-of-range noise and
sets the number of measurements to be taken. These measurements
are arranged in a temporary array, where the first value is the
smallest measurement and the last value is the largest measure-
ment. Bit 6 and Bit 5 in Control Register 2 (MED1, MED0) set
the window of the median filter and, therefore, the number of
measurements taken.
Table 8. Median Filter Size
MED1 MED0 Number of Measurements
0 0 Median filter disabled
0 1 4
1 0 8
1 1 16
The averaging filter size determines the number of values to
average. Bit 8 and Bit 7 in Control Register 2 (AVG1, AVG0)
set the average to 2, 4, 8, or 16 samples. Only the final averaged
result is written into the result register.
Table 9. Averaging Filter Size
AVG1 AVG0 Filter Size
0 0 Average of 2 middle samples
0 1 Average of 4 middle samples
1 0 Average of 8 middle samples
1 1 Average of 16 samples
When both filter values are 00, only one measurement is
transferred to the register map.
The number specified with the MED1 and MED0 settings must
be greater than or equal to the number specified with the AVG1
and AVG0 settings. If both settings specify the same number,
the median filter is switched off.
Table 10. Median Averaging Filters (MAVF) Settings
Setting Function
M = A Median filter is disabled; output is the average of
A converted results
M > A Output is the average of the middle A values from
the array of M measurements
M < A Not possible because the median filter size is always
larger than the averaging window size
Example
In this example, MED1, MED0 = 11 and AVG1, AVG0 = 10;
the median filter has a window size of 16. This means that 16
measurements are taken and arranged in descending order in a
temporary array.
The averaging window size in this example is 8. The output is
the average of the middle eight values of the 16 measurements
taken with the median filter.
AVERAGING
FILTER
MEDIAN
FILTER
12-BI T SAR
ADC
6
2
13
4
16
5
15
10
9
3
11
8
1
12
14
7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
M = 16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A = 8
CONVERTED
RESULTS 16 M E AS URE M E NTS
ARRANGED AVERAGE OF
MI DDLE 8 VALUES
07667-027
Figure 27. Median and Averaging Filter Example
It takes approximately 2 μs to sort the data in the rank filter
(tSORT in Figure 34); tSORT adds to the update rate of the AD7879.
AD7879/AD7889
Rev. C | Page 18 of 40
AUX/VBAT/GPIO PIN
The AUX/VBAT/GPIO pin on the AD7879/AD7889 can be
programmed as an auxiliary input to the ADC, as a battery
monitoring input, or as a general-purpose digital input/output.
To select the auxiliary measurement, set the ADC channel
address to 011 (Bits[14:12] in Control Register 1, Address 0x01).
To select a battery measurement, set the ADC channel address
to 010. To select the GPIO function, set Bit 13 in Control
Register 2 (Address 0x02) to 1.
AUXILIARY INPUT
The AD7879/AD7889 have an auxiliary analog input, AUX.
When the auxiliary input function is selected, the signal on the
AUX pin (AUX/VBAT/GPIO) is connected directly to the ADC
input. This channel has a full-scale input range from 0 V to VCC.
The ADC channel address for AUX is 011 (Bits[14:12] in
Control Register 1, Address 0x01), and the result is stored in
the AUX/VBAT result register (Address 0x0C).
BATTERY INPUT
The AD7879/AD7889 can monitor battery voltages from 0.5 V
to 5 V when the BAT measurement is selected. Figure 28 shows
a block diagram of a battery voltage monitored through the VBAT
pin. The voltage to the VCC pin (VCC/REF) of the AD7879/AD7889
is maintained at the desired supply voltage via the dc-to-dc
converter, and the input to the converter is monitored. This
voltage on VBAT is divided by 4 internally, so that a 5 V battery
voltage is presented to the ADC as 1.25 V. To conserve power,
the divider circuit is on only during the sampling of a voltage on
VBAT. Note that the possible maximum input is 5 V.
The ADC channel address for VBAT is 010 (Bits[14:12] in
Control Register 1, Address 0x01), and the result is stored in
the AUX/VBAT result register (Address 0x0C).
ADC
0.125V TO 1.25V
SW
VBAT V
CC
12kΩ
4kΩ
DC-TO-DC
CONVERTER
BATTERY
0.5V TO 5V
07667-028
Figure 28. Block Diagram of Battery Measurement Circuit
The maximum battery voltage that the AD7879/AD7889 can
measure changes when a different reference voltage is used. The
maximum voltage that is measurable is VCC × 4 because this
voltage gives a full-scale output from the ADC. The battery
voltage can be calculated using the following formula:
VBAT (V) = [(Register Value) × VCC × 4]/4095
LIMIT COMPARISON
The AUX measurement and the battery measurement can
be compared with high and low limits stored on chip. An
out-of-limit result generates an alarm output at the INT pin
(PENIRQ/INT/DAV) when the INT function is enabled. The
high limit for both channels is stored in the AUX/VBAT high
limit register (Address 0x04), and the low limit is stored in the
AUX/VBAT low limit register (Address 0x05).
After a measurement from either AUX or VBAT is taken, it
is compared with the high and low limits. The out-of-limit
comparison sets a status bit in Control Register 3. Separate
status bits for the high limit and the low limit indicate which
limit was exceeded. The interrupt sources can be masked by
clearing the corresponding enable bit in Control Register 3.
GPIO
The AD7879/AD7889 have one general-purpose logic input/
output pin, GPIO (AUX/VBAT/GPIO). To enable GPIO, set Bit
13 in Control Register 2 to 1. If this bit is set to 0, the
AUX/VBAT function is active on the pin. If the GPIO is not
enabled, the other GPIO configuration bits have no effect.
The GPIO data bit is Bit 12 in Control Register 2.
Direction (Bit 11, Control Register 2, Address 0x02)
Bit 11 sets the direction of the GPIO pin (AUX/VBAT/GPIO).
When GPIO DIR = 0, the pin is an output. Setting or clearing
the GPIO data bit (Bit 12 in Control Register 2) outputs a value
on the GPIO pin.
When GPIO DIR = 1, the pin is an input. An input value on the
GPIO pin sets or clears the GPIO data bit (Bit 12 in Control
Register 2). GPIO data register bits are read-only when GPIO
DIR = 1.
Polarity (Bit 10, Control Register 2, Address 0x02)
When GPIO POL = 0, the GPIO pin is active low. When GPIO
POL = 1, the GPIO pin is active high. How this bit affects the
GPIO operation also depends on the GPIO DIR bit.
If GPIO POL = 1 and GPIO DIR = 1, a 1 at the input pin sets
the corresponding GPIO data register bit to 1. A 0 at the input
pin clears the corresponding GPIO data bit to 0.
If GPIO POL = 1 and GPIO DIR = 0, a 1 in the GPIO data
register bit puts a 1 on the corresponding GPIO output pin. A 0
in the GPIO data register bit puts a 0 on the GPIO output pin.
If GPIO POL = 0 and GPIO DIR = 1, a 1 at the input pin sets
the corresponding GPIO data bit to 0. A 0 at the input pin clears
the corresponding GPIO data bit to 1.
If GPIO POL = 0 and GPIO DIR = 0, a 1 in the GPIO data
register bit puts a 0 on the corresponding GPIO output pin. A 0
in the GPIO data register bit puts a 1 on the GPIO output pin.
AD7879/AD7889
Rev. C | Page 19 of 40
GPIO Interrupt Enable (Bit 12, Control Register 3,
Address 0x03)
The GPIO pin can operate as an interrupt source to trigger the
INT output. This is controlled by Bit 12 in Control Register 3.
If the GPIO ALERT interrupt enable bit is set to 0, the GPIO can
trigger INT. If this bit is set to 1, the GPIO cannot trigger INT.
INT is asserted if the GPIO data register bit is set when the
GPIO is configured as an input, provided that INT is enabled.
INT is triggered only when the GPIO is configured as an input,
that is, when GPIO DIR = 1.
INT is cleared only when the GPIO signal or the GPIO enable
bit changes.
AD7879/AD7889
Rev. C | Page 20 of 40
CONVERSION TIMING
Conversion timing or update rate is the rate at which the
AD7879 provides converted values from the ADC so that the
XY positions in the touch screen can be updated. In other
words, the update rate is the timing required to give valid
measurements in the sequencer.
Figure 29 shows conversion timing for a conversion sequence.
F
C
DTMEASURE F
C
DTMEASURE F
C
DTMEASURE F
C
D
F
C
D
TMEASURE TMEASURE TMEASURE
X+
× M × M × M × M × M × M
Y+ Z1 Z2 VBAT/AUX TEMP
07667-046
Figure 29. Conversion Timing Sequence
FCD is required before each touch screen measurement (X+,
Y+, Z1, and Z2). This time is required to allow the screen inputs
to settle before converting. If the sequence does not contain any
screen channel (VBAT, AUX, or TEMP), only one FCD is added
at start of the sequence. At the end of the sequence, there is
always another FCD.
TMEASURE is the time required to perform one measurement in
the conversion sequence.
TMEASURE = [ACQ (2 μs, 4 μs, 8 μs, 16 μs) + TCONV (7.5 μs) + TSORT
(2 μs)]
where:
ACQ is the acquisition time which is programmable in Control
Register 1. For temperature measurements, ACQ is fixed at 16 μs.
TCONV (typical ADC conversion time) is specified at 7.5 μs.
TSORT is the time needed to sort the new sample within the
median filter array. The TSORT value is approximately 2 μs. If a
median filter is not used (MED =0), the TSORT value is 0.
TMEASURE_MIN = 9.5 μs (ACQ = 2 μs, no median filter)
Conversion time per channel depends on the number of
samples to be converted. The number of samples is pro-
grammed using the following median filter settings:
TCHANNEL = TMEASURE × MED
TCHANNEL_MIN =9.5 μs (ACQ = 2 μs, MED = 0)
TCHANNEL_MAX = 376 μs (ACQ = 16 μs, MED = 16)
Update Rate = [FCD + (TMEASURE × MED)] × N + FCD + TMR
where:
N = number of channels to be measured (1 to 6).
MED = median filter setting (1, 4, 8, 16).
TMR = timer setting (0 μs to 9.4 ms).
The total update rate depends on the median filter settings and
the number of channels in the conversion sequence. The timer
setting (TMR) allows the user more flexibility to program the
update rate.
For example, if
ACQ = 4 us
MED = 8
N = 2
FCD = 1.024 ms
TMR = 620 μs
TMEASURE = 4 + 7.5 + 2 = 13.5 μs
TCHANNEL = (13.5 × 8) = 108 μs
Then
Update rate = [1024 + 108] × 2 + 1024 + 620 = 3.9 ms
AD7879/AD7889
Rev. C | Page 21 of 40
REGISTER MAP
Table 11. Register Table
Address1 Register Name Description Default Value Type
0x00 Unused Unused 0x0000 R/W
0x01 Control Register 1 Pen interrupt enable, channel selection for manual conversion,
ADC mode, acquisition time, and conversion timer
0x0000 R/W
0x02 Control Register 2 ADC power management, GPIO control, pen interrupt mode,
averaging, median filter, software reset, and FCD
0x4040 R/W
0x03 Control Register 3 Status of high/low limit comparisons for TEMP and AUX/VBAT,
and enable bits to allow them to become interrupts; channel
selection for slave/master mode
0x0000 R/W
0x04 AUX/VBAT high limit AUX/VBAT high limit for comparison 0x0000 R/W
0x05 AUX/VBAT low limit AUX/VBAT low limit for comparison 0x0000 R/W
0x06 TEMP high limit TEMP high limit for comparison 0x0000 R/W
0x07 TEMP low limit TEMP low limit for comparison 0x0000 R/W
0x08 X+ X+ measurement for Y position 0x0000 R
0x09 Y+ Y+ measurement for X position 0x0000 R
0x0A X+ (Z1) X+ measurement for touch-pressure calculation (Z1) 0x0000 R
0x0B Y− (Z2) Y− measurement for touch-pressure calculation (Z2) 0x0000 R
0x0C AUX/VBAT AUX/VBAT voltage measurement 0x0000 R
0x0D TEMP Temperature conversion measurement 0x0000 R
0x0E Revision and device ID Revision and device ID 0x0379
(AD7879-1/AD7889-1)
R
0x037A
(AD7879/AD7889)
R
1 Do not write to addresses outside the register map.
AD7879/AD7889
Rev. C | Page 22 of 40
DETAILED REGISTER DESCRIPTIONS
All addresses and default values are expressed in hexadecimal.
Table 12. Control Register 1
Address Bit Name Data Bit Description
Default
Value
0x01 Disable PENIRQ 15 Pen interrupt enable. 0x0000
0 = PENIRQ is enabled.
1 = PENIRQ is disabled and INT is enabled.
CHNL ADD[2:0] [14:12] ADC channel address for manual conversion (ADC mode = 01).
111 = X+ input (Y position).
110 = Y+ input (X position).
101 = X+ (Z1) input for touch-pressure calculation.
100 = Y− (Z2) input (used for touch-pressure measurement).
011 = AUX input.1
010 = VBAT input.1
001 = temperature measurement.
000 = not applicable.
ADC MODE[1:0] [11:10] ADC mode.
00 = no conversion.
01 = single conversion.2
10 = conversion sequence (slave mode).2
11 = conversion sequence (master mode).
ACQ[1:0] [9:8] ADC acquisition time.
00 = 4 clock periods (2 µs).
01 = 8 clock periods (4 µs).
10 = 16 clock periods (8 µs).
11 = 32 clock periods (16 µs).
Note that the acquisition time does not apply to the temperature sensor channels;
the temperature channel has a constant settling time of 16 μs.
TMR[7:0] [7:0] Conversion interval timer.
Starts at 550 µs (00000001) and continues to 9.440 ms (11111111) in steps of 35 µs
(see Table 18).
Note that, in slave mode, the conversion interval timer starts to count as soon as the
conversion sequence is finished; in master mode, it starts to count again only if the
screen remains touched. If the screen is released, the timer stops counting and, on
the next screen touch, a conversion starts immediately.
1 If GPIO is enabled in Control Register 2 (Bit 13), AUX and VBAT are both ignored. If AUX and VBAT are both selected in Control Register 3 and GPIO is disabled, AUX is
ignored and VBAT is measured.
2 Note that these bits are cleared to 00 at the end of the conversion sequence if the conversion interval timer bits in Control Register 1 (Address 0x01) Bits[7:0] = 0x00 at
the end of the conversion sequence.
AD7879/AD7889
Rev. C | Page 23 of 40
Table 13. Control Register 2
Address Bit Name Data Bit Description
Default
Value
0x02 PM[1:0] [15:14] ADC power management. 0x4040
00 = full shutdown; the ADC, oscillator, bias, and temperature sensor are all powered down.
01 = analog blocks to be powered down depend on the ADC mode.
If ADC mode is master mode, the ADC, oscillator, bias, and temperature sensor are powered
down and must wake up when the user touches the screen.
If ADC mode is slave mode, the ADC and temperature sensor are powered down when not
being used. They wake up automatically when required. The oscillator and bias are powered
up because they are needed to measure time. This also applies to the single-conversion mode.
10 = ADC, bias, and oscillator are powered up continuously, irrespective of ADC mode.
11 = same as 01.
GPIO EN 13 GPIO enable.
0 = AUX/VBAT channel active.
1 = GPIO enabled on AUX/VBAT/GPIO pin.
GPIO DAT 12 GPIO data bit.
GPIO DIR 11 GPIO direction.
0 = output.
1 = input.
GPIO POL 10 GPIO polarity.
0 = GPIO pin is active low.
1 = GPIO pin is active high.
SER/DFR 9 Selects normal (single-ended) or ratiometric (differential) conversion.
0 = ratiometric (differential).
1 = normal (single-ended).
AVG[1:0] [8:7] ADC averaging.
00 = 2 middle values averaged (one measurement when median filter is disabled).
01 = 4 middle values averaged.
10 = 8 middle values averaged.
11 = 16 values averaged.
MED[1:0] [6:5] Median filter size.
00 = median filter disabled.
01 = 4 measurements.
10 = 8 measurements.
11 = 16 measurements.
SW/RST 4 Software reset; digital logic is reset when this bit is set.
FCD[3:0] [3:0] ADC first conversion delay.1
Starts at 128 µs (default) and continues to 4.096 ms in steps of 128 µs (see Table 22).
1 This delay occurs before conversion of the X and Y coordinate channels (including Z1 and Z2) to allow for screen settling and before the first conversion to allow the
ADC to power up.
AD7879/AD7889
Rev. C | Page 24 of 40
Table 14. Control Register 3
Address Bit Name Data Bit Description
Default
Value
0x03 TEMP MASK 15 TEMP mask bit. 0x0000
0 = temperature measurement is allowed to cause interrupt.
1 = temperature measurement is not allowed to cause interrupt.
AUX/VBAT MASK 14 AUX/VBAT mask bit.
0 = AUX/VBAT measurement is allowed to cause interrupt.
1 = AUX/VBAT measurement is not allowed to cause interrupt.
INT MODE 13 DAV/INT mode select.
0 = enable DAV mode.
1 = enable INT mode.
Note that this bit overrides any mask bits associated with individual channels.
GPIO ALERT 12 GPIO interrupt enable.
0 = GPIO can cause an alert on the INT output.
1 = mask GPIO from causing an alert on the INT output.
AUX/VBAT LOW 11 1 = AUX/VBAT below low limit.
AUX/VBAT HIGH 10 1 = AUX/VBAT above high limit.
TEMP LOW 9 1 = TEMP below low limit.
TEMP HIGH 8 1 = TEMP above high limit.
X+ 7 1 = include measurement of Y position (X+ input).
Y+ 6 1 = include measurement of X position (Y+ input).
Z1 5 1 = include Z1 touch-pressure measurement (X+ input).
Z2 4 1 = include measurement of Z2 touch-pressure measurement (Y− input).
AUX 3 1 = include measurement of AUX channel.1
VBAT 2 1 = include measurement of battery monitor (VBAT).1
TEMP 1 1 = include temperature measurement.
Not used 0 Unused.
1 If GPIO is enabled in Control Register 2 (Bit 13), AUX and VBAT are both ignored. If AUX and VBAT are both selected and GPIO is disabled, AUX is ignored and VBAT is
measured.
Table 15. Limit Registers
Address Register Name Data Bit Description
Default
Value
0x04 AUX/VBAT high limit [15:0] User-programmable AUX/VBAT high limit register 0x0000
0x05 AUX/VBAT low limit [15:0] User-programmable AUX/VBAT low limit register 0x0000
0x06 TEMP high limit [15:0] User-programmable TEMP high limit register 0x0000
0x07 TEMP low limit [15:0] User-programmable TEMP low limit register 0x0000
AD7879/AD7889
Rev. C | Page 25 of 40
Table 16. Measurement Result Registers (Read Only)
Address Register Name Data Bits Description Default Value
0x08 X+ [15:0] Measured X+ input with Y excitation (Y position) 0x0000
0x09 Y+ [15:0] Measured Y+ input with X excitation (X position) 0x0000
0x0A X+ (Z1) [15:0] Measured X+ input with X − and Y+ excitation (touch-pressure calculation Z1) 0x0000
0x0B Y− (Z2) [15:0] Measured Y − input with X− and Y+ excitation (touch-pressure calculation Z2) 0x0000
0x0C AUX/VBAT [15:0] AUX/VBAT voltage measurement 0x0000
0x0D TEMP [15:0] Temperature conversion measurement 0x0000
Table 17. Revision and Device ID Register (Read Only)
Address Data Bits Description Default Value
0x0E [15:12] Unused 0x0379 (AD7879-1/AD7889-1)
0x037A (AD7879/AD7889)
[11:8] Revision and device ID bits
[7:0] Device ID
AD7879/AD7889
Rev. C | Page 26 of 40
CONTROL REGISTERS
DISABLE
PENIRQ CHNL
ADD2 CHNL
ADD1 CHNL
ADD0 ADC
MODE1 ADC
MODE0 ACQ1 ACQ0 TMR7 TMR6 TMR5 TMR4 TMR3 TMR2 TMR1 TMR0
07667-029
15 0
Figure 30. Control Register 1
CONTROL REGISTER 1
Control Register 1 (Address 0x01) contains the ADC channel
address and the ADC mode bits. It sets the acquisition time and
the timer. It also contains a bit to disable the pen interrupt.
Control Register 1 should always be the last register programmed
prior to starting conversions. Its power-on default value is 0x0000.
To change any parameter after conversion has begun, the part
must first be put into ADC Mode 00. Make the changes, and
then reprogram Control Register 1, ensuring that it is always
the last register programmed before conversions begin.
Timer (Control Register 1, Bits[7:0])
The TMR bits in Control Register 1 set the conversion interval
timer, which enables the ADC to perform a conversion sequence
at regular intervals from 550 µs (00000001) up to 9.440 ms
(11111111) in increments of 35 µs (see Table 18). The default
value of these bits is 00000000, which enables the ADC to
perform one conversion only.
In slave mode, the timer starts as soon as the conversion sequence
is finished. In master mode, the timer starts at the end of a conver-
sion sequence only if the screen remains touched. If the touch is
released at any stage, the timer stops. The next time that the
screen is touched, a conversion sequence begins immediately.
Table 18. Timer Selection
TMR[7:0] Conversion Interval
00000000 Convert one time only (default)
00000001 Every 550 µs
00000010 Every 585 µs
00000011 Every 620 µs
… …
11111101 Every 9.370 ms
11111110 Every 9.405 ms
11111111 Every 9.440 ms
Acquisition Time (Control Register 1, Bits[9:8])
The ACQ bits in Control Register 1 allow the selection of acquisi-
tion times for the ADC of 2 µs (default), 4 µs, 8 µs, or 16 µs. The
user can program the ADC with an acquisition time suitable for
the type of signal being sampled. For example, signals with large
RC time constants can require longer acquisition times.
Table 19. Acquisition Time Selection
ACQ1 ACQ0 Acquisition Time
0 0 4 clock periods (2 µs)
0 1 8 clock periods (4 µs)
1 0 16 clock periods (8 µs)
1 1 32 clock periods (16 µs)
ADC Mode (Control Register 1, Bits[11:10])
The mode bits select the operating mode of the ADC. The
AD7879/AD7889 have three operating modes. These modes are
selected by writing to the mode bits in Control Register 1. If the
mode bits are set to 00, no conversion is performed.
Table 20. Mode Selection
ADC
MODE1
ADC
MODE0 Function
0 0 Do not convert (default)
0 1 Single-channel conversion; the device is
in slave mode
1 0 Sequence 0; the device is in slave mode
1 1 Sequence 1; the device is in master mode
If the mode bits are set to 01, a single conversion is performed
on the channel selected by writing to the channel bits of Control
Register 1 (Bits[14:12]). At the end of the conversion, if the TMR
bits in Control Register 1 are set to 00000000, the mode bits
revert to 00 and the ADC returns to no convert mode until a
new conversion is initiated by the host. Setting the TMR bits to
a value other than 00000000 causes the conversion to be repeated.
The AD7879/AD7889 can also be programmed to automatically
convert a sequence of selected channels. The two modes for this
type of conversion are slave mode and master mode.
For slave mode operation, the channels to be digitized are selected
by setting the corresponding bits in Control Register 3. Conversion
is initiated by writing 10 to the mode bits of Control Register 1.
The ADC then digitizes the selected channels and stores the
results in the corresponding result registers. At the end of the
conversion, if the TMR bits in Control Register 1 are set to
00000000, the mode bits revert to 00 and the ADC returns to no
convert mode until a new conversion is initiated by the host.
Setting the TMR bits to a value other than 00000000 causes the
conversion sequence to be repeated.
For master mode operation, the channels to be digitized are
written to Control Register 3. Master mode is then selected by
writing 11 to the mode bits in Control Register 1. In this mode,
the wake-up on touch feature is active; therefore, conversion
does not begin immediately. The AD7879/AD7889 wait until
the screen is touched before beginning the sequence of conver-
sions. The ADC then digitizes the selected channels, and the
results are written to the result registers. Before beginning
another sequence of conversions, the AD7879/AD7889 wait for
the screen to be touched again or for a timer event if the screen
remains touched.
AD7879/AD7889
Rev. C | Page 27 of 40
ADC Channel (Control Register 1, Bits[14:12])
The ADC channel address is selected by Bits[14:12] of Control
Register 1 (CHNL ADD2 to CHNL ADD0). A complete list of
channel addresses is given in Table 21.
For single-channel conversion, the channel address is selected
by writing the appropriate code to the CHNL ADD2 to CHNL
ADD0 bits in Control Register 1.
For sequential channel conversion, the channels to be converted
are selected by setting the bits corresponding to the channel
number in Control Register 3 for slave and master mode
sequencing.
For both single-channel and sequential conversion, a normal
conversion (single-ended) is selected by setting the SER/DFR
bit in Control Register 2 (Bit 9). Ratiometric (differential)
conversion is selected by clearing the SER/DFR bit.
PENIRQ Enable (Control Register 1, Bit 15)
The AD7879/AD7889 have a dual function output that performs
as PENIRQ or INT depending on the pen interrupt enable bit
(Bit 15 of Control Register 1). When this bit is set to 0, the pin
functions as a pen interrupt and goes low whenever the screen
is touched. When the pen interrupt enable bit is set to 1, the pen
interrupt request is disabled and the pin functions as an interrupt
when a measurement exceeds a preprogrammed limit (INT).
Table 21. Codes for Selecting Input Channel and Normal or Ratiometric Conversion
Channel SER/DFR CHNL ADD[2:0] Analog Input X Switches Y Switches REF+ REF−
0 0 111 X+ (Y position) Off On Y+ Y−
1 0 110 Y+ (X position) On Off X+ X−
2 0 101 X+ (Z1 touch pressure) X+ off, X− on Y+ on, Y− off Y+ X−
3 0 100 Y− (Z2 touch pressure) X+ off, X− on Y+ on, Y− off Y+ X−
4 0 011 AUX Off Off VCC GND
5 0 010 VBAT Off Off VCC GND
6 0 001 TEMP Off Off VCC GND
0 000 Invalid address
7 1 111 X+ (Y position) Off On VCC GND
8 1 110 Y+ (X position) On Off VCC GND
9 1 101 X+ (Z1 touch pressure) Off Off VCC GND
12 1 100 Y− (Z2 touch pressure) Off Off VCC GND
13 1 011 AUX Off Off VCC GND
14 1 010 VBAT Off Off VCC GND
15 1 001 TEMP Off Off VCC GND
1 000 Invalid address
AD7879/AD7889
Rev. C | Page 28 of 40
PM1 PM0 GPIO
EN GPIO
DAT GPIO
DIR GPIO
POL AVG1 AVG0 MED1 MED0 SW/
RST FCD3 FCD2 FCD1 FCD0
07667-030
015
SER/
DFR
Figure 31. Control Register 2
CONTROL REGISTER 2
Control Register 2 (Address 0x02) contains the ADC power
management bits, the GPIO settings, the SER/DFR bit (to
choose the single-ended or differential method of touch screen
measurement), the averaging and median filter settings, a bit
that allows resetting of the part, and the first conversion delay
bits. Its power-on default value is 0x4040. See the Detailed
Register Descriptions section for more information about the
control registers.
For information about the averaging and median filter settings,
see the Median and Averaging Filters section. For information
about the GPIO settings, see the GPIO section.
First Conversion Delay (Control Register 2, Bits[3:0])
The first conversion delay (FCD) bits in Control Register 2
program a delay from 128 µs (default) up to 4.096 ms before
the first conversion to allow the ADC time to power up. This
delay also occurs before conversion of the X and Y coordinate
channels to allow extra time for screen settling, and after the
last conversion in a sequence to precharge PENIRQ.
Table 22. First Conversion Delay Selection
FCD[3:0] Delay
0000 128 µs
0001 256 µs
0010 384 µs
0011 512 µs
0100 640 µs
0101 768 µs
0110 896 µs
0111 1.024 ms
1000 1.152 ms
1001 1.280 ms
1010 1.536 ms
1011 1.792 ms
1100 2.048 ms
1101 2.560 ms
1110 3.584 ms
1111 4.096 ms
Power Management (Control Register 2, Bits[15:14])
The power management (PM) bits in Control Register 2 allow
the power management features of the ADC to be programmed
(see Table 23). If the PM bits are set to 00, the ADC is in full
shutdown. This setting overrides any setting of the mode bits in
Control Register 1. Power management overrides the ADC modes.
Table 23. Power Management Selection
PM1 PM0 Function
0 0 Full shutdown; ADC, oscillator, bias, and temp-
erature sensor are turned off. The only way to
exit this mode is to write to the part over the
serial interface and change the PM bits. This
setting overrides any other setting on the
part, including the ADC mode bits.
0 1 The analog blocks to be powered down
depend on the ADC mode setting. In master
mode, the ADC, bias, temperature sensor, and
oscillator are powered down and must wake
up when the user touches the screen. In slave
mode, the ADC and temperature sensor are
powered down when not being used. They
wake up automatically when required. The
oscillator and bias are powered up because
they are needed to measure time. This setting
also applies to the single-conversion mode.
1 0 The ADC, bias, and oscillator are powered up
continuously, irrespective of ADC mode.
1 1 Same as 01.
AD7879/AD7889
Rev. C | Page 29 of 40
TEMP
MASK
AUX/
VBAT
MASK
INT
MODE GPIO
ALERT
AUX/
VBAT
LOW
AUX/
VBAT
HIGH
TEMP
HIGH X+ Y+ Z1 Z2 AUX VBAT TEMP NOT
USED
07667-031
015
TEMP
LOW
Figure 32. Control Register 3
CONTROL REGISTER 3
Control Register 3 (Address 0x03) includes the interrupt
register (Bits[15:8]) and the sequencer bits (Bits[7:0]).
Sequencer (Control Register 3, Bits[7:0])
The sequencer bits control which channels are converted during
a conversion sequence in both slave mode and master mode.
To include a measurement in a sequence, the relevant bit must
be set in the sequence. Setting Bit 7 includes a measurement on
the X+ channel (Y position). Setting Bit 6 includes a measure-
ment on the Y+ channel (X position), and so on (see Table 14).
Figure 32 illustrates the correspondence between the bits in
Control Register 3 and the various measurements. Bit 0 is
not used.
SLAVE MO DE
CONVERSION
SEQUENCE
TIMER = 00?
START TIMER
WAIT FOR TIMER
SINGLE
CONVERSION
MASTER MODE
WAIT FOR
FIRST TOUCH
CONVERSION
SEQUENCE
SCREEN
TOUCHED?
TIMER = 00?
START TIMER
WAIT FOR TIMER
SCREEN
TOUCHED?
IDLE
ADC MO DE ?
10
YES
YES
YES
NO
NO
YES
NO
NO
11
00
07667-032
01
Figure 33. Conversion Modes
FCD
REQ’D?
WAIT FOR
ACQUISITION
ACQ
SET CHANNEL
CONV E RT DATA
AVERAGE DATATRANSF E R DATA
TO REGISTERS
SET ALERT AND
INTERRUPT
1
MEDIAN # MEANS M E DIAN
FILT ER SIZ E.
RANK NEW
DATA
(WAIT t
SORT
)
MEDIAN
# OF SAMPLES
TAKEN?
1
NO
YES
07667-033
START O F
CONVERSION
SEQUENCE
FCD
FCD
MAV F ILTER
ENABLED
?
OUT-OF-
LIMIT?
END O F
SEQUENCE
?
YES
YES
YES
NO
NO
NO
YES
NO
Figure 34. Conversion Sequence
AD7879/AD7889
Rev. C | Page 30 of 40
INTERRUPTS
The AD7879/AD7889 have a dual function interrupt output,
INT, as well as a pen-down interrupt, PENIRQ. The INT output
can be configured as a data available interrupt (DAV), as an
out-of-limit interrupt (INT), or as a GPIO interrupt.
DAV—Data Available Interrupt
The behavior of the interrupt output is controlled by Bit 13 in
Control Register 3. In default mode (Bit 13 = 0), INT operates
as a data available interrupt (DAV). When the AD7879/AD7889
finish a conversion or a conversion sequence, the interrupt is
asserted to let the host know that new ADC data is available in
the result registers.
While the ADC is idle or is converting, DAV is high. When the
ADC has finished converting and new data has been written to
the result registers, DAV goes low. Reading the result registers
resets DAV to a high condition. DAV is also reset if a new con-
version is started by the AD7879/AD7889 because the timer
expired. The host should read the result registers only when
DAV is low. To ensure correct operation of the DAV mode
when using the SPI interface, it is necessary to write 0x0000
to Register 0x81 after a set of register reads. This clears the
internal data read signal.
ADC
CONVERTING
SETUP
BY HOST
IDLE NEW DATA
AVAILABLE HOST READS
RESULTS IDLE
t
CONV
AD7879/
AD7889
STATUS
DAV
07667-034
Figure 35. Operation of DAV Output
When the on-board timer is programmed to perform automatic
conversions, limited time is available to the host to read the
result registers before another sequence of conversions begins.
The DAV signal is reset high when the timer expires, and the
host should not access the result registers while DAV is high.
INT—Out-of-Limit Interrupt
The INT pin operates as an alarm or interrupt output when
Bit 13 in Control Register 3 (Address 0x03) is set to 1. The
output goes low if any one of the interrupt sources is asserted.
The results of high and low limit comparisons on the AUX,
VBAT, and TEMP channels are interrupt sources. An out-of-
limit comparison sets a status bit in the interrupt register. A
separate status bit for the high limit and the low limit on each
channel indicates which limit was exceeded. The interrupt
sources can be masked by setting the corresponding enable bit
in this register to 1. There is one enable bit per channel.
PENIRQ—Pen Interrupt
The pen interrupt request output (PENIRQ) goes low whenever
the screen is touched and the PENIRQ enable bit is set to 0
(Control Register 1, Bit 15). When PENIRQ enable is set to 1,
the pen interrupt request output is disabled.
The pen interrupt equivalent output circuitry is shown in
Figure 36. This digital logic output has an internal 50 kΩ pull-
up resistor, so it does not need an external pull-up. The
PENIRQ output idles high, and the PENIRQ circuitry is always
enabled in master mode (ADC mode = 11), except during
conversions.
07667-035
X+
TOUCH
SCREEN
Y+
50kΩ
Y–
X–
PENIRQ
ENABLE
PENIRQ
V
CC
V
CC
Figure 36. PENIRQ Output Equivalent Circuit
When the screen is touched, PENIRQ goes low. This generates
an interrupt request to the host. When the screen touch ends,
PENIRQ immediately goes high if the ADC is idle. If the ADC
is converting, PENIRQ goes high when the ADC becomes idle.
The PENIRQ operation for these two conditions is shown in
Figure 37.
07667-036
SCREEN
PENIRQ
ADC
STATUS
TOUCHED NOT
TOUCHED
NOT
TOUCHED
NOT
TOUCHED
NOT
TOUCHED
ADC IDL E
SCREEN
PENIRQ
ADC
STATUS
TOUCHED
ADC IDL E ADC
CONVERTING ADC IDLE
RELEASE NOT
DETECTED
PENIRQ
DETECTS
RELEASE
PENIRQ
DETECTS
RELEASE
PENIRQ
DETECTS
TOUCH
PENIRQ
DETECTS
TOUCH
Figure 37. PENIRQ Operation for ADC Idle and ADC Converting
AD7879/AD7889
Rev. C | Page 31 of 40
SYNCHRONIZING THE AD7879/AD7889 TO THE
HOST CPU
The two methods for synchronizing the AD7879/AD7889 to its
host CPU are slave mode (in which the mode bits are set to 01
or 10) and master mode (in which the mode bits set to 11).
In master mode (ADC mode bits = 11), PENIRQ can be used
as an interrupt to the host. When PENIRQ goes low to indicate
that the screen has been touched, the host is awakened. The
host can then program the AD7879/AD7889 to convert in any
mode and read the results after the conversions are completed.
In master mode, INT or DAV can also be used as an interrupt to
the host. The host should first define a conversion sequence in
Control Register 3, initialize the AD7879/AD7889 in Mode 11,
and enable INT or DAV using Bit 15 in Control Register 1 and
Bit 13 in Control Register 3. The host can then enter sleep mode
to conserve power. The wake-up on touch feature of the
AD7879/AD7889 is active in this mode; therefore, when the
screen is touched, the programmed sequence of conversions
automatically begins. When the INT or DAV signal is asserted,
the host reads the new data available in the AD7879/AD7889
result registers and returns to sleep mode. This method can
significantly reduce the load on the host.
Figure 38 shows how the PENIRQ circuit is enabled. The wake-up
on touch circuit and the PENIRQ circuit are enabled only in master
mode (ADC mode = 11). In slave mode, the PENIRQ/INT/DAV
pin can output only INT or DAV signals.
ADC MO DE = 11?
MASTER MODE
0
1
0
1
DAV
(END OF CONVE RS ION S E QUENCE )
INT
(GPIO ALERT/OUT OF LIMITS)
INT/DAV/GPIOALERT
TOUCH SCREE N TOUCHED
CONTROL REGIST ER 3
BIT 13
CONTROL REGIST ER 1
BIT 15
PENIRQ/INT/DAV PIN
TO THE DIGITAL CORE
ENABLE
WAKE-UP
ON TOUCH
ENABLE
PENIRQ
DETECTION
CIRCUIT
TOUCH SCREE N TOUCHED
YES YES
07667-037
Figure 38. Master Mode Operation
AD7879/AD7889
Rev. C | Page 32 of 40
SERIAL INTERFACE
The AD7879 and AD7879-1 (and the AD7889 and AD7889-1)
differ only in the serial interface provided on the part. The
AD7879 and the AD7889 are available with a serial peripheral
interface (SPI). The AD7879-1 and the AD7889-1 are available
with an I2C-compatible interface. It is recommended that
addresses outside the register map not be written to.
SPI INTERFACE
The AD7879/AD7889 have a 4-wire SPI. The SPI has a data
input pin (DIN) for inputting data to the device, a data output
pin (DOUT) for reading data back from the device, and a data
clock pin (SCL) for clocking data into and out of the device. A
chip select pin (CS) enables or disables the serial interface. CS is
required for correct operation of the SPI interface. Data is
clocked out of the AD7879/AD7889 on the falling edge of SCL,
and data is clocked into the device on the rising edge of SCL.
SPI Command Word
All data transactions on the SPI bus begin with the master
taking CS from high to low and sending out the command
word. This indicates to the AD7879/AD7889 whether the
transaction is a read or a write and gives the address of the
register from which to begin the data transfer. The bit map in
Table 24 shows the SPI command word.
Table 24. SPI Command Word
MSB LSB
15 14 13 12 11 10 [9:0]
1 1 1 0 0 R/W Register address
Bits[15:11] of the command word must be set to 11100 to
successfully begin a bus transaction.
Bit 10 is the read/write bit; 1 indicates a read, and 0 indicates
a write.
Bits[9:0] contain the target register address. When reading or
writing to more than one register, this address indicates the
address of the first register to be written to or read from.
Writing Data
Data is written to the AD7879/AD7889 in 16-bit words. The
first word written to the device is the command word, with the
read/write bit set to 0. The master then supplies the 16-bit input
data-word on the DIN line. The AD7879/AD7889 clock the
data into the register addressed in the command word. If there
is more than one word of data to be clocked in, the AD7879/
AD7889 automatically increment the address pointer and clock
the next data-word into the following register.
The AD7879/AD7889 continue to clock in data on the DIN line
until the master ends the write transition by pulling CS high or
until the address pointer reaches its maximum value. The AD7879/
AD7889 address pointer does not wrap. When the address
pointer reaches its maximum value, any data provided by the
master on the DIN line is ignored by the AD7879/AD7889.
NOTES
1. DATA BITS ARE LATCHE D ON SCL RIS ING E DGES . SCL CAN IDL E HIGH OR L OW BE TWE E N WRI TE O P E RATI ONS.
2. ALL 32 BIT S M US T BE W RIT TEN: 16 BIT S FO R THE CO M M AND WO RD AND 16 BITS FO R DATA.
3. 16-BIT COMMAND WORD SETTINGS FOR SINGLE WRITE OPERATION:
CW[ 15: 11] = 11100 ( E NABLE WO RD)
CW[ 10] = 0 ( R/W )
CW[ 9: 0] = [ AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (10- BIT M S B JUS TI FIE D RE GI S TER ADDRES S )
CW
11 CW
10
CW
13 CW
12
DIN
CW
15 CW
14 CW
9CW
7CW
6CW
5CW
4CW
3CW
2CW
1CW
0D2 D1 D0
CW
8
t
4
t
8
16-BI T COM M AND WO RD
16-BI T DATA
5326 7 8 9 10 11 12 13 14 15 16 30 31
SCL
1 2 3 4
D15 D14 D13
17 18 19
CS
ENABL E WORD R/W REGISTER ADDRESS
07667-038
t
2
t
1
t
3
t
5
Figure 39. Single Register Write, SPI Timing
AD7879/AD7889
Rev. C | Page 33 of 40
DIN
CW
15 CW
14 CW
13 CW
8CW
1CW
0D15 D14
SCL
CW
12
NOTES
1. M ULTIPLE SE QUENTIAL REGI S TERS CAN BE LO ADE D CONTINUO US LY.
2. THE FIRST (LOWEST ADDRESS) REGISTER ADDRESS IS WRITTEN, FOLLOWED BY MULTIPLE 16-BIT DATA-WORDS.
3. THE ADDRES S AUTO M ATICALL Y INCREME NTS WI TH EACH 16-BIT DATA-W ORD (ALL 16 BITS M US T BE WRITT E N) .
4. CS IS HELD L OW UNTI L THE LAST DES IRED REGI S TER HAS BE E N LO ADE D.
5. 16-BIT COMMAND WORD SETTINGS FOR SEQUENTIAL WRITE OPERATION:
CW[ 15: 11] = 11100 ( E NABLE WO RD)
CW[ 10] = 0 ( R/W )
CW[ 9: 0] = [ AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (S TART ING M S B JUS TIFI E D RE GIS TER ADDRE S S )
D1 D0D1 D0 D15
DATA FOR STARTING
REGISTER ADDRESS DATA FO R NE X T
REGISTER ADDRESS
D15D14
132
234 15 16 17 18 31 3433 4847 49
CS
CW
11 CW
10 CW
9CW
7CW
2
CW
6CW
5CW
4CW
3
11 12 13 14
5678910
16-BI T COM M AND WO RD
ENABL E WORD R/W STARTING REGISTERADDRESS
07667-039
Figure 40. Sequential Register Write, SPI Timing
NOTES
1. DATA BITS ARE LATCHE D ON SCL RIS ING E DGES . SCL CAN IDL E HIGH OR L OW BE TWE E N WRI TE O P E RATI ONS.
2. THE 16-BIT COMMAND WO RD M US T BE W RIT TEN ON DIN: 5 BIT S FOR E NABLE WO RD, 1 BIT F OR R/W, AND 10 BIT S FOR RE GI S TER ADDRES S .
3. THE REGI S TER DAT A IS RE AD BACK ON THE DOUT P IN.
4. X DE NOTE S DON’ T CARE.
5. XXX DENOTES HIGH IMPEDANCE THREE-STATE OUTPUT.
6. CS IS HELD L OW UNTI L ALL REGI S TER BI TS HAV E BE E N RE AD BACK.
7. 16- BIT COMM AND WORD S E TT INGS FO R S ING LE READBACK OPE RATION:
CW[ 15: 11] = 11100 ( E NABLE WO RD)
CW[ 10] = 1 ( R/W )
CW[ 9: 0] = [ AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (10- BIT M S B JUS TI FIE D RE GI S TER ADDRES S )
CW
11 CW
10
CW
13 CW
12
DIN
CW
15 CW
14 CW
9CW
7CW
6CW
5CW
4CW
3CW
2CW
1CW
0X X X
CW
8
16-BI T READBACK DATA
5326 7 8 9 10 11 12 13 14 15 16 30 31
SCL
1234
X X X
17 18 19
CS
XXX XXXXXX XXX
DOUT
XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX D2 D1 D0
XXX D15 D14 D13 XXX
16-BI T COM M AND WO RD
ENABL E WORD R/W REGISTER ADDRESS
t4t5
t1t3
t2
t6t7
t8
07667-040
Figure 41. Single Register Readback, SPI Timing
Reading Data
A read transaction begins when the master writes the command
word to the AD7879/AD7889 with the read/write bit set to 1. The
master then supplies 16 clock pulses per data-word to be read,
and the AD7879/AD7889 clock out data from the addressed
register on the DOUT line. The first data-word is clocked out
on the first falling edge of SCL following the command word,
as shown in Figure 41.
The AD7879/AD7889 continue to clock out data on the DOUT
line provided that the master continues to supply the clock signal
on SCL. The read transaction ends when the master takes CS high.
If the AD7879/AD7889 address pointer reaches its maximum
value, the AD7879/AD7889 repeatedly clock out data from the
addressed register. The address pointer does not wrap.
AD7879/AD7889
Rev. C | Page 34 of 40
07667-041
DIN CW
15 CW
14 CW
13 CW
8CW
1CW
0X X
SCL
CW
12 X XX X X
READBACK DAT A FOR
STARTING REGISTER
ADDRESS
XX
132234 15 16 17 18 31 3433 4847 49
CS
CW
11 CW
10 CW
9CW
7CW
2
CW
6CW
5CW
4CW
3
11 12 13 145678910
XXX XXX XXX XXX D15 D14 D1 D0D1 D0 D15 D15D14
XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX
DOUT
16-BI T COM M AND WO RD
ENABL E WORD R/W S TARTING RE GIS TER ADDRE S S
NOTES
1. M ULTIPLE SE QUENTIAL REGI S TERS CAN BE RE AD BACK CONT INUOUS LY.
2. THE 16-BIT COMMAND WO RD M US T BE W RIT TEN ON DIN: 5 BIT S FOR E NABLE WO RD, 1 BIT F OR R/W, AND 10 BIT S FOR RE GI S TER ADDRES S .
3. THE ADDRES S AUTO M ATICALL Y INCREME NTS WI TH EACH 16-BIT DATA-W ORD BEING RE AD BACK ON THE DOUT P IN.
4. CS IS HELD L OW UNTI L ALL REGI S TER BI TS HAV E BE E N RE AD BACK.
5. X DE NOTE S DON’ T CARE.
6. XXX DENOTES HIGH IMPEDANCE THREE-STATE OUTPUT.
7. 16- BIT COMM AND WORD S E TT INGS FO R S E QUENTIAL READBACK OPERATI ON:
CW[ 15: 11] = 11100 ( E NABLE WO RD)
CW[ 10] = 1 ( R/W )
CW[ 9: 0] = [ AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (S TART ING M S B JUS TIFI E D RE GIS TER ADDRE S S )
READBACK DAT A FOR
NEXT REG ISTER ADDRES S
Figure 42. Sequential Register Readback, SPI Timing
I2C-COMPATIBLE INTERFACE
The AD7879-1/AD7889-1 support the industry standard 2-wire
I2C serial interface protocol. The two wires associated with the
I2C timing are the SCL and SDA inputs. SDA is an I/O pin that
allows both register write and register readback operations. The
AD7879-1/AD7889-1 are always slave devices on the I2C serial
interface bus.
The devices have a 7-bit device address, Address 0101 1XX. The
lower two bits are set by tying the ADD0 and ADD1 pins high or
low. The AD7879-1/AD7889-1 respond when the master device
sends its device address over the bus. The AD7879-1/AD7889-1
cannot initiate data transfers on the bus.
Table 25. I2C Device Addresses for the AD7879-1/AD7889-1
ADD1 ADD0 I2C Address
0 0 0101 100
0 1 0101 101
1 0 0101 110
1 1 0101 111
Data Transfer
Data is transferred over the I2C serial interface in 8-bit bytes.
The master initiates a data transfer by establishing a start
condition, defined as a high-to-low transition on the serial data
line, SDA, while the serial clock line, SCL, remains high. This
indicates that an address/data stream follows.
All slave peripherals connected to the serial bus respond to the
start condition and shift in the next eight bits, consisting of a
7-bit address (MSB first) plus a R/W bit that determines the
direction of the data transfer. The peripheral whose address
corresponds to the transmitted address responds by pulling the
data line low during the ninth clock pulse. This is known as the
acknowledge bit. All other devices on the bus then remain idle
while the selected device waits for data to be read from or written
to it. If the R/W bit is a 0, the master writes to the slave device.
If the R/W bit is a 1, the master reads from the slave device.
Data is sent over the serial bus in a sequence of nine clock
pulses (eight bits of data followed by an acknowledge bit from
the slave device). Transitions on the data line must occur during
the low period of the clock signal and remain stable during the
high period because a low-to-high transition when the clock
is high can be interpreted as a stop signal. The number of data
bytes transmitted over the serial bus in a single read or write
operation is limited only by what the master and slave devices
can handle.
When all data bytes are read or written, a stop condition is
established. A stop condition is defined by a low-to-high
transition on SDA while SCL remains high. If the AD7879-1/
AD7889-1 encounter a stop condition, they return to the idle
condition.
AD7879/AD7889
Rev. C | Page 35 of 40
NOTES
1. A S TART CONDI TION AT THE BEGI NNING IS DEFI NE D AS A HIGH- TO - LO W TRANS IT ION ON SDA WHI LE SCL REM AINS HI GH.
2. A S TOP CONDI TION AT THE END IS DE FI NE D AS A LOW-TO- HIG H TRANSITIO N ON SDA W HIL E S CL REM AINS HI GH.
3. 7- BIT DE V ICE ADDRE S S [ DE V A6: DE V A0] = [ 01011X X ] , WHE RE THE X s ARE DON'T CARE BITS .
4. RE GIS TER DATA [D15:D8] AND RE GI S TER DAT A [ D7: D0] ARE ALW AY S S E P ARATED BY A LOW ACK BI T.
SDA DEV
A6 DEV
A5 DEV
A4 R/W
SCL
DEV
A3
1 2 3 4 17
DEV
A2 DEV
A1 DEV
A0 ACK A7 A6
11 16
5 6 7 8 910
STARTAD7879- 1/AD7889-1 DEV ICE ADDRESS
A1 A0
REGISTER ADDRESS[A7:A0]
D15 D14 D9 D8
2618 19 20 25 2827 3429 35
D1 D0
D7 D6
REG IST E R DATA[D15: D8] REGIST ER DATA[D7:D0]
ACK ACK
36 37
ACK
STOP
DEV
A6 DEV
A5 DEV
A4
1 2 3
START
t
1
AD7879-1/AD7889-1
DEVICE ADDRESS
07667-042
t
3
t
2
t
4
t
5
t
6
t
8
t
7
Figure 43. Example of I2C Timing for Single Register Write Operation
Writing Data over the I2C Bus
The process of writing to the AD7879-1/AD7889-1 over the I2C
bus is shown in Figure 43 and Figure 45. The device address is
sent over the bus followed by the R/W bit set to 0. This is followed
by one byte of data that contains the 8-bit address of the internal
data register to be written. The bit map in Table 26 shows the
register address byte.
Table 26. I2C Register Address Byte
MSB LSB
7 6 5 4 3 2 1 0
Register Address
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
The third data byte contains the eight MSBs of the data to be
written to the internal register. The fourth data byte contains
the eight LSBs of data to be written to the internal register.
The AD7879-1/AD7889-1 address pointer register automatically
increments after each write. This allows the master to sequentially
write to all registers on the AD7879-1/AD7889-1 in the same
write transaction. However, the address pointer register does
not wrap after the last address.
Any data written to the AD7879-1/AD7889-1 after the address
pointer has reached its maximum value is discarded.
All registers on the AD7879-1/AD7889-1 have 16 bits. Two
consecutive 8-bit data bytes are combined and written to the
16-bit registers. To avoid errors, all writes to the device must
contain an even number of data bytes.
To end the transaction, the master generates a stop condition on
SDA, or it generates a repeat start condition if the master is to
maintain control of the bus.
Reading Data over the I2C Bus
To read from the AD7879-1/AD7889-1, the address pointer
register must first be set to the address of the required internal
register. The master performs a write transaction and writes to
the AD7879-1/AD7889-1 to set the address pointer. The master
then outputs a repeat start condition to keep control of the bus
or, if this is not possible, the master ends the write transaction
with a stop condition. A read transaction is initiated, with the
R/W bit set to 1.
The AD7879-1/AD7889-1 supply the upper eight bits of data
from the addressed register in the first readback byte, followed
by the lower eight bits in the next byte. This is shown in Figure 44
and Figure 45.
Because the address pointer automatically increments after each
read, the AD7879-1/AD7889-1 continue to output readback data
until the master puts a no acknowledge and a stop condition on
the bus. If the address pointer reaches its maximum value and
the master continues to read from the part, the AD7879-1/
AD7889-1 repeatedly send data from the last register addressed.
AD7879/AD7889
Rev. C | Page 36 of 40
NOTES
1. A S TART CONDI TION AT THE BE GINNING IS DEFI NE D AS A HIGH- TO - LO W TRANS IT ION ON SDA WHI LE SCL REM AINS HI GH.
2. A S TOP CONDI TION AT THE E ND IS DEFI NE D AS A LOW-TO- HIG H TRANSITIO N ON SDA W HIL E S CL REM AINS HI GH.
3. THE MAS TER GENERATES THE ACK AT THE E ND OF THE READBACK TO S IGNAL T HAT I T DOE S NOT WANT ADDIT IO NAL DATA.
4. 7- BIT DE V ICE ADDRE S S [ DE V A6: DE V A0] = [ 01011X X ] , WHE RE THE TWO L S B X s ARE DON'T CARE BIT S .
5. RE GIS TER DATA [D15:D8] AND RE GI S TER DATA [D7:D0] ARE ALW AY S S E P ARATED BY A LO W ACK BIT.
6. THE R/ W BI T IS S E T T O 1 T O INDICAT E A RE ADBACK OPERATI ON.
SDA
DEV
A6 DEV
A5 DEV
A4 R/W
SCL
DEV
A3
1234 17 18
DEV
A2 DEV
A1 DEV
A0 ACK A7 A6
11 16
5678910
START AD7879-1/AD7889-1
DEVICE ADDRESS
A1 A0
REGISTER ADDRESS[A7:A0]
ACK
26
19 21 25 2827 3529 36
D1 D0
D7 D6
REGISTER DATA[D7:D0]
SR
ACK
37
P
DEV
A6 DEV
A5 DEV
A4
12 3
t
2
AD7879-1/AD7889-1
DEVICE ADDRESS
AD7879-1/AD7889-1
DEVICE ADDRESS
DEV
A6 DEV
A5 DEV
A1 DEV
A0
07667-043
R/W
20 30
26
19 21 25 2827 3529 36
D1 D0
D7 D6
REGISTER DATA[D7:D0]
S
ACK
37
P
AD7879-1/AD7889-1
DEVICE ADDRESS
DEV
A6 DEV
A5 DEV
A1 DEV
A0 R/W
20 30
P
USING
REPEATED
START
SEPARATE
READ AND
WRITE
TRANSACTIONS
ACK
ACK
t
1
t
3
t
4
t
4
t
5
t
5
t
6
t
8
t
7
Figure 44. Example of I2C Timing for Single Register Readback Operation
7-BI T DEVICE
ADDRESS 7- BIT DE V ICE
ADDRESS
REG IST E R ADDR
[7:0] RE AD DATA
HIGH BYT E [ 15: 8] READ DAT A
LOW BYTE [7:0] READ DAT A
HIGH BYT E [ 15: 8] READ DAT A
LOW BYTE [7:0]
W
S P S R P
ACK
ACK
ACK
ACK
ACK
. . .
ACK
READ (WRITE TRANSACT IO N S E TS UP RE GI S TER ADDRE S S )
7-BI T DEVICE
ADDRESS 7- BIT DE V ICE
ADDRESS
REG IST E R ADDR
[7:0] RE AD DATA
HIGH BYT E [ 15: 8] READ DATA
LOW BYTE [7:0] READ DAT A
HIGH BYT E [ 15: 8] READ DAT A
LOW BYTE [7:0]
W
S R P
ACK
ACK
ACK
SR
ACK
ACK
. . .
ACK
READ (US ING RE P E ATED S TART)
S7-BI T DEVICE
ADDRESS RE GIS TER ADDR
[7:0] WRITE DATA
HIGH BYT E [ 15: 8] W RIT E DATA
LOW BYTE [7:0] W RITE DATA
HIGH BYT E [ 15: 8] WRITE DATA
LOW BYTE [7:0]
WP
ACK
ACK
ACK
ACK
ACK
. . .
WRITE
OUTPUT FROM MASTER
OUTPUT FROM
AD7879-1/AD7889-1
S = START BIT
P = STOP BIT
SR = REP E ATED S TART BIT
R = READ BI T
W = WRITE BIT
ACK = ACKNOWL E DGE BIT
ACK = NO ACKNOW LEDGE BI T
07667-044
Figure 45. Example of Sequential I2C Write and Readback Operation
AD7879/AD7889
Rev. C | Page 37 of 40
GROUNDING AND LAYOUT
For detailed information on grounding and layout considerations
for the AD7879/AD7889, refer to the AN-577 Application Note,
Layout and Grounding Recommendations for Touch Screen
Digitizers.
LEAD FRAME CHIP SCALE PACKAGES
The lands on the lead frame chip scale package (CP-16-10) are
rectangular. The printed circuit board (PCB) pad for these lands
should be 0.1 mm longer than the package land length and
0.05 mm wider than the package land width. Center the land on
the pad to maximize the solder joint size.
The bottom of the lead frame chip scale package has a central
thermal pad. The thermal pad on the PCB should be at least as
large as this exposed pad. To avoid shorting, provide a clearance
of at least 0.25 mm between the thermal pad and the inner
edges of the land pattern on the PCB. Thermal vias can be used
on the PCB thermal pad to improve the thermal performance of
the package. If vias are used, incorporate them into the thermal
pad at a 1.2 mm pitch grid. The via diameter should be between
0.3 mm and 0.33 mm, and the via barrel should be plated with
1 oz. of copper to plug the via.
Connect the PCB thermal pad to GND.
WLCSP ASSEMBLY CONSIDERATIONS
For detailed information on the WLCSP PCB assembly and
reliability, see the AN-617 Application Note, MicroCSP™ Wafer
Level Chip Scale Package.
NC = NO CONNECT
1Y+
2NC
3NC
4X–
11
NC
12
10
NC
9
DOUT
5678
15
16 14 13
07667-045
AD7879/
AD7889
PENIRQ/INT/DAV
Y–
DIN
GND
SCL
V
CC
/REF
X+
AUX/
VBAT/
GPIO
CS
TOUCH
SCREEN
0.1µF 0.1µF TO 10µF
(OPTIONAL)
VOLTAGE
REGULATOR MAIN
BATTERY
INT
SCLK
MISO
MOSI
SPI
INTERFACE
HOST
CS
Figure 46. Typical Application Circuit
AD7879/AD7889
Rev. C | Page 38 of 40
OUTLINE DIMENSIONS
120808-A
A
B
C
D
1
2
3
BOTTOM VI EW
(BALL SIDE UP)
TOP VIEW
(BALL SI DE DOW N)
0.36
0.32
0.28
0.17
0.15
0.13
1.50
REF
BALL 1
IDENTIFIER
SEATING
PLANE
0.50
REF
0.37
0.35
0.33 0.28
0.24
0.20
0.10 M AX
COPLANARITY
1.67
1.61
1.55
2.07
2.01
1.95
0.65
0.59
0.53
Figure 47. 12-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-12-1)
Dimensions shown in millimeters
010410-A
A
B
C
D
0.650
0.59
5
0.540
1.555
1.505
1.455
2.055
2.005
1.955
1
2
3
BOTTOMVIEW
(BALLSIDEUP)
TOP VIEW
(BALL SIDE DOWN)
0.340
0.320
0.300
1.50
REF
BALL 1
IDENTIFIER
SEATING
PLANE
1.00
REF
0.50
REF
0.380
0.355
0.330
0
.040 MAX
0.020 MIN
0.270
0.240
0.210
0.10 MAX
COPLANARITY
Figure 48. 12-Ball, Backside-Coated Wafer Level Chip Scale Package [WLCSP]
(CB-12-5)
Dimensions shown in millimeters
16
5
13
8
9
12 1
4
1.95 BS C
PI N 1
INDICATOR TOP
VIEW
4.00
BSC SQ
3.75
BSC SQ
COPLANARITY
0.08
EXPOSED
PAD
(BOTTOM VIEW)
COMPLIANT TO JEDE C S TANDARDS MO-220- V GG C
12° M AX
1.00
0.85
0.80 SEATING
PLANE
0.35
0.30
0.25
0.80 M AX
0.65 TYP0. 05 M AX
0.02 NOM
0.20 RE F
0.65 BS C
0.60 M AX 0.60 MAX
PI N 1
INDICATOR
0.50
0.40
0.30 0.25 MI N
2.50
2.35 S Q
2.20
082008-A
FOR PRO P E R CONNECTION O F
THE EXPOSED PAD, REFER TO
THE P IN CONFI GURATIO N AND
FUNCTION DES CRIPT IO NS
SECTION OF THIS DATA SHEET.
Figure 49. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm, Very Thin Quad
(CP-16-10)
Dimensions shown in millimeters
AD7879/AD7889
Rev. C | Page 39 of 40
ORDERING GUIDE
Model1
Temperature
Range
Serial Interface
Description Package Description
Package
Option Branding
AD7879ACBZ-RL −40°C to +85°C SPI Interface 12-Ball WLCSP CB-12-1 T2Y
AD7879ACBZ-500R7 −40°C to +85°C SPI Interface 12-Ball WLCSP CB-12-1 T2Y
AD7879ACPZ-RL −40°C to +85°C SPI Interface 16-Lead LFCSP_VQ CP-16-10
AD7879ACPZ-500R7 −40°C to +85°C SPI Interface 16-Lead LFCSP_VQ CP-16-10
AD7879-1ACBZ-RL −40°C to +85°C I2C Interface 12-Ball WLCSP CB-12-1 T0Q
AD7879-1ACBZ-500R7 −40°C to +85°C I2C Interface 12-Ball WLCSP CB-12-1 T0Q
AD7879-1ACPZ-RL −40°C to +85°C I2C Interface 16-Lead LFCSP_VQ CP-16-10
AD7879-1ACPZ-500R7 −40°C to +85°C I2C Interface 16-Lead LFCSP_VQ CP-16-10
AD7889ACBZ-RL −40°C to +85°C SPI Interface 12-Ball, Backside-Coated WLCSP CB-12-5 T3R
AD7889ACBZ-500R7 −40°C to +85°C SPI Interface 12-Ball, Backside-Coated WLCSP CB-12-5 T3R
AD7889-1ACBZ-RL −40°C to +85°C I2C Interface 12-Ball, Backside-Coated WLCSP CB-12-5 T3Q
AD7889-1ACBZ-RL7 −40°C to +85°C I2C Interface 12-Ball, Backside-Coated WLCSP CB-12-5 T3Q
AD7889-1ACBZ-500R7 −40°C to +85°C I2C Interface 12-Ball, Backside-Coated WLCSP CB-12-5 T3Q
EVAL-AD7879EBZ SPI Interface Evaluation Board
EVAL-AD7879-1EBZ I2C Interface Evaluation Board
1 Z = RoHS Compliant Part.
AD7879/AD7889
Rev. C | Page 40 of 40
NOTES
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2008–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07667-0-11/10(C)