REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
a
AD13465
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2001
Dual Channel, 14-Bit, 65 MSPS A/D Converter
with Analog Input Signal Conditioning
FUNCTIONAL BLOCK DIAGRAM
100⍀ OUTPUT TERMINATORS
TIMING 3
11 14
14
ENC
ENC
D9A
D10A
D11A D0B
(LSB)
D1B D3BD2B D4B D5B D6B
D9B
D10B
TIMING
D11B
9
5
ENC
ENC
B–IN
D12B
D13B (MSB)
(LSB) D0A
D1A
D2A
D3A
D4A
D5A
D6A
D7A
D8A
AD13465
DROUTA
100⍀ OUTPUT TERMINATORS
AMP-IN-B-2 AMP-IN-B-1
AMP-IN-A-2 AMP-IN-A-1
AMP-OUT-A
A–IN
A+IN B+IN
AMP-OUT-B
DROUTB
DROUT
VREF
D13A
(MSB)
D12A D8B
D7B
VREF
DROUT
FEATURES
Dual, 65 MSPS Minimum Sample Rate
Channel-to-Channel Matching, ⴞ1% Gain Error
90 dB Channel-to-Channel Isolation
DC-Coupled Signal Conditioning
85 dB Spurious-Free Dynamic Range
Selectable Bipolar Inputs
(ⴞ1 V and ⴞ0.5 V Ranges)
Integral Two-Pole Low-Pass Nyquist Filter
Two’s Complement Output Format
3.3 V Compatible Outputs
1.8 W per Channel
Industrial and Military Grade
APPLICATIONS
Radar Processing
Optimized for I/Q Baseband Operation
Phased Array Receivers
Multichannel, Multimode Receivers
GPS Antijamming Receivers
Communications Receivers
PRODUCT DESCRIPTION
The AD13465 is a complete dual channel signal processing
solution including on-board amplifiers, references, ADCs,
and output termination components to provide optimized
system performance. The AD13465 has on-chip track-and-hold
circuitry and utilizes an innovative multipass architecture to
achieve 14-bit, 65 MSPS performance. The AD13465 uses
state-of-the-art high-density circuit design and laser-trimmed
thin-film resistor networks to achieve exceptional channel
matching and impedance control, and provide for significant
board area savings.
Multiple options are provided for driving the analog input, includ-
ing single-ended, differential, and optional series filtering. The
AD13465 also offers the user a choice of analog input signal
ranges to further minimize additional external signal condition-
ing, while remaining general-purpose. The AD13465 operates
with ±5.0 V for the analog signal conditioning, 5.0 V supply for
the analog-to-digital conversion, and 3.3 V digital supply for
the output stage. Each channel is completely independent, allow-
ing operation with independent Encode and Analog Inputs, while
maintaining minimal crosstalk and interference.
The AD13465 is packaged in a 68-lead ceramic gull wing
package. Manufacturing is done on Analog Devices’ MIL-
38534 Qualified Manufacturers Line (QML) and components
are available up to Class-H (–40°C to +85°C). The components
are manufactured using Analog Devices’ high-speed comple-
mentary bipolar process (XFCB).
PRODUCT HIGHLIGHTS
1. Guaranteed sample rate of 65 MSPS.
2. Input signal conditioning included; gain and impedance
matching.
3. Single-ended, differential, or off-module filter options.
4. Fully tested/characterized full channel performance
5. Pin compatible with 12-bit AD13280 product family.
REV. 0
–2–
AD13465–TARGET SPECIFICATIONS
(AVCC = 5 V; AVEE = –5 V; DVCC = 3.3 V applies to each ADC with Front
End Amplifier unless otherwise noted.)
Test Mil Sub- AD13465AZ/BZ
Parameter Temp Level Group Min Typ Max Unit
RESOLUTION 14 Bits
DC ACCURACY
No Missing Codes Full IV 12 Guaranteed
Offset Error 25°C I 1 –2.2 ±0.2 +2.2 % FS
Full VI 2, 3 –2.2 ±1.0 +2.2 % FS
Offset Error Channel Match Full VI 1, 2, 3 –1.0 ±0.1 +1.0 % FS
Gain Error
1
25°C I 1 –3.0 –1.0 +1.0 % FS
Full VI 2, 3 –5.0 ±2.0 +5.0 % FS
Gain Error Channel Match 25°C I 1 +1.5 ±0.5 +1.5 % FS
Max VI 2 –3.0 ±1.0 +3.0 % FS
Min VI 3 –5.0 ±1.0 +5.0 % FS
SINGLE-ENDED ANALOG INPUT
Input Voltage Range
AMP-IN-X-1 Full V ±0.5 V
AMP-IN-X-2 Full V ±1.0 V
Input Resistance
AMP-IN-X-1 Full IV 12 99 100 101 Ω
AMP-IN-X-2 Full IV 12 198 200 202 Ω
Input Capacitance
2
4.0 7.0 pF
Analog Input Bandwidth
3
Full V 100 MHz
DIFFERENTIAL ANALOG INPUT
Analog Signal Input Range
A+IN to A–IN and B+IN to B–IN
4
Full V ±1.0 V
Input Impedance Full V 618 Ω
Analog Input Bandwidth
3
Full V 50 MHz
ENCODE INPUT (ENC, ENC)
5
Differential Input Voltage Full IV 12 0.4 V p-p
Differential Input Resistance 25°CV 10 kΩ
Differential Input Capacitance 25°C V 2.5 pF
SWITCHING PERFORMANCE
Maximum Conversion Rate
6
Full VI 4, 5, 6 65 MSPS
Minimum Conversion Rate
6
Full IV 12 20 MSPS
Aperture Delay (t
A
)25°C V 1.5 ns
Aperture Delay Matching 25°C IV 12 250 500 ps
Aperture Uncertainty (Jitter) 25°C V 0.3 ps rms
ENCODE Pulse with High 25°C IV 12 5.0 7.7 9.5 ns
ENCODE Pulse with Low 25°C IV 12 5.0 7.7 9.5 ns
Output Delay (t
OD
) Full IV 12 7.5 ns
Encode, Rising to Data Ready, Full V 11.5 ns
Rising Delay
SNR
7
Analog Input @ 4.98 MHz 25°C V 72 dBFS
Analog Input @ 9.9 MHz 25°C I 4 70 72 dBFS
Full II 5, 6 69 71 dBFS
Analog Input @ 21 MHz 25°C I 4 69 71 dBFS
Full II 5, 6 68 70 dBFS
Analog Input @ 32 MHz 25°C V 70 dBFS
Full V 69 dBFS
SINAD
8
Analog Input @ 4.98 MHz 25°C V 72 dBFS
Analog Input @ 9.9 MHz 25°C I 4 69 72 dBFS
Full II 5, 6 68.5 70.5 dBFS
Analog Input @ 21 MHz 25°C I 4 66.5 70 dBFS
Full II 5, 6 66 69 dBFS
Analog Input @ 32 MHz 25°C V 63 dBFS
Full V 61 dBFS
REV. 0 –3–
AD13465
Test Mil Sub- AD13465AZ/BZ
Parameter Temp Level Group Min Typ Max Unit
SPURIOUS-FREE DYNAMIC RANGE
9
Analog Input @ 4.98 MHz 25°C V 85 dBFS
Analog Input @ 9.9 MHz 25°C I 4 80 86 dBFS
Full II 5, 6 78 84 dBFS
Analog Input @ 21 MHz 25°C I 4 70 76 dBFS
Full II 5, 6 69 74 dBFS
Analog Input @ 32 MHz 25°C V 63 dBFS
Full V 62 dBFS
SINGLE-ENDED ANALOG INPUT
Pass Band Ripple to 10 MHz 25°C V 0.05 dB
Pass Band Ripple to 25 MHz 25°C V 0.1 dB
DIFFERENTIAL ANALOG INPUT
Pass Band Ripple to 10 MHz 25°C V 0.3 dB
Pass Band Ripple to 25 MHz 25°C V 0.82 dB
TWO-TONE IMD REJECTION
10
f
IN
= 9.1 MHz and 10.1 MHz 25°C I 4 77.5 82 dBc
f
1
and f
2
are –7 dB Full II 5, 6 76.5 80
f
IN
= 19.1 MHz and 20.7 MHz 25°C V 72 dBc
f
1
and f
2
are –7 dB
CHANNEL-TO-CHANNEL ISOLATION
11
25°CIV 12 90 dB
TRANSIENT RESPONSE 25°C V 15.3 ns
DIGITAL OUTPUTS
12
Logic Compatibility CMOS
DV
CC
= 3.3 V
Logic 1 Voltage Full I 1, 2, 3 2.5 DVCC – 0.2 V
Logic 0 Voltage Full I 1, 2, 3 0.2 0.5 V
DV
CC
= 5 V
Logic 1 Voltage Full V DVCC – 0.3 V
Logic 0 Voltage Full V 0.35 V
Output Coding Two’s Complement
POWER SUPPLY
AV
CC
Supply Voltage
13
Full VI 4.85 5.0 5.25 V
I (AV
CC
) Current Full V 270 308 mA
AV
EE
Supply Voltage
13
Full VI –5.25 –5.0 –4.75 V
I (AV
EE
) Current Full V 38 49 mA
DV
CC
Supply Voltage
13
Full VI 3.135 3.3 3.465 V
I (DV
CC
) Current Full V 34 46 mA
(Total) Supply Current per Channel Full I 1, 2, 3 369 403 mA
Power Dissipation (Total) Full I 1, 2, 3 3.57 3.9 W
Power Supply Rejection Ratio (PSRR) Full V 0.02 % FSR/
% V
S
NOTES
1
Gain tests are performed on AMP-IN-X-1 input voltage range.
2
Input capacitance spec. combines AD8037 capacitance and ceramic package capacitance.
3
Full Power Bandwidth is the frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis) is reduced by 3 dB.
4
For differential input: +IN = 1 V p-p and –IN = 1 V p-p (signals are 180° out of phase). For single ended input: +IN = 2 V p-p and –IN = GND.
5
All AC specifications tested by driving ENCODE and ENCODE differentially. AMP-IN-X-1 = 1 V p-p, AMP-IN-X-2 = GND.
6
Minimum and Maximum conversion rates allow for variation in Encode Duty Cycle of 50% ± 5%.
7
Analog Input signal power at –1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first five harmonics removed).
Encode = 65 MSPS. SNR is reported in dBFS, related back to converter full scale.
8
Analog Input signal power at –1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics.
Encode = 65 MSPS. SINAD is reported in dBFS, related back to converter full scale.
9
Analog Input signal power at –1 dBFS; SFDR is ratio of converter full scale to worst spur.
10
Both input tones at –7 dBFS; two tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst third order intermod product.
11
Channel-to-channel isolation tested with A Channel grounded and a full-scale signal applied to B Channel.
12
Digital output logic levels: DV
CC
= 3.3 V, C
LOAD
= 10 pF. Capacitive loads > 10 pF will degrade performance.
13
Supply voltage recommended operating range. AV
CC
may be varied from 4.85 V to 5.25 V. However, rated ac (harmonics) performance is valid only over the range
AV
CC
= 5.0 V to 5.25 V.
Specifications subject to change without notice.
REV. 0
AD13465
–4–
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD13465 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS
1
ELECTRICAL
AV
CC
Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 7 V
AV
EE
Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . –7 V to 0 V
DV
CC
Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 7 V
Analog Input Voltage . . . . . . . . . . . . . . . . . . . . . V
EE
to V
CC
Analog Input Current . . . . . . . . . . . . . . –10 mA to +10 mA
Digital Input Voltage (ENCODE) . . . . . . . . . . . . . 0 to V
CC
ENCODE, ENCODE Differential Voltage . . . . . . . . . . 4 V
Digital Output Current . . . . . . . . . . . . –10 mA to +10 mA
ENVIRONMENTAL
2
Operating Temperature (Case) . . . . . . . . . –40°C to +85°C
Maximum Junction Temperature . . . . . . . . . . . . . . . 175°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . 300°C
Storage Temperature Range (Ambient) . . –65°C to +150°C
NOTES
1
Absolute maximum ratings are limiting values applied individually, and beyond
which the serviceability of the circuit may be impaired. Functional operability is not
necessarily implied. Exposure to absolute maximum rating conditions for an
extended period of time may affect device reliability.
2
Typical thermal impedance for “ES” package: θ
JC
, 2.2°C/W; θ
JA
, 24.3°C/W.
TEST LEVEL
I 100% Production Tested.
II 100% Production Tested at 25°C, and sample tested at
specified temperatures. AC testing done on sample basis.
III Sample Tested Only.
IV Parameter is guaranteed by design and characteriza-
tion testing.
V Parameter is a typical value only.
VI 100% production tested at temperature at 25°C: sample
tested at temperature extremes.
ORDERING GUIDE
Model Temperature Range (Case) Package Description Package Option
AD13465AZ –25°C to +85°C 68-Lead Ceramic Leaded Chip Carrier ES-68C
AD13465AF –25°C to +85°C 68-Lead Ceramic Leaded Chip Carrier ES-68C
with Nonconductive Tie-Bar
5962-0150601HXA –40°C to +85°C 68-Lead Ceramic Leaded Chip Carrier ES-68C
AD13465/PCB 25°C Evaluation Board with AD13465AZ
REV. 0
AD13465
–5–
PIN FUNCTION DESCRIPTIONS
Pin No. Mnemonic Function
1, 35 SHIELD Internal Ground Shield Between Channels.
2, 3, 9, 10, 13, 16 AGNDA A Channel Analog Ground. A and B grounds should be connected as close to the
device as possible.
4 A–IN Inverting Differential Input (Gain = 1).
5 A+IN Noninverting Differential Input (Gain = 1).
6 AMP-OUT-A Single-Ended Amplifier Output (Gain = 2).
7 AMP-IN-A-1 Analog Input for A Side ADC (Nominally ±0.5 V).
8 AMP-IN-A-2 Analog Input for A Side ADC (Nominally ±1.0 V).
11 AV
EE
A A Channel Analog Negative Supply Voltage (Nominally –5.0 V or –5.2 V).
12 AV
CC
A A Channel Analog Positive Supply Voltage (Nominally 5.0 V).
14 ENCA Complement of Encode; Differential Input.
15 ENCA Encode Input; Conversion Initiated on Rising Edge.
17 DV
CC
A A Channel Digital Positive Supply Voltage (Nominally 5.0 V/3.3 V).
18–25, 28–33 D0A–D13A Digital Outputs for ADC A. D0 (LSB).
26, 27 DGNDA A Channel Digital Ground.
34 DROUTA Data Ready A Output.
36 DROUTB Data Ready B Output.
37–42, 45–52 D0B–D13B Digital Outputs for ADC B. D0 (LSB).
43, 44 DGNDB B Channel Digital Ground.
53 DV
CC
B B Channel Digital Positive Supply Voltage (Nominally 5.0 V/3.3 V).
54, 57, 60, 61, 67, 68 AGNDB B Channel Analog Ground.
55 ENCB Encode Input; Conversion Initiated on Rising Edge.
56 ENCB Complement of Encode; Differential Input.
58 AV
CC
B B Channel Analog Positive Supply Voltage (Nominally 5.0 V).
59 AV
EE
B B Channel Analog Negative Supply Voltage (Nominally –5.0 V or –5.2 V).
62 AMP-IN-B-2 Analog Input for B Side ADC (Nominally ±1.0 V).
63 AMP-IN-B-1 Analog Input for B Side ADC (Nominally ±0.5 V).
64 AMP-OUT-B Single-Ended Amplifier Output (Gain = 2).
65 B+IN Noninverting Differential Input (Gain = 1).
66 B–IN Inverting Differential Input (Gain = 1).
PIN CONFIGURATION
10
11
12
13
14
15
16
17
18
19
20
22
23
24
25
26
21
27 4328 29 30 31 32 33 34 35 36 37 38 39 40 41 42
9618765 686766656463624321
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
AD13465
AGNDB
AGNDB
D12A
DROUTB
AGNDA
D0A(LSB)
D3A
D4A
D5A
D6A
D7A
AGNDB
ENCB
ENCB
D0B(LSB)
AGNDA
AGNDA
AMP-OUT-A
A+IN
A–IN
AGNDA
AMP-IN-A-2
AMP-IN-A-1
AGNDB
SHIELD
D3B
D4B
D5B
DGNDA
D13B(MSB)
D12B
D11B
DGNDB
AGNDB
B–IN
B+IN
AGNDB
AMP-IN-B-2
AMP-OUT-B
AMP-IN-B-1
D10B
D9B
D8B
D7B
D6B
DGNDB
SHIELD
DROUTA
D13A(MSB)
D10A
D11A
D9A
D8A
DGNDA
ENCA
ENCA
AGNDA
AGNDA
D1B
D2B
D1A
D2A
AVEEA
AVCCA
DVCCA
AVEEB
AVCCB
DVCCB
REV. 0
AD13465
–6–
–Typical Performance Characteristics
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
0 32.530.027.5 25.022.520.017.515.012.510.07.5 5.0 2.5
FREQUENCY – MHz
ENCODE = 65MSPS
A
IN
= 5MHz(–1dBFS)
SNR = 72.12dBFS
SFDR = 86.05dBc
dB
TPC 1. Single Tone @ 5 MHz
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
0 32.530.027.5 25.022.520.017.515.012.510.07.5 5.0 2.5
FREQUENCY – MHz
ENCODE = 65MSPS
A
IN
= 21MHz(–1dBFS)
SNR = 71.74dBFS
SFDR = 73.07dBc
dB
TPC 2. Single Tone @ 21 MHz
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
0 32.530.027.5 25.022.520.017.515.012.510.07.5 5.0 2.5
FREQUENCY – MHz
ENCODE = 65MSPS
AIN = 9.1MHz AND 10.1MHz(–1dBFS)
SFDR = 85.01dBc
dB
TPC 3. Two-Tone @ 9.1 MHz/10.1 MHz
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
0 32.530.027.5 25.022.520.017.515.012.510.07.5 5.0 2.5
FREQUENCY – MHz
ENCODE = 65MSPS
A
IN
= 9.9MHz(–1dBFS)
SNR = 72.09dBFS
SFDR = 84.04dBc
dB
TPC 4. Single Tone @ 9.9 MHz
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
0 32.530.027.5 25.022.520.017.515.012.510.07.5 5.0 2.5
FREQUENCY – MHz
ENCODE = 65MSPS
A
IN
= 32MHz(–1dBFS)
SNR = 70.8dBFS
SFDR = 62.57dBc
dB
TPC 5. Single Tone @ 32 MHz
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
0 32.530.027.5 25.022.520.017.515.012.510.07.5 5.0 2.5
FREQUENCY – MHz
ENCODE = 65MSPS
A
IN
= 19MHz AND
20.7MHz(–1dBFS)
SNR = 70.8dBFS
SFDR = 75.40dBc
dB
TPC 6. Two-Tone @ 19 MHz/20.7 MHz
REV. 0
AD13465
–7–
3.0
2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
0 1433612288 10240819261444096 2048
ENCODE = 65MSPS
DNL MAX = 0.632 CODES
DNL MIN = –0.52 CODES
16384
LSB
TPC 7. Differential Nonlinearity
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
1.0 3.5 6.0 8.5 11.0 13.5 16.0 18.5 21.0 23.5 26.0
FREQUENCY – MHz
dBFS
ENCODE = 65MSPS
ROLLOFF = –0.18dB
TPC 8. Passband Ripple to 25 MHz
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
0 20.017.515.012.510.07.5 5.0 2.5
FREQUENCY – MHz
ENCODE = 40MSPS
A
IN
= 9.1MHz AND
10.1MHz(–1dBFS)
SFDR = 84.16dBc
dB
TPC 9. Two-Tone @ 9.1 MHz/10.1 MHz
3.0
2.0
1.0
0
–1.0
–2.0
–3.0
0 1433612288 10240819261444096 2048
ENCODE = 65MSPS
INL MAX = 1.18 CODES
INL MIN = –1.06 CODES
16384
LSB
TPC 10. Integral Nonlinearity
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
0 20.017.515.012.510.07.5 5.0 2.5
FREQUENCY – MHz
ENCODE = 40MSPS
A
IN
= 5MHz(–1dBFS)
SNR = 72dBFS
SFDR = 87.57dBc
dB
TPC 11. Single Tone @ 5 MHz
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
0 20.017.515.012.510.07.5 5.0 2.5
FREQUENCY – MHz
ENCODE = 40MSPS
A
IN
= 18MHz(–1dBFS)
SNR = 71.5dBFS
SFDR = 78.7dBc
dB
TPC 12. Single Tone @ 18 MHz
REV. 0
AD13465
–8–
DEFINITION OF SPECIFICATIONS
Analog Bandwidth
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Aperture Delay
The delay between a differential crossing of ENCODE and
ENCODE command and the instant at which the analog input
is sampled.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Differential Analog Input Resistance, Differential Analog
Input Capacitance, and Differential Analog Input Impedance
The real and complex impedances measured at each analog
input port. The resistance is measured statically and the capaci-
tance and differential input impedances are measured with a
network analyzer.
Differential Analog Input Voltage Range
The peak-to-peak differential voltage that must be applied to
the converter to generate a full-scale response. Peak differential
voltage is computed by observing the voltage from the other pin,
which is 180 degrees out of phase. Peak-to-peak differential is
computed by rotating the inputs phase 180 degrees and taking
the peak measurement again. The difference is then computed
between both peak measurements.
Differential Nonlinearity
The deviation of any code from an ideal 1 LSB step.
Encode Pulsewidth/Duty Cycle
Pulsewidth high is the minimum amount of time that the
ENCODE pulse should be left in Logic 1 state to achieve rated
performance; pulsewidth low is the minimum time ENCODE
pulse should be left in low state. At a given clock rate, these
specs define an acceptable encode duty cycle.
Harmonic Distortion
The ratio of the rms signal amplitude to the rms value of the
worst harmonic component.
Integral Nonlinearity
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a “best straight line”
determined by a least square curve fit.
Minimum Conversion Rate
The encode rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed limit.
Maximum Conversion Rate
The encode rate at which parametric testing is performed.
Output Propagation Delay
The delay between a differential crossing of ENCODE and
ENCODE command and the time when all output data bits are
within valid logic levels.
Overvoltage Recovery Time
The amount of time required for the converter to recover to
0.02% accuracy after an analog input signal of the specified
percentage of full scale is reduced to midscale.
Power Supply Rejection Ratio
The ratio of a change in input offset voltage to a change in
power supply voltage.
Signal-to-Noise-and-Distortion (SINAD)
The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral compo-
nents, including harmonics but excluding dc. May be reported
in dB (i.e., degrades as signal level is lowered) or in dBFS
(always related back to converter full scale).
Signal-to-Noise Ratio (without Harmonics)
The ratio of the rms signal amplitude (set at 1 dB below full scale)
to the rms value of the sum of all other spectral components,
excluding the first five harmonics and dc. May be reported in
dB (i.e., degrades as signal level is lowered) or in dBFS (always
related back to converter full scale).
Spurious-Free Dynamic Range
The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious compo-
nent may or may not be a harmonic.
Transient Response
The time required for the converter to achieve 0.02% accu-
racy when a one-half full-scale step function is applied to the
analog input.
Two-Tone Intermodulation Distortion Rejection
The ratio of the rms value of either input tone to the rms value
of the worst third order intermodulation product; reported in dBc.
tA
A
IN
ENC, ENC
D[13:0]
DRY
N
N+1
N+2
N+3
N+4
NN+1 N+2 N+3 N+4
N–3N–2N–1N
tENCL
tENCH
tENC
tE_DR tOD
Figure 1. Timing Diagram
REV. 0
AD13465
–9–
AMP-IN-X-1
100⍀
100⍀
TO AD8037
AMP-IN-X-2
Figure 2. Single-Ended Input Stage
LOADS
LOADS
ENCODE
10k⍀
10k⍀
ENCODE
AV CC
10k⍀
10k⍀
AV CC
AV CC
AV CC
Figure 3. ENCODE Inputs
CURRENT MIRROR
CURRENT MIRROR
DR OUT
DVCC
VREF
DVCC
Figure 4. Digital Output Stage
CURRENT MIRROR
CURRENT MIRROR
D0–D13
100⍀
DV
CC
V
REF
DV
CC
Figure 5. Digital Output Stage
THEORY OF OPERATION
The AD13465 is a high-dynamic range, 14-bit, 65 MHz pipe-
line delay (three pipelines) analog-to-digital converter. The
custom analog input section provides input ranges of 1 V p-p and
2 V p-p, and input impedance configurations of 50 Ω, 100 Ω,
and 200 Ω.
The AD13465 employs four monolithic ADI components per
channel (AD8037, AD8138, AD8031, and AD6644), along
with multiple passive resistor networks and decoupling capacitors
to fully integrate a complete 14-bit analog-to-digital converter.
In the single-ended input configuration, the input signal is
passed through a precision laser trimmed resistor divider allowing
the user to externally select operation with a full-scale signal of
±0.5 V or ±1.0 V by choosing the proper input terminal for the
application. The result of the resistor divider is to apply a full-scale
input approximately 0.4 V to the noninverting input of the
internal AD8037 amplifier.
The AD13465 analog input includes an AD8037 amplifier
featuring an innovative architecture that maximizes the dynamic
range capability on the amplifier’s inputs and outputs. The
AD8037 amplifier provides a high-input impedance and gain for
driving the AD8138 in a single-ended-to-differential amplifier
configuration. The AD8138 has a –3 dB bandwidth at 300 MHz
and delivers a differential signal with the lowest harmonic
distortion available in a differential amplifier. The AD8138
differential outputs help balance the differential inputs to the
AD6644 maximizing the performance of the device.
The AD8031 provides the buffer for the internal reference
analog-to-digital converter. The internal reference voltage of the
AD6644 is designed to track the offsets and drifts and is used to
ensure matching over an extended temperature range of opera-
tion. The reference voltage is connected to the output common
mode input on the AD8138. This reference voltage sets the
output common mode on the AD8138 at 2.4 V, which is the
midsupply level for the ADC.
The AD6644 has complementary analog input pins, AIN and
AIN. Each analog input is centered at 2.4 V and should swing
±0.55 V around this reference. Since AIN and AIN are 180
degrees out of phase, the differential analog input signal is 2.2 V
peak-to-peak. Both analog inputs are buffered prior to the first
track-and-hold.
The AD6644 digital outputs drive 100 Ω series resistors (Figure
5.) The result is a 14-bit parallel digital CMOS-compatible
word, coded as two’s complement.
USING THE SINGLE-ENDED INPUT
The AD13465 has been designed with the user’s ease of opera-
tion in mind. Multiple input configurations have been included
on board to allow the user a choice of input signal levels and
input impedance. The standard inputs are ±0.5 V and ±1.0 V.
The user can select the input impedance of the AD13465 on
any input by using the other inputs as alternate locations for the
GND. The following chart summarizes the impedance options
available at each input location.
AMP-IN-X-1 = 100 Ω when AMP-IN-X-2 is open.
AMP-IN-X-1 = 50 Ω when AMP-IN-X-2 is shorted to GND.
AMP-IN-X-2 = 200 Ω when AMP-IN-X-1 is open.
Each channel has two analog inputs AMP-IN-A-1 and AMP-
IN-A-2 or AMP-IN-B-1 and AMP-IN-B-2. Use AMP-IN-A-1
REV. 0
AD13465
–10–
or AMP-IN-B-1 when an input of ±5 V full scale is desired. Use
AMP-IN-A-2 or AMP-IN-B-2 when ±1 V full scale is desired.
Each channel has an AMP-OUT that must be tied to either a
noninverting or inverting input of a differential amplifier with
the remaining input grounded. For example, Side A, AMP-
OUT-A (Pin 6) must be tied to A+IN (Pin 5) with A–IN (Pin 4)
tied to ground for noninverting operation or AMP-OUT-A (Pin 6)
tied to A–IN (Pin 4) with A+IN (Pin 5) tied to ground for
inverting operation.
USING THE DIFFERENTIAL INPUT
Each channel of the AD13465 was designed with two optional
differential inputs, A+IN, A–IN and B+IN, B–IN. The inputs
provide system designers with the ability to bypass the AD8037
amplifier and drive the AD8138 directly. The AD8138 differen-
tial ADC driver can be deployed in either a single-ended or
differential input configuration. The differential analog inputs
have a nominal input impedance of 620 Ω and nominal full-
scale input range of 1.2 V p-p. The AD8138 amplifier drives a
differential filter and the custom analog-to-digital converter. The
differential input configuration provides the lowest even-order
harmonics and signal-to-noise (SNR) performance improve-
ment of up to 3 dB (SNR = 73 dBFS). Exceptional care was taken
in the layout of the differential input signal paths. The differen-
tial input transmission line characteristics are matched and
balanced. Equal attention to system level signal paths must be
provided in order to realize significant performance improvements.
APPLYING THE AD13465
Encoding the AD13465
The AD13465 encode signal must be a high quality, extremely
low phase noise source, to prevent degradation of performance.
Maintaining 14-bit accuracy at 65 MSPS places a premium on
encode clock phase noise. SNR performance can easily degrade
3 dB to 4 dB with 32 MHz input signals when using a high-jitter
clock source. See Analog Devices’ Application Note AN-501,
“Aperture Uncertainty and ADC System Performance,” for
complete details. For optimum performance, the AD13465
must be clocked differentially. The encode signal is usually
ac-coupled into the ENCODE and ENCODE pins via a trans-
former or capacitors. These pins are biased internally and require
no additional bias.
Shown below is one preferred method for clocking the AD13465.
The clock source (low jitter) is converted from single-ended to
differential using an RF transformer. The back-to-back Schottky
diodes across the transformer secondary limit clock excursions
into the AD13465 to approximately 0.8 V p-p differential. This
helps prevent the large voltage swings of the clock from feeding
through to the other portions of the AD13465, and limits the
noise presented to the ENCODE inputs. A crystal clock oscillator
can also be used to drive the RF transformer if an appropriate
limited resistor (typically 100 Ω) is placed in the series with
the primary.
T1-4T
100
0.1mF
ENCODE
ENCODE
AD13465
HSMS2812
DIODES
CLOCK
SOURCE
⍀
Figure 6. Crystal Clock Oscillator—Differential Encode
If a low jitter ECL/PECL clock is available, another option is to
ac-couple a differential ECL/PECL signal to the encode input
pins as shown below. A device that offers excellent jitter perfor-
mance is the MC100LVEL16 (or same family) from Motorola.
ENCODE
ENCODE
AD13465
0.1␮F
ECL/
PECL
VT
VT
0.1␮F
Figure 7. Differential ECL for Encode
Jitter Consideration
The signal-to-noise ratio (SNR) for any ADC can be predicted.
When normalized to ADC codes, the equation below, accurately
predicts the SNR based on three terms. These are jitter, average
DNL error, and thermal noise. Each of these terms contributes
to the noise within the converter.
SNR f t V
NANALOG RMS
NOISE RMS
N
=× +
+×× × +
–log (()
/
20 1
222
2
212
επ
J
f
ANALOG
=analog input frequency
t
J RMS
= rms jitter of the encode (rms sum of encode
source and internal encode circuitry)
ε= average DNL of the ADC (typically 0.50 LSB)
N= Number of bits in the ADC
V
NOISE RMS
= V rms noise referred to the analog input of the
ADC (typically 5 LSB)
For a 14-bit analog-to-digital converter like the AD13465, aper-
ture jitter can greatly affect the SNR performance as the analog
frequency is increased. The chart below shows a family of curves
that demonstrates the expected SNR performance of the AD13465
as jitter increases. The chart is derived from the above equation.
For a complete discussion of aperture jitter, please consult Ana-
log Devices’ Application Note AN-501, “Aperture Uncertainty
and ADC System Performance.”
CLOCK JITTER – ps
0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6
SNR – –dBFS
60
61
62
63
64
65
66
67
68
69
70
71
59
58
4.0 4.4 4.8 5.0
A
IN
= 5MHz
A
IN
= 32MHz
A
IN
= 21MHz
A
IN
= 9.9MHz
Figure 8. SNR vs. Jitter
REV. 0
AD13465
–11–
Power Supplies
Care should be taken when selecting a power source. Linear
supplies are strongly recommended. Switching supplies tend to
have radiated components that may be received by the AD13465.
Each of the power supply pins should be decoupled as closely to
the package as possible, using 0.1 µF chip capacitors.
The AD13465 has separate digital and analog power supply pins.
The analog supplies are denoted AV
CC
and the digital supply
pins are denoted DV
CC
. AV
CC
and DV
CC
should be separate
power supplies. This is because the fast digital output swings
can couple switching current back into the analog supplies.
Note that AV
CC
must be held within +5% and –3% of 5 V. The
AD13465 is specified for DV
CC
= 3.3 V as this is a common
supply for digital ASICs.
Output Loading
Care must be taken when designing the data receivers for the
AD13465. The digital outputs drive an internal series resistor
(e.g., 100 Ω) followed by a gate like 75LCX574. To minimize
capacitive loading, there should be only one gate on each output
pin. An example of this is shown in the evaluation board sche-
matic shown in Figure 10. The digital outputs of the AD13465
have a constant output slew rate of 1 V/ns. A typical CMOS
gate combined with a PCB trace will have a load of approximately
10 pF. Therefore, as each bit switches, 10 mA (10 pF × 1 V ÷ 1 ns)
of dynamic current per bit will flow in or out of the device. A full-
scale transition can cause up to 140 mA (14 bits × 10 mA/bit)
of transient current through the output stages. These switch-
ing currents are confined between ground and the DV
CC
pin.
Standard TTL gates should be avoided since they can apprecia-
bly add to the dynamic switching currents of the AD13465. It
should also be noted that extra capacitive loading will increase
output timing and invalidate timing specifications. Digital out-
put timing is guaranteed with 10 pF loads.
Figure 9. Evaluation Board Mechanical Layout
LAYOUT INFORMATION
The schematic of the evaluation board (Figure 10) represents a
typical implementation of the AD13465. The pinout of the
AD13465 is very straightforward and facilitates ease of use and
the implementation of high frequency/high resolution design
practices. It is recommended that high quality ceramic chip
capacitors be used to decouple each supply pin to ground directly
at the device. All capacitors can be standard high quality ceramic
chip capacitors.
Care should be taken when placing the digital output runs.
Because the digital outputs have such a high slew rate, the
capacitive loading on the digital outputs should be minimized.
Circuit traces for the digital outputs should be kept short and
connect directly to the receiving gate. Internal circuitry buffers
the outputs of the ADC through a resistor network to eliminate
the need to externally isolate the device from the receiving gate.
EVALUATION BOARD
The AD13465 evaluation board (Figure 9) is designed to
provide optimal performance for evaluation of the AD13465
analog-to-digital converter. The board encompasses everything
needed to ensure the highest level of performance for evaluating
the AD13465. The board requires an analog input signal, encode
clock, and power supply inputs. The clock is buffered on-board
to provide clocks for the latches. The digital outputs and out
clocks are available at the standard 40-pin connectors J1 and J2.
Power to the analog supply pins is connected via banana jacks.
The analog supply powers the associated components and
the analog section of the AD13465. The digital outputs of the
AD13465 are powered via banana jacks with 3.3 V. Contact the
factory if additional layout or applications assistance is required.
REV. 0
AD13465
–12–
Bill of Materials List for Evaluation Board
Qty Component Name Ref/Des Value Description Manufacturing Part No.
2 74CLX16373MTD U7, U8 Latch 74LCX1673MTD (Fairchild)
1 AD13465AZ U1 AD13465AZ AD13465AZ
2 ADP3330 U5, U6 Regulator ADP3330ART-3.3RL7
10 BJACK BJ1-BJ10 Banana Jacks 108-0740-001 (Johnson Components)
2 BRES0805 R41, R53 25 Ω0805 SM Resistor EFJ-6GEYJ240V
4 BRES0805 R38, R39, R55, R56 33 kΩ0805 SM Resistor EFJ-6GEYJ333V
6 RES2 R1, R2, R5, R7, R8 50 Ω0805 SM Resistor EFJ-6GEYJ333V
R54
36 RES2 R3, R4, R6, R9 100 Ω0805 SM Resistor EFJ-6GEYJ333V
R12–R15, R19–R28,
R31–R36, R37,
R42–R46, R51, R52
28 CAP2 C1, C2, C5–C10, 0.1 µF 0805 SM Resistor GRM 40X7R104K025BL
C12, C16–C18
C20–C26, C28
C30–C38
2 CAP2 C13, C27 0.47 µF 0805 SM Resistor VJ1206U474MFXMB
2 H40DM J1, J2 2 × 20 40-Pin Male Connector TSW-120-08-G-D
6 IND2 L1–L6 47 ΩSM Inductor 2743019447
4 MC10EL16 U2, U3, U9, U11 Clock Drivers MC1016EP16D
2 MC100ELT23 U4, U10 ECL/TTL Clock Drivers SY100ELT23L
8 POLCAP2 C3, C4, C11, C14, 10 µF Tantalum Polar Caps T491C106M016A57280
C15, C19, C29, C30
4 RES2 R47–R50 0 Ω0805 SM Resistor ERJ-6GEY OR 00V
12 SMA J3–J14 SMA Connectors 142-0701-201
4 Stand-Off Stand-Off 313-2477-016 (Johnson Components)
4 Screws Screws (Stand-Off) MPMS 004 0005 PH (Building Fasteners)
1 PCB AD13465 Eval Board (Rev B) GS03361
REV. 0
AD13465
–13–
AGNDA
10
AGNDA
11
12
–5VAA
13 +5VAA
14
D2A
15
D3A
16
D4A
17
D5A
18
D6A
19
D7A
20
21
22
23
24
25
DGNDA
26
AGNDB 60
59
58
AGNDB
57
56
55
54
53
ENCBB
52
ENCB
51
+3.3VDB
50
D13B(MSB)
49
D9B 48
D8B 47
D7B 46
D6B 45
DGNDB 44
9
8
7
6
5
4
3
2
1
68
67
66
65
64
63
62
61
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
AGNDA
AMP IN A 2
A+IN
A–IN
AGNDA
SHIELD
AGNDB
AGNDB
D12A
D13A(MSBA)
SHIELD
DRBOUT
D3B
D4B
D5B
DGNDB
U1
AD13465
D3A
D4A
D5A
D6A
D7A
D2A
DGNDA
AGNDA
AGNDA
ENCAB
D0A(LSB)
D1A
ENCA
AGNDA
+3VDA
D0A
D1A
AGNDA
ENCA
ENCA
–5VAA
C9
0.1␮F
C10
0.1␮F
C36
0.1␮F
OUT 3.3VDA
C34
0.1␮F
+5VAA
AGNDA
AGNDA
C35
0.1␮F
AGNDA
AMP IN A 1
AMP OUT A
AGNDA
AGNDB
B–IN
B+IN
AMP OUT B
AMP IN B 1
AMP IN B 2
–5.2VAB
+5VAB
DGNDA
AGNDB
D10B
D11B
D12B
D0B(LSBB)
DRAOUT
D11A
D10A
D9A
D8A
DGNDA
D12A
D13A
DRBOUT
D3B
D4B
D5B
DGNDB
D0B
DRAOUT
D11A
D10A
D9A
D8A
DGNDA
E56 E55
LIDB
E65
E48 E40
DGNDA DGNDB
E69 E70
E49
AGNDA
E51
E50
E72
E74
E77 E75
E73
E71
J4
SMA
AGNDA
J3
SMA
E76
E78
E83
E81
E79
AGNDA
J9
SMA
AGNDA
J13
SMA AGNDA
E68 E66 AGNDB
E54
E53 J7
SMA
AGNDB
E86E85
E52
AGNDB
AGNDB
J14
SMA
AGNDB
J8
SMA
AGNDB
J6
SMA
DGNDB
–5VAB
C33
0.1␮F
C18
0.1␮F
C37
0.1␮F
OUT 3.3VDB
C17
0.1␮F
+5VAB
AGNDB
AGNDB
C38
0.1␮F
AGNDB
AGNDB
ENCB
ENCB
D13B
D9B
D8B
D7B
D6B
DGNDB
AGNDB
D10B
D11B
D12B
E67
LIDA
E80
E82
E84
L1
C29
10␮F
+3VDA
U7
C62
0.1␮F
47⍀
ⴞ20%
@100MHz
DGNDA
DUT 3.3VDA
BJ10
1
L2
C30
10␮F
+3VDB
U8
C16
0.1␮F
47⍀
ⴞ20%
@100MHz
DGNDB
DUT 3.3VDB
BJ9
1
L3
C3
10␮F
+3VAA
U1
C20
0.1␮F
47⍀
ⴞ20% @100MHz
AGNDA
+5VAA
BJ6
1
AGNDA
L4
C4
10␮F
+5VAB
U1
C21
0.1␮F
47⍀
ⴞ20%@100MHz
AGNDB
+5VAB
BJ5
1
AGNDB
L5
C11
10␮F
–5VAA
U1
C32
0.1␮F
47⍀
ⴞ20%@100MHz
AGNDA
–5VAA
BJ2
1
AGNDA
L6
C19
10␮F
–5VAB
U1
C31
0.1␮F
47⍀
ⴞ20%@100MHz
AGNDB
–5VAB
BJ1
1
AGNDB
D1BD1B
D2BD2B
Figure 10a. Evaluation Board
REV. 0
AD13465
–14–
(MSB) B13B
B12B
B11B
B10B
B9B
B8B
F1B
DGNDB
(LSB) B0B
B1B
B2B
B3B
DGNDB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
B7B
B6B
C14
10␮F
BUFLATB
R2
50⍀
E64
E63 E62
DRAOUT
3.3VDB
DGNDB
H40DN
J2
F0B
U7
29
30
31
32
33
34
35
36
37
38
39
40
43
44
45
46
47
48
41
42
R11, DNI
25
26
27
28 113
112
VCC
111
110
GND
19
18
17
16
GND
15
13
12
GND
11
10
14
VCC
LE2
115
114
GND
O13
O12
VCC
O11
O10
GND
O9
O8
O7
O6
GND
O5
O3
O2
GND
O1
O0
O4
VCC
OE2
O15
O14
GND
20
19
18
17
16
15
14
13
12
11
10
9
6
5
4
3
2
1
8
7
24
23
22
21
DUT 3.3VDB
DGNDB
DGNDB
DGNDB
DUT 3.3VDB
DGNDB
DGNDB
R10, DNI
R30, DNI
R29, DNI
R28, 100⍀
R27, 100⍀
R26, 100⍀
R12, 100⍀
R9, 100⍀
R35, 100⍀
R34, 100⍀
R33, 100⍀
R32, 100⍀
R31, 100⍀
R25, 100⍀
LE1 OE1
DUT 3.3VDB
DGNDB
DGNDB
DGNDB
DUT 3.3VDB
DGNDB
R49
0⍀
R50
0⍀
DGNDB
R8
50⍀LATCHB
E57
(LSB) D0B
D1B
D4B
D5B
D6B
D7B
D8B
D9B
D10B
D11B
D12B
(MSB) D13B
F0B
F1B
B0B (LSB)
B1B
B2B
B3B
B4B
B5B
B6B
B7B
B8B
B9B
B10B
B13B (MSB)
B11B
B12B
DGNDB
74LCX16374
R36, 100⍀
(MSB) B13A
B12A
B11A
B10A
B9A
B8A
F1A
DGNDA
(LSB) B0A
B1A
B2A
B3A
DGNDA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
B7A
B6A
C15
10␮F
BUFLATA
R5
50⍀
E61
E60 E59
DRAOUT
3.3VDA
DGNDA
H40DM
J1
F0A
U8
29
30
31
32
33
34
35
36
37
38
39
40
43
44
45
46
47
48
41
42
R18, DNI
25
26
27
28 113
112
VCC
111
110
GND
19
18
17
16
GND
15
13
12
GND
11
10
14
VCC
LE2
115
114
GND
O13
O12
VCC
O11
O10
GND
O9
O8
O7
O6
GND
O5
O3
O2
GND
O1
O0
O4
VCC
OE2
O15
O14
GND
20
19
18
17
16
15
14
13
12
11
10
9
6
5
4
3
2
1
8
7
24
23
22
21
DUT 3.3VDA
DGNDA
DGNDA
DGNDA
DUT 3.3VDA
DGNDA
DGNDA
R17, DNI
R40, DNI
R44, DNI
R45, 100⍀
R46, 100⍀
R15, 100⍀
R14, 100⍀
R13, 100⍀
R24, 100⍀
R23, 100⍀
R22, 100⍀
R21, 100⍀
R20, 100⍀
R19, 100⍀
R12, 100⍀
LE1 OE1
DUT 3.3VDA
DGNDA
DGNDA
DGNDA
DUT 3.3VDA
DGNDA
R47
0⍀
R48
0⍀
DGNDA
R7
50⍀LATCHA
E58
(LSB) D0A
D1A
D4A
D5A
D6A
D7A
D8A
D9A
D10A
D11A
D12A
(MSB) D13A
DGNDA
74LCX16374
D2A
D3A
B4A
B5A
D2B
D3B
B4B
B5B
F0A
F1A
B0A (LSB)
B1A
B2A
B3A
B4A
B5A
B6A
B7A
B8A
B9A
B10A
B13A (MSB)
B11A
B12A
Figure 10b. Evaluation Board
REV. 0
AD13465
–15–
NC = NO CONNECT
VCC
Q
VEE
NC
D
VBB
U2
MC10EL16
AGNDA
1
2
3
4
8
7
6
5
OUT
NR
IN
SD
U5
3
5
1
ERR
GND
4
ADP3330
5
AGNDA
DB QB
C13
0.47␮F
3.3VA C7
0.1␮F
C8
0.1␮F
ENCA
ENCA
AGNDA
R42
100⍀
R43
100⍀
AGNDA
R56
33k⍀
NC = NO CONNECT
VCC
Q
VEE
NC
D
VBB
U3
MC10EL16
1
2
3
4
8
7
6
5
DB QB
NC = NO CONNECT
VCC
Q0
VEE
NC
D
VBB
U4
MC100EPT23
1
2
3
4
8
7
6
5
DB Q1
3.3VDA
C6
0.47␮F
R55
33k⍀
DGNDA
C2
0.1␮F
R41
25⍀
J12
SMA
J5
ENCODE
SMA
R1
50⍀
C1
0.1␮F
AGNDA
AGNDA
AGNDA
DGNDA
DGNDA
AGNDA
R3
100⍀
R4
100⍀
DGNDA
DGND
C5
0.47␮F
+3.3VDA
LATCHA
BUFLATA
E23
E19
+5VAA
E17
E27
E25
E21
E32
E44
E42
E10
E33
E6
E18
E28
E26
E20
E31
E43
E41
E9
E34
E5
DGNDA AGNDA
E38
E29
E1
E36
E14
E37
E30
E2
E35
E13
DGNDB AGNDB
SO1
SO2
SO3
SO4
SO5
SO6
E45
E3
E46
E4
E15
E7
E16
E12
DGNDA DGNDB
E11
E39
E8
E47
DGNDA DGNDB
AGNDB
1
BJ3
AGNDA
1
BJ4
DGNDB
1
BJ7
DGNDB
DGNDA
1
BJ8
DGNDA
NC = NO CONNECT
VCC
Q
VEE
NC
D
VBB
U11
MC10EL16
AGNDB
1
2
3
4
8
7
6
5
OUT
NR
IN
SD
U6
3
5
1
ERR
GND
4
ADP3330
5
AGNDB
DB QB
C27
0.47␮F
3.3VB C24
0.1␮F
C28
0.1␮F
ENCB
ENCB
AGNDB
R52
100⍀
R51
100⍀
AGNDA
R38
33k⍀
NC = NO CONNECT
VCC
Q
VEE
NC
D
VBB
U9
MC10EL16
1
2
3
4
8
7
6
5
DB QB
NC = NO CONNECT
VCC
Q0
VEE
NC
D
VBB
U10
MC100EPT23
1
2
3
4
8
7
6
5
DB Q1
3.3VDB
C25
0.47␮F
R39
33k⍀
DGNDB
C23
0.1␮F
R53
25⍀
J11
SMA
J10
ENCODE
SMA
R54
50⍀
C22
0.1␮F
AGNDB
AGNDB
AGNDB
DGNDB
DGNDB
DGNDB R37
100⍀
R6
100⍀
DGNDB
DGNDB
C26
0.1␮F
3.3VDA
LATCHB
BUFLATB
E24
E22
+5VAB
Figure 10c. Evaluation Board
REV. 0
AD13465
–16–
Figure 11a. Top Silk
Figure 11b. Top Layer
REV. 0
AD13465
–17–
Figure 11c. GND1
Figure 11d. GND2
REV. 0
AD13465
–18–
Figure 11e. Bottom Silk
Figure 11f. Bottom Layer
REV. 0
AD13465
–19–
68-Lead Ceramic Leaded Chip Carrier
(ES-68C)
TOE DOWN
ANGLE
0–8 DEGREES
0.010 (0.254)
30ⴗ
0.050 (1.27)
0.020 (0.508)
DETAIL A
ROTATED 90ⴗ CCW
1.190 (30.23)
1.180 (29.97) SQ
1.170 (29.72)
PIN 1
10 26
9
61
60
43
27
44
TOP VIEW
(PINS DOWN)
0.800
(20.32)
BSC
0.960 (24.38)
0.950 (24.13) SQ
0.940 (23.88)
0.055 (1.40)
0.050 (1.27)
0.045 (1.14)
0.020 (0.508)
0.017 (0.432)
0.014 (0.356)
0.175 (4.45)
MAX
0.235 (5.97)
MAX
DETAIL A
0.010 (0.25)
0.008 (0.20)
0.007 (0.18)
0.060 (1.52)
0.050 (1.27)
0.040 (1.02)
1.070
(27.18)
MIN
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
REV. 0
–20–
C01973–2.5–4/01(0)
PRINTED IN U.S.A.
AD13465
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
68-Lead Ceramic Leaded Chip Carrier with Nonconductive Tie-Bar
(ES-68C)
DETAIL A
0.010 (0.254)
30ⴗ
0.050 (1.27)
0.020 (0.508)
0.175 (4.45)
MAX
0.235 (5.97)
MAX
DETAIL A 0.010 (0.25)
0.008 (0.20)
0.007 (0.18)
PIN 1
TOP VIEW
(PINS DOWN)
0.800 (20.32)
BSC
0.960 (24.38)
0.950 (24.13) SQ
0.940 (23.88)
0.055 (1.40)
0.050 (1.27)
0.045 (1.14)
0.020 (0.508)
0.017 (0.432)
0.014 (0.356)
0.040 (1.02)
ⴛ 45ⴗ
0.015 (0.3)
ⴛ 45ⴗ
3 PLS
0.040 (1.02) R
TYP
0.350
(8.89)
TYP
2.000
(8.89)
TYP