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FEATURES
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SN65LVDS048AD (Marked as LVDS048A)
SN65LVDS048APW (Marked as DL048A)
(TOP VIEW)
EN
ROUT1
ROUT2
VCC
GND
ROUT3
ROUT4
EN
EN
EN
functional diagram
RIN1+
RIN1–
RIN2+
RIN2–
RIN3+
RIN3–
RIN4+
RIN4– ROUT4
ROUT3
ROUT2
ROUT1
R1
R2
R3
R4
RIN1–
RIN1+
RIN2+
RIN2–
RIN3–
RIN3+
RIN4+
RIN4–
DESCRIPTION
SN65LVDS048A
SLLS451B – SEPTEMBER 2000 – REVISED SEPTEMBER 2002
LVDS QUAD DIFFERENTIAL LINE RECEIVER
•>400 Mbps (200 MHz) Signaling Rates•Flow-Through Pinout Simplifies PCB Layout•50 ps Channel-to-Channel Skew (Typ)•200 ps Differential Skew (Typ)•Propagation Delay Times 2.7 ns (Typ)•3.3-V Power Supply Design•High Impedance LVDS Inputs on Power Down•Low-Power Dissipation (40 mW at 3.3 V Static)•Accepts Small Swing (350 mV) DifferentialSignal Levels•Supports Open, Short, and Terminated InputFail-Safe
•Industrial Operating Temperature Range(–40°C to 85°C)•Conforms to TIA/EIA-644 LVDS Standard•Available in SOIC and TSSOP Packages•Pin-Compatible With DS90LV048A FromNational
The SN65LVDS048A is a quad differential line receiver that implements the electrical characteristics oflow-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5-Vdifferential standard levels (such as EIA/TIA-422B) to reduce the power, increase the switching speeds, andallow operation with a 3.3-V supply rail. Any of the quad differential receivers will provide a valid logical outputstate with a ±100-mV differential input voltage within the input common-mode voltage range. The inputcommon-mode voltage range allows 1 V of ground potential difference between two LVDS nodes
The intended application of this device and signaling technique is for point-to-point baseband data transmissionover controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit boardtraces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuationcharacteristics of the media, the noise coupling to the environment, and other system characteristics.
The SN65LVDS048A is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2000–2002, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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TRUTH TABLE
(1)
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
7 V 7 V
300 kΩ300 kΩ
Input Input
VCC
50 Ω
300 kΩ
VCC
7 V
EN,EN 5 Ω
VCC
7 V
Output
ABSOLUTE MAXIMUM RATINGS
SN65LVDS048A
SLLS451B – SEPTEMBER 2000 – REVISED SEPTEMBER 2002
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
DIFFERENTIAL INPUT ENABLES OUTPUT
R
IN+
– R
IN–
EN EN R
OUT
V
ID
≥100 mV HL orV
ID
≤–100 mV H LOPENOpen/short or terminated HX All other conditions Z
(1) H = high level, L = low level, X = irrelevant, Z = high impedance(off)
over operating free-air temperature range (unless otherwise noted)
(1) (2)
UNIT
V
CC
Supply voltage range –0.3 V to 4 VV
I
(R
IN+
, Input voltage range –0.3 V to 4 VR
IN-
)
Enable input voltage (EN, EN ) –0.3 V to (V
CC
+0.3 V)V
O
(R
OUT
) Output voltage –0.3 V to (V
CC
+0.3 V)Bus-pin (R
IN+
, R
IN–
) electrostatic discharge
(3)
> 10 kVContinuous power dissipation See Dissipation Rating TableStorage temperature range –65°C to 150°CLead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.(3) Tested in accordance with MIL-STD-883C Method 3015.7.
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DISSIPATION RATING TABLE
RECOMMENDED OPERATING CONDITIONS
|VID|
2
2.4
|VID|
2
ELECTRICAL CHARACTERISTICS
SN65LVDS048A
SLLS451B – SEPTEMBER 2000 – REVISED SEPTEMBER 2002
T
A
≤25°C OPERATING FACTOR
(1)
T
A
= 85°CPACKAGE
POWER RATING ABOVE T
A
= 25°C POWER RATING
D 950 mW 7.6 mW/°C 494 mWPW 774 mW 6.2 mW/°C 402 mW
(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no airflow.
MIN NOM MAX UNIT
V
CC
Supply voltage 3 3.3 3.6 VReceiver input voltage GND 3 V
V
IC
Common-mode input voltage V
V
CC
– 0.8T
A
Operating free-air temperature –40 25 85 °C
over recommended operating free-air temperature range (unless otherwise noted)
(1)
PARAMETER TEST CONDITIONS MIN TYP
(2)
MAX UNIT
V
IT+
Differential input high threshold voltage 100V
CM
= 1.2 V, 0.05 V, 2.35 V
(3)
mVV
IT–
Differential input low threshold voltage –100V
(CMR)
Common mode voltage range V
ID
= 200 mV pk to pk
(4)
0.1 2.3 VV
IN
= 2.8 V –20 ±1 20 µAV
CC
= 3.6 V or 0 VI
IN
Input current V
IN
= 0 V –20 ±1 20 µAV
IN
= 3.6 V, V
CC
= 0 V –20 ±1 20 µAI
OH
= -0.4 mA, V
ID
= 200 mV 2.7 3.2 VV
OH
Output high voltage I
OH
= -0.4 mA, input terminated 2.7 3.2 VI
OH
= -0.4 mA, input shorted 2.7 3.2 VV
OL
Output low voltage I
OL
= 2 mA, V
ID
= -200 mV 0.05 0.25 VI
OS
Output short circuit current Enabled, V
OUT
= 0 V
(5)
–65 –100 mAI
O(Z)
Output 3-state current Disabled, V
OUT
= 0 V or V
CC
–1 1 µAV
IH
Input high voltage 2.0 V
CC
VV
IL
Input low voltage GND 0.8 VV
IN
= 0 V or V
CC
,I
I
Input current (enables) –10 10 µAOther input = V
CC
or GNDV
IK
Input clamp voltage I
CL
= –18 mA –1.5 –0.8 VI
CC
No load supply current, receivers enabled EN = V
CC
, Inputs open 8 15 mAI
CC(Z)
No load supply current, receivers disabled EN = GND, Inputs open 0.6 1.5 mA
(1) Current into device pin is defined as positive. Current out of the device is defined as negative. All voltages are referenced to ground,unless otherwise specified.(2) All typical values are at 25°C and with a 3.3-V supply.(3) V
CC
is always higher than R
IN+
and R
IN-
voltage, R
IN-
and R
IN+
have a voltage range of -0.2 V to V
CC
-V
ID
/2. To be compliant with acspecifications the common voltage range is 0.1 V to 2.3 V.(4) The VCMR range is reduced for larger V
ID
, Example: If V
ID
= 400 mV, the VCMR is 0.2 V to 2.2 V. The fail-safe condition with inputsshorted is not supported over the common-mode range of 0 V to 2.4 V, but is supported only with inputs shorted and no externalcommon-mode voltage applied. A V
ID
up to V
CC
-0 V may be applied to the R
IN+
and R
IN-
inputs with the common-mode voltage set toV
CC
/2. Propagation delay and differential pulse skew decrease when V
ID
is increased from 200 mV to 400 mV. Skew specificationsapply for 200 mV < V
ID
< 800 mV over the common-mode range.(5) Output short circuit current (I
OS
) is specified as magnitude only, minus sign indicates direction only. Only one output should be shortedat a time. Do not exceed maximum junction temperature specification.
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SWITCHING CHARACTERISTICS
SN65LVDS048A
SLLS451B – SEPTEMBER 2000 – REVISED SEPTEMBER 2002
over recommended operating conditions (unless otherwise noted)
(1)
PARAMETER TEST CONDITIONS MIN TYP
(2)
MAX UNIT
t
PHL
Differential propagation delay, high-to-low 1.9 2.7 3.7 nst
PLH
Differential propagation delay, low-to-high 1.9 2.9 3.7 nst
SK(p)
Differential pulse skew (t
PHLD -
t
PLHD
)
(3)
200 450 psC
L
= 15 pFt
SK(o)
Differential channel-to-channel skew; same device
(4)
50 500 psV
ID
= 200 mVt
SK(pp)
Differential part-to-part skew
(5)
1 ns(see Figure 1 and Figure 2 )t
SK(lim)
Differential part-to-part skew
(6)
1.5 nst
r
Rise time 0.5 1 nst
f
Fall time 0.5 1 nst
PHZ
Disable time high to Z 8 9 nsR
L
= 2 K Ωt
PLZ
Disable time low to Z 6 8 nsC
L
= 15 pFt
PZH
Enable time Z to high 8 10 ns(see Figure 3 and Figure 4 )t
PZL
Enable time Z to low 7 8 nsf
(MAX)
Maximum operating frequency
(7)
All channels switching 200 250 MHz
(1) Generator waveform for all tests unless otherwise specified: f = 1 MHz, Z
O
= 50 Ω, t
r
and t
f
(0%–100%) ≤3 ns for R
IN
.(2) All typical values are at 25°C and with a 3.3-V supply.(3) t
SK(p)
|t
PLH
– t
PHL
| is the magnitude difference in differential propagation delay time between the positive going edge andthe negativegoing edge of the same channel.(4) t
SK(o)
is the differential channel-to-channel skew of any event on the same device.(5) t
SK(pp)
is the differential part-to-part skew, and is defined as the difference between the minimum and the maximum specified differentialpropagation delays. This specification applies to devices at the same VCC and within 5°C of each other within the operating temperaturerange.
(6) t
sk(lim)
part-to-part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devicesover recommended operating temperature and voltage ranges, and across process distribution. t
sk(lim)
is defined as |Min - Max|differential propagation delay.(7) f
(MAX)
generator input conditions: t
r
= t
f
< 1 ns (0% to 100%), 50% duty cycle, 0 V to 3 V. Output criteria: duty cycle = 45% to 55%,V
OD
>250 mV, all channels switching
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PARAMETER MEASUREMENT INFORMATION
Generator
50 Ω50 Ω
RIN+
RIN–
CL
ROUT
Receiver Enabled
R
OV Differential VID = 200 mV 1.2 V
tPLH tPHL
trtf
80% 80%
1.5 V 1.5 V
1.3 V
1.1 V
VOH
VOL
RIN–
RIN+
ROUT 20%
20%
SN65LVDS048A
SLLS451B – SEPTEMBER 2000 – REVISED SEPTEMBER 2002
Figure 1. Receiver Propagation Delay and Transition Time Test Circuit
Figure 2. Receiver Propagation Delay and Transition Time Waveforms
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tPLZ tPZL
tPHZ tPZH
0.5 V
0.5 V
50%
50%
3 V
0 V
3 V
0 V
VCC
VOL
VOH
GND
EN When EN = GND or Open
EN When EN = VCC
Output When
VID = –100 mV
Output When
VID = 100 mV
1.5 V 1.5 V
SN65LVDS048A
SLLS451B – SEPTEMBER 2000 – REVISED SEPTEMBER 2002
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 3. Receiver 3-State Delay Test Circuit
Figure 4. Receiver 3-State Delay Waveforms
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TYPICAL CHARACTERISTICS
2.8
3
3.2
3.4
3.6
3 3.3 3.6
− Output High Voltage − V
VOH
VCC − Power Supply Voltage − V
TA = 25°C
VID = 200 mV
52
53
54
55
56
57
3 3.3 3.6
TA = 25°C
VID = 200 mV
− Output Low Voltage − mV
VCC − Power Supply Voltage − V
VOL
0
10
20
30
40
50
3 3.3 3.6
− Differential Transition Voltage − mV
VCC − Power Supply Voltage − V
VIT+VIT−
TA = 25°C
−80
−76
−72
−68
−64
−60
−563 3.3 3.6
− Output Short Circuit Current − mA
VCC − Power Supply Voltage − V
IOS
TA = 25°C
VO = 0 V
SN65LVDS048A
SLLS451B – SEPTEMBER 2000 – REVISED SEPTEMBER 2002
OUTPUT HIGH VOLTAGE OUTPUT LOW VOLTAGEvs vsPOWER SUPPLY VOLTAGE POWER SUPPLY VOLTAGE
Figure 5. Figure 6.
OUTPUT SHORT CIRCUIT CURRENT DIFFERENTIAL TRANSITION VOLTAGEvs vsPOWER SUPPLY VOLTAGE POWER SUPPLY VOLTAGE
Figure 7. Figure 8.
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0
1
2
3
4
0 500 1000 1500 2000 2500 3000
− Differential Propagation Delay − nstPHL
tPLH,
tPLH
tPHL
Differential Input Voltage − mV
TA = 25°C
f = 20 MHz
VCM = 1.2 V
CI = 15 pF
VCC = 3.3 V
0
1
2
3
4
−0.5 0 0.5 1 1.5 2 2.5
TA = 25°C
f = 20 MHz
VCM = 1.2 V
CI = 15 pF
VCC = 3.3 V
tPLH
tPHL
− Differential Propagation Delay − nstPHL
tPLH,
Common-Mode Voltage − V
TA − Free-Air Temperature − °C
400
450
500
550
600
650
700
750
800
−40 −20 0 20 40 60 80
Data Transfer Rate − Mxfr/s
215 −1 prbs NRZ
VCC = 3.3 V
VID = 0.4 V
VIC = 1.2 V
CL = 5.5 pF
40% Open Eye
4 Receivers Switching
Input Jitter < 45 ps
SN65LVDS048A
SLLS451B – SEPTEMBER 2000 – REVISED SEPTEMBER 2002
TYPICAL CHARACTERISTICS (continued)
DIFFERENTIAL PROPAGATION DELAY DIFFERENTIAL PROPAGATION DELAYvs vsDIFFERENTIAL INPUT VOLTAGE COMMON-MODE VOLTAGE
Figure 9. Figure 10.
DATA TRANSFER RATEvsFREE-AIR TEMPERATURE
Figure 11.
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APPLICATION INFORMATION
FAIL SAFE
Rt = 100 Ω (Typ)
300 kΩ300 kΩ
VCC
VIT ≈ 2.3 V
A
BY
SN65LVDS048A
SLLS451B – SEPTEMBER 2000 – REVISED SEPTEMBER 2002
One of the most common problems with differential signaling applications is how the system responds when nodifferential voltage is present on the signal pair. The LVDS receiver is like most differential line receivers, in thatits output logic state can be indeterminate when the differential input voltage is between –100 mV and 100 mVand within its recommended input common-mode voltage range. TI's LVDS receiver is different in how it handlesthe open-input circuit situation, however.
Open-circuit means that there is little or no input current to the receiver from the data line itself. This could bewhen the driver is in a high-impedance state or the cable is disconnected. When this occurs, the LVDS receiverwill pull each line of the signal pair to near V
CC
through 300-k Ωresistors as shown in Figure 10. The fail-safefeature uses an AND gate with input voltage thresholds at about 2.3 V to detect this condition and force theoutput to a high-level regardless of the differential input voltage.
Figure 12. Open-Circuit Fail Safe of the LVDS Receiver
It is only under these conditions that the output of the receiver will be valid with less than a 100-mV differentialinput voltage magnitude. The presence of the termination resistor, Rt, does not affect the fail-safe function aslong as it is connected as shown in the figure. Other termination circuits may allow a dc current to ground thatcould defeat the pullup currents from the receiver and the fail-safe feature.
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PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
SN65LVDS048AD ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS048ADG4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS048ADR ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS048ADRG4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS048APW ACTIVE TSSOP PW 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS048APWG4 ACTIVE TSSOP PW 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS048APWR ACTIVE TSSOP PW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS048APWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 6-Dec-2006
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN65LVDS048ADR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
SN65LVDS048APWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 25-Sep-2009
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN65LVDS048ADR SOIC D 16 2500 346.0 346.0 33.0
SN65LVDS048APWR TSSOP PW 16 2000 346.0 346.0 29.0
PACKAGE MATERIALS INFORMATION
www.ti.com 25-Sep-2009
Pack Materials-Page 2
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