56F800
16-bit Digital Signal Controllers
freescale.com
56F805
Data Sheet
Preliminary Technical Data
DSP56F805
Rev. 16
09/2007
56F805 Technical Data, Rev. 16
Freescale Semiconductor 3
56F805 Block Diagram
JTAG/
OnCE
Port
Digital Reg Analog Reg
Low Voltage
Supervisor
Program Contro ller
and
Hardware Looping Unit
Data ALU
16 x 16 + 36 → 36-Bit MAC
Three 16-bit Input Registers
Two 36-bit Accu mulators
Address
Generation
Unit
Bit
Manipulation
Unit
PLL
Clock Gen
16-Bit
56800
Core
PAB
PDB
XDB2
CGDB
XAB1
XAB2
XTAL
EXTAL
INTERRUPT
CONTROLS IPBB
CONTROLS
IPBus Bridge
(IPBB)
MODULE CONTROLS
ADDRESS BUS [8:0]
DATA BUS [15:0]
COP RESET
RESET
IRQAIRQB
Applica-
tion-Specific
Memory &
Peripherals
Interrupt
Controller
Program Memory
32252 x 16 Flash
512 x 16 SRAM
Boot Flash
2048 x 16 Flash
Data Memory
4096 x 16 Flash
2048 x 16 SRA M
COP/
Watchdog
SPI
or
GPIO
SCI0
or
GPIO
Quad Timer D
/ Alt Func
Quad Timer C
A/D1
A/D2 ADC
4
2
4
4
4
4
6PWM Outputs
Fault Inputs
PWMA
16 16
VCAPC VDD VSS VDDA VSSA
628 8*
••
•
•
•••
•
EXTBOOT
Current Sense Inputs
3
Quadrature
Decoder 0/
Quad Timer A
CAN 2.0A/B
2
CLKO
External
Address Bus
Switch
Bus
Control
External
Data Bus
Switch
External
Bus
Interface
Unit
RD Enable
WR Enable
DS Select
PS Select
10
16
6A[00:05]
D[00:15]
A[06:15] or
GPIO-E2:E3 &
GPIO-A0:A7
4
4
6PWM Outputs
Fault Inputs
PWMB
Current Sense Inputs
3
Quadrature
Decoder 1/
Quad B T i me r
4
2
SCI1
or
GPIO
2
Dedicated
GPIO
14
VPP
RSTO
VREF
• Up to 40 MIPS at 80MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• Hardware DO and REP loops
• MCU-friendly instruction set supports bot h DSP
and controller functi ons: MAC, bit manipulation
unit, 14 addressing modes
• 31.5K × 16-bit words (64KB) Program Flash
• 512 × 16-bit words (1KB) Progr am RAM
•4K × 16-bit words (8KB) Data Flash
•2K × 16-bit words (4KB) Data RAM
•2K × 16-bit words (4KB) Boot Flash
• Up to 64K × 16-bit words (128KB) each of external
Program and Data memory
• Two 6-channel PWM Modules
• Two 4-channel, 12-bit ADCs
• Two Quadrature Decoders
• CAN 2.0 B Module
• Two Serial Communication Interfaces (SCIs)
• Serial Peripheral Interface (SPI)
• Up to four General Purpose Quad Timers
• JTAG/OnCETM port for debugging
• 14 Dedicated and 18 Shared GPIO lines
• 144-pin LQFP Package
*includes TCS pin which is reserved for factory use and is tie d to VSS
56F805 General Description
56F805 Technical Data, Rev. 16
4 Freescale Semiconductor
Part 1 Overview
1.1 56F805 Features
1.1.1 Processing Core
• Efficient 16-bit 56800 family processor engine with dual Harvard architecture
• As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency
• Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)
• Two 36-bit accumulators, including extension bits
• 16-bit bidirectional barrel shifter
• Parallel instruction set with unique processor addressing mo des
• Hardware DO and REP loops
• Three internal address buses and one external address bus
• Four internal data buses and one external data bus
• Instruction set supports both DSP and controller functions
• Controller style addressing modes and instructions for compact code
• Efficient C compiler and local variable support
• Software subroutine and interrupt stack with depth limited only by memory
• JTAG/OnCE debug programming interface
1.1.2 Memory
• Harvard architecture permits as many as three simultaneous accesses to Program and Data memory
• On-chip memory including a low-cost, high-volume Flash solution
—31.5K × 16 bit words of Pro gram Flash
—512 × 16-bit words of Program RAM
—4K× 16-bit words of Data Flash
—2K × 16-bit words of Data RAM
—2K × 16-bit words of Boot Flash
• Off-chip memory expansion capabilities programmable for 0, 4, 8, or 12 wait states
— As much as 64K × 16 bits of Data memory
— As much as 64K × 16 bits of Program memory
1.1.3 Peripheral Circuits for 56F805
• Two Pulse Width Modulator modules each with six PWM outputs, three Current Sense inputs, and four
Fault inputs, fault tolerant design with dead time insertion; supports both center- and edge-aligned modes
• Two 12-bit Analog-to-Digital Converters (ADC) which support two simultaneous conversions; ADC and
PWM modules can be synchronized
• Two Quadrature Decoders each with four inputs or two additional Quad Timers
56F805 Description
56F805 Technica l Data, Rev. 16
Freescale Semiconductor 5
• Two General Purpose Quad Timers totaling six pins: Timer C with two pins and Timer D with four pins
• CAN 2.0 B Module with 2-pin port for transmit and receive
• Two Serial Communication Interfaces, each with two pins (or four additional GPIO lines)
• Serial Peripheral Interface (SPI) with configurable four-pin port (or four additional GPIO lines)
• 14 dedicated General Purpose I/O (GPIO) pins, 18 multiplexed GPIO pins
• Computer Operating Properly (COP) watchdog timer
• Two dedicated external interrupt pins
• External reset input pin for hardware reset
• External reset output pin for system reset
• JTAG/On-Chip Emulation (OnCE™) module for unobtrusive, processor speed-independent debugging
• Software-programmable, Phase Locked Loop-based frequency synthesizer for the controller core clock
1.1.4 Energy Information
• Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs
• Uses a single 3.3V power supply
• On-chip regulators for digital and analog circuitry to lower cost and reduce noise
• Wait and Stop modes available
1.2 56F805 Description
The 56F805 is a member of the 56800 core-based family of processors. It combines, on a single chip, the
processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to
create an extremely cost-effective solution. Because of its low cost, configuration flexibility, and compact
program code, the 56F805 is well-suited for many applications. The 56F805 includes many peripherals
that are especially useful for applications such as motion control, smart appliances, steppers, encoders,
tachometers, limit switches, power supply and control, automotive control, engine management, noise
suppression, remote utility metering, and industrial control for power, lighting, and automation.
The 56800 core is based on a Harvard-style architecture consisting of three execution units operating in
parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming
model and optimized instruction set allow straightforward generation of efficient, compact code for both
MCU and DSP applications. The instruction set is also highly efficient for C compilers to enable rapid
development of optimized control applications.
The 56F805 supports program execution from either internal or external memories. Two data operands can
be accessed from the on-chip Data RAM per instruction cycle. The 56F805 also provides two external
dedicated interrupt lines, and up to 32 General Purpose Input/Output (GPIO) lines, depending on
peripheral configuration.
The 56F805 controller includes 31.5K words (16-bit) of Program Flash and 4K words of Data Flash (each
programmable through the JTAG port) with 512 words of Program RAM and 2K words of Data RAM. It
also supports program execution from external memory (64K).
56F805 Technical Data, Rev. 16
6 Freescale Semiconductor
The 56F805 incorporates a total of 2K words of Boot Flash for easy customer-inclusion of
field-programmable software routines that can be used to program the main Program and Data Flash
memory areas. Both Program and Data Flash memories can be independently bulk-erased or erased in page
sizes of 256 words. The Boot Flash memory can also be either bulk- or page-erased.
Key application-specific features of the 56F805 include the two Pulse Width Modulator (PWM) modules.
These modules each incorporate three complementary, individually programmable PWM signal outputs
(each module is also capable of supporting six independent PWM functions for a total of 12 PWM outputs)
to enhance motor control functionality. Complementary operation permits programmable dead time
insertion, distortion correction via current sensing by software, and separate top and bottom output polarity
control. The up-counter value is programmable to support a continuously variable PWM frequency. Edge-
and center-aligned synchronous pulse width control (0% to 100% modulation) is supported. The device is
capable of controlling most motor types: ACIM (AC Induction Motors), both BDC and BLDC (Brush and
Brushless DC motors), SRM and VRM (Switched and Variable Reluctance Motors), and stepper motors.
The PWMs incorporate fault protection and cycle-by-cycle current limiting with sufficient output drive
capability to directly drive standard opto-isolators. A “smoke-inhibit”, write-once protection feature for
key parameters and a patented PWM waveform distortion correction circuit are also provided. Each PWM
is double-buffered and includes interrupt controls to permit integral reload rates to be programmable from
1 to 16. The PWM modules provide a reference output to synchronize the ADCs.
The 56F805 incorporates two separate Quadrature Decoders capable of capturing all four transitions on
the two-phase inputs, permitting generation of a number proportional to actual position. Speed
computation capabilities accommodate both fast and slow moving shafts. The integrated watchdog timer
in the Quadrature Decoder can be programmed with a time-out value to alarm when no shaft motion is
detected. Each input is filtered to ensure only true transitions are recorded.
This controller also provides a full set of standard programmable peripherals that include two Serial
Communications Interfaces (SCI), one Serial Peripheral Interface (SPI), and four Quad Timers. Any of
these interfaces can be used as General Purpose Input/Outputs (GPIOs) if that function is not required. A
Controller Area Network interface (CAN Version 2.0 A/B-compliant), an internal interrupt controller and
14 dedicated GPIO are also included on the 56F805.
1.3 State of the Art Development Environment
• Processor ExpertTM (PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use
component-based software application creation with an expert knowledge system.
• The Code Warrior Integrated Development Environment is a sophisticated tool for code navigation,
compiling, and debugging. A complete set of evaluation modules (EVMs) and development system cards
will support concurrent engineering. Together, PE, Code Warrior and EVMs create a complete, scalable
tools solution for easy, fast, and efficient development.
Product Documentation
56F805 Technica l Data, Rev. 16
Freescale Semiconductor 7
1.4 Product Documentation
The four documents listed in Table 2-1 are required for a complete description and proper design with the
56F805. Documentation is available from local Freescale distributors, Freescale semiconductor sales
offices, Freescale Literature Distribution Centers, or online at www.freescale.com.
1.5 Data Sheet Conventions
This data sheet uses the following conventions:
Table 1-1 Chip Documentation
Topic Description Order Number
56800E
Family Manual Detailed description of the 56800 family architecture, and
16-bit core processor and the instruction set 56800EFM
DSP56F801/803/805/807
User’s Manual Detailed description of memory, peripherals, and interfac es
of the 56F801, 56F803, 56F805, and 56F807 DSP56F801-7UM
56F805
Technical Data Sheet Electrical and timing specifications, pin descriptions, and
package descriptions (th is document) DSP56F805
56F805
Errata Details any chip issues that might be present DSP56F805E
OVERBAR This is used to indicate a signal that is active when pulled low. For example, the RESET pin is
active when low.
“asserted” A high true (active high) signal is high or a low true (active low) signal is low.
“deasserted” A high true (active high) signal is low or a low true (active low) signal is high.
Examples: Signal/Symbol Logic State Signal State Voltage1
1. Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.
PIN True Asserted VIL/VOL
PIN False Deasserted VIH/VOH
PIN True Asserted VIH/VOH
PIN False Deasserted VIL/VOL
56F805 Technical Data, Rev. 16
8 Freescale Semiconductor
Part 2 Signal/Connection Descriptions
2.1 Introduction
The input and output signals of the 56F805 are organized into functional groups, as shown in Table 2-1
and as illustrated in Figure 2-1. In Table 2-2 through Table 2-18, each table row describes the signal or
signals present on a pin.
Table 2-1 Functional Group Pin Allocations
Functional Group Number of
Pins Detailed
Description
Power (VDD or VDDA)9Table 2-2
Ground (VSS or VSSA)9Table 2-3
Supply Capacitors and VPP 3 Table 2-4
PLL and Clock 3 Table 2-5
Address Bus116 Table 2-6
Data Bus 16 Table 2-7
Bus Control 4 Table 2-8
Interrupt and Program Control 5 Table 2-9
Dedicated General Purpose Inpu t/Output 14 Table 2-10
Pulse Width Modulator (PWM) Port 26 Table 2-11
Serial Peripheral Interface (SPI) Port1
1. Alternately, GPIO pins
4Table 2-12
Quadrature Decoder Port2
2. Alternately, Quad Timer pins
8Table 2-13
Serial Communications Interface (SCI) Port14Table 2-14
CAN Port 2 Table 2-15
Analog to Digital Converter (ADC) Port 9 Table 2-16
Quad Timer Module Ports 6 Table 2-17
JTAG/On-Chip Emulation (OnCE) 6 Table 2-18
Introduction
56F805 Technica l Data, Rev. 16
Freescale Semiconductor 9
Figure 2-1 56F805 Signals Identified by Functional Group1
1. Alternate pin functionality is shown in parenthesis.
56F805
Power Port
Ground Port
Power Port
Ground Port
PLL
and
Clock
External
Address Bus or
GPIO
External
Data Bus
External
Bus Control
Dedicated
GPIO
SCI0 Port
or GPIO
SCI1 Port
or GPI0
VDD
VSS
VDDA
VSSA
VCAPC
VPP
EXTAL
XTAL
CLKO
A0-A5
A6-7 (GPIOE2-E3)
A8-15 (GPIOA0-A7)
D0–D15
PS
DS
RD
WR
PHASEA0 (TA0)
PHASEB0 (TA1)
INDEX0 (TA2)
HOME0 (TA3)
PHASEA1 (TB0)
PHASEB1 (TB1)
INDEX1 (TB2)
HOME1 (TB3)
TCK
TMS
TDI
TDO
TRST
DE
Quadrature
Decoder0 or
Quad Timer A
JTAG/OnCE™
Port
GPIOB0–7
GPIOD0–5
PWMA0-5
ISA0-2
FAULTA0-3
PWMB0-5
ISB0-2
FAULTB0-3
SCLK (GPIOE4)
MOSI (GPIOE5)
MISO (GPIOE6)
SS (GPIOE7)
TXD0 (GPIOE0)
RXD0 (GPIOE1)
TXD1 (GPIOD6)
RXD1 (GPIOD7)
ANA0-7
VREF
MSCAN_RX
MSCAN_TX
TC0-1
TD0-3
IRQA
IRQB
RESET
RSTO
EXTBOOT
PWMB
Port
Quad
Timers
C & D
ADCA
Port
Other
Supply
Ports
8
8*
1
1
2
1
1
1
1
6
2
8
16
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Interrupt/
Program
Control
8
6
6
3
4
6
3
4
1
1
1
1
1
1
1
1
8
1
1
1
2
4
1
1
1
1
1
Quadrature
Decoder1 or
Quad Timer B
PWMA
Port
SPI Port
or GPIO
CAN
*includes TCS pin which is reserved for factory use and is tied to VSS
56F805 Technical Data, Rev. 16
10 Freescale Semiconductor
2.2 Power and Ground Signals
Table 2-2 Power Inputs
No. of Pins Signal Name Signal Description
8VDD Power—These pins provide power to the internal structures of the chip, and
should all be attached to VDD.
1VDDA Analog Power—This pin is a dedicated power pin for the analog portion of the
chip and should be connected to a low noise 3.3V supp ly.
Table 2-3 Grounds
No. of Pins Signal Name Signal Description
7VSS GND—These pins provide grounding for the internal structures of the chip, and
should all be attached to VSS.
1VSSA Analog Ground —This pin supplies an analog ground.
1TCS TCS—This Schmitt pin is reserved for factory use and must be tied to VSS for
normal use. In block diagrams, this pin is considered an additional VSS.
Table 2-4 Supply Capacitors and VPP
No. of
Pins Signal
Name Signal
Type State During
Reset Signal Description
2VCAPC Supply Supply VCAPC—Connect each pin to a 2.2μF or greater byp a ss
capacitor in order to bypass the core logic voltage regulator,
required for proper chip operation. For more information,
please refer to Section 5.2.
1VPP Input Input VPP—This pin should be left unconnected as an open circuit
for normal functionality.
Clock and Phase Locked Loop Signals
56F805 Technica l Data, Rev. 16
Freescale Semiconductor 11
2.3 Clock and Phase Locked Loop Signals
2.4 Address, Data, and Bus Control Signals
Table 2-5 PLL and Clock
No. of
Pins Signal
Name Signal
Type State During
Reset Signal Description
1EXTAL Input Input External Crystal Oscillator Input—This input sh ou l d be
connected to an 8MHz external crystal or ceramic resonator. For
more information, please refe r to Section 3.5.
1XTAL Input/O
utput Chip-driven Crystal Oscillator Output—This output should be connected to
an 8MHz external crystal or ceramic resonator. For more
information, please refer to Section 3.5.
This pin can also be connected to an external clock source. For
more information, please refe r to Section 3.5.3.
1CLKO Output Chip-driven Clock Output—This pin outputs a buffered clock sign al. By
programming the CLKOSEL[4:0] bits in the CLKO Select
Register (CLKOSR), the user can select between outputting a
version of the signal applied to XTAL and a version of the
device’s master clock at the output of the PLL. The clock
frequency on this pin can also be disabled by programming the
CLKOSEL[4:0] bits in CLKOSR.
Table 2-6 Address Bus Signals
No. of
Pins Signal
Name Signal
Type State During
Reset Signal Description
6A0–A5 Output Tri-stated Address Bus—A0–A5 specify the address for external
Program or Data memory accesses.
2A6–A7
GPIOE2–
GPIOE3
Output
Input/O
utput
Tri-stated
Input
Address Bus—A6–A7 specify the address for external
Program or Data memory accesses.
Port E GPIO—These two General Purpose I/O (GPIO) pins
can be individually programmed as input or output pins.
After reset, the default state is Address Bus.
8A8–A15
GPIOA0–
GPIOA7
Output
Input/O
utput
Tri-stated
Input
Address Bus—A8–A15 specify th e address for external
Program or Data memory accesses.
Port A GPIO—These eight General Purpose I/O (GPIO) pins
can be individually be programmed as input or output pins.
After reset, the default state is Address Bus.
56F805 Technical Data, Rev. 16
12 Freescale Semiconductor
Table 2-7 Data Bus Signals
No. of
Pins Signal
Name Signal
Type State During
Reset Signal Description
16 D0–D15 Input/O
utput Tri-stated Data Bus— D0–D15 specify the data for external Program or
Data memory accesses. D0–D15 are tri-stated when the external
bus is inact ive. Internal pullups may be active.
Table 2-8 Bus Control Signals
No. of
Pins Signal
Name Signal
Type State During
Reset Signal Description
1PS Output Tri-stated Program Memory Se lect—PS is asserted low for external
Program memory access.
1DS Output Tri-stated Data Memory Select—DS is asserted low for external Data
memory access.
1WR Output Tri-stated Write Enable—WR is asserted during external memo ry write
cycles. When WR is asserted low, pins D0–D15 become
outputs and the device puts data on the bus. When WR is
deasserted high, the external data is latched inside the
external device. When WR is asserted, it qualifies the A0–A15,
PS, and DS pins. WR can be connected directly to the WE pin
of a Static RAM.
1RD Output Tri-stated Read Enable—RD is asserted during external memory read
cycles. When RD is asserted low, pins D0–D15 become inputs
and an external device is enabled onto the device’s data bus.
When RD is deasserted high, the exte rnal data is latched
inside the device. When RD is asserte d, it qualifies the
A0–A15, PS, and DS pins. RD can be connected directly to
the OE pin of a Static RAM or ROM.
Interrupt and Program Control Signals
56F805 Technica l Data, Rev. 16
Freescale Semiconductor 13
2.5 Interrupt and Program Control Signals
Table 2-9 Interrupt and Program Control Signals
No. of
Pins Signal
Name Signal
Type
State
During
Reset Signal Description
1IRQA Input
(Schmitt) Input External Interrupt Request A—The IRQA input is a synchronized
external interrupt request indicating an external device is requesting
service. It can be programmed to be level-sensitive or
negative-edge-triggered.
1IRQB Input
(Schmitt) Input External Interrupt Request B—The IRQB inpu t is an external
interrupt request indicating an external device is requesting service.
It can be programmed to be level-sensitive or
negative-edge-triggered.
1RESET Input
(Schmitt) Input Reset—This input is a direct hardware reset on the processor.
When RESET is asserted low, the device is initialized and placed in
the Reset state. A Schmitt trigger input is used for noise immunity.
When the RESET pin is deasserted, the initial chip operating mode
is latched from the EXTBOOT pin. The internal reset signal will be
deasserted synchronous with the internal clocks, after a fixed
number of internal clocks.
To ensure complete hardware reset, RESET and TRST should be
asserted together. The only exce ption occurs in a debugging
environment when a hardware device reset is required and it is
necessary not to reset the OnCE/JTAG module. In this case, assert
RESET, but do not assert TRST.
1RSTO Output Output Reset Output—This output reflects the internal reset state of the
chip.
1EXTBOOT Input
(Schmitt) Input External Boot—This input is tied to VDD to force device to boot
from off-chip memory. Otherwise, it is tied to VSS.
56F805 Technical Data, Rev. 16
14 Freescale Semiconductor
2.6 GPIO Signals
2.7 Pulse Width Modulator (PWM) Signals
Table 2-10 Dedicated General Purpose Input/Output (GPIO) Signals
No. of
Pins Signal
Name Signal
Type State During
Reset Signal Description
8GPIOB0–
GPIOB7 Input or
Output Input Port B GPIO—These eight dedicated Gene ral Purpose I/O
(GPIO) pins can be individually programmed as input or output
pins.
After reset, the default state is GPIO input.
6GPIOD0–
GPIOD5 Input or
Output Input Port D GPIO—These six dedicated General Purpose I/O (GPIO)
pins can be individually programmed as input or output pins.
After reset, the default state is GPIO input.
Table 2-11 Pulse Width Modulator (PWMA and PWMB) Signals
No. of
Pins Signal
Name Signal
Type State During
Reset Signal Description
6PWMA0–5Output Tri- stated PWMA0–5—These are six PWMA output pins.
3ISA0–2Input
(Schmitt) Input ISA0–2—These three input current status pins are used for
top/bottom pulse width correction in complementary
channel operation for PWMA.
4FAULTA0–3Input
(Schmitt) Input FAULTA0–3—These four Fault input pins are used for
disabling selected PWMA outputs in cases where fault
conditions originate off-chip.
6PWMB0–5Output Output PWMB0–5—These are six PWMB output pins.
3ISB0–2Input
(Schmitt) Input ISB0–2— These three input current status pins are used
for top/bottom pulse width correction in complementary
channel operation for PWMB.
4FAULTB0–3Input
(Schmitt) Input FAULTB0–3—These four Fault input pins are used for
disabling selected PWMB outputs in cases where fault
conditions originate off-chip.
Serial Peripheral Interface (SPI) Signals
56F805 Technica l Data, Rev. 16
Freescale Semiconductor 15
2.8 Serial Peripheral Interface (SPI) Signals
Table 2-12 Serial Peripheral Interface (SPI) Signals
No. of
Pins Signal
Name Signal
Type State During
Reset Signal Description
1MISO
GPIOE6
Input/
Output
Input/
Output
Input
Input
SPI Master In/Slave Out (MISO)—This serial data pin is an input to
a master device and an output from a slave device. The MISO line
of a slave device is placed in the high-impedance state if the slave
device is not selected.
Port E GPIO—This pin is a Gene ra l Purpose I/O (GPIO) pin that
can individually be programmed as an input or output pin .
After reset, the default state is MISO.
1MOSI
GPIOE5
Input/
Output
Input/
Output
Input
Input
SPI Master Out/Slave In (MOSI) —This serial data pin is an output
from a master device and an input to a slave device. The master
device places data on the MOSI line a half-cycle before the clock
edge that the slave device uses to latch the data.
Port E GPIO—This General Purpose I/O (GPIO) pin can be
individually programmed as an input or output pin.
After reset, the default state is MOSI.
1SCLK
GPIOE4
Input/
Output
Input/
Output
Input
Input
SPI Serial Clock—In master mode, this pin serves as an output,
clocking slaved listeners. In slave mode, this pin serves as the data
clock input.
Port E GPIO—This General Purpose I/O (GPIO) pin can be
individually programmed as an input or output pin.
After reset, the default state is SCLK.
1SS
GPIOE7
Input
Input/
Output
Input
Input
SPI Slave Select—In master mode, this pin is used to arbitrate
multiple masters. In slave mode, this pin is used to select the slave.
Port E GPIO—This General Purpose I/O (GPIO) pin can be
individually programmed as an input or output pin.
After reset, the default state is SS.
56F805 Technical Data, Rev. 16
16 Freescale Semiconductor
2.9 Quadrature Decoder Signals
Table 2-13 Quadrature Decoder (Quad Dec0 and Quad Dec1) Signals
No. of
Pins Signal
Name Signal
Type State During
Reset Signal Description
1PHASEA0
TA0
Input
Input/Output
Input
Input
Phase A—Quadrature Decoder #0 PHASEA input
TA0—Timer A Channel 0
1PHASEB0
TA1
Input
Input/Output
Input
Input
Phase B—Quadrature Decoder #0 PHASEB input
TA1—Timer A Channel 1
1INDEX0
TA2
Input
Input/Output
Input
Input
Index—Quadrature Decoder #0 INDEX input
TA2—Timer A Channel 2
1HOME0
TA3
Input
Input/Output
Input
Input
Home—Quadrature Decoder #0 HOME input
TA3—Timer A Channel 3
1PHASEA1
TB0
Input
Input/Output
Input
Input
Phase A—Quadrature Decoder #1 PHASEA input
TB0—Timer B Channel 0
1PHASEB1
TB1
Input
Input/Output
Input
Input
Phase B—Quadrature Decoder #1 PHASEB input
TB1—Timer B Channel 1
1INDEX1
TB2
Input
Input/Output
Input
Input
Index—Quadrature Decoder #1 INDEX input
TB2—Timer B Channel 2
1HOME1
TB3
Input
Input/Output
Input
Input
Home—Quadrature Decoder #1 HOME input
TB3—Timer B Channel 3
Serial Communications Interface (SCI) Signals
56F805 Technica l Data, Rev. 16
Freescale Semiconductor 17
2.10 Serial Communications Interface (SCI) Signals
2.11 CAN Signals
Table 2-14 Serial Communications Interface (SCI0 and SCI1) Signals
No. of
Pins Signal
Name Signal
Type State During
Reset Signal Description
1TXD0
GPIOE0
Output
Input/Output
Input
Input
Transmit Data (TXD0)—SCI0 transmit data output
Port E GPIO—This pin is a General Purpose I/O (GPIO) pin that
can individually be programmed as inpu t or output pin.
After reset, the default state is SCI output.
1RXD0
GPIOE1
Input
Input/Output
Input
Input
Receive Data (RXD0)— SCI0 receive data input
Port E GPIO—This pin is a General Purpose I/O (GPIO) pin that
can individually be programmed as inpu t or output pin.
After reset, the default state is SCI input.
1TXD1
GPIOD6
Output
Input/Output
Input
Input
Transmit Data (TXD1)—SCI1 transmit data output
Port D GPIO—This pin is a General Purpose I/O (GPIO) pin that
can individually be programmed as an input or output pin.
After reset, the default state is SCI output.
1RXD1
GPIOD7
Input
Input/Output
Input
Input
Receive Data (RXD1)—SCI1 receive data input
Port D GPIO—This pin is a General Purpose I/O (GPIO) pin that
can individually be programmed as an input or output pin.
After reset, the default state is SCI input.
Table 2-15 CAN Module Signals
No. of
Pins Signal
Name Signal
Type State During
Reset Signal Description
1MSCAN_ RX Input
(Schmitt) Input MSCAN Receive Data—This is the MSCAN input. This pin has
an internal pull-up resistor.
1MSCAN_ TX Output Output MSCAN Transmit Data—MSCAN output. CAN output is
open-drain output and a pull-up resistor is needed.
56F805 Technical Data, Rev. 16
18 Freescale Semiconductor
2.12 Analog-to-Digital Converter (ADC) Signals
2.13 Quad Timer Module Signals
Table 2-16 Analog to Digital Converter Signals
No. of
Pins Signal
Name Signal
Type State During
Reset Signal Description
4ANA0–3Input Input ANA0–3—Analog inputs to ADC channel 1
4ANA4–7Input Input ANA4–7—Analog inputs to ADC channel 2
1VREF Input Input VREF—Analog reference voltage for ADC. Must be set to
VDDA - 0.3V for optimal performance.
Table 2-17 Quad Timer Module Signals
No. of
Pins Signal
Name Signal Type State Durin g
Reset Signal Description
2TC0-1 Input/Output Input TC0–1—Timer C Channels 0 and 1
4TD0-3 Input/Output Input TD0–3—Timer D Channe ls 0, 1, 2, and 3
JTAG/OnCE
56F805 Technica l Data, Rev. 16
Freescale Semiconductor 19
2.14 JTAG/OnCE
Part 3 Specifications
3.1 General Characteristics
The 56F805 is fabricated in high-density CMOS with 5V-tolerant TTL-compatible digital inputs. The term
“5V-tolerant” refers to the capability of an I/O pin, built on a 3.3V-compatible process technology, to
withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture of devices
designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V and 5V-compatible
I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of 3.3V ± 10% during
Table 2-18 JTAG/On-Chip Emulation (OnCE) Signals
No. of
Pins Signal
Name Signal
Type State During
Reset Signal Description
1TCK Input
(Schmitt) Input, pulled
low internally Test Clock Input—This input pin provides a gated clock to
synchronize the test logic and shift serial data to the JTAG/OnCE
port. The pin is connected internally to a pull-down resistor.
1TMS Input
(Schmitt) Input, pulled
high internally Test Mode Select Input—This input pin is used to sequence the
JTAG TAP controller’s state machine. It is sampled on the rising
edge of TCK and has an on-chip pull-up resistor.
Note: Always tie the TMS pin to VDD through a 2.2K resistor.
1TDI Input
(Schmitt) Input, pulled
high internally Test Data Input—This input pin provides a serial input data stream
to the JTAG/OnCE port. It is sampled on the rising edge of TCK and
has an on-chip pull-up resistor.
1TDO Output Tri-stated Test Data Output—This tri-statable output pin provides a serial
output data stream from the JTAG/OnCE port. It is driven in the
Shift-IR and Shift-DR controller states, and changes on the fa lling
edge of TCK.
1TRST Input
(Schmitt) Input, pulled
high internally Test Reset—As an input, a low signal on this pin provides a reset
signal to the JTAG TAP controller. To ensure complete hardware
reset, TRST should be asserted at power-up and whenever RESET
is asserted. The only exception occurs in a debugging environment
when a hardware device reset is required and it is necessary not to
reset the OnCE/JTAG module. In this case, assert RESET, but do
not assert TRST.
Note: For normal operation, connect TRST directly to VSS. If the design
is to be used in a debugging environment, TRST may be tied to VSS
through a 1K resistor.
1DE Output Output Debug Event—DE provides a low pulse on recognized debug
events.
56F805 Technical Data, Rev. 16
20 Freescale Semiconductor
normal operation without causing damage). This 5V-tolerant capability therefore offers the power savings
of 3.3V I/O levels while being able to receive 5V levels without being damaged.
Absolute maximum ratings given in Table 3-1 are stress ratings only, and functional operation at the
maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent
damage to the device.
The 56F805 DC/AC electrical specifications are preliminary and are from design simulations. These
specifications may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized
specifications will be published after complete characterization and device qualifications have been
completed.
CAUTION
This device contains protective circuitry to guard against damage due
to high static voltage or electrical fields. However, normal precautions
are advised to avoid application of any voltages higher than maximum
rated voltages to this high-impedance circuit. Reliability of operation
is enhanced if unused inputs are tied to an appropriate voltage level.
Table 3-1 Absolute Maximum Ratings
Characteristic Symbol Min Max Unit
Supply voltage VDD VSS – 0.3 VSS + 4.0 V
All other input voltages, excluding Analog inputs, EXTAL
and XTAL VIN VSS – 0.3 VSS + 5.5V V
Voltage difference VDD to VDDA ΔVDD - 0.3 0.3 V
Voltage difference VSS to VSSA ΔVSS - 0.3 0.3 V
Analog inputs, ANA0-7 and VREF VIN VSSA – 0.3 VDDA + 0.3 V
Analog inputs EXTAL and XTAL VIN VSSA– 0.3 VSSA+ 3.0 V
Current drain per pin excluding VDD, VSS, PWM outputs,
TCS, VPP, VDDA, VSSA
I—10mA
Table 3-2 Recommended Operating Conditions
Characteristic Symbol Min Typ Max Unit
Supply voltage, digital VDD 3.0 3.3 3.6 V
Supply Voltage, analog VDDA 3.0 3.3 3.6 V
General Characteristics
56F805 Technica l Data, Rev. 16
Freescale Semiconductor 21
Notes:
1. Theta-JA determined on 2s2p test boards is frequently lower than would be observed in an application.
Determined on 2s2p thermal test board.
2. Junction to ambient thermal resistance, Theta-JA (RθJA) was simulated to be equ ivalen t to th e JEDEC
specification JESD51-2 in a horizontal configuration in natural convection. Theta-JA was also simulated on
a thermal test board with two internal planes (2s2p where “s” is the number of signal layers and “p” is the
number of planes) per JESD51-6 and JESD51-7. The correct name for Theta-JA for forced convection or with
the non-single layer boards is Theta-JMA.
3. Junction to case thermal resistance, Theta-JC (RθJC ), was simulated to be equivalent to the measured values
using the cold plate technique with the cold plate temperature used as the “case” temperature. The basic cold
plate measurement technique is described by MIL-STD 883D, Method 1012.1. This is the correct thermal
metric to use to calculate thermal perform ance when the package is being used with a heat sink.
Voltage difference VDD to VDDA ΔVDD -0.1 - 0.1 V
Voltage difference VSS to VSSA ΔVSS -0.1 - 0.1 V
ADC reference voltage VREF 2.7 – VDDA V
Ambient operating temperature TA–40 – 85 °C
Table 3-3 Thermal Characteristics6
Characteristic Comments Symbol Value Unit Notes
144-pin LQFP
Junction to ambient
Natural convection RθJA 47.1 °C/W 2
Junction to ambient (@1m/sec) RθJMA 43.8 °C/W 2
Junction to ambient
Natural convection Four layer board
(2s2p) RθJMA
(2s2p) 40.8 °C/W 1,2
Junction to ambient (@1m/sec) Four layer board
(2s2p) RθJMA 39.2 °C/W 1,2
Junction to case RθJC 11.8 °C/W 3
Junction to center of case ΨJT 1°C/W4, 5
I/O pin power dissipation P I/O User Determined W
Power dissipation P D P D = (IDD x VDD + P I/O)W
Junction to center of case PDMAX (TJ - TA) /RθJA W7
Table 3-2 Recommended Operating Conditions
Characteristic Symbol Min Typ Max Unit
56F805 Technical Data, Rev. 16
22 Freescale Semiconductor
4. Thermal Characterization Parameter, Psi-JT (ΨJT ), is the “resistance” from junction to reference point
thermocouple on top center of case as defined in JESD51-2. ΨJT is a useful value to use to estimate junction
temperature in steady-state customer environments.
5. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and
board thermal resistance.
6. See Section 5.1 from more details on thermal design considerations.
7. TJ = Junction Temperature
TA = Ambient Temperature
3.2 DC Electrical Characteristics
Table 3-4 DC Electrical Characteristics
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz
Characteristic Symbol Min Typ Max Unit
Input high voltage (XTAL/EXTAL) VIHC 2.25 — 2.75 V
Input low voltage (XTAL/EXTAL) VILC 0—0.5V
Input high voltage (Schmitt trigger inputs)1VIHS 2.2 — 5.5 V
Input low voltage (Schmitt trigger inputs)1VILS -0.3 — 0.8 V
Input high voltage (all other digital inputs) VIH 2.0 — 5.5 V
Input low voltage (all other digital inputs) VIL -0.3 — 0.8 V
Input current high (pullup/pulldown resistors disabled, VIN=VDD)I
IH -1 — 1 μA
Input current low (pullup/pulldown resistors disabled, VIN=VSS)I
IL -1 — 1 μA
Input current high (with pullup resistor, VIN=VDD)I
IHPU -1 — 1 μA
Input current low (with pullup resistor, VIN=VSS)I
ILPU -210 — -50 μA
Input current high (with pulldown re sistor, VIN=VDD)I
IHPD 20 — 180 μA
Input current low (with pulldown resistor, VIN=VSS)I
ILPD -1 — 1 μA
Nominal pullup or pulldown resi stor value RPU, RPD 30 KΩ
Output tri-state current low IOZL -10 — 10 μA
Output tri-state current high IOZH -10 — 10 μA
Input current high (analog inputs, VIN=VDDA)2IIHA -15 — 15 μA
Input curr en t l ow (analog inputs, VIN=VSSA)3IILA -15 — 15 μA
Output High Voltage (at IOH) VOH VDD – 0.7 — — V
DC Electrical Characteristics
56F805 Technica l Data, Rev. 16
Freescale Semiconductor 23
Output Low Voltage (at IOL) VOL ——0.4V
Output source current IOH 4——mA
Output sink current IOL 4——mA
PWM pin output source current3IOHP 10 — — mA
PWM pin output sink current4IOLP 16 — — mA
Input capacitance CIN —8—pF
Output capacitance COUT —12—pF
VDD supply current IDDT5
Run 6— 126 152 mA
Wait7— 105 129 mA
Stop —6084mA
Low Voltage Interrupt, external power supply8VEIO 2.4 2.7 3.0 V
Low Voltage Interrupt, internal power supply9VEIC 2.0 2.2 2.4 V
Power on Reset10 VPOR —1.72.0V
1. Schmitt Trigger inputs are: EXTBOOT, IRQA, IRQB, RESET, ISA0-2, FAULTA0-3, ISB0-2, FAULT0B-3, TCS, TCK, TRST, TMS,
TDI, and MSCAN_RX
2. Analog inputs are: ANA[0:7], XTAL and EXTAL. Specification assumes ADC is not sampling.
3. PWM pin output source current measured with 50% duty cycle.
4. PWM pin output sink current measured with 50% duty cycle.
5. IDDT = IDD + IDDA (Total supply current for VDD + VDDA)
6. Run (operating) IDD measured using 8MHz clock source. All inputs 0.2V from rail; outputs unloaded. All ports configured as inputs;
measured with all modules enabled.
7. Wait IDD measured using external square wave clock source (fosc = 8MHz) into XTAL; all inputs 0.2V from rail; no DC loads; less
than 50pF on all outputs. CL = 20pF on EXTAL; all ports configured as inputs; EXTAL capacitance linearly affects wait IDD; measured
with PLL enabled.
8. This low voltage interrupt monitors the VDDA external power supply. V DDA is gener ally connected to the same potential as VDD
via separate traces. If VDDA drops below VEIO, an in terrupt is generated. Functionality of the device is guaranteed u nder transient
conditions when VDDA>VEIO (between the minimum specified VDD and the point when the VEIO interrupt is generated).
9. This low voltage interrupt monitors the internally regulated core power supply. If the output from the in ternal volta ge is re gulator
drops below VEIC, an interrupt is generated. Since the core logic supply is internally regulated, this interrupt will not be generated
unless the external power supply drops below the minimum specified value (3.0V).
10. Power–on reset occurs whenever the internally regulated 2.5V digital supply drops below 1.5V typical. While power is ramping
up, this signal remains active as long as the internal 2.5V is below 1.5V typical, no matter how long the ramp-up rate is. The internally
regulated voltage is typically 100mV less than VDD during ramp-up until 2.5V is reached, at which time it self-regulates.
Table 3-4 DC Electrical Characteristics (Continued)
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz
Characteristic Symbol Min Typ Max Unit
56F805 Technical Data, Rev. 16
24 Freescale Semiconductor
Figure 3-1 Maximum Run IDD vs. Frequency (see Note 6. in Figure 3-14)
3.3 AC Electrical Characteristics
Timing waveforms in Section 3.3 are tested using the VIL and VIH levels specified in the DC Characteristics
table. In Figure 3-2 the levels of VIH and VIL for an input signal are shown.
Figure 3-2 Input Signal Measurement References
Figure 3-3 shows the definitions of the following signal states:
• Active state, when a bus or signal is driven, and enters a low impedance state
• Tri-stated, when a bus or signal is placed in a high impedance state
• Data Valid state, when a signal level has reached VOL or VOH
• Data Invalid state, when a signal level is in transition between VOL and VOH
0
30
90
120
180
60
20 40 60 80
Freq. (MHz)
IDD (mA)
150
IDD Digital IDD Analog IDD Total
VIH
VIL
Fall Time
Input Signal
Note: The midpoint is VIL + (VIH – VIL)/2.
Midpoint1
Low High 90%
50%
10%
Rise Time
Flash Memory Characteristics
56F805 Technica l Data, Rev. 16
Freescale Semiconductor 25
Figure 3-3 Signal States
3.4 Flash Memory Characteristics
Table 3-5 Flash Memory Truth Table
Mode XE1
1. X address enable, all rows are disabled when XE = 0
YE2
2. Y address enable, YMUX is disabled when YE = 0
SE3
3. Sense amplifier enable
OE4
4. Output enable, tri-state Flash data out bus when OE = 0
PROG5
5. Defines program cycle
ERASE6
6. Defines erase cycle
MAS17
7. Defines mass erase cycle, erase whole block
NVSTR8
8. Defines non-volatile store cycle
Standby L L L L L L L L
Read HHHH L L L L
Word Program H H L L H L L H
Page Erase H L L L L H L H
Mass Erase H L L L L H H H
Table 3-6 IFREN Truth Table
Mode IFREN = 1 IFREN = 0
Read Read information block Read main memory block
Word program Program information block Program main memory block
Page erase Erase information block Erase main memory block
Mass erase Erase both block Erase main memory block
Data Invalid State
Data1
Data2 Valid
Data
Tri-stated
Data3 Valid
Data2 Data3
Data1 Valid
Data Active Data Active
56F805 Technical Data, Rev. 16
26 Freescale Semiconductor
Table 3-7 Flash Timing Parameters
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6V, TA = –40° to +85°C, CL ≤ 50pF
Characteristic Symbol Min Typ Max Unit Figure
Program time Tprog* 20 – – us Figure 3-4
Erase time Terase* 20 – – ms Figure 3-5
Mass erase time Tme* 100 – – ms Figure 3-6
Endurance1
1. One cycle is equal to an erase program and read.
ECYC 10,000 20,000 – cycles
Data Retention1DRET 10 30 – years
The following parameters should only be used in the Manual Word Programmin g Mode
PROG/ERASE to NVSTR set up
time Tnvs* –5–usFigure 3-4,
Figure 3-5,
Figure 3-6
NVSTR hold time Tnvh* –5–usFigure 3-4,
Figure 3-5
NVSTR hold time (mass erase) Tnvh1* – 100 – us Figure 3-6
NVSTR to program set up time Tpgs* –10–usFigure 3-4
Recovery time Trcv* –1–usFigure 3-4,
Figure 3-5,
Figure 3-6
Cumulative program
HV period2
2. Thv is the cumulative high voltage programming time to the same row before next erase. The same address cannot be pro-
grammed twice before next erase.
Thv –3–ms Figure 3-4
Program hold time3
3. Parameters are guaranteed by design in smart programming mode and must be one cycle or greater.
*The Flash interface unit provides registers for the control of these parameters.
Tpgh ––– Figure 3-4
Address/data set up time3Tads ––– Figure 3-4
Address/data hold time3Tadh ––– Figure 3-4
Flash Memory Characteristics
56F805 Technica l Data, Rev. 16
Freescale Semiconductor 27
Figure 3-4 Flash Program Cycle
Figure 3-5 Flash Erase Cycle
XADR
YADR
YE
DIN
PROG
NVSTR
Tnvs
Tpgs
Tadh
Tprog
Tads
Tpgh
Tnvh Trcv
Thv
IFREN
XE
XADR
YE=SE=OE=MAS1=0
ERASE
NVSTR
Tnvs
Tnvh Trcv
Terase
IFREN
XE
56F805 Technical Data, Rev. 16
28 Freescale Semiconductor
Figure 3-6 Flash Mass Erase Cycle
3.5 External Clock Operation
The 56F805 system clock can be derived from a crystal or an external system clock signal. To generate a
reference frequency using the internal oscillator, a reference crystal must be connected between the
EXTAL and XTAL pins.
3.5.1 Crystal Oscillator
The internal oscillator is also designed to interface with a parallel-resonant crystal resonator in the
frequency range specified for the external crystal in Table 3-9. In Figure 3-7 a recommended crystal
oscillator circuit is shown. Follow the crystal supplier’s recommendations when selecting a crystal,
because crystal parameters determine the component values required to provide maximum stability and
reliable start-up. The crystal and associated components should be mounted as close as possible to the
EXTAL and XTAL pins to minimize output distortion and start-up stabilization time. The internal 56F80x
oscillator circuitry is designed to have no external load capacitors present. As shown in Figure 3-8, no
external load capacitors should be used.
The 56F80x components internally are modeled as a parallel resonant oscillator circuit to provide a
capacitive load on each of the oscillator pins (XTAL and EXTAL) of 10pF to 13pF over temperature and
process variations. Using a typical value of internal capacitance on these pins of 12pF and a value of 3pF
XADR
YE=SE=OE=0
ERASE
NVSTR
Tnvs
Tnvh1 Trcv
Tme
MAS1
IFREN
XE
External Clock Operation
56F805 Technica l Data, Rev. 16
Freescale Semiconductor 29
as a typical circuit board trace capacitance the parallel load capacitance presented to the crystal is 9pF as
determined by the following equation:
This is the value load capacitance that should be used when selecting a crystal and determining the actual
frequency of operation of the crystal oscillator circuit.
Figure 3-7 Connecting to a Crystal Oscillator
3.5.2 Ceramic Resonator
It is also possible to drive the internal oscillator with a ceramic resonator, assuming the overall system
design can tolerate the reduced signal integrity. In Figure 3-8, a typical ceramic resonator circuit is shown.
Refer to supplier’s recommendations when selecting a ceramic resonator and associated components. The
resonator and components should be mounted as close as possible to the EXTAL and XTAL pins. The
internal 56F80x oscillator circuitry is designed to have no external load capacitors present. As shown in
Figure 3-7 no external load capacitors should be used.
Figure 3-8 Connecting a Ceramic Resonator
Note: Freescale recommends only two terminal ceramic resonators vs. three terminal resonators
(which contain an in ternal bypass capacitor to gr ound).
CL = CL1 * CL2
CL1 + CL2 + Cs = + 3 = 6 + 3 = 9pF
12 * 12
12 + 12
Recommended External Crystal
Parameters:
Rz = 1 to 3 MΩ
fc = 8MHz (optimized for 8MHz)
EXTAL XTAL
Rz
fc
Recommended Ceramic Resonator
Parameters:
Rz = 1 to 3 MΩ
fc = 8MHz (optimized for 8MHz)
EXTAL XTAL
Rz
fc
56F805 Technical Data, Rev. 16
30 Freescale Semiconductor
3.5.3 External Clock Source
The recommended method of connecting an external clock is given in Figure 3-9. The external clock
source is connected to XTAL and the EXTAL pin is grounded.
Figure 3-9 Connecting an External Clock Signal
Figure 3-10 External Clock Timing
Table 3-8 External Clock Operation Timing Requirements3
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6V, TA = –40° to +85°C
Characteristic Symbol Min Typ Max Unit
Frequency of operation (external clock driver)1
1. See Figure 3-9 for details on using the recommended connection of an external clock driver.
fosc 0—80MHz
Clock Pulse Width2, 5
2. The high or low pulse width must be no smaller than 6.25ns or the chip will not function. However, the high pulse width
does not have to be any particular percent of the low pulse width.
3. Parameters listed are guaranteed by design.
tPW 6.25 — — ns
56F805
XTAL EXTAL
External VSS
Clock
External
Clock
VIH
VIL
Note: The midpoint is VIL + (VIH – VIL)/2.
90%
50%
10%
90%
50%
10% tPW tPW
External Clock Operation
56F805 Technica l Data, Rev. 16
Freescale Semiconductor 31
3.5.4 Phase Locked Loop Timing
Table 3-9 PLL Timing
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6V, TA = –40° to +85°C
Characteristic Symbol Min Typ Max Unit
External reference crystal frequency for the PLL1
1. An externally supplied reference clock should be as free as possible from a ny phase jitter for the PLL to work
correctly. The PLL is optimized for 8MHz input crystal.
fosc 4810MHz
PLL output frequency2
2. ZCLK may not exceed 80MHz. For additional information o n ZCLK and fout/2, please refer to the OCCS chapter in the
User Manual. ZCLK = fop
fout/2 40 — 110 MHz
PLL stabilization time 3 0o to +85oC
3. This is the minimum time required after the PLL set-up is changed to ensure reliable operation.
tplls —110ms
PLL stabilization time3 -40o to 0oCtplls — 100 200 ms
56F805 Technical Data, Rev. 16
32 Freescale Semiconductor
3.6 External Bus Asynchronous Timing
Table 3-10 External Bus Asynchronous Timing 1, 2
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz
Characteristic Symbol Min Max Unit
Address Valid to WR Asserted tAWR 6.5 — ns
WR Width Asserted
Wait states = 0
Wait states > 0
tWR 7.5
(T*WS)+7.5 —
—ns
ns
WR Asserted to D0–D15 Out Valid tWRD —T+4.2ns
Data Out Hold Time from WR Deasserted tDOH 4.8 — ns
Data Out Set Up Time to WR Deasserted
Wait states = 0
Wait states > 0
tDOS 2.2
(T*WS)+6.4 —
—ns
ns
RD Deasserted to Address Not Valid tRDA 0—ns
Address Valid to RD Deasserted
Wait states = 0
Wait states > 0
tARDD 18.7
(T*WS) + 18.7
—ns
ns
Input Data Hold to RD Deasserted tDRD 0—ns
RD Assertion Width
Wait states = 0
Wait states > 0
tRD 19
(T*WS)+19 —
—ns
ns
Address Valid to Input Data Valid
Wait states = 0
Wait states > 0
tAD —
—1
(T*WS)+1 ns
ns
Address Valid to RD Asserted tARDA -4.4 — ns
RD Asserted to Input Data Valid
Wait states = 0
Wait states > 0
tRDD —
—2.4
(T*WS) + 2.4 ns
ns
WR Deasserted to RD Asserted tWRRD 6.8 — ns
RD Deasserted to RD Asserted tRDRD 0—ns
WR Deasserted to WR Asserted tWRWR 14.1 — ns
RD Deasserted to WR Asserted tRDWR 12.8 — ns
External Bus Asynchronous Timing
56F805 Technica l Data, Rev. 16
Freescale Semiconductor 33
Figure 3-11 External Bus Asynchronous Timing
1. Timing is both wait state- and frequency-dependent. In the formulas listed, WS = the number of wait states and
T = Clock Period. For 80MHz operation, T = 12.5ns.
2. Parameters listed are guaranteed by design.
To calculate the required access time for an external memory for any frequency < 80Mhz, use this formula:
Top = Clock period @ desired operating frequency
WS = Number of wait states
Memory Access Time = (Top*WS) + (Top- 11.5)
A0–A15,
PS, DS
(See Note)
WR
D0–D15
RD
Note: During read-modify-write instructions and internal instructions, the address li nes do not change state.
Data In
Data Out
tAWR
tARDA
tARDD tRDA
tRD tRDRD
tRDWR
tWRWR tWR
tDOS
tWRD
tWRRD
tAD
tDOH
tDRD
tRDD
56F805 Technical Data, Rev. 16
34 Freescale Semiconductor
3.7 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Table 3-11 Reset, Stop, Wait, Mode Select, and Interrupt Timing 1, 6
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF
1. In the formulas, T = clock cycle. For an operating frequency of 80MHz, T = 12.5ns.
Characteristic Symbol Min Max Unit See Figure
RESET Assertion to Address, Data and Control
Signals High Impedance tRAZ —21nsFigure 3-12
Minimum RESET Assertion Duration2
OMR Bit 6 = 0
OMR Bit 6 = 1
2. Circuit stabilization delay is required during reset when using an external clock or crystal oscillator in two cases:
• After power-on reset
• When recovering from Stop state
tRA 275,000T
128T —
—ns
ns
Figure 3-12
RESET Deassertion to First External Address Output tRDA 33T 34T ns Figure 3-12
Edge-sensitive Interrupt Request Width tIRW 1.5T — ns Figure 3-13
IRQA, IRQB Assertion to External Data Memory
Access Out Valid, caused by first instruction
execution in the int errupt service routine
tIDM 15T — ns Figure 3-14
IRQA, IRQB Assertion to General Purpose Output
Valid, caused by first instruction execution in the
interrupt service routine
tIG 16T — ns Figure 3-14
IRQA Low to First Valid Interrupt Vector Address Out
recovery from Wait State3
3. The minimum is specified for the duration of an edge-sensit ive IRQA interr upt re quired to r eco ver from the Stop state. This is
not the minimum required so that the IRQA interrupt is accepted.
tIRI 13T — ns Figure 3-15
IRQA Width Assertion to Recover from Stop State4
4. The interrupt instruction fetch is visible on the pins only in Mode 3.
tIW 2T — ns Figure 3-16
Delay from IRQA Assertion to Fetch of first instruction
(exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
tIF
—
—275,000T
12T ns
ns
Figure 3-16
Duration for Level Sensitive IRQA Assertion to Cause
the Fetch of First IRQA Interrupt Instruction (exiting
Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
tIRQ
—
—275,000T
12T ns
ns
Figure 3-17
Delay from Level Sensitive IRQA Assertion to First
Interrupt Vector Address Out Valid (exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
tII
—
—275,000T
12T ns
ns
Figure 3-17
RSTO pulse width5
normal operati on
internal reset mode
5. ET = External Clock period, For an external crystal frequency of 8MHz, ET=125ns.
6. Parameters listed are guaranteed by design.
tRSTO 63ET
2,097,151ET ns
ns
Figure 3-18
Reset, Stop, Wait, Mode Select, and Interrupt Timing
56F805 Technica l Data, Rev. 16
Freescale Semiconductor 35
Figure 3-12 Asynchronous Reset Timing
Figure 3-13 External Interrupt Timing (Negative-Edge-Sensitive)
Figure 3-14 External Level-Sensitive Interrupt Timing
First Fetch
A0–A15,
D0–D15
PS, DS,
RD, WR
RESET
First Fetch
tRDA
tRA
tRAZ
IRQA
IRQB tIRW
A0–A15,
PS, DS,
RD, WR
IRQA,
IRQB
First Interrupt Instruction Execution
a) First Interrupt Instruction Execution
Purpose
I/O Pin
IRQA,
IRQB
b) General Purpose I/O
tIG
tIDM
56F805 Technical Data, Rev. 16
36 Freescale Semiconductor
Figure 3-15 Interrupt from Wait State Timing
Figure 3-16 Recovery from Stop State Using Asynchronous Interrupt Timing
Figure 3-17 Recovery from Stop State Using IRQA Interrupt Service
Figure 3-18 Reset Output Timing
Instruction Fetch
IRQA,
IRQB
First Interrupt Vector
A0–A15,
PS, DS,
RD, WR
tIRI
Not IRQA Interrupt Vector
IRQA
A0–A15,
PS, DS,
RD, WR First Instruction Fetch
tIW
tIF
Instruction Fetch
IRQA
A0–A15
PS, DS,
RD, WR First IRQA Interrupt
tIRQ
tII
RSTO
tRSTO
Serial Peripheral Interface (SPI) Timing
56F805 Technica l Data, Rev. 16
Freescale Semiconductor 37
3.8 Serial Peripheral Interface (SPI) Timing
Table 3-12 SPI Timing1
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF, fOP = 80MHz
1. Parameters listed are guaranteed by design.
Characteristic Symbol Min Max Unit See Figure
Cycle time
Master
Slave
tC50
25 —
—ns
ns
Figures
3-19, 3-20,
3-21, 3-22
Enable lead time
Master
Slave
tELD —
25 —
—ns
ns
Figure 3-22
Enable lag time
Master
Slave
tELG —
100 —
—ns
ns
Figure 3-22
Clock (SCLK) high time
Master
Slave
tCH 17.6
12.5 —
—ns
ns
Figures
3-19, 3-20,
3-21, 3-22
Clock (SCLK) low time
Master
Slave
tCL 24.1
25 —
—ns
ns
Figure 3-22
Data set-up time required for inputs
Master
Slave
tDS 20
0—
—ns
ns
Figures
3-19, 3-20,
3-21, 3-22
Data hold time required for inputs
Master
Slave
tDH 0
2—
—ns
ns
Figures
3-19, 3-20,
3-21, 3-22
Access time (time to data active from
high-impedance state)
Slave
tA4.8 15 ns Figure 3-22
Disable time (hold time to high-impedance state)
Slave tD3.7 15.2 ns Figure 3-22
Data Valid for outputs
Master
Slave (after enable edge)
tDV —
—4.5
20.4 ns
ns
Figures
3-19, 3-20,
3-21, 3-22
Data invalid
Master
Slave
tDI 0
0—
—ns
ns
Figures
3-19, 3-20,
3-21, 3-22
Rise time
Master
Slave
tR—
—11.5
10.0 ns
ns
Figures
3-19, 3-20,
3-21, 3-22
Fall time
Master
Slave
tF—
—9.7
9.0 ns
ns
Figures
3-19, 3-20,
3-21, 3-22
56F805 Technical Data, Rev. 16
38 Freescale Semiconductor
Figure 3-19 SPI Master Timing (CPHA = 0)
Figure 3-20 SPI Master Timing (CPHA = 1)
SCLK (CPOL = 0)
(Output)
SCLK (CPOL = 1)
(Output)
MISO
(Input)
MOSI
(Output)
MSB in Bits 14–1 LSB in
Master MSB out Bits 14–1 Master LSB out
SS
(Input) SS is held High on master
tCtRtF
tCH
tCL
tFtR
tCH
tCH
tDV
tDH
tDS
tDI tDI(ref)
tFtR
tCL
SCLK (CPOL = 0)
(Output)
SCLK (CPOL = 1)
(Output)
MISO
(Input)
MOSI
(Output)
MSB in Bits 14–1 LSB in
Master MSB out Bits 14– 1 Master LSB out
SS
(Input) SS is held High on master
tR
tF
tC
tCH
tCL
tCH
tCL
tF
tDS tDH
tR
tDI
tDV(ref) tDV
tFtR
Serial Peripheral Interface (SPI) Timing
56F805 Technica l Data, Rev. 16
Freescale Semiconductor 39
Figure 3-21 SPI Slave Timing (CPHA = 0)
Figure 3-22 SPI Slave Timing (CPHA = 1)
SCLK (CPOL = 0)
(Input)
SCLK (CPOL = 1)
(Input)
MISO
(Output)
MOSI
(Input)
Slave MSB out Bits 14–1
MSB in Bits 14–1 LSB in
SS
(Input)
Slave LSB out
tDS
tCL
tCL
tDI tDI
tCH
tCH
tR
tR
tELG
tDH
tELD
tCtF
tFtD
tA
tDV
SCLK (CPOL = 0)
(Input)
SCLK (CPOL = 1)
(Input)
MISO
(Output)
MOSI
(Input)
Slave MSB out Bits 14–1
MSB in Bits 14–1 LSB in
SS
(Input)
Slave LSB out
tELG
tDI
tDS
tDH
tELD
tC
tCL tCH
tR
tF
tF
tCL
tCH
tDV
tA
tDV
tRtD
56F805 Technical Data, Rev. 16
40 Freescale Semiconductor
3.9 Quad Timer Timing
Figure 3-23 Timer Timing
3.10 Quadrature Decoder Timing
Table 3-13 Timer Timing1, 2
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6V, TA = –40° to +85°C, CL ≤ 50pF, fOP = 80MHz
1. In the formulas listed, T = clock cycle. For 80MHz operation, T = 12.5ns.
2. Parameters listed are guaranteed by design.
Characteristic Symbol Min Max Unit
Timer input period PIN 4T+6 — ns
Timer input high/low peri od PINHL 2T+3 — ns
Timer output period POUT 2T — ns
Timer output high/low period POUTHL 1T — ns
Table 3-14 Quadrature Decoder Timing1, 2
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6V, TA = –40° to +85°C, CL < 50pF, fOP = 80MHz
1. In the formulas listed, T = clock cycle. For 80MHz operation, T = 12.5ns. VSS = 0V, VDD = 3.0–3.6V,
TA = –40° to +85°C, CL ≤ 50pF.
2. Parameters listed are guaranteed by design.
Characteristic Symbol Min Max Unit
Quadrature input period PIN 8T+12 — ns
Quadrature input high/low perio d PHL 4T+6 — ns
Quadrature phase period PPH 2T+3 — ns
Timer Inputs
Timer Outputs
PINHL PINHL
PIN
POUTHL
POUTHL
POUT
Serial Communication Interface (SCI) Timing
56F805 Technica l Data, Rev. 16
Freescale Semiconductor 41
Figure 3-24 Quadrature Decoder Timing
3.11 Serial Communication Interface (SCI) Timing
Figure 3-25 RXD Pulse Width
Table 3-15 SCI Timing4
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6V, TA = –40° to +85°C, CL ≤ 50pF, fOP = 80MHz
Characteristic Symbol Min Max Unit
Baud Rate1
1. fMAX is the frequency of operation of the system clock in MHz.
BR — (fMAX*2.5)/(80) Mbps
RXD2 Pulse Width
2. The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1.
RXDPW 0.965/BR 1.04/BR ns
TXD3 Pulse Width
3. The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1.
4. Parameters listed are guaranteed by design.
TXDPW 0.965/BR 1.04/BR ns
Phase B
(Input)
Phase A
(Input)
PPH
PPH
PPH
PPH
PIN
PIN PHL PHL
PHL
PHL
RXD
SCI receive
data pin
(Input) RXDPW
56F805 Technical Data, Rev. 16
42 Freescale Semiconductor
Figure 3-26 TXD Pulse Width
3.12 Analog-to-Digital Converter (ADC) Characteristics
Table 3-16 ADC Characteristics
Characteristic Symbol Min Typ Max Unit
ADC input voltages VADCIN 01—VREF2V
Resolution RES 12 — 12 Bits
Integral Non-Linearity3INL — +/-2.5 +/-4 LSB4
Differential Non-Linearity DNL — +/- 0.9 +/-1 LSB4
Monotonicity GUARANTEED
ADC internal clock5fADIC 0.5 — 5 MHz
Conversion range RAD VSSA —V
DDA V
Conversion time tADC —6 —
tAIC cycles6
Sample time tADS —1 —
tAIC cycles6
Input capacitance CADI —5 — pF6
Gain Error (transfer gain)5EGAIN .95 1.00 1.10 —
Offset Voltage5VOFFSET -80 -15 +20 mV
Total Harmonic Distortion5THD 60 64 — dB
Signal-to-Noise plus Distortion5SINAD 55 60 — dB
Effective Number Of Bits5ENOB 9 10 — bit
Spurious Free Dynamic Range5SFDR 65 70 — dB
Bandwidth BW — 100 — KHz
TXD
SCI receive
data pin
(Input) TXDPW
Controller Area Network (CAN) Timing
56F805 Technica l Data, Rev. 16
Freescale Semiconductor 43
1. Parasitic capacitance due to package, pin to pin, and pin to package base coupling. (1.8pf)
2. Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing. (2.04pf)
3. Equivalent resistance for the ESD isolation resistor and the channel select mux. (500 ohms)
4. Sampling capacitor at the sample and hold circuit. (1pf)
Figure 3-27 Equivalent Analog Input Circuit
3.13 Controller Area Network (CAN) Timing
ADC Quiescent Current (both ADCs) IADC —50 — mA
VREF Quiescent Current (both ADCs) IVREF —1216.5 mA
1. For optimum ADC performance, keep the minimum VADCIN value > 25mV. Inputs less than 25mV may convert to a digital
output code of 0.
2. VREF must be equal to or less than VDDA and must be greater than 2.7V. For optimal ADC performance, set VREF to VD-
DA-0.3V.
3. .Measured in 10-90% range.
4. LSB = Least Significant Bit.
5. Guaranteed by characterization.
6. tAIC = 1/fADIC
Table 3-17 CAN Timing2
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF, MSCAN Clock = 30MHz
Characteristic Symbol Min Max Unit
Baud Rate BRCAN —1Mbps
Bus Wakeup detection 1
1. If Wakeup glitch filter is enabled during the design initialization and also CAN is put into Sleep mode then, any bus event
(on MSCAN_RX pin) whose duration is less than 5 microseconds is filtered away. However, a valid CAN bus wakeup detection
takes place for a wakeup pulse equal to or greater than 5 microseconds. The number 5 microseconds originates from the fact
that the CAN wakeup message consists of 5 dominant bits at the highest possible baud rate of 1Mbps.
2. Parameters listed are guaranteed by design.
T WAKEUP 5—us
Table 3-16 ADC Characteristics (Continued)
Characteristic Symbol Min Typ Max Unit
12
3
4
ADC analog input
56F805 Technical Data, Rev. 16
44 Freescale Semiconductor
Figure 3-28 Bus Wakeup Detection
3.14 JTAG Timing
Figure 3-29 Test Clock Input Timing Diagram
Table 3-18 JTAG Timing1, 3
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, C L ≤ 50pF, fOP = 80MHz
1. Timing is both wait state- and frequency-dependent. Fo r the values listed, T = clock cycle. For 80MHz operation,
T = 12.5ns.
Characteristic Symbol Min Max Unit
TCK frequency of operation2
2. TCK frequency of operation must be less than 1/8 the processor rate.
3. Parameters listed are guaranteed by design.
fOP DC 10 MHz
TCK cycle time tCY 100 — ns
TCK clock pulse width tPW 50 — ns
TMS, TDI data set-up time tDS 0.4 — ns
TMS, TDI data hold ti me tDH 1.2 — ns
TCK low to TDO data valid tDV — 26.6 ns
TCK low to TDO tri-state tTS — 23.5 ns
TRST assertion time tTRST 50 — ns
DE assertion time tDE 4T — ns
MSCAN_RX
CAN receive
data pin
(Input) T WAKEUP
TCK
(Input) VM
VIL
VM = VIL + (VIH – VIL)/2
VM
VIH
tPW
tPW
tCY
JTAG Timing
56F805 Technica l Data, Rev. 16
Freescale Semiconductor 45
Figure 3-30 Test Access Port Timing Diagram
Figure 3-31 TRST Timing Dia g ra m
Figure 3-32 OnCE—Debug Event
Input Data Valid
Output Data Valid
Output Data Valid
TCK
(Input)
TDI
(Input)
TDO
(Output)
TDO
(Output)
TDO
(Output)
TMS
tDV
tTS
tDV
tDS tDH
TRST
(Input) tTRST
DE tDE
56F805 Technical Data, Rev. 16
46 Freescale Semiconductor
Part 4 Packaging
4.1 Package and Pin-Out Information 56F805
This section contains package and pin-out information for the 144-pin LQFP configuration of the 56F805.
Figure 4-1 Top View, 56F805 144-pin LQFP Package
EXTBOOT
RESET
DE
CLKO
TD0
TD1
VDD
TD2
VSS
TD3
RSTO
SS
GPIOD3
MISO
GPIOD4
MOSI
SCLK
VCAPC
GPIOD5
D0
VPP
D1
D2
INDEX1
VDD
PHASEB1
VSS
PHASEA1
D3
HOME1
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
A0
VDD
VSS
A1
PWMB2
A2
PWMB3
A3
A4
A5
PWMB4
A6
PWMB5
A7
ISB0
A8
ISB1
A9
ISB2
A10
FAULTB0
A11
FAULTB1
A12
A13
VDD
PS
DS
A14
A15
VSS
WR
RD
IRQA
IRQB
FAULTB2
TCS
FAULTB3
TCK
TC0
TMS
TC1
TDI
TXD1
TDO
TRST
VCAPC
ISA0
VDD
ISA1
VSS
ISA2
RXD1
FAULTA0
MSCAN_TX
FAULTA1
MSCAN_RX
FAULTA2
FAULTA3
VREF
ANA0
ANA1
ANA2
ANA3
ANA4
ANA5
ANA6
ANA7
XTAL
EXTAL
VSSA
VDDA
VDD
VDD
VSS
GPIOB0
PHASEA0
GPIOB1
PHASEB0
GPIOB2
VDD
GPIOB3
VSS
GPIOB4
INDEX0
GPIOB5
HOME0
GPIOB6
PWMA0
GPIOB7
PWMA1
GPIOD0
PWMA2
GPIOD1
PWMA3
GPIOD2
PWMA4
PWMA5
TXD0
RXD0
Pin 1
Orientation Mark
Pin 73
Pin 109
Pin 37
PWMB0
PWMB1
Package and Pin-Out Information 56F805
56F805 Technica l Data, Rev. 16
Freescale Semiconductor 47
Table 4-1 56F805 Pin Identification by Pin Number
Pin
No. Signal Name Pin
No. Signal Name Pin
No. Signal Name Pin
No. Signal Name
1 D10 37 A14 73 ANA4 109 EXTBOOT
2 D11 38 A15 74 ANA5 110 RESET
3 D12 39 VSS 75 ANA6 111 DE
4 D13 40 WR 76 ANA7 112 CLKO
5 D14 41 RD 77 XTAL 113 TD0
6 D15 42 IRQA 78 EXTAL 114 TD1
7A043IRQB
79 VSSA 115 VDD
8V
DD 44 FAULTB2 80 VDDA 116 TD2
9PWMB045 TCS 81 V
DD 117 VSS
10 VSS 46 FAULTB3 82 VDD 118 TD3
11 PWMB1 47 TCK 83 VSS 119 RSTO
12 A1 48 TC0 84 GPIOB0 120 SS
13 PWMB2 49 TMS 85 PHASEA0 121 GPIOD3
14 A2 50 TC1 86 GPIOB1 122 MISO
15 PWMB3 51 TDI 87 PHASEB0 123 GPIOD4
16 A3 52 TXD1 88 GPIOB2 124 MOSI
17 A4 53 TDO 89 VDD 125 SCLK
18 A5 54 TRST 90 GPIOB3 126 VCAPC
19 PWMB4 55 VCAPC 91 VSS 127 GPIOD5
20 A6 56 ISA0 92 GPIOB4 128 D0
21 PWMB5 57 VDD 93 INDEX0 129 VPP
22 A7 58 ISA1 94 GPIOB5 130 D1
23 ISB0 59 VSS 95 HOME0 131 D2
24 A8 60 ISA2 96 GPIOB6 132 INDEX1
25 ISB1 61 RXD1 97 PWMA0 133 VDD
26 A9 62 FAULTA0 98 GPIOB7 134 PHASEB1
27 ISB2 63 MSCAN_TX 99 PWMA1 135 VSS
28 A10 64 FAULTA1 100 GPIOD0 136 PHASEA1
29 FAULTB0 65 MSCAN_RX 101 PWMA2 137 D3
30 A11 66 FAULTA2 102 GPIOD1 138 HOME1
56F805 Technical Data, Rev. 16
48 Freescale Semiconductor
31 FAULTB1 67 FAULTA3 103 PWMA3 139 D4
32 A12 68 VREF 104 GPIOD2 140 D5
33 A13 69 ANA0 105 PWMA4 141 D6
34 VDD 70 ANA1 106 PWMA5 142 D7
35 PS 71 ANA2 107 TXD0 143 D8
36 DS 72 ANA3 108 RXD0 144 D9
Table 4-1 56F805 Pin Identification by Pin Number (Continued)
Pin
No. Signal Name Pin
No. Signal Name Pin
No. Signal Name Pin
No. Signal Name
Package and Pin-Out Information 56F805
56F805 Technica l Data, Rev. 16
Freescale Semiconductor 49
Figure 4-2 144-pin LQFP Mechanical Information
Please see www.freescale.com for the most current case outline.
56F805 Technical Data, Rev. 16
50 Freescale Semiconductor
Part 5 Design Considerations
5.1 Thermal Design Considerations
An estimation of the chip junction temperature, TJ, in °C can be obtained from the equation:
Equation 1:
Where:
TA = ambient temperature °C
RθJA = package junction-to-ambient thermal resistance °C/W
PD = power dissipation in package
Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal res istance and
a case-to-ambient thermal resistance:
Equation 2:
Where:
RθJA = package junction-to-ambient thermal resistance °C/W
RθJC = package junction-to-case thermal resistance °C/W
RθCA = package case-to-ambient thermal resistance °C/W
RθJC is device-related and cannot be influenced by the user. The user controls the thermal environment to
change the case-to-ambient thermal resistance, RθCA. For example, the user can change the air flow around
the device, add a heat sink, change the mounting arrangement on the Printed Circuit Board (PCB), or
otherwise change the thermal dissipation capability of the area surrounding the device on the PCB. This
model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through
the case to the heat sink and out to the ambient environment . For ceramic packages, in situations where
the heat flow is split between a path to the case and an alternate path through the PCB, analysis of the
device thermal performance may need the additional modeling capability of a system level thermal
simulation tool.
The thermal performance of plastic packages is more dependent on the temperature of the PCB to which
the package is mounted. Again, if the estimations obtained from RθJA do not satisfactorily answer whether
the thermal performance is adequate, a system level model may be appropriate.
Definitions:
A complicating factor is the existence of three common definitions for determining the junction-to-case
thermal resistance in plastic packages:
• Measure the thermal resistance from the junction to the outside surface of the package (case) closest to the
chip mounting area when that surface has a proper heat sink. This is done to minimize temperature vari ation
across the surface.
• Measure the thermal resistance from the junction to where the leads are attached to the case. This definition
is approximately equal to a junction to board thermal resistance.
TJTAPDRθJA
×()+=
RθJA RθJC RθCA
+=
Electrical Design Considerations
56F805 Technica l Data, Rev. 16
Freescale Semiconductor 51
• Use the value obtained by the equation (TJ – TT)/PD where TT is the temperature of the package case
determined by a thermocouple.
The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T
thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so
that the thermocouple junction rests on the package. A small amount of epoxy is placed over the
thermocouple junction and over about 1mm of wire extending from the junction. The thermocouple wire
is placed flat against the package case to avoid measurement errors caused by cooling effects of the
thermocouple wire.
When heat sink is used, the junction temperature is determined from a thermocouple inserted at the
interface between the case of the package and the interface material. A clearance slot or hole is normally
required in the heat sink. Minimizing the size of the clearance is important to minimize the change in
thermal performance caused by removing part of the thermal interface to the heat sink. Because of the
experimental difficulties with this technique, many engineers measure the heat sink temperature and then
back-calculate the case temperature using a separate measurement of the thermal resistance of the
interface. From this case temperature, the junction temperature is determined from the junction-to-case
thermal resistance.
5.2 Electrical Design Considerations
Use the following list of considerations to assure correct operation:
• Provide a low-impedance path from the board power supply to each VDD pin on the controller , and from the
board ground to each VSS pin.
• The minimum bypass requirement is to place 0.1μF capacitors positioned as close as possible to the package
supply pins. The recommended bypass configuration is to place one bypass capacitor on each of the
VDD/VSS pairs, including VDDA/VSSA. Ceramic and tantalum capacitors tend to provide better performance
tolerances.
• Ensure that capacitor leads and associated printed circuit traces that connect to the chip VDD and VSS pins
are less than 0.5 inch per capacitor lead.
• Bypass the VDD and VSS layers of the PCB with approximately 100μF, preferably with a high-grade
capacitor such as a tantalum ca pacitor.
CAUTION
This device contains protective c ircuitry to guard against
damage due to high static voltage or electrical fields.
However, normal precautions are advised to avoid
application of any voltages higher than maximum rated
voltages to this high-impedance circuit. Reliability of
operation is enhanced if unused inputs are tied to an
appropriate voltage level.
56F805 Technical Data, Rev. 16
52 Freescale Semiconductor
• Because the processor’s output signals have fast rise and fall times, PCB trace lengths should be minimal.
• Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance.
This is especially critical in systems with higher capacitive loads that could create higher transient currents
in the VDD and VSS circuits.
• Take special care to minimize noise levels on the VREF, VDDA and VSSA pins.
• Designs that utilize the TRST pin for JTAG port or OnCE module functionality (such as development or
debugging systems) should allow a means to assert TRST whenever RESET is asserted, as well as a means
to assert TRST independently of RESET. TRST must be asserted at power up for proper operation. Designs
that do not require debugging functionality, such as consumer products, TRST should be tied low.
• TRST must be externally asserted even when the user relies on the internal power on reset for functional
test purposes.
• Because the Flash memory is programmed through the JTAG/OnCE port, designers should provide an
interface to this port to allow in-circuit Flash programming.
Electrical Design Considerations
56F805 Technica l Data, Rev. 16
Freescale Semiconductor 53
Part 6 Ordering Information
Table 6-1 lists the pertinent information needed to place an order. Consult a Freescale Semiconductor
sales office or authorized distributor to determine availability and to order parts.
*This package is RoHS compliant.
Table 6-1 56F805 Ordering Information
Part Supply
Voltage Package Type Pin
Count
Ambient
Frequency
(MHz) Order Number
56F805 3.0–3.6 V Low Profile Plastic Quad Flat Pack (LQFP) 144 80 DSP56F805FV80
56F805 3.0–3.6 V Low Profile Plastic Quad Flat Pack (LQFP) 144 80 DSP56F805FV80E*
56F805 Technical Data, Rev. 16
54 Freescale Semiconductor
Electrical Design Considerations
56F805 Technica l Data, Rev. 16
Freescale Semiconductor 55
How to Reach Us:
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Inc. All oth er produ ct or se rvice nam es are t he proper ty of th eir respe ctive ow ners.
This product incorporates Supe rFlash® technology licensed from SST.
© Freescale Semiconductor, Inc. 2005. All rights reserved.
DSP56F805
Rev. 16
09/2007
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