February 1984
Revised February 1999
MM74HCT138 3-to-8 Line Decoder
© 1999 Fairchild Semicond uctor Corpor ation DS005362.prf www.fairchildsemi.com
MM74HCT138
3-to-8 Line Decoder
General Descript ion
The MM74HCT138 decoder utilizes advanced silicon-gate
CMOS techno logy, and are well suited to me mor y address
decodin g or data rou ting app lications. Both c ircuits feature
high noise immunity and low power consumption usually
associated with CMOS circuitry, yet have speeds co mpara-
ble to low power Schottky TTL logic.
The MM74 HCT138 have 3 binar y select inputs (A, B, and
C). If the device is enabled these inputs determine which
one of the eight normally HIGH outputs will go LOW. Two
active LOW and one active HIGH enables (G1, G2A and
G2B) are provided to ease the cascading decoders.
The decoders’ output can drive 10 low power Schottky TTL
equivalent l oads and are functi onally a nd pin equ ivalent to
the 74L S138 . All inputs a re p rotecte d from dam age d ue to
static discharge by diodes to VCC and ground.
MM74HC T device s are intended to interface between TTL
and NMOS components and standard CMOS devices.
These parts are also plug-in replacements for LS-TTL
devices and can be u sed to reduce p ower consumption in
existing designs.
Features
■TTL input compatible
■Typical propagation delay: 20 ns
■Low quiescent current: 80 µA maximum (74HCT Series)
■Low input current: 1 µA maximum
■Fanout of 10 LS-TTL loads
Ordering Code:
Devices also available in Tape and Reel. Specify by appen ding the suffix lett er “X” to the orde ring code.
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and T SSOP
Order Number Package Number Package Description
MM74HCT138M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
MM74HCT138SJ M16D 16-Lead Small Outline Packa ge (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HCT138M T C MTC16 16-Lead Thin Shrink Small Outline P ackage (TSSOP), JEDEC MO -153, 4.4mm Wide
MM74HCT138N N16E 16-Lead Plastic Dual- In-Line Pac kage (PDIP), JEDEC MS-001, 0.300” Wide
www.fairchildsemi.com 2
MM74HCT138
Truth Table
H = HIGH Level
L = LO W Level
X = Don’t Care
Note 1: G2 = G2A + G2B
Logic Diagra m
Inputs Outputs
Enable Select
G1 G2
(Note 1) C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
X H XXXHHHHHHHH
L X XXXHHHHHHHH
H L LLLLHHHHHHH
H L LLHHLHHHHHH
H L LHLHHLHHHHH
H L LHHHHHLHHHH
H L HLLHHHHLHHH
H L HLHHHHHHLHH
H L HHLHHHHHHLH
H L HHHHHHHHHHL
3 www.fairchildsemi.com
MM74HCT138
Absolute Maximum Ratings(Note 2)
(Note 3) Recommended Operating
Conditions
Note 2: A bsolute Maximum R atings are those va lues beyond which dam -
age to the device may occur.
Note 3: Unless ot herwise specif ied all voltages are reference d t o ground.
Note 4: Power Dis sipation t emperature derating — plastic “ N” package: −
12 mW/°C from 65°C to 85°C.
DC Electrical Characteristics
VCC = 5V ±10% (unless otherwise specified)
Note 5: Th is is m eas ured per inp ut pin. All other input s are held at VCC or ground.
Supply Vol ta ge (VCC)−0.5 to +7.0V
DC Input Voltage (VIN)−1.5 to VCC +1.5V
DC Output Voltage (VOUT)−0.5 to VCC +0.5V
Clamp Diode Current (IIK, IOK)±20 mA
DC Output Current, per pin (IOUT)±25 mA
DC VCC or GND Current, per pin (ICC)±50 mA
Storage Temperature Range (TSTG)−65°C to +150°C
Power Dissipation (PD)
(Note 4) 600 mW
S.O. Package only 500 mW
Lead Temperature (TL)
(Soldering 10 seconds ) 260 °C
Min Max Units
Supply Voltage (VCC)4.55.5V
DC Input or Output Vol ta ge
(VIN, VOUT)0V
CC V
Operating Temperatur e Range (TA)−40 +85 °C
Input Rise or Fall Times
(tr, tf) 500 ns
Symbol Parameter Conditions TA = 25°CT
A = −40 to 85°CT
A = −55 to 125°CUnits
Typ Guaranteed Limits
VIH Minimum HIGH Level 2.0 2.0 2.0 V
Input Voltage
VIL Maximum LOW Level 0.8 0.8 0.8 V
Input Voltage
VOH Minimum HIG H Level VIN = VIH or VIL
Output Voltage |IOUT| = 20 µAV
CC VCC− 0.1 VCC− 0.1 VCC− 0.1 V
|IOUT| = 4.0 mA, VCC = 4.5V 4.2 3.98 3.84 3.7 V
|IOUT| = 4.8 mA, VCC = 5.5V 5.2 4.98 4.84 4.7 V
VOL Maximum LOW Level VIN = VIH or VIL
Voltage |IOUT| = 20 µA 0 0.1 0.1 0.1 V
|IOUT| = 4.0 mA, VCC = 4.5V 0.2 0.26 0.33 0.4 V
|IOUT| = 4.8 mA, VCC = 5.5V 0.2 0.26 0.33 0.4 V
IIN Maximum Input VIN = VCC or GND, ±0.1 ±1.0 ±1.0 µA
Current VIH or VIL
ICC Maximum Quiescent VIN = VCC or GND 8.0 80 160 µA
Supply Current IOUT = 0 µA
VIN = 2.4V or 0.5V (Note 5) 0.3 0.4 0.5 mA
www.fairchildsemi.com 4
MM74HCT138
AC El ectrical Charac terist ics
TA = 25°C, VCC = 5.0V, tr = tf = 6 ns, CL = 15 pF (unless otherwise specified)
AC El ectrical Charac terist ics
VCC = 5V ± 10%, CL = 50 pF, tr = tf = 6 ns (unless otherwise specified)
Note 6: CPD determ ines the no load dy namic power cons um ption, PD = CPD VCC2f + ICC VCC, and the no loa d dynamic cu rrent consumpt ion,
IS = CPD VCC f + ICC.
Symbol Parameter Conditions Typ Guaranteed Units
Limit
tPHL Maximum Propagation Delay, A, B, or C to Output 20 35 ns
tPLH Maximum Propagation Delay, A, B, or C to Output 13 25 ns
tPHL Maximum Propagation Delay, G1 to Y Output 14 25 ns
tPLH Maximum Propagation Delay, G1 to Y Output 13 25 ns
tPHL Maximum Propagation Delay, G2A or G2B to Y Output 17 30 ns
tPLH Maximum Propagation Delay, G2A or G2B to Y Output 13 25 ns
Symbol Parameter Conditions TA = 25°CT
A = −40 to 85°CT
A = −55 to 125°CUnits
Typ Guaranteed Limits
tPHL Maximum Propagation Delay 24 40 50 6 0 ns
A, B, or C to Output
tPLH Maximum Propagation Delay 18 30 38 45 ns
A, B, or C to Output
tPHL Maximum Propagation Delay 17 30 38 4 5 ns
G1 to Y Output
tPLH Maximum Propagation Delay 20 30 38 45 ns
G1 to Y Output
tPHL Maximum Propagation Delay 23 35 43 5 2 ns
G2A or G2B to Y Output
tPLH Maximum Propagation Delay 18 30 38 45 ns
G2A or G2B to Y Output
tTHL, tTLH Maximum Output 15 19 22 ns
Rise and Fall Time
CIN Input Capacitance 5 10 10 pF
CPD Power Dissipation 55 pF
Capacitance (Note 6)
5 www.fairchildsemi.com
MM74HCT138
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circ uit (SOIC), JE DEC MS-012, 0.150” Narrow
Package Number M16A
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
www.fairchildsemi.com 6
MM74HCT138
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC16
F airchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and F airchild reserves the right at any tim e without notice to change said circuitry and specifications.
MM74HCT138 3-to-8 Line Decoder
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or system s a re devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain lif e, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A cr itical c ompon ent in any com ponent of a li fe support
device or system whose failure to perform can be rea-
sonably expected to cause th e failure of the li fe suppor t
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N16E
