FAST CMOS IDT54/74FCT841AT/BT/CT/DT dt BUS INTERFACE LATCHES htegrated Devine Technobgy, Re. FEATURES: + Common features: Low input and output leakage <1HA (max.)} Extended commercial range of -40C to +85C CMOS power levels True TTL input and output compatibility VOH = 3.3V (typ.) VOL = 0.3V (typ.) Meets or exceeds JEDEC standard 18 specifications Product available in Radiation Tolerant and Radiation Enhanced versions Military product compliant to MIL-STD-883, Class B and DESC listed (dual marked) Available in DIP, SOIC, SSOP, GSOP, CERPACK and LCC packages + Features for FCT841T: A,B,C and D speed grades High drive outputs (-15mA IOH, 48mA IOL) Power off disable outputs permit live insertion DESCRIPTION: The FCT8xxT series is built using an advanced dual metal CMOS technology. The FCT8xxT bus interface latches are designed to elimi- nate the extra packages required to buffer existing latches and provide extra data width for wider address/data paths or buses carrying parity. The FCT841T are buffered, 10-bit wide versions of the popular FCT373T function. They are ideal for use as an output port requiring high IOL/IOH. All of the FCT8xxT high-performance interface family can drive large capacitive loads, while providing low-capacitance bus loading at both inputs and outputs. All inputs have clamp diodes to ground and all outputs are designed for low-capaci- tance bus loading in high-impedance state. FUNCTIONAL BLOCK DIAGRAM Do Di De Ds Da Ds Ds Da ol ] Ol | ol | ol LE LE LE Ol ] = Mm oO | | ol ] LE - LE is] PY PY LY PY LY ry LY PY ane Yo 1 Y2 Y3 Ya 5 Ys 9 2571 dw 01 The IDT logo is a registered trademark of Integrated Device Technology, Inc. MILITARY AND INDUSTRIAL TEMPERATURE RANGES SEPTEMBER 1996 91997 Integrated Device Technology, Inc. 6.21 DSC-2571/7 For the latest information regarding this part, please contact IDTs web site at ttp:/waww.idt.com or fax-on-demand service at (US) 1-800-9-IDT-FAX / (International) 408-492-8391. 1IDT54/74FCT841 AT/BT/CT/DT FAST CMOS BUS INTERFACE LATCHES MILITARY AND INDUSTRIAL TEMPERATURE RANGES PIN CONFIGURATIONS OE Do bc De Ds q Ds (7 Ds De DFT De (I Dg 1 ~" 2417 Vec 2 23[5 Yo 3 2214 1 4 P24-1 9417 Ye 5 De4-1 OE 5 80242 oF y, 8024-7 igh y soe4-8 = 8 "2 17[F] Ye 8 Epg.1 'OY? 10 15|-] 8 11 14 Y9 12 13 LE GND DIP/SOIC/SSOP/QSOP/CERPACK INDEX NG TOP VIEW 2571 drwO? TOP VIEW 2571 drw 03 PIN DESCRIPTION FUNCTION TABLE") Name tO Description DI | The latch data inputs. In LE | The latch enable input. The latches are OE LE Function transparent when LE is HIGH. Input data H High Z is latched on the HIGH-to-LOW H High Z transition. Yl 0 The 3-state latch outputs. H Latched (High 2) OE | The output enable control. When OE is L Transparent LOW, the outputs are enabled. When OE L Transparent is HIGH, the outputs V| are in high- L Latched impedance (off) state. NOTE: 9671 tbl OP 2o71blo1 = 1. H= HIGH, L= LOW, X=Dont Care, NC = No Change, Z = High Impedance ABSOLUTE MAXIMUM RATINGS") CAPACITANCE (Ta = +25C, f = 1.0MHz) Symbol Description Max. Unit Symbol Parameter(1) Conditions | Typ. | Max. | Unit VTERM(2)| Terminal Voltage with Respect to] -0.5to+7.0 ] V CIN Input VIN =OV 6 10 | pF GND Capacitance VTERM(3)] Terminal Voltage with Respect to -0.5 to V CouT Output VOUT = OV 8 12 pF GND Vcc +0.5 Capacitance Tsta | Storage Temperature -65to +150 | c | NOTE: 2971 Ink 04 1. This parameter is measured at characterization but not tested. IOUT DG Output Current 60to +120 | mA NOTES: 2571 Ink 03 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT- INGS may cause permanent damage to the device. Thisis astress rating only and functional operation ofthe device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed Vcc by +0.5V unless otherwise noted. 2. Input and Vcc terminals only. 3. Outputs and I/O terminals only. 6.21IDT54/74FCT841AT/BT/CT/DT FAST CMOS BUS INTERFACE LATCHES MILITARY AND INDUSTRIAL TEMPERATURE RANGES DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Commercial: TA = 40C to +85C, Vcc = 5.0V + 5%; Military: TA = 55C to +125C, Voc = 5.0V + 10% Symbol Parameter Test Conditions Min. | Typ] Max. | Unit VIH Input HIGH Level Guaranteed Logic HIGH Level 2.0 Vv VIL Input LOW Level Guaranteed Logic LOW Level _ _ 0.8 V HH Input HIGH Current!*) Vcc = Max. Vi=2.7V _ = H yA HL Input LOW Current!) Vi =0.5V = +H IOZH High Impedance Output Current Vcc = Max. Vo=2.7V _ _ +1 LA lozL (3-State Output pins) (4) Vo=0.5V = = H lI Input HIGH Current!*) Vcc = Max., Vi= Vcc (Max.) _ = +H yA VIK Clamp Diode Voltage Vcc = Min., lin =18mA 0.7 | -1.2 V VH Input Hysteresis _ _ 200 _ mv lec Quiescent Power Supply Current | Vcc = Max., VIN = GND or Vcc _ 0.04 1 mA 2571 Ink OS OUTPUT DRIVE CHARACTERISTICS FOR FCT841T Symbol Parameter Test Conditions) Min. | Typ.2)| Max. | Unit VOH Output HIGH Voltage Voc = Min. IOH=6MA MIL. 2.4 3.3 _ Vv VIN = VIH or VIL IOH = -8mA COMLL. JOH=-12mA MIL. 2.0 3.0 _ Vv 1OH=15mA COM. VoL Qutput LOW Voltage Vcc = Min. lOL= 32mA MIL. _ 0.3 0.5 Vv VIN = ViH or VIL loL=48mA COML. los Short Circuit Current Vcc = Max., Vo = GND&) -60 | -120] -225] mA lOFF Input/Output Power Off Leakage'5)! Vcc = OV, VIN or Vo < 4.5V = _ +H LA NOTES: 2571 Ink 06 aoRwN Fer conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. Typical values are at Vcc = 5.0V, +25C ambient. Not mere than one output should be shorted at one time. Duration of the short circuit test should not exceed one second. The test limit for this parameter is t5yA at TA = -55C. This parameter is guaranteed but not tested. 6.21IDT54/74FCT841 AT/BT/CT/DT FAST CMOS BUS INTERFACE LATCHES MILITARY AND INDUSTRIAL TEMPERATURE RANGES POWER SUPPLY CHARACTERISTICS Symbol Parameter Test Conditions) Min. _|Typ.2)| Max. | Unit Alcc Quiescent Power Supply Current | Voc = Max. _ 0.5 2.0 mA TTL Inputs HIGH VIN= 3.443) lccp Dynamic Power Supply Current!#)] Voc = Max. VIN = Vee | 015 | 0.25 | mA Outputs Open VIN = GND MHz OE = GND LE = Vcc One Input Toggling 50% Duty Cycle Ic Total Power Supply Current() Vcc = Max. VIN = Vcc 1.5 3.5 mA Outputs Open VIN = GND fi = 10MHz 50% Duty Cycle VIN =3.4 1.8 45 OE =GND VIN = GND LE = Vcc One Bit Togaling Veco = Max. VIN = Vec _ 3.0 | 6.08) Outputs Open VIN = GND fi = 2.5MHz 50% Duty Cycle VIN = 3.4 5.0 | 14.0%) OE =GND VIN = GND LE = Vcc Eight Bits Teggling NOTES: 2571 tbl OF 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 5.0V, +25C ambient. 3. Per TTL driven input (VIN= 3.4V). All other inputs at Vcc or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested. 6. Ic = lQUIESCENT + IINPUTS + IDYNAMIC Ic = lec + Alcc DHNT + Iccp (fcP/2 + fiNi) Icc = Quiescent Current Alcc = Power Supply Current for a TTL High Input (VIN = 3.4) DH = Duty Cycle for TTL Inputs High Nt = Number of TTL Inputs at DH Iccp = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices) fi = Input Frequency Ni = Number of Inputs at fi All currents are in milliamps and all frequencies are in megahertz. 6.21 4IDT54/74FCT841AT/BT/CT/DT FAST CMOS BUS INTERFACE LATCHES MILITARY AND INDUSTRIAL TEMPERATURE RANGES SWITCHING CHARACTERISTICS OVER OPERATING RANGE FCT841AT FCT841BT Com'l. Mil. Com'l. Mil. Symbol Parameter Conditions(} | Min.@)| Max. |Min.@)] Max. | Min.) Max. | Min.{2)] Max. | Unit tPLH Propagation Delay CL = 50pF 1.5 93.0 1.5 10.0 1.5 6.5 1.5 7.5 ns tPHL DI to YI (LE = HIGH) RL = 5002 CL = 300pF4) 15 | 130] 15 | 150] 15 | 130] 1.5 | 15.0 RL = 5002 tPLH Propagation Delay CL = 50pF 1.5 12.0 1.5 13.0 1.5 8.0 1.5 10.5 | ns tPHL LE to YI AL = 5002 CL = 300pF4) 15 | 160] 15 | 200] 15 | 155] 15 | 180 RL = 5002 tPZH Output Enable Time OE to YI CL = 50pF 1.5 11.5 1.5 13.0 1.5 8.0 1.5 8.5 ns tPZL RL = 5002 CL = 300pF(4) 15 | 20] 15 | 2.0] 15 | 140] 15 | 150 RAL = 5002 tPHZ Output Disable Time OE to | CL = 5pF4) 1.5 7.0 1.5 9.0 1.5 6.0 1.5 6.5 | ns tPLZ RL = 5002 CL = 50pF 1.5 8.0 1.5 10.0 1.5 7.0 1.5 7.5 RL = 5002 tsu Data to LE Set-up Time CL = 50pF 2.5 _ 2.5 _ 2.5 _ 2.5 _ ns tH Data to LE Hold Time RL = 5002 2.5 _ 3.0 _ 2.5 _ 2.5 _ ns tw LE Pulse Width HIGH(S) 4.0 5.0 _ 4.0 _ 4.0 | ns NOTES: 2571 tbl 08 1. See test circuit and waveforms. 3. These parameters are guaranteed but not tested. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 4. These conditions are guaranteed but not tested. SWITCHING CHARACTERISTICS OVER OPERATING RANGE FCT841CT FCT841DT Com'l. Mil. Com'l. Mil. Symbol Parameter Conditions) Min.) Max. | Min] Max. | Min.@)) Max. | Min.@)] Max. | Unit tPLH Propagation Delay CL = 50pF 1.5 5.5 1.5 6.3 1.5 42 _ _ ns tPHL DI to YI (LE = HIGH) RL = 5000 CL = 300pR4) 15 | 130] 15 15.0] 15 8.0 _ _ RL = 5000 tPLH Propagation Delay CL = 50pF 1.5 6.4 1.5 6.8 1.5 4.0 _ _ ns {PHL LE to YI RL = 5000 CL = 300pR4) 15 | 150] 15 16.0 ] 15 8.0 _ _ RL = 5002 {PZH Output Enable Time OE to YI CL = 50pF 1.5 6.5 1.5 7.3 1.5 48 _ _ ns tPZL RL = 5000 CL = 300pF\4) 15 | 120 | 15 | 130] 15 3.0 RL = 5000 tPHZ Output Disable Time OE to | CL = 5pFl4) 1.5 57 15 6.0 1.5 4.0 _ | ns tPLZ RL = 5000 CL = 50pF 1.5 6.0 1.5 6.3 1.5 4.0 _ _ RL = 5000 {su Data to LE Set-up Time CL = 50pF 2.5 _ 2.5 _ 1.5 _ _ _ ns tH Data to LE Hold Time RL = 5009 25 _ 25 _ 1.0 _ _ _ ns tw LE Pulse Width HIGH!) 4.0 4.0 3.0 | ns NOTES: 25711 tbl 09 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. These parameters are guaranteed but not tested. 4. These conditions are guaranteed but not tested. 6.21IDT54/74FCT841 AT/BT/CT/DT FAST CMOS BUS INTERFACE LATCHES TEST CIRCUITS AND WAVEFORMS TEST CIRCUITS FOR ALL OUTPUTS MILITARY AND INDUSTRIAL TEMPERATURE RANGES SWITCH POSITION Voc me 70 Test Switch | | Open Drain . 5000 Disable Low Closed , Enable Low Pulse All Other Tests Open Generator DEFINITIONS: 2571 Ink 11 Ct= Load capacitance: includes jig and probe capacitance. SET-UP, HOLD AND RELEASE TIMES DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET GLEAR CLOCK ENABLE ETC. PROPAGATION DELAY SAME PHASE ___ INPUT TRANSITION tPLH tPHL OUTPUT / a {PLH {PHL OPPOSITE PHASE INPUT TRANSITION RT= Termination resistance: should be equal to Zour of the Pulse Generator. 2571 drw 04 PULSE WIDTH 3V 1.5V OV LOW-HIGH-LOW BV PULSE 1.5V 1.5V ov tw 3V 1.5V HIGH-LOW-HIGH 1.5V ov PULSE 3V 1 5YV P57 1 drew 06 ov 2571 drw 05 ENABLE AND DISABLE TIMES ENABLE DISABLE 3V 3V 1.5V CONTROL fi 1.5V ov INPUT 1 / ov VOH sel {PLZ lege 1.5V OUTPUT 3.5V VoL NORMALLY KK Y Low : 0.3V VoL 3V " +PHz feae] fi vad OUTPUT oy Vou ov NORMALLY SWECH I 2571 dw OF HIGH Poy NS ov 2571 drw 08 NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable- HIGH 2. Pulse Generator for All Pulses: Rate < 1.0MHz; tf < 2.5ns; iR < 2.5ns 6.21 6IDT54/74FCT841AT/BT/CT/DT FAST CMOS BUS INTERFACE LATCHES MILITARY AND INDUSTRIAL TEMPERATURE RANGES ORDERING INFORMATION IDT XX FCT XXXX X X Temp. Range Device Type Package Process [| Blank ~rmovu w $0 841AT 841BT 841CT 841DT 54 74 Commercial MIL-STD-883, Class B Plastic DIP CERDIP CERPACK Leadless Chip Carrier Small Outline IC Shrink Small Outline Package Quarter-size Small Outline Package 10-Bit Non-Inverting Latch 55C to +125C 40C to +85C 2571 drw 09 6.21