DG401
NC GND
NC VL
NC V+
NC IN2
D2S2
D1S1
NC
Dual-In-Line and SOIC
IN1
NC V–
NC
V–
NC
GND
NC
NC
NC
VL
NC
V+
DG401
DG401/403/405
Siliconix
S-53748—Rev. E, 05-Jun-97 1
Low-Power, High-Speed CMOS Analog Switches
Features Benefits Applications
44-V Supply Max Rating
15-V Analog Signal Range
On-Resistance—rDS(on): 20
Low Leakage—ID(on): 40 pA
Fast Switching—tON: 100 ns
Ultra Low Power
Requirements—PD: 0.35 W
TTL, CMOS Compatible
Single Supply Capability
Wide Dynamic Range
Low Signal Errors and Distortion
Break-Before-Make Switching Action
Simple Interfacing
Audio and Video Switching
Sample-and-Hold Circuits
Battery Operation
Test Equipment
Hi-Rel Systems
PBX, PABX
Description
The DG401/403/405 monolithic analog switches were
designed to provide precision, high performance switching of
analog signals. Combining low power (0.35 W, typ) with
high speed (tON: 100 ns, typ), the DG401 series is ideally
suited for portable and battery powered industrial and military
applications.
Built on the Siliconix proprietary high-voltage silicon-gate
process to achieve high voltage rating and superior
switch on/off performance, break-before-make is guaranteed
for the SPDT configurations. An epitaxial layer prevents
latchup.
Each switch conducts equally well in both directions when on,
and blocks up to 30 V peak-to-peak when off. On-resistance
is very flat over the full 15-V analog range, rivaling JFET
performance without the inherent dynamic range limitations.
The three devices in this series are differentiated by the type
of switch action as shown in the functional block diagrams.
Functional Block Diagrams and Pin Configurations
Two SPST Switches per Package
Truth Table
Logic Switch
0 OFF
1 ON
Logic “0” 0.8 V
Logic
“
1
”
24V
Logic “1” 2.4 V
Updates to this data sheet may be obtained via facsimile by calling Siliconix FaxBack, 1-408-970-5600. Please request FaxBack document #70049.
DG403
D1S1
NC
Dual-In-Line and SOIC
IN1
D3V–
S3GND
S4VL
D4V+
NC IN2
D2S2
D3
V–
S3
GND
NC
NC
S4
VL
D4
V+
DG403
DG405
D1S1
NC
Dual-In-Line and SOIC
IN1
D3V–
S3GND
S4VL
D4V+
NC IN2
D2S2
D3
V–
S3
GND
NC
NC
S4
VL
D4
V+
DG405
DG401/403/405
2 Siliconix
S-53748—Rev. E, 05-Jun-97
Functional Block Diagrams and Pin Configurations (Cont’d)
Two SPDT Switches per Package
Truth Table
Logic SW1, SW2SW3, SW4
0 OFF ON
1 ON OFF
Logic “0” 0.8 V
Lo
g
ic “1” 2.4 V
Logic
1
2
.
4
V
Two DPST Switches per Package
Truth Table
Logic Switch
0 OFF
1 ON
Logic “0” 0.8 V
Lo
g
ic “1” 2.4 V
Logic
1
2
.
4
V
DG401/403/405
Siliconix
S-53748—Rev. E, 05-Jun-97 3
Ordering Information
Temp Range Package Part Number
DG401
–40 to 85_C16-Pin Plastic DIP DG401DJ
16
-
Pin CerDIP
DG401AK
–55 to 125_C
16
-
Pi
n
C
er
DIP
DG401AK/883
LCC-20 DG401AZ/883
DG403
–
40 to 85
_
C
16-Pin Plastic DIP DG403DJ
–
40
t
o
85_C
16-Pin Narrow SOIC DG403DY
16
-
Pin CerDIP
DG403AK
–55 to 125_C
16
-
Pi
n
C
er
DIP
DG403AK/883
LCC-20 5962-8976301M2A
DG405
–
40 to 85
_
C
16-Pin Plastic DIP DG405DJ
–
40
t
o
85_C
16-Pin Narrow SOIC DG405DY
–
55 to 125
_
C
16-Pin CerDIP DG405AK/883
–
55
t
o
125_C
LCC-20 5962-89961012A
Absolute Maximum Ratings
V+ to V– 44 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GND to V– 25 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VL (GND – 0.3 V) to (V+) +0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital Inputsa VS, VD(V–) –2 V to (V+ plus 2 V). . . . . . . . . . . . . . . . .
or 30 mA, whichever occurs first
Current (Any Terminal) Continuous 30 mA. . . . . . . . . . . . . . . . . . . . . .
Current, S or D (Pulsed 1 ms 10% duty) 100 mA. . . . . . . . . . . . . . . . . .
Storage Temperature (AK, AZ Suffix) –65 to 150_C. . . . . . . . . .
(DJ, DY Suffix) –65 to 125_C. . . . . . . . . . .
Power Dissipation (Package)b
16-Pin Plastic DIPc450 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16-Pin CerDIPd900 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16-Pin SOICe600 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LCC-20f900 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Notes:
a. Signals on SX, DX, or INX exceeding V+ or V– will be clamped by
internal diodes. Limit forward diode current to maximum current
ratings.
b. All leads welded or soldered to PC Board.
c. Derate 6 mW/_C above 75_C
d. Derate 12 mW/_C above 75_C
e. Derate 7.6 mW/_C above 75_C
f. Derate 13 mW/_C above 75_C
DG401/403/405
4 Siliconix
S-53748—Rev. E, 05-Jun-97
Specificationsa
Test Conditions
Unless Specified A Suffix
–55 to 125_CD Suffix
–40 to 85_C
Parameter Symbol V+ = 15 V, V– = –15 V
VL = 5 V, VIN = 2.4 V, 0.8 VfTempbTypcMindMaxdMindMaxdUnit
Analog Switch
Analog Signal RangeeVANALOG Full –15 15 –15 15 V
Drain-Source
On-Resistance rDS(on) IS = –10 mA, VD = 10 V
V+ = 13.5 V, V– = –13.5 V Room
Full 20 35
45 45
55
W
D Drain-Source
On-Resistance DrDS(on) IS = –10 mA, VD = 5 V, 0 V
V+ = 16.5 V, V– = –16.5 V Room
Full 3 3
53
5
W
Switch Off
Lk C
IS(off) V+ = 16.5, V– = –16.5 V
V155VV155V
Room
Hot –0.01 –0.25
–20 0.25
20 –0.5
–5 0.5
5
Leakage Current ID(off)
,
VD = 15.5 V, VS = 15.5 V Room
Hot –0.01 –0.25
–20 0.25
20 –0.5
–5 0.5
5nA
Channel On
Leakage Current ID(on) V+ = 16.5 V, V– = –16.5 V
VS = VD = 15.5 V Room
Hot –0.04 –0.4
–40 0.4
40 –1
–10 1
10
Digital Control
Input Current VIN Low IIL VIN under test = 0.8 V
All Other = 2.4 V Full 0.005 –1 1 –1 1
mA
Input Current VIN High IIH VIN under test = 2.4 V
All Other = 0.8 V Full 0.005 –1 1 –1 1
m
A
Dynamic Characteristics
Turn-On Time tON RL = 300 W, CL = 35 pF
SFi 2
Room 100 150 150
Turn-Off Time tOFF
L,Lp
See Figure 2 Room 60 100 100 ns
Break-Before-Make
Time Delay (DG403) tDRL = 300 W, CL = 35 pF Room 12 5 5
ns
Charge Injection Q CL = 10,000 pF
Vgen = 0 V, Rgen = 0 WRoom 60 pC
Off Isolation Reject Ratio OIRR
RL= 100 WCL=5pF
Room 72
Channel-to-Channel Cross-
talk XTALK
R
L =
100
W
,
C
L =
5
p
F
f = 1 MHz Room 90 dB
Source Off Capacitance CS(off) Room 12
Drain Off Capacitance CD(off) f = 1 MHz, VS = 0 V Room 12 pF
Channel On Capacitance CD, CS(on) Room 39
Power Supplies
Positive Supply Current I+ Room
Full 0.01 1
51
5
Negative Supply Current I– V+ = 16.5 V, V– = –16.5 V
V05V
Room
Full –0.01 –1
–5 –1
–5
mA
Logic Supply Current IL
,
VIN = 0 or 5 V Room
Full 0.01 1
51
5
m
A
Ground Current IGND Room
Full –0.01 –1
–5 –1
–5
Notes:
a. Refer to PROCESS OPTION FLOWCHART.
b. Room = 25_C, Full = as determined by the operating temperature suffix.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
e. Guaranteed by design, not subject to production test.
f. VIN = input voltage to perform proper function.
DG401/403/405
Siliconix
S-53748—Rev. E, 05-Jun-97 5
Typical Characteristics
V+ = 15 V, V– = –15 V
VL = 5 V
CL = 10 k pF
1 k pF
100 pF
Input Switching Threshold vs. Supply VoltagesInput Switching Threshold vs. Logic Supply Voltage
(V)
T
V
10
8
00 2 4 6 8 10 12 14 16 18 20
6
4
2
V+ = 15 V
V– = –15 V
TA = 25_C
DG403
SW3, 4
3.5
3.0
2.5
0510 40
2.0
1.5
1.0
0.5
15 20 25 30 35(V+) –5 –10 0–15 –10 –5 0 0(V–)
VL = 5 V
VL = 7 V
(V)
IN
V
VL – Logic Supply (V)
VD – Drain Voltage (V)
rDS(on) vs. VD and Temperature
Charge Injection vs. Analog Voltage
Q (pC)
rDS(on) vs. VD and Power Supply Voltage
rDS(on) vs. VD and Power Supply Voltage
(V– = 0 V)
–15 –10 15–5 0 5 10 –25 –15 26–5 5 15
70
60
10
025
50
40
30
20
2015105
200
180
140
40
0–15 –10 –5 0 5 10 15
160
120
20
60
100
80
VS – Source Voltage (V)
VD – Drain Voltage (V)
VD – Drain Voltage (V)
10
30
20
35 40 TA = 25_C
TA = 25_C
25_C
85_C
0_C
–40_C
–55_C
10
30
25
20
15
125_C
V+ = 15 V, V– = –15 V
VL = 5 V 6 V
10 V
12 V
15 V
20 V
22 V
7.5 V
10 V
12 V
15 V 20 V
22 V
rDS(on) – Drain-Source On-Resistance (
rDS(on) – Drain-Source On-Resistance (
rDS(on) – Drain-Source On-Resistance (
DG401/403/405
6 Siliconix
S-53748—Rev. E, 05-Jun-97
Typical Characteristics (Cont’d)
Leakage Current vs. Analog VoltageLeakage Current vs. Temperature
(pA)I , I
SD
Temperature (_C)
ID(off)
100 pA
–55 –35 –15 5 25 45 65 85 105 125
0.1 pA
1 pA
10 pA
1 nA
10 nA
100 nA V+ = 15 V
V– = –15 V
VL = 5 V
VD = 14 V
ID(on)
ID(off)
90
60
–150 –15 –10 –5 0 5 10 15
30
0
–30
–60
–90
–120
V+ = 15 V, V– = –15 V
VL = 5 V, TA = 25_C
For ID(off), VS = 0 V
For IS(off), VD = 0 V
ID(on)
ID(off), IS(off)
VD or VS – Drain or Source Voltage (V)
V+, V– Positive and Negative Supplies (V)
Switching Time vs. Temperature*Supply Current vs. Temperature
Switching Time vs. Positive Supply Voltage*Switching Time vs. Power Supply Voltage*
I+, I–, I L(A)
–55 –35 –15 5 25 45 65 85 105 125
1 p
100 p
10.0 p
1 n
10 n
100 n
IL
I–
I+
IL
I–
tON (ns), tOFF
tON (ns), tOFF
tON (ns), tOFF
240
180
120
60
0–55 –35 –15 5 25 45 65 85 105 125
V+ = 15 V, V– = –15 V, VL = 5 V
tON tOFF
VS = –10 V
VS = 10 V
210
150
90
30
*Refer to Figure 2 for test conditions.
VS = 10 V
VS = –10 V
200
180
140
40
0
160
120
20
60
100
80
tON tOFF
VL = 5 V
VS = 5 V
VS = –5 V
VS = 5 V
VS = –5 V
0 ”5 ”10 ”20 ”25”15
300
270
210
60
0025
240
180
30
90
150
120
2015105
tON tOFF
V+ = 15 V, V– = –15 V
VL = 5 V
VS = 5 V
0 V
0 V
0 V
–15 V
–15 V
–5 V
–5 V
TA – Temperature (_C)
V+ – Positive Supply (V)
TA – Temperature (_C)
–15 V
DG401/403/405
Siliconix
S-53748—Rev. E, 05-Jun-97 7
Schematic Diagram (Typical Channel)
Figure 1.
Level
Shift/
Drive
VIN
VL
S
V+
GND
V–
D
V–
V+
Test Circuits
Figure 2. Switching Time
Figure 3. Break-Before-Make
0 V
Logic
Input
Switch
Input*
Switch
Output
3 V
0 V
Switch
Input*
VO is the steady state output with the switch on. Feedthrough via switch capacitance may result in spikes at the leading and trailing edge of
the output waveform.
VS
tr <20 ns
tf <20 ns
90%
–VS
tOFF
tON
VO90%
VO
*VS = 10 V for tON, VS = –10 V for tOFF
Note: Logic input waveform is inverted for switches that
have the opposite logic sense control
0 V
Logic
Input
Switch
Switch
Output
3 V
50%
0 V
Output
0 V
90%
VO2
VO1
90%
VS1
VS2
tDtD
CL (includes fixture and stray capacitance)
V+
IN
RL
RL + rDS(on)
VO = VS
S D
–15 V
VO
GND
10 V
VL
CL
35 pF
V–
RL
1 k
+15 V+5 V
VO2
CL (includes fixture and stray capacitance)
V+
RL1
S2
CL1
V–
S1
VL
VS2
IN
D2
VS1
RL2
D1VO1
CL2
–15 V
GND
+5 V +15 V
50%
DG401/403/405
8 Siliconix
S-53748—Rev. E, 05-Jun-97
Test Circuits (Cont’d)
RL
100 W
Figure 4. Charge Injection
Figure 5. Off Isolation Figure 6. Insertion Loss
Figure 7. Crosstalk
RL
100 W
D
0V, 2.4 V
V+
Rg = 50 W
–15 V
GND V– C
VS
Off Isolation = 20 log VS
VO
IN
VL
VO
+5 V
C
+15 V
S
C
S
VSVO
0V, 2.4 V IN
VLD
Rg = 50 W
+5 V
–15 V
GND V– C
C+15 V
V+
C
Rg = 50 W
IN
0.8 V
VLV+
V–
XTALK Isolation = 20 log VS
VO
GND
S2
VS
VO
S1
RL
D
C = RF bypass
50 W
+15 V
–15 V
C
C+5 V C
D
f = 1 MHz
IN
S
VLV+
–15 V
GND V– C
0 V, 2.4 V
Meter
HP4192A
Impedance
Analyzer
or Equivalent
+5 V
C
+15 V
C
C = RF bypass
C = RF bypass
Off OnOn
IN
DVO
VO
Q = DVO x CL
CL
10 nF
D
RgVO
V+
S
V–
3 V IN
VL
Vg
–15 V
GND
+15 V+5 V
Figure 8. Capacitances
DG401/403/405
Siliconix
S-53748—Rev. E, 05-Jun-97 9
Applications
DG403
Right
Right
Left
Left
Channel
Select
Source 1
Source 2
TTL
Left
Right
–15 V
+15 V+5 V
GND V–
V+
S1
IN2
S3
S2
S4
D1
D3
D2
D4
VL
IN1
DG403
Integrate/
Reset
Slope
Select
TTL
+
–
–15 V
+15 V+5 V
GND V–
V+
S1
IN2
S3
S2
S4
D1
D3
D2
D4
VL
IN1C1
C2
eout
ein
Figure 9. Stereo Source Selector Figure 10. Dual Slope Integrator
Stereo Source Selector:
A single logic signal controls the status of all four switches of
the device, simplifying stereo source switching.
The low on-resistance (<35 ) minimizes total harmonic
distortion.
Dual Slope Integrators:
The DG403 is well suited to configure a selectable slope
integrator. One control signal selects the timing capacitor
C1 or C2. Another one selects ein or discharges the capacitor
in preparation for the next integration cycle.
Band-Pass Switched Capacitor Filter:
Single-pole double-throw switches are a common element
for switched capacitor networks and filters. The fast
switching times and low leakage of the DG403 allow for
higher clock rates and consequently higher filter operating
frequencies.
–15 V
+15 V+5 V
GND V–
V+
Clock
+
–
VL
eout
ein
DG403
S1
IN2
S3
S2
S4
D1
D3
D2
D4
IN1
Figure 11. Band-Pass Switched Capacitor Filter
DG401/403/405
10 Siliconix
S-53748—Rev. E, 05-Jun-97
Applications (Cont’d)
Peak Detector:
A3 acting as a comparator provides the logic drive for
operating SW1. The output of A2 is fed back to A3 and
compared to the analog input ein. If ein > eout the output of
A3 is high keeping SW1 closed. This allows C1 to charge
up to the analog input voltage. When ein goes below eout A3
goes negative, turning SW1 off. The system will therefore
store the most positive analog input experienced.
A2
+
–eout
+
–A3
+
–A1
ein
Reset
SW1
SW2
DG401
R1
C1
Figure 12. Positive Peak Detector
