SN74GTLPH1627
18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
WITH SOURCE SYNCHRONOUS CLOCK OUTPUTS
SCES356C – JUNE 2001 – REVISED FERUAR Y 2003
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Member of the Texas Instruments
Widebus Family
D
TI-OPC Circuitry Limits Ringing on
Unevenly Loaded Backplanes
D
OEC Circuitry Improves Signal Integrity
and Reduces Electromagnetic Interference
D
Bidirectional Interface Between GTLP
Signal Levels and LVTTL Logic Levels
D
GTLP Buffered SYSCLK Signal (SSCLK) for
Source-Synchronous Applications
D
LVTTL Interfaces Are 5-V Tolerant
D
High-Drive GTLP Outputs (100 mA)
D
LVTTL Outputs (–24 mA/24 mA)
D
GTLP Rise and Fall Times Designed for
Optimal Data-Transfer Rate and Signal
Integrity in Distributed Loads
D
Ioff, Power-Up 3-State, and BIAS VCC
Support Live Insertion
D
Bus Hold on A-Port Data Inputs
D
Distributed VCC and GND Pins Minimize
High-Speed Switching Noise
D
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
description/ordering information
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING
–40°C to 85°CTSSOP – DGG Tape and reel SN74GTLPH1627DGGR GTLPH1627
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Copyright 2003, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
OEC, TI-OPC, and Widebus are trademarks of Texas Instruments.
DGG PACKAGE
(TOP VIEW)
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DIR
OE
A1
A2
GND
A3
VCC
A4
A5
CMS
A6
GND
A7
A8
A9
VCC
A10
GND
A11
A12
GND
A13
A14
GND
A15
VCC
A16
GND
A17
A18
CLKOUT
CKOE
FSTA
BIAS VCC
B1
B2
GND
B3
ERC
B4
B5
VREF
B6
GND
B7
B8
B9
VCC
B10
GND
B11
B12
GND
B13
B14
GND
B15
VCC
B16
GND
B17
B18
SSCLK
SYSCLK
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN74GTLPH1627
18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
WITH SOURCE SYNCHRONOUS CLOCK OUTPUTS
SCES356C – JUNE 2001 – REVISED FERUARY 2003
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
The SN74GTLPH1627 is a high-drive, 18-bit bus transceiver that provides LVTTL-to-GTLP and
GTLP-to-L VTTL signal-level translation. The device allows for transparent and latched modes of data transfer.
Additionally , with the use of the clock-mode select (CMS) input, the device can be used in source-synchronous
and clock-synchronous applications. Source-synchronous applications require the skew between the clock
output and data output to be minimized for optimum maximum-frequency system performance. In order to
reduce this skew, a flexible setup time adjustment (FSTA) feature is incorporated into the device that sets a
predetermined delay between the clock and data. The CMS and direction (DIR) inputs control the mode of the
device. The system clock (SYSCLK) and CLKOUT pins are LVTTL compatible, while the source synchronous
I/O is GTLP compatible. The benefits include compensation for output-to-output skew coming from the driver
itself, and compensation for process skew if more than one driver is used. The device provides a high-speed
interface between cards operating at LVTTL logic levels and a backplane operating at GTLP signal levels.
High-speed (about three times faster than standard TTL or LVTTL) backplane operation is a direct result of
GTLP’s reduced output swing (<1 V), reduced input threshold levels, improved differential input, OECcircuitry,
and TI-OPC circuitry. Improved GTLP OEC and TI-OPC circuits minimize bus-settling time and have been
designed and tested using several backplane models. The high drive allows incident-wave switching in heavily
loaded backplanes, with equivalent load impedance down to 11 Ω.
GTLP is the Texas Instruments derivative of the Gunning T ransceiver Logic (GTL) JEDEC standard JESD 8-3.
The ac specification for the SN74GTLPH1627 is given only at the preferred higher noise-margin GTLP, but the
user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or GTLP (VTT = 1.5 V
and VREF = 1 V) signal levels. For information on using GTLP devices in FB+/BTL applications, refer to TI
application reports, Texas Instruments GTLP Frequently Asked Questions, literature number SCEA019, and
GTLP in BTL Applications, literature number SCEA017.
Normally , the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels,
but are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs. VREF is the B-port differential input
reference voltage.
This device is fully specified for live-insertion applications using Ioff, power-up 3-state, and BIAS V CC. The Ioff
circuitry disables the outputs, preventing damaging current backflow through the device when it is powered
down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power
down, which prevents driver conflict. The BIAS VCC circuitry precharges and preconditions the B-port
input/output connections, preventing disturbance of active data on the backplane during card insertion or
removal, and permits true live-insertion capability.
This GTLP device features TI-OPC circuitry, which actively limits the overshoot caused by improperly
terminated backplanes, unevenly distributed cards, or empty slots during low-to-high signal transitions. This
improves signal integrity, which allows adequate noise margin to be maintained at higher frequencies.
High-drive GTLP backplane interface devices feature adjustable edge-rate control (ERC). Changing the ERC
input voltage between low and high adjusts the B-port output rise and fall times. This allows the designer to
optimize system data-transfer rate and signal integrity to the backplane load.
Active bus-hold circuitry holds unused or undriven LVTTL data inputs at a valid logic state. Use of pullup or
pulldown resistors with the bus-hold circuitry is not recommended.
When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.
However , to ensure the high-impedance state above 1.5 V, the output-enable (OE) input should be tied to VCC
through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of
the driver.
SN74GTLPH1627
18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
WITH SOURCE SYNCHRONOUS CLOCK OUTPUTS
SCES356C – JUNE 2001 – REVISED FERUARY 2003
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional description
The SN74GTLPH1627 is a high-drive (100 mA), 18-bit bus transceiver containing D-type latches and D-type
flip-flops for data-path operation in transparent or latched modes and can replace any of the functions shown
in Table 1. Data polarity is noninverting.
Table 1. SN74GTLPH1627 Bus Transceiver Replacement Functions
FUNCTION 8 BIT 9 BIT 10 BIT 16 BIT 18 BIT
Transceiver ’245, ’623, ’645 ’863 ’861 ’16245, ’16623 ’16863
Buffer/driver ’241, ’244, ’541 ’827 ’16241, ’16244, ’16541 ’16825
Latched transceiver ’543 ’16543 ’16472
Latch ’373, ’573 ’843 ’841 ’16373 ’16843
SN74GTLPH1627 bus transceiver replaces all above functions.
Additionally , the device allows for conversion of the system clock (SYSCLK) to GTLP signal levels (SSCLK) and
LVTTL signal levels (CLKOUT). It also provides conversion of a GTLP source-synchronous clock to LVTTL
signal levels (CLKOUT).
The device allows for conversion of the LVTTL system clock (SYSCLK) to GTLP (SSCLK) and LVTTL
(CLKOUT) signal levels when used as the transmitter and GTLP source-synchronous clock (SSCLK) to L VTTL
(CLKOUT) signal levels when used as the receiver in source-synchronous applications. Source-synchronous
operation removes time-of-flight restrictions and allows for increased data throughput. CMS is used to switch
between system-synchronous mode and clock-synchronous mode. The clock output-enable (CKOE) input is
used to switch between latched and transparent mode.
Data flow in each direction is controlled by CKOE, clock (SYSCLK or SSCLK), direction (DIR), and OE. OE
controls the 18 bits of data. The CLKOUT/SSCLK buffered clock path for the A-to-B and B-to-A directions is
controlled by CKOE. In the data isolation mode (OE high, CKOE low), A data may be stored in one register
and/or B data may be stored in the other register.
SN74GTLPH1627
18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
WITH SOURCE SYNCHRONOUS CLOCK OUTPUTS
SCES356C – JUNE 2001 – REVISED FERUARY 2003
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
FSTA
OE
DIR
CMS
CKOE
A1 1D
C1
CLK
1D
C1
CLK
SYSCLK
CLKOUT
B1
VREF
SSCLK
2
1
10
32
3
31
64
33
34
55
62
MUX
1 OF 18 CHANNELS
ERC
58
SN74GTLPH1627
18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
WITH SOURCE SYNCHRONOUS CLOCK OUTPUTS
SCES356C – JUNE 2001 – REVISED FERUARY 2003
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Function Tables
A-TO-B DIRECTION
INPUTS OUTPUTS
MODE
CKOE OE CMS DIR SYSCLK A SSCLK CLKOUT B
MODE
L L X L H or L X SYSCLK SYSCLK B0Latched storage of A
S
L L X L ↑L SYSCLK SYSCLK L
Clocked storage of A
Source
synchronous
LLXL ↑H SYSCLK SYSCLK H
Clocked
storage
of
A
synchronous
L H X L X X SYSCLK SYSCLK Z Data isolation
H L X L X L Z Z L
Trans
p
arent transmission of A
HLXL X H Z ZH
Transparent
transmission
of
A
H H X X X X Z Z Z Isolation
L H H X ↑X SYSCLK SYSCLK Z
Transmit SYSCLK
L H H X H or L X SYSCLK SYSCLK Z
Transmit
SYSCLK
B-TO-A DIRECTION
INPUTS OUTPUTS
MODE
CKOE OE CMS DIR SYSCLK SSCLK B SSCLK CLKOUT A
MODE
L L L H X H or L X Input SSCLK A0Latched storage of B
S
L L L H X ↑L Input SSCLK L
Clocked storage of B
Source
synchronous
LLLH X ↑H Input SSCLK H
Clocked
storage
of
B
synchronous
L H L H X X X Input SSCLK Z Data isolation
L L H H H or L Output X SYSCLK SYSCLK A0Latched storage of B
Cl k
L L H H ↑Output L SYSCLK SYSCLK L
Clocked storage of B
Clock
synchronous
LLHH ↑Output H SYSCLK SYSCLK H
Clocked
storage
of
B
synchronous
L H H H X Output X SYSCLK SYSCLK Z Data isolation
H L X H X Output L Z Z L
Trans
p
arent transmission of B
H L X H X Output H Z ZH
Transparent
transmission
of
B
H H X X X Output X Z Z Z Isolation
L H L X X ↑X Input SSCLK Z
Receive SSCLK
L H L X X H or L X Input SSCLK Z
Receive
SSCLK
OUTPUT EDGE-RATE CONTROL (ERC)
INPUT
ERC OUTPUT
B-PORT
LOGIC LEVEL EDGE RATE
H Slow
L Fast
SN74GTLPH1627
18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
WITH SOURCE SYNCHRONOUS CLOCK OUTPUTS
SCES356C – JUNE 2001 – REVISED FERUARY 2003
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC and BIAS VCC –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1): A-port and control inputs –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . .
B port and VREF –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1):A port –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B port –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the low state, IO: A port 48 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B port 200 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any A-port output in the high state, IO (see Note 2) 48 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through each VCC or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 3) 55°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
SN74GTLPH1627
18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
WITH SOURCE SYNCHRONOUS CLOCK OUTPUTS
SCES356C – JUNE 2001 – REVISED FERUARY 2003
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions (see Notes 4 through 7)
MIN NOM MAX UNIT
VCC,
BIAS VCC Supply voltage 3.15 3.3 3.45 V
VTT
Termination voltage
GTL 1.14 1.2 1.26
V
V
TT
Termination
voltage
GTLP 1.35 1.5 1.65
V
VREF
Reference voltage
GTL 0.74 0.8 0.87
V
V
REF
Reference
voltage
GTLP 0.87 1 1.1
V
VI
In
p
ut voltage
B port and SSCLK VTT
V
V
I
Input
voltage
Except B port and SSCLK VCC 5.5
V
VIH
High level in
p
ut voltage
B port and SSCLK VREF+0.05
V
V
IH
High
-
level
input
voltage
Except B port and SSCLK 2
V
VIL
Low level in
p
ut voltage
B port and SSCLK VREF–0.05
V
V
IL
Low
-
level
input
voltage
Except B port and SSCLK 0.8
V
IIK Input clamp current –18 mA
IOH High-level output current A port and CLKOUT –24 mA
IOL
Low level out
p
ut current
A port and CLKOUT 24
mA
I
OL
Low
-
level
output
current
B port and SSCLK 100
mA
∆t/∆vInput transition rise or fall rate Outputs enabled 10 ns/V
∆t/∆VCC Power-up ramp rate 20 µs/V
TAOperating free-air temperature –40 85 °C
NOTES: 4. All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
5. Proper connection sequence for use of the B-port I/O precharge feature is GND and BIAS VCC = 3.3 V first, I/O second, and
VCC = 3.3 V last, because the BIAS VCC precharge circuitry is disabled when any VCC pin is connected. The control and VREF inputs
can be connected anytime, but normally are connected during the I/O stage. If B-port precharge is not required, any connection
sequence is acceptable, but generally, GND is connected first.
6. VTT and RTT can be adjusted to accommodate backplane impedances if the dc recommended IOL ratings are not exceeded.
7. VREF can be adjusted to optimize noise margins, but normally is two-thirds VTT. TI-OPC circuitry is enabled in the A-to-B direction
and is activated when VTT > 0.7 V above VREF. If operated in the A-to-B direction, VREF should be set to within 0.6 V of VTT to
minimize current drain.
SN74GTLPH1627
18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
WITH SOURCE SYNCHRONOUS CLOCK OUTPUTS
SCES356C – JUNE 2001 – REVISED FERUARY 2003
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range for GTLP
(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
VIK VCC = 3.15 V, II = –18 mA –1.2 V
Atd
VCC = 3.15 V to 3.45 V, IOH = –100 µA VCC–0.2
VOH A port and
CLKOUT
VCC = 3 15 V
IOH = –12 mA 2.4 V
CLKOUT
V
CC =
3
.
15
V
IOH = –24 mA 2
Atd
VCC = 3.15 V to 3.45 V, IOL = 100 µA 0.2
A port and
CLKOUT
VCC = 3 15 V
IOL = 12 mA 0.4
CLKOUT
V
CC =
3
.
15
V
IOL = 24 mA 0.5
VOL VCC = 3.15 V to 3.45 V, IOL = 100 µA 0.2 V
B
p
ort and SSCLK
IOL = 10 mA 0.2
B
port
and
SSCLK
VCC = 3.15 V IOL = 64 mA 0.4
IOL = 100 mA 0.55
IISYSCLK and
control inputs VCC = 3.45 V, VI = 0 to 5.5 V ±10 µA
B port and SSCLK VCC = 3.45 V, VREF within 0.6 V of VTT, VO = 0 to 2.3 V ±10
µA
OZ
CLKOUT VCC = 3.45 V, VO = 0 to 5.5 V ±10 µ
A
IOZH‡A port VCC = 3.45 V, VO = VCC 10 µA
IOZL‡A port VCC = 3.45 V, VO = GND –10 µA
IBHL§A port VCC = 3.15 V, VI = 0.8 V 75 µA
IBHHA port VCC = 3.15 V, VI = 2 V –75 µA
IBHLO#A port VCC = 3.45 V, VI = 0 to VCC 500 µA
IBHHO|| A port VCC = 3.45 V, VI = 0 to VCC –500 µA
AtBt
VCC
=
3.45 V, IO
=
0,
Outputs high 50
ICC A port, B port, or
SSCLK
VCC
=
3
.
45
V
,
IO
=
0
,
VI (A-port or control input) = VCC or GND, Outputs low 50 mA
SSCLK
VI (B port) = VTT or GND Outputs disabled 50
∆ICC
k
VCC = 3.45 V, One A-port or control input at VCC – 0.6 V,
Other A-port or control inputs at VCC or GND 1.5 mA
SYSCLK inputs VI = 3.15 V or 0 4 5 p
F
iControl inputs VI = 3.15 V or 0 3.5 5.5
pF
A port VO = 3.15 V or 0 7.5 9.5 p
F
io B port or SSCLK VO = 1.5 V or 0 9.5 12
pF
CoCLKOUT VO = 3.15 V or 0 6 7.5 pF
†All typical values are at VCC = 3.3 V, TA = 25°C.
‡For I/O ports, the parameter II includes the off-state output leakage current.
§The bus-hold circuit can sink at least the minimum low sustaining current at VILmax. IBHL should be measured after lowering VIN to GND and
then raising it to VILmax.
The bus-hold circuit can source at least the minimum high sustaining current at VIHmin. IBHH should be measured after raising VIN to VCC and
then lowering it to VIHmin.
#An external driver must source at least IBHLO to switch this node from low to high.
|| An external driver must sink at least IBHHO to switch this node from high to low.
k
This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
SN74GTLPH1627
18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
WITH SOURCE SYNCHRONOUS CLOCK OUTPUTS
SCES356C – JUNE 2001 – REVISED FERUARY 2003
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
hot-insertion specifications for A port over recommended operating free-air temperature range
PARAMETER TEST CONDITIONS MIN MAX UNIT
Ioff VCC = 0, BIAS VCC = 0, VI or VO = 0 to 5.5 V 10 µA
IOZPU VCC = 0 to 1.5 V, VO = 0.5 V to 3 V, OE = 0 ±30 µA
IOZPD VCC = 1.5 V to 0, VO = 0.5 V to 3 V, OE = 0 ±30 µA
live-insertion specifications for B port over recommended operating free-air temperature range
PARAMETER TEST CONDITIONS MIN MAX UNIT
Ioff VCC = 0, BIAS VCC = 0, VI or VO = 0 to 1.5 V 10 µA
IOZPU VCC = 0 to 1.5 V, BIAS VCC = 0, VO = 0.5 V to 1.5 V, OE = 0 ±30 µA
IOZPD VCC = 1.5 V to 0, BIAS VCC = 0, VO = 0.5 V to 1.5 V, OE = 0 ±30 µA
ICC (BIAS VCC)
VCC = 0 to 3.15 V
BIAS VCC =315Vto345V
VO(B
p
ort)=0to15V
5 mA
I
CC
(BIAS
V
CC
)
VCC = 3.15 V to 3.45 V
BIAS
V
CC =
3
.
15
V
to
3
.
45
V
,
V
O
(B
port)
=
0
to
1
.
5
V
10 µA
VOVCC = 0, BIAS VCC = 3.3 V, IO = 0 0.95 1.05 V
IOVCC = 0, BIAS VCC = 3.15 V to 3.45 V, VO (B port) = 0.6 V –1µA
timing requirements over recommended ranges of supply voltage and operating free-air
temperature, VTT = 1.5 V and VREF = 1 V for GTLP (unless otherwise noted)
MIN MAX UNIT
fclock Clock frequency 175 MHz
SYSCLK (A to B) or (B to A) high or low 2.5
SYSCLK to CLKOUT high or low 2.8
SYSCLK to SSCLK (FSTA GND) high or low 2.8
twPulse duration SYSCLK to SSCLK (FSTA VCC) high or low 2.3 ns
SSCLK (B to A) high or low 2.8
SSCLK to CLKOUT high or low 2.8
CKOE (A to B) or (B to A) high 2.5
A before SYSCLK↑1.1
B before SYSCLK↑2.2
tsu Setup time B before SSCLK↑1.6 ns
A before CKOE↓1.4
B before CKOE↓0.8
A after SYSCLK↑0.3
B after SYSCLK↑0.7
thHold time B after SSCLK↑1.1 ns
A after CKOE↓0
B after CKOE↓0.7
SN74GTLPH1627
18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
WITH SOURCE SYNCHRONOUS CLOCK OUTPUTS
SCES356C – JUNE 2001 – REVISED FERUARY 2003
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, VTT = 1.5 V and VREF = 1 V for GTLP (see Figure 1)
PARAMETER CLOCK FROM
(INPUT) TO
(OUTPUT) EDGE RATE†FSTA MIN TYP‡MAX UNIT
A or B B or A – – 175
SYSCLK
SYSCLK CLKOUT – – 175
f
SYSCLK
SYSCLK SSCLK –GND 175
MHz
f
max SYSCLK SSCLK –VCC 150
MHz
SSCLK
B A – – 175
SSCLK
SSCLK CLKOUT – – 175
–
A
B
Fast –2.3 6.2
–
A
B
Slow –3 7.3
td
–
CKOE
B
Fast –2.6 6
ns
t
pd –
CKOE
B
Slow –3.1 7.6
ns
–
SYSCLK
B
Fast –2.6 6
–
SYSCLK
B
Slow –3 7.1
ten
OE
B
Fast
2.3 5.1
ns
tdis –
OE
B
Fast
–2.7 5.5
ns
ten
OE
B
Slow
2.9 6
ns
tdis –
OE
B
Slow
–3.6 6.6
ns
t
Rise time, B and SSCLK outputs Fast 1.1
ns
t
r–
,
(20% to 80%) Slow –2.1
ns
tf
Fall time, B and SSCLK outputs Fast 1.8
ns
t
f–
,
(80% to 20%) Slow –2.4
ns
–B A – – 1.5 4.6
–CKOE A– – 2.1 6
td
–SYSCLK A – – 1.9 6
ns
t
pd –SSCLK A – – 2.3 6.6
ns
–SYSCLK CLKOUT – – 3.3 8.3
–SSCLK CLKOUT – – 3.7 9
ten
OE
A
1.6 5
ns
tdis –
OE
A
– – 2.1 6.4
ns
ten
CKOE
CLKOUT
2 5.2
ns
tdis –
CKOE
CLKOUT
– – 2.4 6.1
ns
†Slow (ERC = H) and Fast (ERC = L)
‡All typical values are at VCC = 3.3 V, TA = 25°C.
SN74GTLPH1627
18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
WITH SOURCE SYNCHRONOUS CLOCK OUTPUTS
SCES356C – JUNE 2001 – REVISED FERUARY 2003
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
skew characteristics over recommended ranges of supply voltage and operating free-air
temperature, VREF = 1 V (unless otherwise noted); standard lumped loads, CL = 30 pF for B port
(see Figure 1)†
PARAMETER FROM
(INPUT) TO
(OUTPUT) EDGE
RATE‡FSTA TEST
CONDITIONS MIN MAX UNIT
tsk(LH)§
SYSCLK
B
Ft
0.5
ns
tsk(HL)§
SYSCLK
B
F
as
t
–0.5
ns
tsk(LH)§
SYSCLK
B
Sl
0.5
ns
tsk(HL)§
SYSCLK
B
Sl
ow –0.5
ns
§
SSCLK + ∆B
VCC = 3.15 V, T = 85°C 3.2 4.6
tsk(LH)
§
SYSCLK
SSCLK
+
∆B
(
see Fi
g
ure 2
)
Fast GND VCC = 3.3 V, T = 25°C 2.9 4.3 ns
(see
Figure
2)
VCC = 3.45 V, T = –40°C 2.8 4.1
§
SSCLK + ∆B
VCC = 3.15 V, T = 85°C 3.6 5
tsk(HL)
§
SYSCLK
SSCLK
+
∆B
(
see Fi
g
ure 2
)
Fast GND VCC = 3.3 V, T = 25°C 3.4 4.8 ns
(see
Figure
2)
VCC = 3.45 V, T = –40°C 3.3 4.6
§
SSCLK + ∆B
VCC = 3.15 V, T = 85°C 3 4.6
tsk(LH)
§
SYSCLK
SSCLK
+
∆B
(
see Fi
g
ure 2
)
Slow GND VCC = 3.3 V, T = 25°C 2.6 4.3 ns
(see
Figure
2)
VCC = 3.45 V, T = –40°C 2.4 4
§
SSCLK + ∆B
VCC = 3.15 V, T = 85°C 3.7 5.2
tsk(HL)
§
SYSCLK
SSCLK
+
∆B
(
see Fi
g
ure 2
)
Slow GND VCC = 3.3 V, T = 25°C 3.6 5.1 ns
(see
Figure
2)
VCC = 3.45 V, T = –40°C 3.5 5
§
SSCLK + ∆B
VCC = 3.15 V, T = 85°C 6.5 8.3
tsk(LH)
§
SYSCLK
SSCLK
+
∆B
(
see Fi
g
ure 2
)
Fast VCC VCC = 3.3 V, T = 25°C 6.3 8.2 ns
(see
Figure
2)
VCC = 3.45 V, T = –40°C 5.6 7.4
§
SSCLK + ∆B
VCC = 3.15 V, T = 85°C 7 8.7
tsk(HL)
§
SYSCLK
SSCLK
+
∆B
(
see Fi
g
ure 2
)
Fast VCC VCC = 3.3 V, T = 25°C 6.5 8.3 ns
(see
Figure
2)
VCC = 3.45 V, T = –40°C 6.2 8
§
SSCLK + ∆B
VCC = 3.15 V, T = 85°C 6.4 8.3
tsk(LH)
§
SYSCLK
SSCLK
+
∆B
(
see Fi
g
ure 2
)
Slow VCC VCC = 3.3 V, T = 25°C 5.9 7.7 ns
(see
Figure
2)
VCC = 3.45 V, T = –40°C 5.5 7.4
§
SSCLK + ∆B
VCC = 3.15 V, T = 85°C 7.2 8.9
tsk(HL)
§
SYSCLK
SSCLK
+
∆B
(
see Fi
g
ure 2
)
Slow VCC VCC = 3.3 V, T = 25°C 6.8 8.6 ns
(see
Figure
2)
VCC = 3.45 V, T = –40°C 6.6 8.3
t§
SYSCLK
B
Fast –1.4
ns
t
sk(t)
§
SYSCLK
B
Slow –2
ns
tsk(prLH)
SYSCLK
B
1.8
ns
tsk(prHL)
SYSCLK
B
– – 2.8
ns
†Actual skew values between the GTLP outputs could vary on the backplane due to the loading and impedance seen by the device.
‡Slow (ERC = H) and Fast (ERC = L)
§tsk(LH)/tsk(HL) and tsk(t) – Output-to-output skew is defined as the absolute value of the difference between the actual propagation delay for all
outputs with the same packaged device. The specifications are given for specific worst-case VCC and temperature. The specifications apply to
any outputs switching in the same direction, either high to low [tsk(HL)], low to high [tsk(LH)] or in opposite directions, both low to high and high
to low [tsk(t)].
tsk(prLH) or tsk(prHL) – Part-to-part skew is designed as the absolute value of the difference between the actual propagation delay for all outputs
from device to device. The parameter is specified for a specific worst-case VCC and temperature. Furthermore, these values are provided by
SPICE simulations.
SN74GTLPH1627
18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
WITH SOURCE SYNCHRONOUS CLOCK OUTPUTS
SCES356C – JUNE 2001 – REVISED FERUARY 2003
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT FOR A OUTPUTS
S1 Open
GND
500 Ω
500 Ω TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
S1
Open
6 V
GND
tPLH tPHL
Output
Control
Output
W aveform 1
S1 at 6 V
(see Note B)
Output
W aveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
3 V
0 V
VOH
VOL
0 V
VOL + 0.3 V
VOH – 0.3 V
≈0 V
3 V
0 V
tw
Input
3 V
3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
(VM = 1.5 V for A port and 1 V for B port)
(VOH = 3 V for A port and 1.5 V for B port)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
(A port to B port)
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
(A port)
Output
Input
1.5 V
Test
Point
CL = 30 pF
(see Note A)
From Output
Under Test
12.5 Ω
LOAD CIRCUIT FOR B OUTPUTS
0 V
VOH
VOL
Input
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
(B port to A port)
Output
1.5 V
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. Load circuit for A outputs also is used for CLKOUT; load circuit for B outputs also is used for SSCLK.
6 V
tPLH tPHL
VOH
0 V
VMVM
Data
Input
3 V
0 V
tsu th
Timing
Input
1.5 V 1.5 V
1.5 V 1.5 V
1 V 1 V
1 V 1 V
1.5 V 1.5 V
1.5 V
1.5 V 1.5 V
1.5 V
1.5 V
Figure 1. Load Circuits and Voltage Waveforms
SN74GTLPH1627
18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
WITH SOURCE SYNCHRONOUS CLOCK OUTPUTS
SCES356C – JUNE 2001 – REVISED FERUARY 2003
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SYSCLK
B1
A
B18
SSCLK
SYSCLK to B tPLH SYSCLK to B tPHL
∆B∆B
SYSCLK to SSCLK
FSTA (Fast)
SYSCLK to SSCLK
FSTA (Slow)
SYSCLK to SSCLK
FSTA (Fast)
SYSCLK to SSCLK
FSTA (Slow)
tsk(LH)
FSTA (Fast)
tsk(LH)
FSTA (Slow)
tsk(HL)
FSTA (Fast)
tsk(HL)
FSTA (Slow)
1.5 V
Test
Point
CL = 30 pF
(see Note A)
From Output
Under Test
12.5 Ω
LOAD CIRCUIT FOR B OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
C. The outputs are measured one at a time with one transition per measurement.
D. Load circuit for B outputs also is used for SSCLK.
Figure 2. Load Circuit and SYSCLK to SSCLK + ∆B Skew Waveforms
SN74GTLPH1627
18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
WITH SOURCE SYNCHRONOUS CLOCK OUTPUTS
SCES356C – JUNE 2001 – REVISED FERUARY 2003
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DISTRIBUTED-LOAD BACKPLANE SWITCHING CHARACTERISTICS
The preceding switching characteristics table shows the switching characteristics of the device into a lumped load
(Figure 1). However , the designer’s backplane application is probably a distributed load. The physical representation
is shown in Figure 3. This backplane, or distributed load, can be closely approximated to a resistor inductance
capacitance (RLC) circuit, as shown in Figure 4. This device has been designed for optimum performance in this RLC
circuit. The following switching characteristics table shows the switching characteristics of the device into the RLC
load, to help the designer to better understand the performance of the GTLP device in this typical backplane. See
www.ti.com/sc/gtlp for more information.
Drvr
1.5 V
.25”1”
1”1”
1.5 V
1”1”
1”.25”
Rcvr Rcvr Rcvr
Figure 3. High-Drive Test Backplane
Slot 1 Slot 2 Slot 19 Slot 20
Conn. Conn. Conn. Conn.
ZO = 50 Ω
22Ω
22Ω
From Output
Under Test Test
Point
1.5 V
CL = 18 pF
11 Ω
LL = 14 nH
Figure 4. High-Drive RLC Network
switching characteristics over recommended operating conditions for the bus transceiver
function (unless otherwise noted) (see Figure 4)
PARAMETER FROM
(INPUT) TO
(OUTPUT) EDGE RATE†FSTA TYP‡UNIT
tPLH
Fast
4.8
tPHL
A
B
Fast
–4.2
ns
tPLH
A
B
Slow
5.6
ns
tPHL
Slow
–5.2
tPLH
Fast
4.9
tPHL
SYSCLK
B
Fast
–4.5
ns
tPLH
SYSCLK
B
Slow
5.5
ns
tPHL
Slow
–5.2
t
Rise time, B and SSCLK outputs Fast –0.9
ns
t
r
,
(20% to 80%) Slow –1.3
ns
tf
Fall time, B and SSCLK outputs Fast –2.3
ns
t
f
,
(80% to 20%) Slow –2.7
ns
†Slow (ERC = H) and Fast (ERC = L)
‡All typical values are at VCC = 3.3 V, TA = 25°C. All values are derived from TI-SPICE models.
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUAR Y 1998
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
4040078/F 12/97
48 PINS SHOWN
0,25
0,15 NOM
Gage Plane
6,00
6,20 8,30
7,90
0,75
0,50
Seating Plane
25
0,27
0,17
24
A
48
1
1,20 MAX
M
0,08
0,10
0,50
0°–8°
56
14,10
13,90
48
DIM
A MAX
A MIN
PINS **
12,40
12,60
64
17,10
16,90
0,15
0,05
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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