MAX3480EA/MAX3480EB
±15kV ESD-Protected, Isolated, 3.3V
RS-485/RS-422 Data Interfaces
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±15kV ESD Protection
As with all Maxim devices, ESD-protection structures
are incorporated on all pins to protect against electro-
static discharges encountered during handling and
assembly. The driver outputs and receiver inputs have
extra protection against static electricity. Maxim’s engi-
neers developed state-of-the-art structures to protect
these pins against ESD of ±15kV without damage. The
ESD structures withstand high ESD in all states: normal
operation, shutdown, and power-down. After an ESD
event, Maxim’s MAX3480EA/MAX3480EB keep working
without latchup. An isolation capacitor of 270pF 4kV
should be placed between ISO COM and logic ground
for optimal performance against an ESD pulse with
respect to logic ground.
ESD protection can be tested in various ways; the
transmitter outputs and receiver inputs of this product
family are characterized for protection to ±15kV using
the Human Body Model.
ESD Test Conditions
The +15kV ESD test specifications apply only to the A, B,
Y, and Z I/O pins. The test surge may be referenced to
either the ISO COM or to the nonisolated GND (this pre-
supposes that a bypass capacitor is installed between
VCC2 and the nonisolated GND).
Human Body Model
Figure 9 shows the Human Body Model, and Figure 10
shows the current waveform it generates when dis-
charged into a low impedance. This model consists of a
100pF capacitor charged to the ESD voltage of interest,
which is then discharged into the test device through a
1.5kΩresistor.
Machine Model
The Machine Model for ESD tests all pins using a 200pF
storage capacitor and zero discharge resistance. Its
objective is to simulate the stress caused by contact that
occurs with handling and assembly during manufactur-
ing. Of course, all pins require this protection during
manufacturing—not just inputs and outputs. Therefore,
after PC board assembly, the Machine Model is less rel-
evant to l/O ports.
The MAX3480EA/MAX3480EB are designed for bidirec-
tional data communications on multipoint bus-transmis-
sion lines. Figure 11 shows a typical network application
circuit. To minimize reflections, terminate the line at both
ends with its characteristic impedance, and keep stub
lengths off the main line as short as possible. The slew-
rate-limited MAX3480EB is more tolerant of imperfect ter-
mination and stubs off the main line.
The MAX3480EA/MAX3480EB are specified and char-
acterized using the resistor values shown in Table 1.
Altering the recommended values can degrade perfor-
mance.
The DI and DE inputs are the cathodes of LEDs whose
anodes are connected to VCC. These points are best
driven by a +3.3V CMOS-logic gate with a series
resistor to limit the current. The resistor values shown
in Table 1 are recommended when the 74HC240 gate
or equivalent is used. DI and DE are intended to be