8523BG www.icst.com/products/hiperclocks.html REV. B JULY 31, 2001
1
Integrated
Circuit
Systems, Inc.
ICS8523
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
BLOCK DIAGRAM PIN ASSIGNMENT
ICS8523
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm body package
G Package
Top View
GND
CLK_EN
CLK_SEL
CLK
nCLK
PCLK
nPCLK
nc
nc
VDD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Q0
nQ0
VDDO
Q1
nQ1
Q2
nQ2
VDDO
Q3
nQ3
CLK
nCLK
PCLK
nPCLK
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
0
1
CLK_EN
CLK_SEL
DQ
LE
GENERAL DESCRIPTION
The ICS8523 is a low skew, high perfor-
mance 1-to-4 Differential-to-L VHSTL fanout buffer
and a member of the HiPerClockS™ family of High
Performance Clock Solutions from ICS. The
ICS8523 has two selectable clock inputs. The
CLK, nCLK pair can accept most standard differential input
levels. The PCLK, nPCLK pair can accept LVPECL, CML, or
SSTL input levels. The clock enable is internally synchronized
to eliminate runt pulses on the outputs during asynchronous
assertion/deassertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics
make the ICS8523 ideal for those applications demanding
well defined performance and repeatability .
FEATURES
•4 differential 1.8V L VHSTL outputs
•Selectable CLK, nCLK or L VPECL clock inputs
•CLK, nCLK pair can accept the following differential input
levels: L VDS, LVPECL, L VHSTL, SSTL, HCSL
•PCLK, nPCLK supports the following input types:
L VPECL, CML, SSTL
•Maximum output frequency up to 650MHz
•Translates any single-ended input signal to 1.8V L VHSTL
levels with resistor bias on nCLK input
•Output skew: 30ps (maximum)
•Part-to-part skew: 150ps (maximum)
•Propagation delay: 1.6ns (maximum)
•3.3V core, 1.8V output operating supply
•0°C to 70°C ambient operating temperature
•Industrial temperature information available upon request
HiPerClockS™
,&6
8523BG www.icst.com/products/hiperclocks.html REV. B JULY 31, 2001
2
Integrated
Circuit
Systems, Inc.
ICS8523
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
TABLE 2. PIN CHARACTERISTICS
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
C
NI
ecnaticapaCtupnI KLCn,KLC4Fp
KLCPn,KLCP4Fp
LES_KLC,NE_KLC4Fp
R
PULLUP
rotsiseRpulluPtupnI 15KΩ
R
NWODLLUP
rotsiseRnwodlluPtupnI 15KΩ
rebmuNemaNepyTnoitpircseD
1DNGrewoP.dnuorgottcennoC.dnuorgylppusrewoP
2NE_KLCtupnIpulluP kcolcwollofstuptuokcolc,HGIHnehW.elbanekcolcgnizinorhcnyS decroferastuptuoQn,woldecroferastuptuoQ,WOLnehW.tupni .slevelecafretniLTTVL/SOMCVL.hgih
3LES_KLCtupnInwodlluP KLCPn,KLCPlaitnereffidstceles,HGIHnehW.tupnitceleskcolC .stupniKLCn,KLCstceles,WOLnehW.stupni .slevelecafretniLTTVL/SOMCVL
4KLCtupnInwodlluP.tupnikcolclaitnereffidgnitrevni-noN
5KLCntupnIpulluP.tupnikcolclaitnereffidgnitrevnI
6KLCPtupnInwodlluP.tupnikcolcLCEPVLlaitnereffidgnitrevni-noN
7KLCPntupnIpulluP.tupnikcolcLCEPVLlaitnereffidgnitrevnI
9,8cndesunU.tcennocoN
01V
DD
rewoP.V3.3ottcennoC.nipylppusevitisoP
21,113Q,3QntuptuO.slevelecafretniLTSHVL.riaptuptuolaitnereffiD
81,31V
ODD
rewoP.V8.1ottcennoC.snipylppustuptuO
51,412Q,2QntuptuO.slevelecafretniLTSHVL.riaptuptuolaitnereffiD
71,611Q,1QntuptuO.slevelecafretniLTSHVL.riaptuptuolaitnereffiD
02,910Q,0QntuptuO.slevelecafretniLTSHVL.riaptuptuolaitnereffiD
:ETON
pulluP
dna
nwodlluP
.seulavlacipytrof,scitsiretcarahCniP,2elbaTeeS.srotsisertupnilanretniotsrefer
8523BG www.icst.com/products/hiperclocks.html REV. B JULY 31, 2001
3
Integrated
Circuit
Systems, Inc.
ICS8523
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
TABLE 3A. CONTROL INPUT FUNCTION TABLE
TABLE 3B. CLOCK INPUT FUNCTION TABLE
stupnIstuptuO
NE_KLCLES_KLCecruoSdetceleS3Qurht0Q3Qnurht0Qn
00 KLCn,KLCWOL;delbasiDHGIH;delbasiD
01 KLCPn,KLCPWOL;delbasiDHGIH;delbasiD
10 KLCn,KLCdelbanEdelbanE
11 KLCPn,KLCPdelbanEdelbanE egdekcolctupnignillafdnagnisiragniwollofdelbanerodelbasiderastuptuokcolceht,sehctiwsNE_KLCretfA .1erugiFninwohssa debircsedsastupniKLCPn,KLCPdnaKLCn,KLCehtfonoitcnufaerastuptuoehtfoetatseht,edomevitcaehtnI .B3elbaTni
stupnIstuptuO edoMtuptuOottupnIytiraloP
KLCProKLCKLCPnroKLCn3Qurht0Q3Qnurht0Qn
00WOLHGIHlaitnereffiDotlaitnereffiDgnitrevnInoN
11 HGIHWOLlaitnereffiDotlaitnereffiDgnitrevnInoN
01ETON;desaiBWOLHGIHlaitnereffiDotdednEelgniSgnitrevnInoN
11ETON;desaiBHGIHWOLlaitnereffiDotdednEelgniSgnitrevnInoN
1ETON;desaiB0HGIHWOLlaitnereffiDotdednEelgniSgnitrevnI
1ETON;desaiB1WOLHGIHlaitnereffiDotdednEelgniSgnitrevnI laitnereffidehtgniriwsessucsidhcihw,9erugiF,8egapnonoitcesnoitamrofnInoitacilppAehtotreferesaelP:1ETON .sleveldedneelgnistpeccaottupni
FIGURE 1 - CLK_EN TIMING DIAGRAM
Enabled
Disabled
nCLK, nPCLK
CLK, PCLK
CLK_EN
nQ0 - nQ3
Q0 - Q3
8523BG www.icst.com/products/hiperclocks.html REV. B JULY 31, 2001
4
Integrated
Circuit
Systems, Inc.
ICS8523
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C
ABSOLUTE MAXIMUM RATINGS
Supply V oltage, VDDx 4.6V
Inputs, VI-0.5V to VDD + 0.5V
Outputs, VO-0.5V to VDDO + 0.5V
Package Thermal Impedance, θJA 73.2°C/W
Storage T emperature, TSTG -65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics
or
AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended peri-
ods may affect product reliability.
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
DD
egatloVylppuSrewoPtupnI 531.33.3564.3V
V
ODD
egatloVylppuSrewoPtuptuO6.18.10.2V
I
DD
tnerruCylppuSrewoP 05Am
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
HI
egatloVhgiHtupnILES_KLC,NE_KLC2567.3V
V
LI
egatloVwoLtupnILES_KLC,NE_KLC3.0-8.0V
I
HI
tnerruChgiHtupnI NE_KLCV
DD
V=
NI
V564.3=5Aµ
LES_KLCV
DD
V=
NI
V564.3=051Aµ
I
LI
tnerruCwoLtupnI NE_KLCV
DD
V,V564.3=
NI
V0=051-Aµ
LES_KLCV
DD
V,V564.3=
NI
V0=5-Aµ
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
I
HI
tnerruChgiHtupnI KLCnV
DD
V=
NI
V564.3=5Aµ
KLCV
DD
V=
NI
V564.3=051Aµ
I
LI
tnerruCwoLtupnI KLCnV
DD
V,V564.3=
NI
V0=051-Aµ
KLCV
DD
V,V564.3=
NI
V0=5-Aµ
V
PP
egatloVtupnIkaeP-ot-kaeP 51.03.1V
V
RMC
;egatloVtupnIedoMnommoC 2,1ETON 5.0V
DD
58.0-V
VsiKLCndnaKLCrofegatlovtupnimumixamehtsnoitacilppadedneelgnisroF:1ETON
DD
.V3.0+
VsadenifedsiegatlovedomnommoC:2ETON
HI
.
8523BG www.icst.com/products/hiperclocks.html REV. B JULY 31, 2001
5
Integrated
Circuit
Systems, Inc.
ICS8523
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
TABLE 4D. LVPECL DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C
TABLE 5. AC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
I
HI
tnerruChgiHtupnI KLCPV
DD
V=
NI
V564.3=051Aµ
KLCPnV
DD
V=
NI
V564.3=5Aµ
I
LI
tnerruCwoLtupnI KLCPV
DD
V,V564.3=
NI
V0=5-Aµ
KLCPnV
DD
V,V564.3=
NI
V0=051-Aµ
V
PP
egatloVtupnIkaeP-ot-kaeP 3.01V
V
RMC
2,1ETON;egatloVtupnIedoMnommoC 5.1V
DD
V
VsadenifedsiegatlovedomnommoC:1ETON
HI
.VsiKLCPndnaKLCProfegatlovtupnimumixamehtsnoitacilppadedneelgnisroF:2ETON
DD
.V3.0+
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
f
XAM
ycneuqerFtuptuOmumixaM 056zHM
t
DP
1ETON;yaleDnoitagaporP IJzHM0563.16.1sn
t
)o(ks4,2ETON;wekStuptuO 03sp
t
)pp(ks4,3ETON;wekStraP-ot-traP 051sp
t
R
emiTesiRtuptuOzHM05@%08ot%02003007sp
t
F
emiTllaFtuptuOzHM05@%08ot%02003007sp
cdoelcyCytuDtuptuO5455%
.esiwrehtodetonsselnuzHM005taderusaemsretemarapllA .rettijddatonseodtrapehT.tuptuoehtnorettijehtlauqelliwtupniehtnorettijelcycotelcycehT .tniopgnissorctuptuolaitnereffidehtottniopgnissorctupnilaitnereffidehtmorfderusaeM:1ETON .snoitidnocdaollauqehtiwdnaegatlovylppusemasehttastuptuoneewtebwekssadenifeD:2ETON .stniopssorclaitnereffidtuptuotaderusaeM segatlovylppusemasehttagnitareposecivedtnereffidnostuptuoneewtebwekssadenifeD:3ETON derusaemerastuptuoeht,ecivedhcaenostupnifoepytemasehtgnisU.snoitidnocdaollauqehtiwdna .stniopssorclaitnereffidehtta .56dradnatSCEDEJhtiwecnadroccanidenifedsiretemarapsihT:4ETON
TABLE 4D. LVHSTL DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
HO
;egatloVhgiHtuptuO 1ETON 14.1V
V
LO
;egatloVwoLtuptuO 1ETON 04.0V
V
XO
egatloVrevossorCtuptuO(x%04V
HO
-V
LO
+)V
LO
V(x%06
HO
V-
LO
V+)
LO
V
V
GNIWS
kaeP-ot-kaeP gniwSegatloVtuptuO 57.052.1V
05htiwdetanimretstuptuO:1ETON Ω.dnuorgot
8523BG www.icst.com/products/hiperclocks.html REV. B JULY 31, 2001
6
Integrated
Circuit
Systems, Inc.
ICS8523
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
FIGURE 4 - OUTPUT SKEW
tsk(o)
Qx
nQx
Qy
nQy
FIGURE 3 - DIFFERENTIAL INPUT LEVEL
VCMR
Cross Points
VPP
CLK, PCLK
nCLK, nPCLK
GND
VDD
FIGURE 2 - OUTPUT LOAD TEST CIRCUIT
SCOPE
LVHSTL
Qx
nQx
VDD = 3.3V ± 5%
VDDO = 1.8V ± 0.2V
VDDO
VDD
GND = 0V
8523BG www.icst.com/products/hiperclocks.html REV. B JULY 31, 2001
7
Integrated
Circuit
Systems, Inc.
ICS8523
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
Clock Inputs
and Outputs
20%
80%
20%
80%
tRtF
VSWING
FIGURE 6 - INPUT AND OUTPUT RISE AND FALL TIME
FIGURE 8 - odc & tPERIOD
Pulse Width
tPERIOD
tPW
tPERIOD
odc =
CLK, PCLK, Qx
nCLK, nPCLK, nQx
FIGURE 7 - PROPAGATION DELAY
t
PD
CLK, PCLK
nCLK, nPCLK
Q0 - Q3
nQ0 - nQ3
FIGURE 5 - PART-TO-PART SKEW
Qx
nQx
Qy
nQy
PART 1
PART 2
tsk(pp)
8523BG www.icst.com/products/hiperclocks.html REV. B JULY 31, 2001
8
Integrated
Circuit
Systems, Inc.
ICS8523
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 9
shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
FIGURE 9: SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
R2
1K
VDD
CLK_IN +
-
R1
1K
C1
0.1uF
V_REF
8523BG www.icst.com/products/hiperclocks.html REV. B JULY 31, 2001
9
Integrated
Circuit
Systems, Inc.
ICS8523
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8523.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8523 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 50mA = 173.3mW
•Power (outputs)MAX = 32mW/Loaded Output pair
If all outputs are loaded, the total power is 4 * 32mW = 128mW
Total Power_MAX (3.465V, with all outputs switching) = 173.3mW + 128mW = 301.3mW
2. Junction T emperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly af fects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = junction-to-ambient thermal resistance
Pd_total = Total device power dissipation (example calculation is in section 1 above)
TA = Ambient T emperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used . Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6 below .
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.301W * 66.6°C/W = 90.05°C. This is well below the limit of 125°C
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow ,
and the type of board (single layer or multi-layer).
qJA by V elocity (Linear Feet per Minute)
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 98.0°C/W 88.0°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W 66.6°C/W 63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
Table 6. Thermal Resistance qJA for 20-pin TSSOP, Forced Convection
8523BG www.icst.com/products/hiperclocks.html REV. B JULY 31, 2001
10
Integrated
Circuit
Systems, Inc.
ICS8523
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVHSTL output driver circuit and termination are shown in
Figure 10.
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of VDD- 2V .
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low .
Pd_H = (VOH_MAX /RL) * (VDD_MAX - VOH_MAX)
Pd_L = (VOL_MAX /RL) * (VDD_MAX - VOL_MAX)
•For logic high, VOUT = VOH_MAX = VDD_MAX – 1.2V
•For logic low , VOUT = VOL_MAX = VDD_MAX – 0.4V
Pd_H = (1.2V/50Ω) * (2V - 1.2V) = 19.2mW
Pd_L = (0.4V/50Ω) * (2V - 0.4V) = 12.8mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 32mW
FIGURE 10 - LVHSTL DRIVER CIRCUIT AND TERMINATION
VDD
VOUT
RL
50Ω
Q1
8523BG www.icst.com/products/hiperclocks.html REV. B JULY 31, 2001
11
Integrated
Circuit
Systems, Inc.
ICS8523
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
RELIABILITY INFORMATION
TRANSISTOR COUNT
The transistor count for ICS8523 is: 472
TABLE 7. θJAVS. AIR FLOW TABLE
qJA by V elocity (Linear Feet per Minute)
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 98.0°C/W 88.0°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W 66.6°C/W 63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
8523BG www.icst.com/products/hiperclocks.html REV. B JULY 31, 2001
12
Integrated
Circuit
Systems, Inc.
ICS8523
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
PACKAGE OUTLINE - G SUFFIX
TABLE 8. PACKAGE DIMENSIONS
Reference Document: JEDEC Publication 95, MS-153
LOBMYS sretemilliM
NIMXAM
N02
A--02.1
1A50.051.0
2A08.050.1
b91.003.0
c90.002.0
D04.606.6
ECISAB04.6
1E03.405.4
eCISAB56.0
L54.057.0
α°0°8
aaa--01.0
8523BG www.icst.com/products/hiperclocks.html REV. B JULY 31, 2001
13
Integrated
Circuit
Systems, Inc.
ICS8523
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
TABLE 9. ORDERING INFORMATION
While the information presented herein has been checked for both accuracy and reliability , Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement
of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications.
Any other applications such as those requiring extended temperature range, high reliability , or other extraordinary environmental requirements are not recommended without additional processing by
ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
rebmuNredrO/traPgnikraMegakcaPtnuoCerutarepmeT
GB3258SCIGB3258SCIPOSSTdael02ebutrep27C°07otC°0
TGB3258SCIGB3258SCIleeRdnaepaTnoPOSSTdael020052C°07otC°0
