PIC12C5XX 8-Pin, 8-Bit CMOS Microcontroller Devices included in this Data Sheet: - EXTRC: External low-cost RC oscillator * PIC12C508 + PIC12C508A - XT: Standard crystal/resonator * PIC12C509 + PIC12C509A - LP: Power saving, low frequency crystal Note: Throughout this data sheet PIC12C508(A) CMOS Technology: refers to the PIC12C508 and PIC12C508A. * Low power, high speed CMOS EPROM PIC12C509(A) refers to the PIC12C509 technology and PIC12C509A. PIC12C5XxX refers to the PIC12C508, PIC12C508A, PIC12C509 and PIC12C509A. * Fully static design * Wide operating voltage range + Wide temperature range: High-Performance RISC CPU: - Commercial: 0C to +70C * Only 33 single word instructions to learn - Industrial: -40C to +85C * All instructions are single cycle (1 ys) except for - Extended: -40C to +125C program branches which are two-cycle + Low power consumption * Operating speed: DC - 4 MHz clock input -<2 MA@ BV, 4 MHz DC - 1 us instruction cycle - 15 pA typical @ 3V, 32 KHz ; - <1 pA typical standby current Device EPROM RAM Pin Di In Diagram PIC12C508 512x 12 25 g PIC12C508A 512x12 25 PDIP, SOIC, Windowed Ceramic Side Brazed PIC12C509 1024 x 12 41 Ves VDD +{]1 uy 8 PIC12C509A 1024 x 12 41 GPS/OSCI/CLKIN f}2 2 2 7 F}+> GPO . 12-bit wide instructions Gp4/osce 3 939 6h GPt * 8-bit wide data path GPaMCLRVep m{]4 SB & 5[]}*+ GP2/TOCK * Seven special function hardware registers Ze * Two-level deep hardware stack * Direct, indirect and relative addressing modes for data and instructions * Internal 4 MHz RC oscillator with programmable calibration * In-circuit serial programming Peripheral Features: * 8-bit real time clock/counter (TMRO) with 8-bit programmable prescaler + Power-On Reset (POR) * Device Reset Timer (DRT) * Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation * Programmable code-protection * Power saving SLEEP mode * Wake-up from SLEEP on pin change * Internal weak pull-ups on I/O pins * Internal pull-up on MCLR pin * Selectable oscillator options: - INTRC: Internal 4 MHz RC oscillator 1998 Microchip Technology Inc. DS40139D-page 1PIC12C5XX Device Differences Volt Oscillator Process Device oltage Oscillator Calibration Technology Range | . (Bits) (Microns) PIC12C508A 3.0-5.5 See Note 1 6 0.7 PIC12LC508A 2.5-5.5 See Note 1 6 0.7 PIC12C508 2.5-5.5 See Note 1 4 0.9 PIC12C509A 3.0-5.5 See Note 1 6 0.7 PIC12LC509A 2.5-5.5 See Note 1 6 0.7 PIC12C509 2.5-5.5 See Note 1 4 0.9 Note 1: If you change from the PIC12C50X to the PIC12C50XA, please verify oscillator characteristics in your appli- cation. Note 2: See Section 7.2.5 for OSCCAL implementation differences. DS40139D-page 2 1998 Microchip Technology Inc.PIC12C5XX TABLE OF CONTENTS 1.0 General Description 2.0 PIC12C5XX Device Varieties... 3.0 Architectural Overview ............. 4.0 Memory Organization 5.0 VO Port eee eecceecceeeeceececeeeceeaeeecesaeeseceeeeaeceseeaecesecaeeceecaeeceesaesaeecaeeaseresaeeeeesaneeeesareceesaeeceeseeaeeireseeeesaneeesaeeeeesareceesaresieenteneeenteaes 6.0 TimerO Module and TMRO Register ... . 7.0 Special Features of the CPU.............. 27 8.0 Instruction Set Summary.......... 9.0 Development Support 10.0 Electrical Characteristics - PIC12C508/PIC12C509/PIC12LC508/PIC12LC509 oo... eeceecceeece cere eeeeneeeeeeeeeneeseeneeeseenneneeentes 57 11.0 12.0 13.0 14.0 To Our Valued Customers Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please check our Worldwide Web site at: http:/Avww.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number. e.g., DS30000A is version A of document DS30000. Errata An errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and recommended workarounds. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revi- sion of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: * Microchips Worldwide Web site; htto:/Avwww.microchip.com * Your local Microchip sales office (see last page) * The Microchip Corporate Literature Center; U.S. FAX: (602) 786-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include lit- erature number) you are using. Corrections to this Data Sheet We constantly strive to improve the quality of all our products and documentation. We have spent a great deal of time to ensure that this document is correct. However, we realize that we may have missed a few things. If you find any information that is missing or appears in error, please: * Fill out and mail in the reader response form in the back of this data sheet. * E-mail us at webmaster@microchip.com. We appreciate your assistance in making this a better document. 1998 Microchip Technology Inc. DS40139D-page 3PIC12C5XX 1.0 GENERAL DESCRIPTION The PIC12C5XX from Microchip Technology is a family of low-cost, high performance, 8-bit, fully static, EPROM/ROM-based CMOS microconirollers. It employs a RISC architecture with only 33 single word/ single cycle instructions. All instructions are single cycle (1 ws) except for program branches which take two cycles. The PIC12C5XX delivers performance an order of magnitude higher than its competitors in the same price category. The 12-bit wide instructions are highly symmetrical resulting in 2:1 code compression over other 8-bit microcontrollers in its class. The easy to use and easy to remember instruction set reduces development time significantly. The PIC12C5XX products are equipped with special features that reduce system cost and power require- ments. The Power-On Reset (POR) and Device Reset Timer (DRT) eliminate the need for external reset cir- cuitry. There are four oscillator configurations to choose from, including INTRC internal oscillator mode and the power-saving LP (Low Power) oscillator mode. Power saving SLEEP mode, Watchdog Timer and code protection features also improve system cost, power and reliability. The PIC12C5XX are available in the cost-effective One-Time-Programmable (OTP) versions which are suitable for production in any volume. The customer can take full advantage of Microchips price leadership in OTP microcontrollers while benefiting from the OTPs flexibility. The PIC12C5XX products are supported by a full-fea- tured macro assembler, a software simulator, an in-cir- cuit emulator, a C compiler, fuzzy logic support tools, a low-cost development programmer, and a full fea- tured programmer. All the tools are supported on IBM PC and compatible machines. 1.1 Applications The PIC12C5XX series fits perfectly in applications ranging from personal care appliances and security systems to low-power remote transmitters/receivers. The EPROM technology makes customizing applica- tion programs (transmitter codes, appliance settings, receiver frequencies, etc.) extremely fast and conve- nient. The small footprint packages, for through hole or surface mounting, make this microcontroller series per- fect for applications with space limitations. Low-cost, low-power, high performance, ease of use and I/O flex- ibility make the PIC12C5XX series very versatile even in areas where no microcontroller use has been considered before (e.g., timer functions, replacement of glue logic and PLDs in larger systems, coproces- sor applications). DS40139D-page 4 1998 Microchip Technology Inc.PIC12C5XX TABLE 1-1: PIC12CXXX & PIC12CEXXX FAMILY OF DEVICES PIC12C508(A) | PIC12C509(A) | PIC12CE518 | PIC12CE519} PIC12C671 | PIC12C672 | PIC12CE673 | PIC12CE674 Maximum 4 4 4 4 10 10 10 10 Frequency of Operation (MHz) EPROM 512 x12 1024 x 12 512x112 1024 x 12 1024 x 14 2048 x 14 1024 x 14 2048 x 14 Program Memory RAM Data 25 41 25 4 128 128 128 128 Memory (bytes) EEPROM _ _ 16 16 _ _ 16 16 Data Memory (bytes) Timer TMRO TMRO TMRO TMRO TMRO TMRO TMRO TMRO Module(s) A/D Con- _ _ _ 4 4 4 4 verter (8-bit) Channels yagi latte) Wake-up Yes Yes Yes Yes Yes Yes Yes Yes from SLEEP on pin change Interrupt _ _ 4 4 4 4 Sources etait \/O Pins 5 5 5 5 5 5 5 5 Input Pins os os os os os os os os Internal Yes Yes Yes Yes Yes Yes Yes Yes Pull-ups In-Circuit Yes Yes Yes Yes Yes Yes Yes Yes Serial Programming Number of 33 33 33 33 35 35 35 35 Instructions Packages 8-pin DIP, 8-pin DIP, 8-pin DIP, 8-pin DIP, 8-pin DIP, 8-pin DIP, 8-pin DIP, 8-pin DIP, JW, SOIC JW, SOIC JW, SOIC JW, SOIC JW, SOIC Jw, Soic [JW Jw All PIC12CXXX & PIC12CEXXX devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. All PIC12CXXX & PIC12CEXXX devices use serial programming with data pin GPO and clock pin GP1. 1998 Microchip Technology Inc. DS40139D-page 5PIC12C5XX NOTES: DS40139D-page 6 1998 Microchip Technology Inc.PIC12C5XX 2.0 PIC12C5XX DEVICE VARIETIES A variety of packaging options are available. Depending on application and production requirements, the proper device option can be selected using the information in this section. When placing orders, please use the PIC12C5XX Product Identification System at the back of this data sheet to specify the correct part number. 2.1 UV Erasable Devices The UV erasable version, offered in ceramic side brazed package, is optimal for prototype development and pilot programs. The UV erasable version can be erased and reprogrammed to any of the configuration modes. Note: Please note that erasing the device will also erase the pre-programmed internal calibration value for the internal oscillator. The calibration value must be saved prior to erasing the part. Microchip's PICSTART PLUS and PRO MATE pro- grammers all support programming of the PIC12C5XX. Third party programmers also are available; refer to the Microchip Third Party Guide for a list of sources. 2.2 One-Time-Programmable (OTP) Devices The availability of OTP devices is especially useful for customers who need the flexibility for frequent code updates or small volume applications. The OTP devices, packaged in plastic packages permit the user to program them once. In addition to the program memory, the configuration bits must also be programmed. 2.3 Quick-Turnaround-Production (QTP) Devices Microchip offers a QTP Programming Service for factory production orders. This service is made available for users who choose not to program a medium to high quantity of units and whose code patterns have stabilized. The devices are identical to the OTP devices but with all EPROM locations and fuse options already programmed by the factory. Certain code and prototype verification procedures do apply before production shipments are available. Please con- tact your local Microchip Technology sales office for more details. 2.4 Serialized Quick-Turnaround Production (SQTP=) Devices Microchip offers a unique programming service where a few user-defined locations in each device are programmed with different serial numbers. The serial numbers may be random, pseudo-random or sequential. Serial programming allows each device to have a unique number which can serve as an entry-code, password or ID number. 1998 Microchip Technology Inc. DS40139D-page 7PIC12C5XX NOTES: DS40139D-page 8 1998 Microchip Technology Inc.PIC12C5XX 3.0 ARCHITECTURAL OVERVIEW The high performance of the PIC12C5XX family can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC12C5XX uses a Harvard architecture in which program and data are accessed on separate buses. This improves bandwidth over traditional von Neumann architecture where program and data are fetched on the same bus. Separating program and data memory further allows instructions to be sized differently than the 8-bit wide data word. Instruction opcodes are 12-bits wide making it possible to have all single word instructions. A 12-bit wide program memory access bus fetches a 12-bit instruction in a single cycle. A two-stage pipeline overlaps fetch and execution of instructions. Consequently, all instructions (33) execute in a single cycle (1s @ 4MHz) except for program branches. The table below lists program memory (EPROM) and data memory (RAM) for each PIC12C5XX device. Device EPROM RAM PIC12C508 512x 12 25 PIC12C508A 512x 12 25 PIC12C509 1024 x 12 A1 PIC12C509A 1024 x 12 A1 The PIC12C5XX can directly or indirectly address its register files and data memory. All special function registers including the program counter are mapped in the data memory. The PIC12C5XX has a_ highly orthogonal (symmetrical) instruction set that makes it possible to carry out any operation on any register using any addressing mode. This symmetrical nature and lack of special optimal situations make programming with the PIC12C5XX simple yet efficient. In addition, the learning curve is reduced significantly. The PIC12C5XX device contains an 8-bit ALU and working register. The ALU is a general purpose arithmetic unit. It performs arithmetic and Boolean functions between data in the working register and any register file. The ALU is 8-bits wide and capable of addition, subtraction, shift and logical operations. Unless otherwise mentioned, arithmetic operations are two's complement in nature. In two-operand instructions, typically one operand is the W (working) register. The other operand is either a file register or an immediate constant. In single operand instructions, the operand is either the W register or a file register. The W register is an 8-bit working register used for ALU operations. It is not an addressable register. Depending on the instruction executed, the ALU may affect the values of the Carry (C), Digit Carry (DC), and Zero (Z) bits in the STATUS register. The C and DC bits operate as a borrow and digit borrow out bit, respectively, in subtraction. See the SUBWF and ADDWF instructions for examples. A simplified block diagram is shown in Figure 3-1, with the corresponding device pins described in Table 3-1. 1998 Microchip Technology Inc. DS40139D-page 9PIC12C5XX FIGURE 3-1: PIC12C5XX BLOCK DIAGRAM " Data Bus 8 GPIO EPROM |<=Program Counte| apo 512 x 12 or 1024 x 12 GP1 Program RAM GP2/TOCKI Memory STACK! eer [x] GP3/MCLR/Vpp STACK2 GP4/O0SC2 Regisiers GP5/OSC1/CLKIN Program 40 Bus Instruction reg | Direct Addr ORS UCLKIN aS Generation > 8 F Device Reset V Timer Instruction Decode & Power-on Control Reset Timin Watchdog Timer Internal RC| OSC ALU 8 | TimerO DS40139D-page 10 1998 Microchip Technology Inc.PIC12C5XX TABLE 3-1: PIC12C5XX PINOUT DESCRIPTION Name DIP Pin # solic Pin # VO/P Type Buffer Type Description GPO 7 7 VO TTL/ST Bi-directional I/O port/ serial programming data. Can be software programmed for internal weak pull-up and wake-up from SLEEP on pin change. This buffer is a Schmitt Trigger input when used in serial programming mode. GP1 VO TTL/ST Bi-directional I/O port/ serial programming clock. Can be software programmed for internal weak pull-up and wake-up from SLEEP on pin change. This buffer is a Schmitt Trigger input when used in serial programming mode. GP2/TOCKI VO ST Bi-directional I/O port. Can be configured as TOCKI. GP3/MCLR/VPP TTL/ST Input port/master clear (reset) input/programming volt- age input. When configured as MCLR, this pin is an active low reset to the device. Voltage on MCLR/VPP must not exceed VDD during normal device operation or the device will enter programming mode. Can be software programmed for internal weak pull-up and wake-up from SLEEP on pin change. Weak pull-up always on if configured as MCLR. ST when in MCLR mode. GP4/OSC2 VO TTL Bi-directional I/O port/oscillator crystal output. Con- nections to crystal or resonator in crystal oscillator mode (XT and LP modes only, GPIO in other modes). GP5/OSC1/CLKIN VO TTL/ST Bidirectional |O port/oscillator crystal input/external clock source input (GPIO in Internal RC mode only, OSC1 in all other oscillator modes). TTL input when GPIO, ST input in external RC oscillator mode. VDD ; ; P Positive supply for logic and I/O pins Vss 8 8 P Ground reference for logic and I/O pins Legend: | = input, O = output, I/O = input/output, P = power, = not used, TTL =TTL input, ST = Schmitt Trigger input 1998 Microchip Technology Inc. DS40139D-page 11PIC12C5XX 3.1 Clocking Scheme/Instruction Cycle The clock input (OSC1/CLKIN pin) is internally divided by four to generate four non-overlapping quadrature clocks namely Q1, Q2, Q3 and Q4. Internally, the program counter is incremented every Q1, and the instruction is fetched from program memory and latched into instruction register in Q4. It is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow is shown in Figure 3-2 and Example 3-1. 3.2 Instruction Flow/Pipelining An Instruction Cycle consists of four Q cycles (Q1, Q2, Q3 and @4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g., GOTO) then two cycles are required to complete the instruction (Example 3-1). A fetch cycle begins with the program counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the Instruction Register (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3, and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write). FIGURE 3-2: CLOCK/INSTRUCTION CYCLE | Qt | Q2 | Q3 | Q4 1 Qt | G2 | QB] a4! at | a {| Qa] ai ose1q MALY LY LY EP PP LY Nr rr Fd) Qi yy N rN rN | Q2 | rN | | fT \ || Internal Q3 "> phase p______fo 4 _______/T / \ | | clock Q4 \ / r 2 eee PC I PC { PC+i f PC+2 Fetch INST (PC) | | Execute INST (PC-1) Fetch INST (PC+1) | Execute INST (PC) Fetch INST (PC+2) Execute INST (PC+1)} | | EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW 1. MOVLW 03H Fetch 1 Execute 1 2. MOVWF GPIO Fetch 2 Execute 2 3. CALL SUB_1 Fetch 3 Execute 3 4. BSF GPIO, BIT1 Fetch 4 Flush Fetch SUB_1] Execute SUB_1 All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is flushed from the pipeline while the new instruction is being fetched and then executed. DS40139D-page 12 1998 Microchip Technology Inc.PIC12C5XX 4.0 MEMORY ORGANIZATION PIC12C5XX memory is organized into program mem- ory and data memory. For devices with more than 512 bytes of program memory, a paging scheme is used. Program memory pages are accessed using one STA- TUS register bit. For the PIC12C509(A) with a data memory register file of more than 32 registers, a bank- ing scheme is used. Data memory banks are accessed using the File Select Register (FSR). 4.1 Program Memory Organization The PIC12C5XX devices have a 12-bit Program Counter (PC) capable of addressing a 2K x 12 program memory space. Only the first 512 x 12 (0000h-01FFh) for the PIC12C508(A) and 1K x 12 (0000h-03FFh) for the PIC12C509(A) are physically implemented. Refer to Figure 4-1. Accessing a location above these boundaries will cause a wrap-around within the first 512 x 12 space (PIC12C508(A)) or 1K x 12 space (PIC12C509(A)). The effective reset vector is at 000h, (see Figure 4-1). Location O1FFh (PIC12C508(A)) or location O3FFh (PIC12C509(A)) contains the internal clock oscillator calibration value. This value should never be overwritten. FIGURE 4-1: PROGRAM MEMORY MAP AND STACK FOR THE PIC12C5XX PC<11:0> CALL, RETLW 12 Stack Level 1 Stack Level 2 Reset Vector (note 1) 0000h On-chip Program Memory ~ p Q $ a 512 Word (PIC12C508(A)) | 914FFh 5 0200h wn a) On-chip Program Memory v 1024 Word (PIC12C509(A))) o3FFn 0400h eo Eee, Oe 7FFh Note 1: Address 0000h becomes the effective reset vector. Location 01FFh (PIC12C508(A)) or location O3FFh (PIC12C509(A)) contains the MovLW xx INTERNAL RC oscil- lator calibration value. 1998 Microchip Technology Inc. DS40139D-page 13PIC12C5XX 4.2 Data Memory Organization Data memory is composed of registers, or bytes of RAM. Therefore, data memory for a device is specified by its register file. The register file is divided into two functional groups: special function registers and general purpose registers. The special function registers include the TMRO register, the Program Counter (PC), the Status Register, the I/O registers (ports), and the File Select Register (FSR). In addition, special purpose registers are used to control the I/O port configuration and prescaler options. The general purpose registers are used for data and control information under command of the instructions. For the PIC12C508(A), the register file is composed of 7 special function registers and 25 general purpose registers (Figure 4-2). For the PIC12C509(A), the register file is composed of 7 special function registers, 25 general purpose registers, and 16 general purpose registers that may be addressed using a banking scheme (Figure 4-3). 4.2.1 GENERAL PURPOSE REGISTER FILE The general purpose register file is accessed either directly or indirectly through the file select register FSR (Section 4.8). FIGURE 4-3: PIC12C509(A) REGISTER FILE MAP FIGURE 4-2: PIC1 MAP 2C508(A) REGISTER FILE Note 1: File Address 00h INDFO) Oth TMRO 02h PCL 03h STATUS 04h FSR O5h OSCCAL 06h GPIO 07h 1Fh General Purpose Registers Not a physical register. See Section 4.8 FSR<6:5>_ 00 File Address O1 INDF) | 00h Oth TMRO 02h PCL 03h STATUS 04h FSR 20h Addresses map back to addr O5h OSCCAL 06h GPIO O7h General Purpose OFh Registers in Bank O. 2Fh 10h General Note 1: 1Fh Purpose Registers 30h General Purpose Registers 3Fh Bank 0 Bank 1 Not a physical register. See Section 4.8 DS40139D-page 14 1998 Microchip Technology Inc.PIC12C5XX 4.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers (SFRs) are registers used by the CPU and peripheral functions to control the operation of the device (Table 4-1). The special registers can be classified into two sets. The special function registers associated with the core functions are described in this section. Those related to the operation of the peripheral features are described in the section for each peripheral feature. TABLE 4-1: SPECIAL FUNCTION REGISTER (SFR) SUMMARY Value on Value on Power-On All Other Address Name Bit7 | Bit | Bits | Bit4 | Bits Bit2 | Bit1| Bito Reset Resets) N/A TRIS \/O control registers --11 1111 --11 1111 Contains control bits to configure TimerO, Timer0/WDT N/A OPTION prescaler, wake-up on change, and weak pull-ups 1111 1111 1111 1111 00h INDF Uses contents of FSR to address data memory (not a physical register) XXXX XXXX uuuu uuuUu Oth TMRO 8-bit real-time clock/counter XXXX XXXX uuuu uuuUu o2ht") PCL Low order 8 bits of PC 1111 1111 | 11121 1111 03h STATUS GPWUF | | PAO | TO | PD | Z | DC | C 0001 1Ixxx |q00q quuu"? FSR (12C508/ 04h 12C508A) Indirect data memory address pointer 111x xxxx 111u uuuu FSR (12C509/ 04h 12C509A) Indirect data memory address pointer 110x xxxx Tluu uuuu OSCCAL (12C508/ 05h 120509) CAL3 CAL2 CAL1 CALO = _ 0111 ---- uuuu ---- OSCCAL (12C508A/ 12C509A) 05h CAL5 CAL4 CAL3 CAL2 CAL CALO _ = 1000 00-- yuuu uu-- 06h GPIO = GP5 GP4 GP3 GP2 GP1 GPO -XX XXXX --uu uuuUu Legend: Shaded boxes = unimplemented or unused, = unimplemented, read as '0' (if applicable) x = unknown, u = unchanged, gq = see the tables in Section 7.7 for possible values. Note 1: for an explanation of how to access these bits. The upper byte of the Program Counter is not directly accessible. See Section 4.6 2: Other (non power-up) resets include external reset through MCLR, watchdog timer and wake-up on pin change reset. 3: If reset was due to wake-up on pin change then bit 7 = 1. All other resets will cause bit 7 = 0. 1998 Microchip Technology Inc. DS40139D-page 15PIC12C5XX 4.3 STATUS Register This register contains the arithmetic status of the ALU, the RESET status, and the page preselect bit for program memories larger than 512 words. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as 000u uluu (where u = unchanged). It is recommended, therefore, that only BCF BSF and MOVWF instructions be used to alter the STATUS register because these instructions do not affect the Z, DC or C bits from the STATUS register. For other instructions, which do affect STATUS bits, see Instruction Set Summary. FIGURE 4-4: STATUS REGISTER (ADDRESS:03h) RW-0 RW-0 RW-0 R-+4 R-4 RW-x __ R/W-x [apwuF| [| pao | To | PD pe | ic R = Readable bit bit7 6 5 4 3 1 bito | W = Writable bit bit 7: GPWUF: GPIO reset bit 0 = After power up or other reset bit 6: Unimplemented bit 5: PAO: Program page preselect bits 1 = Page 1 (200h - 3FFh) - PIC12C509(A) Each page is 512 bytes. bit 4: TO: Time-out bit 0 = AWDT time-out occurred bit 3: | PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2: Z: Zero bit 1 = Reset due to wake-up from SLEEP on pin change 0 = Page 0 (000h - 1FFh) - PIC12C508(A) and PIC12C509(A) Using the PAO bit as a general purpose read/write bit in devices which do not use it for program page preselect is not recommended since this may affect upward compatibility with future products. 1 = After power-up, CLRWDT instruction, or SLEEP instruction -n= Value at POR reset bit 1: bit O: 1 =The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero DC: Digit carry/borrow bit (for ADDWF and SUBWF instructions) ADDWF 1 =Acarry from the 4th low order bit of the result occurred 0 =Acarry from the 4th low order bit of the result did not occur SUBWF 1 = A borrow from the 4th low order bit of the result did not occur 0 = A borrow from the 4th low order bit of the result occurred C: Carry/borrow bit (for ADDWF, SUBWF and RRF, RLF instructions) ADDWF SUBWF 1 =Acarry occurred 1 = A borrow did not occur 0 = Acarry did not occur 0 = A borrow occurred RRF or RLF Load bit with LSB or MSB, respectively DS40139D-page 16 1998 Microchip Technology Inc.PIC12C5XX 4.4 OPTION Register Note: [f TRIS bit is set to 0, the wake-up on The OPTION register is a 8-bit wide, write-only change and pull-up functions are disabled register which contains various control bits to for that pin; i.e., note that TRIS overrides configure the Timer0/WDT prescaler and Timer0. OPTION control of GPPU and GPWU. By executing the OPTION instruction, the contents of Note: [f the TOCS bit is set to 1, GP2 8 forced to the W register will be transferred to the OPTION be an input even if TRIS GP2 = 0. register. A RESET sets the OPTION<7:0> bits. FIGURE 4-5: OPTION REGISTER W-1 W-1 W-1 W-1 W-1 W-1 W-1 W-1 | GPwu | GPPU | Tocs | Tose | PSA PS2 PS1 PSO W = Writable bit bit7 6 5 4 3 2 1 bito | U = Unimplemented bit 1 = Disabled 0 = Enabled bit 6: GPPU: Enable weak pull-ups (GPO, GP1, GP3) 1 = Disabled 0 = Enabled bit 5: TOCS: TimerO clock source select bit 1 = Transition on TOCKI pin bit 7: GPWU: Enable wake-up on pin change (GPO, GP1, GP3) bit 4: 0 = Transition on internal instruction cycle clock, Fosc/4 TOSE: TimerO source edge select bit 1 = Increment on high to low transition on the TOCKI pin 0 = Increment on low to high transition on the TOCKI pin bit 3: PSA: Prescaler assignment bit 1 = Prescaler assigned to the WDT 0 = Prescaler assigned to Timer0 bit 2-0: PS2:PS0: Prescaler rate select bits Bit Value TimerO Rate WDT Rate 000 1:2 1:1 001 1:4 1:2 010 1:8 1:4 011 1:16 1:8 100 1:32 1:16 101 1:64 1:32 110 1:128 1:64 111 1: 256 1:128 -n =Value at POR reset Reference Table 4-1 for other resets. 1998 Microchip Technology Inc. DS40139D-page 17PIC12C5XX 45 OSCCAL Register The Oscillator Calibration (OSCCAL) register is used to calibrate the internal 4 MHz oscillator. It contains four to six bits for calibration. Increasing the cal value increases the frequency. See Section 7.2.5 for more information on the internal oscillator. FIGURE 4-6: _OSCCAL REGISTER (ADDRESS 8Fh) RAW-0 RAW-1-RAW-1RYW-1RAW-0RIW-0 U-0 U-0 | cats | care | cart | caco | | fo _ R = Readable bit bit7 bito |W = Writable bit U = Unimplemented bit, read as 0 -n = Value at POR reset bit 7-4: CAL<3:0>: Calibration bit 3-0: Unimplemented: Read as '0' FIGURE 4-7: _OSCCAL REGISTER (ADDRESS 8Fh)PIC12C508A/C509A RAW-1RAW-0-RAW-0-RYW-0RAW-0 RIO U-0 U-0 | cats | cata | cats | cate | cat1 | caco | | | IR =Readable bit bit7 bito |W = Writable bit U = Unimplemented bit, read as 0 -n = Value at POR reset bit 7-2: CAL<5:0>: Calibration bit 1-0: Unimplemented: Read as '0' DS40139D-page 18 1998 Microchip Technology Inc.PIC12C5XX 4.6 Program Counter As a program instruction is executed, the Program Counter (PC) will contain the address of the next program instruction to be executed. The PC value is increased by one every instruction cycle, unless an instruction changes the PC. For a GOTO instruction, bits 8:0 of the PC are provided by the GoTo instruction word. The PC Latch (PCL) is mapped to PC<7:0>. Bit 5 of the STATUS register provides page information to bit 9 of the PC (Figure 4- 8). For a CALL instruction, or any instruction where the PCL is the destination, bits 7:0 of the PC again are provided by the instruction word. However, PC<8> does not come from the instruction word, but is always cleared (Figure 4-8). Instructions where the PCL is the destination, or Modify PCL instructions, include MoVWF PC, ADDWF PC, and BSF PC,5. Note: Because PC<8> is cleared in the CALL instruction, or any Modify PCL instruction, all subroutine calls or computed jumps are limited to the first 256 locations of any pro- gram memory page (512 words long). FIGURE 4-8: LOADING OF PC BRANCH INSTRUCTIONS - PIC12C5XX GOTO Instruction 1110 9 87 0 pct | Tt | PCL A A Instruction Word PAO 7 0 EE TETT EY] STATUS 4.6.1 EFFECTS OF RESET The Program Counter is set upon a RESET, which means that the PC addresses the last location in the last page i.e., the oscillator calibration instruction. After executing MOVLW XxX, the PC will roll over to location 00h, and begin executing user code. The STATUS register page preselect bits are cleared upon a RESET, which means that page 0 is pre- selected. Therefore, upon a RESET, a_ GoTo instruction will automatically cause the program to jump to page 0 until the value of the page bits is altered. 4.7 Stack PIC12C5XX devices have a 12-bit wide L.I.FO. hardware push/pop stack. A CALL instruction will push the current value of stack 1 into stack 2 and then push the current program counter value, incremented by one, into stack level 1. If more than two sequential CALLs are executed, only the most recent two return addresses are stored. A RETLW instruction will pop the contents of stack level 1 into the program counter and then copy stack level 2 contents into level 1. If more than two sequential RETLWs are executed, the stack will be filled with the address previously stored in level 2. Note that the W register will be loaded with the literal value specified in the instruction. This is particularly useful for the implementation of data look-up tables within the program memory. Upon any reset, the contents of the stack remain unchanged, however the program counter (PCL) will also be reset to 0. CALL or Modify PCL Instruction 1110 9 8 7 0 pol | | | | PCL | A if Reset to 0 PAO 7 0 [2S TESS) STATUS Note 1: [here are no STATUS bits to indicate stack overflows or stack underflow condi- tions. Note 2: There are no instructions mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL and RETLW instructions. 1998 Microchip Technology Inc. DS40139D-page 19PIC12C5XX 48 Indirect Data Addressing: INDF and FSR Registers The INDF register is not a physical register. Addressing INDF actually addresses the register whose address is contained in the FSR register (FSR is a pointer). This is indirect addressing. EXAMPLE 4-1: INDIRECT ADDRESSING * Register file 07 contains the value 10h * Register file 08 contains the value OAh * Load the value 07 into the FSR register * A read of the INDF register will return the value of 10h * Increment the value of the FSR register by one (FSR = 08) * A read of the INDR register now will return the value of OAh. Reading INDF itself indirectly (FSR = 0) will produce 00h. Writing to the INDF register indirectly results in a no-operation (although STATUS bits may be affected). A simple program to clear RAM locations 10h-1Fh using indirect addressing is shown in Example 4-2. EXAMPLE 4-2: HOWTO CLEAR RAM USING INDIRECT ADDRESSING moviw 0x10 ; initialize pointer movwt FSR ; to RAM NEXT clrf INDF ; clear INDF register incf FSR,F jinc pointer btfse FSR, 4 ;all done? goto NEXT ;NO, clear next CONTINUE ;YES, continue The FSR is a 5-bit wide register. It is used in conjunction with the INDF register to indirectly address the data memory area. The FSR<4:0> bits are used to select data memory addresses 00h to 1Fh. PIC12C508(A): Does not use banking. FSR<7:5> are unimplemented and read as '1's. PIC12C509(A): Uses FSR<5>. Selects between bank 0 and bank 1. FSR<7:6> is unimplemented, read as 1 Indirect Addressing 6 5 4 (FSR) O location select bank 01 Addr map back to addresses in Bank 0. 3Fh FIGURE 4-9: DIRECT/INDIRECT ADDRESSING Direct Addressing (FSR) 6 5 4 (opcode) 0 bank select _ location select \ | 00 00h Data OFh Memory) 10h 1Fh Bank 0 Note 1: For register map detail see Section 4.2. Note 2: PIC12C509(A) only Bank 1@) DS40139D-page 20 1998 Microchip Technology Inc.PIC12C5XX 5.0 I/O PORT As with any other register, the I/O register can be written and read under program control. However, read instructions (e.g., MOVF _GPIO,W) always read the I/O pins independent of the pins input/output modes. On RESET, all I/O ports are defined as input (inputs are at hi-impedance) since the |/O control registers are all set. 5.1 GPIO GPIO is an 8-bit I/O register. Only the low order 6 bits are used (GP5:GP0). Bits 7 and 6 are unimplemented and read as '0's. Please note that GP3 is an input only pin. The configuration word can set several |/Os to alternate functions. When acting as alternate functions the pins will read as 0 during port read. Pins GPO, GP1, and GP3 can be configured with weak pull-ups and also with wake-up on change. The wake-up on change and weak pull-up functions are not pin selectable. If pin 4 is configured as MCLR, weak pull- up is always on and wake-up on change for this pin is not enabled. 5.2 TRIS Register The output driver control register is loaded with the contents of the W register by executing the TRIS f instruction. A '1' from a TRIS register bit puts the corresponding output driver in a hi-impedance mode. A '0' puts the contents of the output data latch on the selected pins, enabling the output buffer. The exceptions are GP3 which is input only and GP2 which may be controlled by the option register, see Figure 4- 5. Note: _ A read of the ports reads the pins, not the output data latches. That is, if an output driver on a pin is enabled and driven high, but the external system Is holding it low, a read of the port will indicate that the pin is low. The TRIS registers are write-only and are set (output drivers disabled) upon RESET. 5.3 I/O Interfacing The equivalent circuit for an I/O port pin is shown in Figure 5-1. All port pins, except GP3 which is input only, may be used for both input and output operations. For input operations these ports are non- latching. Any input must be present until read by an input instruction (e.g., MOVF GPIO,W). The outputs are latched and remain unchanged until the output latch is rewritten. To use a port pin as output, the corresponding direction control bit in TRIS must be cleared (= 0). For use as an input, the corresponding TRIS bit must be set. Any I/O pin (except GP3) can be programmed individually as input or output. FIGURE 5-1: EQUIVALENT CIRCUIT FOR A SINGLE I/O PIN Data Bus D Q Data WR Latch oD ort x yee ppt Ww OH N ie) Reg D Q pin TRIS o Latch Vss TRIS f cK GLE Reset | (2) RD Port Note 1: I/O pins have protection diodes to VDD and Vss. 2: See Table 3-1 for buffer type. TABLE 5-1: SUMMARY OF PORT REGISTERS Value on Power-On Value on Address Name Bit 7 Bit 6 Bit 5 Bit4 | Bit3 | Bit2 | Bit1| Bito Reset All Other Resets N/A TRIS I/O control registers --11 1111 --11 1111 N/A OPTION | GPWU | GPPU] TOCS | TOSE | PSA |} PS2 } PS1 | PSO 1111 1111 1111 1111 03H STATUS | GPWUF _ PAO TO PD Z DG C 0001 1xxx qo0g gquuu! 06h GPIO GP5 GP4 GP3 | GP2 | GP1 | GPO --xxX XXxXX --uu uuuu Legend: Shaded cells not used by Port Registers, read as 0, = unimplemented, read as '0', x = unknown, u = unchanged, q = see tables in Section 7.7 for possible values. Note 1: If reset was due to wake-up on change, then bit 7 = 1. All other resets will cause bit 7 = 0. 1998 Microchip Technology Inc. DS40139D-page 21PIC12C5XX 5.4 1/O Programming Considerations 5.4.1 BI-DIRECTIONAL I/O PORTS Some instructions operate internally as read followed by write operations. The BCF and BSF instructions, for example, read the entire port into the CPU, execute the bit operation and re-write the result. Caution must be used when these instructions are applied to a port where one or more pins are used as input/outputs. For example, a BSF operation on bit5 of GPIO will cause all eight bits of GPIO to be read into the CPU, bit5 to be set and the GPIO value to be written to the output latches. If another bit of GPIO is used as a bi- directional I/O pin (say bit0) and it is defined as an input at this time, the input signal present on the pin itself would be read into the CPU and rewritten to the data latch of this particular pin, overwriting the previous content. As long as the pin stays in the input mode, no problem occurs. However, if bitO is switched into output mode later on, the content of the data latch may now be unknown. Example 5-1 shows the effect of two sequential read- modify-write instructions (.g., BCF, BSF, etc.) onan I/ O port. A pin actively outputting a high or a low should not be driven from external devices at the same time in order to change the level on this pin (wired-or, wired-and). The resulting high output currents may damage the chip. FIGURE 5-2: SUCCESSIVE I/O OPERATION EXAMPLE 5-1: READ-MODIFY-WRITE INSTRUCTIONS ON AN 1/0 PORT ; Initial GPIO Settings ; GPIO<5:3> Inputs ; GPIO<2:0> Outputs GPIO latch GPIO pins ' ' ' ' ' BCF GPIO, 5 ;--01 -ppp --11 pppp BCF GPIo, 4 ;--10 -ppp --11 pppp MOVLW 007h ; TRIS GPIO ;--10 -ppp --11 pppp ;Note that the user may have expected the pin jvalues to be --00 pppp. The 2nd BCF caused ;GP5 to be latched as the pin value (High). 5.4.2 SUCCESSIVE OPERATIONS ON I/O PORTS The actual write to an I/O port happens at the end of an instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle (Figure 5-2). Therefore, care must be exercised if a write followed by a read operation is carried out on the same I/O port. The sequence of instructions should allow the pin voltage to stabilize (load dependent) before the next instruction, which causes that file to be read into the CPU, is executed. Otherwise, the previous state of that pin may be read into the CPU rather than the new state. When in doubt, it is better to separate these instructions with a NoP or another instruction not accessing this I/O port. " Qt] G2] Q3] Q4* Qt] G2] Q3] Q4* Q1] Q2] Q3] Q4* Qt] Q2] _Q3] 4" _ PC K PC +1 X 1 PC+2 x PC+3 ' This example shows a write to GPIO followed ns goned ' ' oy ' , by aread from GPIO. ' MOVWF GPIO | MOVF GPIO,W Ss! 1 NOP ' NOP ' : ; ; my Data setup time = (0.25 Tcy TPD) GP5:GP0' ; vo ; ; where: TCY = instruction cycle. ' 1 st 1 1 TPD = propagation delay i i . i + ! 1 . : 1 ' Port pin 1 Port pin 1 1 Therefore, at higher clock frequencies, a ' ' written here | sampled here: ' write followed by a read may be problematic. Instruction ! ! ' ' ' executed | 1 MOVWF GPIO. 1 MOVFGPIO.W 1 NOP ' ' ' (Write to ' (Read ' ' ' ' GPIO) ' GPIO) ' ' DS40139D-page 22 1998 Microchip Technology Inc.PIC12C5XX 6.0 TIMERO MODULE AND TMRO REGISTER The TimerO module has the following features: * 8-bit timer/counter register, TMRO - Readable and writable * 8-bit software programmable prescaler * Internal or external clock select - Edge select for external clock Figure 6-1 is a simplified block diagram of the TimerO module. Timer mode is selected by clearing the TOCS bit (OPTION<5=>). In timer mode, the TimerO module will increment every instruction cycle (without prescaler). If TMRO register is written, the increment is inhibited for the following two instruction cycles (Figure 6-2 and Figure 6-3). The user can work around this by writing an adjusted value to the TMRO register. FIGURE 6-1: TIMERO BLOCK DIAGRAM Counter mode is selected by setting the TOCS bit (OPTION<5>). In this mode, TimerO will increment either on every rising or falling edge of pin TOCKI. The TOSE bit (OPTION<4>) determines the source edge. Clearing the TOSE bit selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 6.1. The prescaler may be used by either the TimerO module or the Watchdog Timer, but not both. The prescaler assignment is controlled in software by the control bit PSA (OPTION<3>). Clearing the PSA bit will assign the prescaler to Timer0. The prescaler is not readable or writable. When the prescaler is assigned to the Timer0 module, prescale values of 1:2, 1:4,..., 1:256 are selectable. Section 6.2 details the operation of the prescaler. A summary of registers associated with the TimerO module is found in Table 6-1. Tocs GP2/TOCKI Fosc/4 0 Pin x} Programmable Prescaler TOSE i 3 Ps2, PS1, PSOM Note 1: Bits TOCS, TOSE, PSA, PS2, PS1 and PSO are located in the OPTION register. 2: The prescaler is shared with the Watchdog Timer (Figure 6-5). Data bus PSout 8 Syne with -___ Internal TMRO reg Clocks PSout (2Tcy delay) Syne PSA) 1998 Microchip Technology Inc. DS40139D-page 23PIC12C5XX FIGURE 6-2: TIMERO TIMING: INTERNAL CLOCK/NO PRESCALE PC (Program Counter) Instruction Fetch TimerO Instruction Executed ,ai]a2|a3] a4; at] a2]a3|a4jat|az|as3] a4 jat| a2] a3] a4,ai1|a2|a3|a4 jat| a2] a3] a4)a1|a2z]a3]a4jai|az|a3|a4} I I ( PO-1 PG X Port PCr? PC+3 Xx PCH, PC+5 _Y Pox) I I I I I I I I I ' ' MOVWETMRO ' MOVF TMRO,W ' MOVF TMRO,W ' MOVF TMRO,W 'MOVF TMRO,W ' MOVF TMRO,W ! ' __10 XY Tort X41 TOre _ __NTO 1 ~___ NTT __X_, NiO? XK : : | WriteTMRO | ReadTMRO ! ReadTMRO ! ReadTMRO | ReadTMRO | ReadTMRO | executed reads NTO reads NTO reads NTO reads NTO +1 reads NTO + 2 FIGURE 6-3: TIMERO TIMING: INTERNAL CLOCK/PRESCALE 1:2 PC ,a1|Q2| a3] a4; a1] a2] a3] a4 }a1|a2]a3] a4 ;a1| a2] a3] a4;a1] a2] a3] a4 |a1| a2] a3] a4) .a1| a2] a3] a4 }a1]a2]a3] a4 | (Program 1 1 1 1 1 1 1 1 ' Counter) ( PCO-t PC x PC+ Y Pov PC+3 YX PCa PCS YX PC+6*Y Instruction ' ' MOVWF TMRO ' MOVF TMRO,W ' MOVF TMRO,W ' MOVE TMRO,W 'MOVFTMRO,W ' MOVF TMROW ! ' Fetch Timer0 10 YI Tot Xo F NTO F YX NTO YX Instruction ' ' ' f ' f : t : t ; t ; t ; Execute | WriteTMRO ! ReadTMRO | ReadTMRO ! ReadTMRO | ReadTMRO ! ReadTMRO ! executed reads NTO reads NTO reads NTO reads NTO reads NTO + 1 TABLE 6-1: REGISTERS ASSOCIATED WITH TIMERO Value on Value on Power-On All Other Address Name Bit 7 Bit 6 Bit5 | Bit4 | Bit3 | Bit2 | Bit1 | Bito Reset Resets Oih TMRO TimerO - 8-bit real-time clock/counter XXXX XXXX | UUUU UUUU N/A OPTION | GPWU | GPPU | TOCS | TOSE | PSA |} PS2 | PS1 |} PSO } 1111 1111 } 1111 1111 N/A TRIS _ _ GP5 | GP4 | GP3 | GP2 | GP1 | GRO | --11 1111 }] --11 1111 Legend: Shaded cells not used by Timer, - = unimplemented, x = unknown, u = unchanged, DS40139D-page 24 1998 Microchip Technology Inc.PIC12C5XX 6.1 Using Timer0 with an External Clock When an external clock input is used for Timer0, it must meet certain requirements. The external clock requirement is due to internal phase clock (Tosc) synchronization. Also, there is a delay in the actual incrementing of TimerO after synchronization. 6.1.1 EXTERNAL CLOCK SYNCHRONIZATION When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of TOCKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks (Figure 6-4). Therefore, it is necessary for TOCKI to be high for at least 2Tosc (and a small RC delay of 20 ns) and low for at least 2Tosc (and a small RC delay of 20 ns). Refer to the electrical specification of the desired device. When a prescaler is used, the external clock input is divided by the asynchronous ripple counter-type prescaler so that the prescaler output is symmetrical. For the external clock to meet the sampling requirement, the ripple counter must be taken into account. Therefore, it is necessary for TOCKI to have a period of at least 4Tosc (and a small RC delay of 40 ns) divided by the prescaler value. The only requirement on TOCKI high and low time is that they do not violate the minimum pulse width requirement of 10 ns. Refer to parameters 40, 41 and 42 in the electrical specification of the desired device. 6.1.2 TIMERO INCREMENT DELAY Since the prescaler output is synchronized with the internal clocks, there is a small delay from the time the external clock edge occurs to the time the TimerO module is actually incremented. Figure 6-4 shows the delay from the external clock edge to the timer incrementing. 6.1.3. OPTION REGISTER EFFECT ON GP2 TRIS If the option register is set to read TIMERO from the pin, the port is forced to an input regardless of the TRIS reg- ister setting. FIGURE 6-4: | TIMERO TIMING WITH EXTERNAL CLOCK Q1l Q21 Q3] Q4 External Clock Input or Prescaler Output (2) Output After Sampling Increment TimerO (Q4) Qi] Q2I Q3l Q4 \ 1 External Clock/Prescaler 4) f a, Q1l Q21 Q3] Q4 | Q11 Q2I Q31 Q4 Small pulse J \umisses sampling i 4 r TimerO X TO +1 X TO +2 Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc). Therefore, the error in measuring the interval between two edges on Timer0 input = + 4Tosc max. 2: External clock if no prescaler selected, Prescaler output otherwise. 3: The arrows indicate the points in time where sampling occurs. 1998 Microchip Technology Inc. DS40139D-page 25PIC12C5XX 6.2 Prescaler An 8-bit counter is available as a prescaler for the TimerO0 module, or as a postscaler for the Watchdog Timer (WDT), respectively (Section 7.6). For simplicity, this counter is being referred to as prescaler throughout this data sheet. Note that the prescaler may be used by either the TimerO module or the WDT, but not both. Thus, a prescaler assignment for the TimerO module means that there is no prescaler for the WDT, and vice-versa. The PSA and PS2:PSO bits (OPTION<3:0>) determine prescaler assignment and prescale ratio. When assigned to the Timer0 module, all instructions writing to the TMRO register (e.g., CLRF 1, MOVWF 1, BSF 1,x, etc.) will clear the prescaler. When assigned to WDT, a CLRWDT instruction will clear the prescaler along with the WDT. The prescaler is neither readable nor writable. On a RESET, the prescaler contains all O's. 6.2.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control (i.e., it can be changed on the fly during program execution). To avoid an unintended device RESET, the following instruction sequence (Example 6-1) must be executed when changing the prescaler assignment from Timer0 to the WDT. FIGURE 6-5: EXAMPLE 6-1: CHANGING PRESCALER (TIMERO>WDT) 1,CLRWDT ;Clear WDT 2.CLRF TMRO ;Clear TMRO & Prescaler 3.MOVLW '00xx1111b ;These 3 lines (5, 6, 7) 4, OPTION ; are required only if ; desired 5.CLRWDT ;PS<2:0> are 000 or OO1 6.MOVLW 'OOxxilxxxb ;Set Postscaler to 7.OPTION ; desired WDT rate To change prescaler from the WDT to the TimerO module, use the sequence shown in Example 6-2. This sequence must be used even if the WDT is disabled. A CLRWDT instruction should be executed before switching the prescaler. EXAMPLE 6-2: CHANGING PRESCALER (WDT>TIMERO) CLRWDT ;Clear WDT and ;prescaler ;Select TMRO, new ;prescale value and MOVLW "xxxxOxxx' ,;clock source OPTION BLOCK DIAGRAM OF THE TIMERO/WDT PRESCALER Tcy ( = Fose/4) Data Bus y 8 M Sync U > 2 =) TMRO reg x Cycles oat 8-bit Prescaler 8 - to - 1MUX ha PS2:PSO 0 GP2/TOCKI M Pin U Ray TOSE Tocs 0 M U 4| X Watchdog 8 Timer PSA . 0 WDT Enable bit MUX #- PSA WDT Time-Out Note: TOCS, TOSE, PSA, PS2:PS0 are bits in the OPTION register. DS40139D-page 26 1998 Microchip Technology Inc.PIC12C5XX 7.0 SPECIAL FEATURES OF THE CPU What sets a microcontroller apart from other processors are special circuits to deal with the needs of real-time applications. The PIC12C5XX family of microcontrollers has a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection. These features are: * Oscillator selection + Reset - Power-On Reset (POR) - Device Reset Timer (DRT) - Wake-up from SLEEP on pin change * Watchdog Timer (WDT) * SLEEP * Code protection * ID locations * In-circuit Serial Programming FIGURE 7-1: The PIC12C5XX has a Watchdog Timer which can be shut off only through configuration bit WDTE. It runs off of its own RC oscillator for added reliability. If using XT or LP selectable oscillator options, there is always an 18 ms (nominal) delay provided by the Device Reset Timer (DRT), intended to keep the chip in reset until the crystal oscillator is stable. If using INTRC or EXTRC there is an 18 ms delay only on VDD power-up. With this timer on-chip, most applications need no external reset circuitry. The SLEEP mode is designed to offer a very low current power-down mode. The user can wake-up from SLEEP through a change on input pins or through a Watchdog Timer time-out. Several oscillator options are also made available to allow the part to fit the application, including an internal 4 MHz oscillator. The EXTRC oscillator option saves system cost while the LP crystal option saves power. A set of configuration bits are used to select various options. 7.1 Configuration Bits The PIC12C5XX configuration word consists of 12 bits. Configuration bits can be programmed to select various device configurations. Two bits are for the selection of the oscillator type, one bit is the Watchdog Timer enable bit, and one bit is the MCLR enable bit. CONFIGURATION WORD FOR PIC12C5XX CONFIG f | | | | | | |mccre] cp [wote|rosci|Fosco| Register: bit1 1 bit 11-5: bit 4: bit 3: bit 2: bit 1-0: Note 1: 10 9 8 7 6 5 4 3 2 1 bitd. | Address): = FFFh Unimplemented MCLRE: MCLR enable bit. 1 = MCLR pin enabled 0 = MCLR tied to VDD, (Internally) CP: Code protection bit. 1 = Code protection off 0 = Code protection on WDTE: Watchdog timer enable bit 1 =WDT enabled 0 =WDT disabled FOSC1:FOSCO: Oscillator selection bits 11 = EXTRC - external RC oscillator 10 = INTRC - internal RC oscillator 01 = XT oscillator 00 = LP oscillator Refer to the PIC12C5XX Programming Specifications to determine how to access the configuration word. This register is not user addressable during device operation. 1998 Microchip Technology Inc. DS40139D-page 27PIC12C5XX 7.2 Oscillator Configurations 7.2.14 OSCILLATOR TYPES The PIC12C5XX can be operated in four different oscillator modes. The user can program two configuration bits (FOSC1:FOSCO0) to select one of these four modes: * LP: Low Power Crystal * XT: Crystal/Resonator * INTRC: Internal 4 MHz Oscillator * EXTRC: External Resistor/Capacitor 7.2.2 CRYSTAL OSCILLATOR / CERAMIC RESONATORS In XT or LP modes, a crystal or ceramic resonator is connected to the GP5/OSC1/CLKIN and GP4/OSC2 pins to establish oscillation (Figure 7-2). The PIC12C5XX oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturers specifications. When in XT or LP modes, the device can have an external clock source drive the GP5/ OSC1/CLKIN pin (Figure 7-3). FIGURE 7-2: CRYSTAL OPERATION (OR CERAMIC RESONATOR) (XT OR LP OSC CONFIGURATION) TABLE 7-1: CAPACITOR SELECTION FOR CERAMIC RESONATORS - PIC12C5XX Osc _ | Resonator | Cap. Range | Cap. Range Type Freq C1 C2 XT 4.0 MHz 30 pF 30 pF These values are for design guidance only. Since each resonator has its own characteristics, the user should consult the resonator manufacturer for appropriate values of external components. TABLE 7-2: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR - PIC12C5XX Osc | Resonator | Cap.Range | Cap. Range Type Freq C1 C2 LP 32 kHz 15 pF 15 pF XT 200 kHz 47-68 pF 47-68 pF 1 MHz 15 pF 15 pF 4 MHz 15 pF 15 pF ci) | . ai C0 XTAL < REG) Osc PIC12C5XX SLEEP ' To internal = logic as@) Osc2 > ce) See Capacitor Selection tables for recommended values of C1 and C2. 2: Aseries resistor (RS) may be required for AT strip cut crystals. 3: RF approximate value = 10 MQ. Note 1: FIGURE 7-3: EXTERNAL CLOCK INPUT OPERATION (XT OR LP OSC CONFIGURATION) Clock from > Osci ext. system PIC12C5XX Open -_J OSC2 Note 1: For VbD > 4.5V, C1 = C2 = 30 pF is recommended. These values are for design guidance only. Rs may be required to avoid overdriving crystals with low drive level specification. Since each crystal has its own characteristics, the user should consult the crys- tal manufacturer for appropriate values of external components. DS40139D-page 28 1998 Microchip Technology Inc.PIC12C5XX 7.2.3 EXTERNAL CRYSTAL OSCILLATOR CIRCUIT Either a prepackaged oscillator or a simple oscillator circuit with TTL gates can be used as an external crystal oscillator circuit. Prepackaged oscillators provide a wide operating range and better stability. A well-designed crystal oscillator will provide good performance with TTL gates. Two types of crystal oscillator circuits can be used: one with parallel resonance, or one with series resonance. Figure 7-4 shows implementation of a parallel resonant oscillator circuit. The circuit is designed to use the fundamental frequency of the crystal. The 74AS04 inverter performs the 180-degree phase shift that a parallel oscillator requires. The 4.7 kQ resistor provides the negative feedback for stability. The 10 kQ potentiometers bias the 74AS04 in the linear region. This circuit could be used for external oscillator designs. FIGURE 7-4: EXTERNAL PARALLEL RESONANT CRYSTAL OSCILLATOR CIRCUIT +5V To Other Devices 10k 4.7k 74AS04 PIC12C5XX 74AS04 CLKIN q > , 10k XTAL +0 10k 1 ete 20 pF L 20 pF Figure 7-5 shows a series resonant oscillator circuit. This circuit is also designed to use the fundamental frequency of the crystal. The inverter performs a 180- degree phase shift in a series resonant oscillator circuit. The 330Q resistors provide the negative feedback to bias the inverters in their linear region. FIGURE 7-5: EXTERNAL SERIES 7.2.4 EXTERNAL RC OSCILLATOR For timing insensitive applications, the RC device option offers additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (Rext) and capacitor (Cext) values, and the operating temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal process parameter variation. Furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low Cext values. The user also needs to take into account variation due to tolerance of external R and C components used. Figure 7-6 shows how the R/C combination is connected to the PIC12C5XxX. For Rext values below 2.2 kQ, the oscillator operation may become unstable, or stop completely. For very high Rext values (e.g., 1 MQ) the oscillator becomes sensitive to noise, humidity and leakage. Thus, we recommend keeping Rext between 3 kQ and 100 kQ Although the oscillator will operate with no external capacitor (Cext = 0 pF), we recommend using values above 20 pF for noise and stability reasons. With no or small external capacitance, the oscillation frequency can vary dramatically due to changes in external capacitances, such as PCB trace capacitance or package lead frame capacitance. The Electrical Specifications sections show RC frequency variation from part to part due to normal process variation. The variation is larger for larger R (since leakage current variation will affect RC frequency more for large R) and for smaller C (since variation of input capacitance will affect RC frequency more). Also, see the Electrical Specifications sections for variation of oscillator frequency due to VppD for given Rext/Cext values as well as frequency variation due to operating temperature for given R, C, and VDD values. FIGURE 7-6: EXTERNAL RC OSCILLATOR RESONANT CRYSTAL OSCILLATOR CIRCUIT To Other 330 330 Devices PIC12C5XX 74AS04 74A804 74AS04 CLKIN 0.1 WF XTAL Uj} MODE VDD Rext Internal OSC1 clock >_- N Cext T PIC12C5XX Vss = = 1998 Microchip Technology Inc. DS40139D-page 29PIC12C5XX 7.2.5 INTERNAL 4 MHz RC OSCILLATOR The internal RC oscillator provides a fixed 4 MHz (nom- inal) system clock at VDD = 5V and 25C, see Electri- cal Specifications section for information on variation over voltage and temperature.. In addition, a calibration instruction is programmed into the top of memory which contains the calibration value for the internal RC oscillator. This location is never code protected regardless of the code protect settings. This value is programmed as a MOVLW Xx instruction where XX is the calibration value, and is placed at the reset vector. This will load the W register with the calibration value upon reset and the PC will then roll over to the users program at address 0x000. The user then has the option of writing the value to the OSCCAL Register (05h) or ignoring it. OSCCAL, when written to with the calibration value, will trim the internal oscillator to remove process variation from the oscillator frequency. . Note: Please note that erasing the device will also erase the pre-programmed internal calibration value for the internal oscillator. The calibration value must be read prior to erasing the part. so it can be repro- grammed correctly later. For the PIC12C508A and PIC12C509A, bits <7:2>, CAL5-CALO are used for calibration. Adjusting CAL5- 0 from 000000 to 111111 yields a higher clock speed. Note that bits 1 and 0 of OSCCAL are unimplemented and should be written as 0 when modifying OSCCAL for compatibility with future devices. For the PIC12C508 and PIC12C509, the lower 4 bits of the register are used. Writing a larger value in this loca- tion yields a higher clock speed. 7.3 RESET The device differentiates between various kinds of reset: a) Power on reset (POR) b) MCLR reset during normal operation c) MCLR reset during SLEEP d) WDT time-out reset during normal operation e) WDT time-out reset during SLEEP ) ) ) ) f) Wake-up from SLEEP on pin change Some registers are not reset in any way; they are unknown on POR and unchanged in any other reset. Most other registers are reset to reset state on power- on reset (POR), MCLR, WDT or wake-up on pin change reset during normal operation. They are not affected by a WDT reset during SLEEP or MCLR reset during SLEEP, since these resets are viewed as resumption of normal operation. The exceptions to this are TO, PD, and GPWUF bits. They are set or cleared differently in different reset situations. These bits are used in software to determine the nature of reset. See Table 7-3 for a full description of reset states of all registers. DS40139D-page 30 1998 Microchip Technology Inc.PIC12C5XX TABLE 7-3: RESET CONDITIONS FOR REGISTERS MCLR Reset Register Address Power-on Reset WDT time-out Wake-up on Pin Change W (PIC12C508/509) qggq xxxx gagq uuu (1) W (PIC12C508A/509A) _ ggaq gaxx () gaaq qquu ) INDF 00h XXXX XXXK uuuu uuUU TMRO Oth XXXX XXXK uuuu uuUU PC 02h 1111 1111 1111 1111 STATUS 03h 0001 1xxx q00q quuu (2/3) FSR (12C508/12C508A) 04h 111x xxxx 111u uuuu FSR (12C509/12C509A) 04h 110x xxxx 1luu uuuu OSCCAL(12C508/509) 05h 0111 ---- uuuu ---- OSCCAL(12C508A/509A) 05h 1000 00-- uuuu uu-- GPIO 06h --XX XMM --uu uuuu OPTION _ 1111 1111 1111 1111 TRIS _ --11 1111 --11 1111 Legend: u = unchanged, x = unknown, - = unimplemented bit, read as 0, q = value depends on condition. Note 1: Bits <7:2> of W register contain oscillator calibration values due to MOVLW Xx instruction at top of memory. Note 2: See Table 7-7 for reset value for specific conditions Note 3: If reset was due to wake-up on pin change, then bit 7 = 1. All other resets will cause bit 7 = 0. TABLE 7-4: RESET CONDITION FOR SPECIAL REGISTERS STATUS Addr: 03h PCL Addr: 02h Power on reset 0001 1xxx 1111 1111 MCLR reset during normal operation o00u uuuu 1111 1111 MCLR reset during SLEEP 0001 OCuuu 1111 1111 WDT reset during SLEEP 0000 Ouuu 1111 1111 WDT reset normal operation 0000 uuuu 1111 1111 Wake-up from SLEEP on pin change 1001 Ouuu 1111 1111 Legend: u = unchanged, x = unknown, - = unimplemented bit, read as 0. 1998 Microchip Technology Inc. DS40139D-page 31PIC12C5XX 7.3.4 MCLR ENABLE This configuration bit when unprogrammed (left in the 1 state) enables the external MCLR function. When programmed, the MCLR function is tied to the internal VDD, and the pin is assigned to be a GPIO. See Figure 7-7. When pin GP3/MCLR/VPr is configured as MCLR, the internal pull-up is always on. FIGURE 7-7: MCLR SELECT MCLRE WEAK 10 pulitup L ) INTERNAL MCLR GP3/MCLR/VPP 7.4 Power-On Reset (POR) The PIC12C5XX family incorporates on-chip Power- On Reset (POR) circuitry which provides an internal chip reset for most power-up situations. The on-chip POR circuit holds the chip in reset until VbpD has reached a high enough level for proper opera- tion. To take advantage of the internal POR, program the GP3/MCLR/VpPp pin as MCLR and tie thru a _resis- tor to VDD or program the pin as GP3. An internal weak pull-up resistor is implemented using a transistor. Refer to Table 10-1 for the pull-up resistor ranges. This will eliminate external RC components usually needed to create a Power-on Reset. A maximum rise time for VDD is specified. See Electrical Specifications for details. When the device starts normal operation (exits the reset condition), device operating parameters (voltage, frequency, temperature, ...) must be met to ensure operation. If these conditions are not met, the device must be held in reset until the operating parameters are met. A simplified block diagram of the on-chip Power-On Reset circuit is shown in Figure 7-8. The Power-On Reset circuit and the Device Reset Timer (Section 7.5) circuit are closely related. On power-up, the reset latch is set and the DRT is reset. The DRT timer begins counting once it detects MCLR to be high. After the time-out period, which is typically 18 ms, it will reset the reset latch and thus end the on- chip reset signal. A power-up example where MCLR is held low is shown in Figure 7-9. VDD is allowed to rise and stabilize before bringing MCLR high. The chip will actually come out of reset TDRT msec after MCLR goes high. In Figure 7-10, the on-chip Power-On Reset feature is being used (MCLR and Vpp are tied together or the pin is programmed to be GP3.). The Vopp is stable before the start-up timer times out and there is no problem in getting a proper reset. However, Figure 7- 11 depicts a problem situation where VDD rises too slowly. The time between when the DRT senses that MCLR is high and when MCLR (and VbbD) actually reach their full value, is too long. In this situation, when the start-up timer times out, VoD has not reached the Vpp (min) value and the chip is, therefore, not guaranteed to function correctly. For such situations, we recommend that external RC circuits be used to achieve longer POR delay times (Figure 7-10). Note: When the device starts normal operation (exits the reset condition), device operat- ing parameters (voltage, frequency, tem- perature, etc.) must be meet to ensure operation. If these conditions are not met, the device must be held in reset until the operating conditions are met. For additional information refer to Application Notes Power-Up Considerations - AN522 and Power-up Trouble Shooting - AN607. DS40139D-page 32 1998 Microchip Technology Inc.PIC12C5XX FIGURE 7-8: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT Power-Up Detect ; Vop POR (Power-On Reset) Pin Change Wake-up on pin change SLEEP GP3/MCLR/VPP WDT Time-out MCLRE RESET 8-bit Asynch s Q On-Chip | EH Ripple Counter DRT OSC (Start-Up Timer) _ R Q -_ CHIP RESET FIGURE 7-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR PULLED LOW) MCLR VppD fF DRT TIME-OUT INTERNAL POR | INTERNAL RESET FIGURE 7-10: TIME-OUT SEQUENCE ON POWER-UP (MCLRTIED TO Vpp): FAST Vpp RISE TIME VDD INTERNAL POR DRT TIME-OUT INTERNAL RESET | ' TDAT + 1998 Microchip Technology Inc. DS40139D-page 33PIC12C5XX FIGURE 7-11: TIME-OUT SEQUENCE ON POWER-UP (MCLRTIED TO Vpp): SLOW Vpp RISE TIME VppD ' INTERNAL POR | ' DRT TIME-OUT INTERNAL RESET When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final value. In this example, the chip will reset properly if, and only if, V1 = Vbb min. 7.5 Device Reset Timer (DRT) In the PIC12C5XX, DRT runs from RESET and varies based on oscillator selection (see Table 7-5.) The DRT operates on an internal RC oscillator. The processor is kept in RESET as long as the DRT is active. The DRT delay allows VDD to rise above VDD min., and for the oscillator to stabilize. Oscillator circuits based on crystals or ceramic resonators require a certain time after power-up to establish a stable oscillation. The on-chip DRT keeps the device in a RESET condition for approximately 18 ms after MCLR has reached a logic high (VIHMCLR) level. Thus, programming GP3/MCLR/Vpp as MCLR and using an external RC network connected to the MCLR input is not required in most cases, allowing for savings in cost-sensitive and/or space restricted applications, as well as allowing the use of the GP3/ MCLR/VPP pin as a general purpose input. The Device Reset time delay will vary from chip to chip due to VDD, temperature, and process variation. See AC parameters for details. The DRT will also be triggered upon a Watchdog Timer time-out. This is particularly important for applications using the WDT to wake from SLEEP mode automatically. 7.6 Watchdog Timer (WDT) The Watchdog Timer (WDT) is a free running on-chip RC oscillator which does not require any external components. This RC oscillator is separate from the external RC oscillator of the GP5/OSC1/CLKIN pin and the internal 4 MHz oscillator. That means that the WDT will run even if the main processor clock has been stopped, for example, by execution of a SLEEP instruction. During normal operation or SLEEP, a WDT reset or wake-up reset generates a device RESET. The TO bit (STATUS<4>) will be cleared upon a Watchdog Timer reset. The WDT can be permanently disabled by programming the configuration bit WDTE as a 0 (Section 7.1). Refer to the PIC12C5XX Programming Specifications to determine how to access the configuration word. TABLE 7-5: DRT (DEVICE RESET TIMER PERIOD) Oscillator Subsequent Configuration POR Reset Resets IntRC & 18 ms (typical) | 300 ps (typical) ExtRC XT & LP 18 ms (typical) | 18 ms (typical) DS40139D-page 34 1998 Microchip Technology Inc.PIC12C5XX 7.6.14 WDT PERIOD The WDT has a nominal time-out period of 18 ms, (with no prescaler). If a longer time-out period is desired, a prescaler with a division ratio of up to 1:128 can be assigned to the WDT (under software control) by writing to the OPTION register. Thus, a time-out period of a nominal 2.3 seconds can be realized. These periods vary with temperature, VDD and part-to- part process variations (see DC specs). Under worst case conditions (VDD = Min., Temperature = Max., max. WDT prescaler), it may take several seconds before a WDT time-out occurs. 7.6.2 WDT PROGRAMMING CONSIDERATIONS The CLRWDT instruction clears the WDT and the postscaler, if assigned to the WDT, and prevents it from timing out and generating a device RESET. The SLEEP instruction resets the WDT and the postscaler, if assigned to the WDT. This gives the maximum SLEEP time before a WDT wake-up reset. FIGURE 7-12: WATCHDOG TIMER BLOCK DIAGRAM From TimerO Clock Source (Figure 6-5) Lo 7 M Watchdog 1 y Timer X WDT Enable PSA Configuration Bit Note: TOCS, TOSE, PSA, PS2:PS0 are bits in the OPTION register. Postscaler 8-to-1MUX HL PS2:PSO To TimerO (Figure 6-4) MUX }.__ PSA WDT Time-out TABLE 7-6: SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER Value on Value on Power-On All Other Bit3 | Bit2 | Bit1 | Bito Reset Resets Address Name Bit 7 Bit 6 Bit 5 Bit 4 N/A OPTION GPWU | GPPU | TOCS | TOSE | PSA | PS2 PS1 PSO | 1111 1111 1111 1111 Legend: Shaded boxes = Not used by Watchdog Timer, = unimplemented, read as '0', u = unchanged 1998 Microchip Technology Inc. DS40139D-page 35PIC12C5XX 7.7 Time-Out Sequence, Power Down, and Wake-up from SLEEP Status Bits (TO/PD/GPWUF) The TO, PD, and GPWUF bits in the STATUS register can be tested to determine if a RESET condition has been caused by a power-up condition, a MCLR or Watchdog Timer (WDT) reset. TABLE 7-7: TO/PD/GPWUF STATUS AFTER RESET GPWUF| TO | PD RESET caused by 0 0 0 |WODT wake-up from SLEEP 0 0 u_ | WDT time-out (not from SLEEP) 0 1 0 |MCLR wake-up from SLEEP 0 1 1 | Power-up 7.8 Reset on Brown-Out A brown-out is a condition where device power (VDD) dips below its minimum value, but not to zero, and then recovers. The device should be reset in the event of a brown-out. To reset PIC12C5XX devices when a_ brown-out occurs, external brown-out protection circuits may be built, as shown in Figure 7-13 and Figure 7-14. FIGURE 7-13: BROWN-OUT PROTECTION u u_ |MCLR not during SLEEP 1 O | Wake-up from SLEEP on pin change Legend: Legend: u = unchanged Note 1: The TO, PD, and GPWUF bits main- tain their status (u) until a reset occurs. A low-pulse on the MCLR input does not change the TO, PD, and GPWUF status bits. CIRCUIT 1 VDD me i VDD 10k al MCLR Z\ 40k" | pic1205xx This circuit will activate reset when VDD goes below Vz + 0.7V (where Vz = Zener voltage). *Refer to Figure 7-7 and Table 10-1 for internal weak pull- up on MCLR. FIGURE 7-14: BROWN-OUT PROTECTION CIRCUIT 2 VppD VppD R1 $ Q1 MCLR R2 * 40k PIC12C5XX This brown-out circuit is less expensive, although less accurate. Transistor Q1 turns off when VDD is below a certain level such that: VDD. _ Rt =0.7V Ri +R2 *Refer to Figure 7-7 and Table 10-1 for internal weak pull-up on MCLR. DS40139D-page 36 1998 Microchip Technology Inc.PIC12C5XX 7.9 Power-Down Mode (SLEEP) A device may be powered down (SLEEP) and later powered up (Wake-up from SLEEP). 7.9.14 SLEEP The Power-Down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the TO bit (STATUS<4>) is set, the PD bit (STATUS<3>) is cleared and the oscillator driver is turned off. The I/O ports maintain the status they had before the SLEEP instruction was executed (driving high, driving low, or hi-impedance). It should be noted that a RESET generated by a WDT time-out does not drive the MCLR pin low. For lowest current consumption while powered down, the TOCKI input should be at VDD or Vss and the GP3/ MCLR/VPP pin must be at a logic high level (VIHMC) if MCLR is enabled. 7.9.2 WAKE-UP FROM SLEEP The device can wake-up from SLEEP through one of the following events: 1. An external reset input on GP3/MCLR/VPP pin, when configured as MCLR. 2. A Watchdog Timer time-out reset (if WDT was enabled). 3. A change on input pin GPO, GP1, or GP3/ MCLR/VPP when wake-up on change is enabled. These events cause a device reset. The TO, PD, and GPWUF bits can be used to determine the cause of device reset. The TO bit is cleared if a WDT time-out occurred (and caused wake-up). The PD bit, which is set on power-up, is cleared when SLEEP is invoked. The GPWUF bit indicates a change in state while in SLEEP at pins GPO, GP1, or GP3 (since the last time there was a file or bit operation on GP port). Caution: Right before entering SLEEP read the input pins. When in SLEEP, wake up occurs when the values at the pins change from the state they were in at the last reading. If a wake-up on change occurs and the pins are not read before reentering SLEEP, a wake up will occur immediately even if no pins change while in SLEEP mode. The WDT is cleared when the device wakes from sleep, regardless of the wake-up source. 7.10 Program Veritication/Code Protection If the code protection bit has not been programmed, the on-chip program memory can be read out for verification purposes. The first 64 locations and the last location can be read regardless of the code protection bit setting. 7.11 ID Locations Four memory locations are designated as |D locations where the user can store checksum or other code- identification numbers. These locations are not accessible during normal execution but are readable and writable during program/verify. Use only the lower 4 bits of the ID locations and always program the upper 8 bits as 0's. 1998 Microchip Technology Inc. DS40139D-page 37PIC12C5XX 7.12 In-Circuit Serial Programming The PIC12C5XX microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data, and three other lines for power, ground, and the programming voltage. This allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. The device is placed into a program/verify mode by holding the GP1 and GPO pins low while raising the MCLR (VPP) pin from VIL to VIHH (see programming specification). GP1 becomes the programming clock and GPO becomes the programming data. Both GP1 and GPO are Schmitt Trigger inputs in this mode. After reset, a 6-bit command is then supplied to the device. Depending on the command, 14-bits of pro- gram data are then supplied to or from the device, depending if the command was a load or a read. For complete details of serial programming, please refer to the PIC12C5XX Programming Specifications. A typical in-circuit serial programming connection is shown in Figure 7-15. FIGURE 7-15: TYPICAL IN-CIRCUIT SERIAL PROGRAMMING Connections CONNECTION To Normal External ' Connections Connector | PIC12C5XX Signals +5V , VDD ov , \ Vss VPP + e MCLR/VpPP CLK- GP1 Data I/O GPo VDD ' To Normal DS40139D-page 38 1998 Microchip Technology Inc.PIC12C5XX 8.0 INSTRUCTION SET SUMMARY Each PIC12C5XxX instruction is a 12-bit word divided into an OPCODE, which specifies the instruction type, and one or more operands which further specify the operation of the instruction. The PIC12C5XX instruction set summary in Table 8-2 groups the instructions into byte-oriented, bit-oriented, and literal and control operations. Table 8-1 shows the opcode field descriptions. For byte-oriented instructions, f' represents a file register designator and d' represents a destination designator. The file register designator is used to specify which one of the 32 file registers is to be used by the instruction. The destination designator specifies where the result of the operation is to be placed. If d' is '0', the result is placed in the W register. If d' is '1', the result is placed in the file register specified in the instruction. For bit-oriented instructions, b' represents a bit field designator which selects the number of the bit affected by the operation, while f' represents the number of the file in which the bit is located. For literal and control operations, 'k' represents an 8 or 9-bit constant or literal value. TABLE 8-1: OPCODE FIELD DESCRIPTIONS All instructions are executed within a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. In this case, the execution takes two instruction cycles. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 us. If a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 2 us. Figure 8-1 shows the three general formats that the instructions can have. All examples in the figure use the following format to represent a hexadecimal number: Oxhhh where h' signifies a hexadecimal digit. FIGURE 8-1: GENERAL FORMAT FOR Field Description Register file address (0x00 to 0x7F) Working register (accumulator) Bit address within an 8-bit file register Vl o;}a [mh Literal field, constant data or label Don't care location (= 0 or 1) The assembler will generate code with x = 0. Itis the recommended form of use for compatibility with all Microchip software tools. Destination select; d = 0 (store result in W) d= 1 (store result in file register 'f) Default is d = 1 INSTRUCTIONS Byte-oriented file register operations 11 6 5 4 0 OPCODE | d | f (FILE #) d =0 for destination W d= 1 for destination f f = 5-bit file register address Bit-oriented file register operations 11 87 54 0 OPCODE | b (BIT #)| f (FILE #) bit bit address b f bit file register address = 3- = 5- Literal and control operations (except GOTO) 11 8 7 0 OPCODE | k (literal) k = 8-bit immediate value Literal and control operations - GOTO instruction 11 9 8 0 OPCODE | k (literal) | k = 9-bit immediate value label | Label name TOS Top of Stack PC Program Counter WDT Watchdog Timer Counter TO Time-Out bit PD Power-Down bit dest Destination, either the W register or the specified register file location [ ] Options () Contents > Assigned to <> Register bit field E In the set of italics | User defined term (font is courier) 1998 Microchip Technology Inc. DS40139D-page 39PIC12C5XX TABLE 8-2: INSTRUCTION SET SUMMARY Mnemonic, 12-Bit Opcode Status Operands Description Cycles | MSb LSb | Affected | Notes ADDWF f,d Add W and f 1 0001 lidf ffff | C,DC,Z | 1,2,4 ANDWF f,d AND W with f 1 0001 Oldf ffff Z 2,4 CLRF f Clear f 1 0000 6011f ffff Z 4 CLRW - Clear W 1 0000 690100 0000 Z COMF f,d Complement f 1 0010 Oldf ffff Z DECF f,d Decrement f 1 0000 1lldf ffff Z 2,4 DECFSZ f,d Decrement f, Skip if 0 1(2) |0010 i11ldf ffff None 2,4 INCF f,d Increment f 1 0010 10df ffff Z 2,4 INCFSZ f,d Increment f, Skip if 0 1(2) |0011 lldf ffff None 2,4 IORWF f,d Inclusive OR W with f 1 0001 OO0df ffff Z 2,4 MOVF f,d Move f 1 0010 OOdf ffff Z 2,4 MOVWF f Move W to f 1 0000 OO1f ffff None 1,4 NOP - No Operation 1 0000 0000 0000 None RLF f,d Rotate left f through Carry 1 0011 Oldft ffff Cc 2,4 RRF f,d Rotate right f through Carry 1 0011 OOd ffff Cc 2,4 SUBWF f,d Subtract W from f 1 0000 10df ffff | C,DC,Z | 1,2,4 SWAPF f,d Swap f 1 0011 10df ffff None 2,4 XORWF f,d Exclusive OR W with f 1 0001 10d ffff Z 2,4 BIT-ORIENTED FILE REGISTER OPERATIONS BCF f,b Bit Clear f 1 0100 bbbf ffff None 2,4 BSF f,b Bit Set f 1 0101 bbbf ffff None 2,4 BTFSC f,b Bit Test f, Skip if Clear 1(2) |0110 bbbf ffff None BTFSS f,b Bit Test f, Skip if Set 1 (2) |0111 bbbf ffff None LITERAL AND CONTROL OPERATIONS ANDLW k AND literal with W 1 1110 kkkk kkkk Z CALL k Call subroutine 2 1001 kkkk kkkk None 1 CLRWDT_ k Clear Watchdog Timer 1 0000 0000 0100 | TO,PD GOTO k Unconditional branch 2 101k kkkk kkkk None IORLW k Inclusive OR Literal with W 1 1101 kkkk kkkk Z MOVLW k Move Literal to W 1 1100 kkkk kkkk None OPTION - Load OPTION register 1 0000 0000 0010 None RETLW k Return, place Literal in W 2 1000 kkkk kkkk None SLEEP - Go into standby mode 1 0000 0000 0011 | TO,PD TRIS f Load TRIS register 1 0000 0000 Offf None 3 XORLW k Exclusive OR Literal to W 1 1111 kkkk kkkk Z Note 1: The 9th bit of the program counter will be forced to a '0' by any instruction that writes to the PC except for GoTo. (Section 4.6) When an I/O register is modified as a function of itself (e.g. MovF GPIO, 1), the value used will be that value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a 0. The instruction TRIS , where f = 6 causes the contents of the W register to be written to the tristate latches of GPIO. A'1' forces the pin to a hi-impedance state and disables the output buffers. If this instruction is executed on the TMRO register (and, where applicable, d = 1), the prescaler will be cleared (if assigned to TMRO). 2: 3: 4: DS40139D-page 40 1998 Microchip Technology Inc.PIC12C5XX ANDWF AND W with f Syntax: [ label] ANDWF _ fd Operands: O<f<31 de [0,1] Operation: (W) .AND. (f) > (dest) Status Affected: Z Description: The contents of the W register are ANDed with register 'f'. If 'd' is 0 the result is stored in the W register. If 'd is '1' the result is stored back in register 'f'. Words: 1 Cycles: 1 Example: ANDWF FSR, 1 Before Instruction W = 0x17 FSR = OxC2 After Instruction W = 0x17 FSR = 0x02 BCF Bit Clear f Syntax: [label] BCF fb Operands: O<f<31 O<b<7 Operation: 0 > (f<b>) Status Affected: None Description: Bit 'b' in register f' is cleared. Words: 1 Cycles: 1 Example: BCE FLAG REG, 7 ADDWF Add W and f Syntax: [ label] ADDWF _ fd Operands: O<f<31 de [0,1] Operation: (W) + (f) > (dest) Status Affected: C, DC, Z Description: Add the contents of the W register and register f. If 'd is 0 the result is stored in the W register. If 'd is '1' the result is stored back in register 'f'. Words: 1 Cycles: 1 Example: ADDWF FSR, 0 Before Instruction W == 0x17 FSR = OxC2 After Instruction W = OxD9 FSR = OxC2 ANDLW And literal with W Syntax: [label] ANDLW_ k Operands: 0<k<255 Operation: (W).AND. (k) > (W) Status Affected: Z Description: The contents of the W register are ANDed with the eight-bit literal 'k'. The result is placed in the W register. Words: 1 Cycles: 1 Example: ANDLW O0x5F Before Instruction W = 0xA3 After Instruction W = 0x03 Before Instruction FLAG_REG = 0xC7 After Instruction FLAG_REG = 0x47 1998 Microchip Technology Inc. DS40139D-page 41PIC12C5XX BSF Bit Set f Syntax: [label] BSF f,b Operands: O<f<31 O<b<7 Operation: 1 > (f<b>) Status Affected: None Description: Bit 'b in register f' is set. Words: 1 Cycles: 1 Example: BSE FLAG REG, 7 Before Instruction FLAG_REG = O0x0A After Instruction FLAG_REG = 0x8A BTFSC Bit Test f, Skip if Clear Syntax: [ label] BTFSC f,b Operands: O<f<31 O<b<7 Operation: skip if (f<b>) = 0 Status Affected: None Description: If bit 'bin register fis 0 then the next instruction is skipped. If bit 'b' is 0 then the next instruction fetched during the current instruction execution is discarded, and an NOP is executed instead, making this a 2 cycle instruction. Words: 1 Cycles: 1(2) Example: HERE BTFSC FLAG, 1 FALSE GOTO TRUE . PROCESS CODE Before Instruction PC = address (HERE) After Instruction ifFLAG<1> = 0, PC = address (TRUE); ifFLAG<1> = 1, PC address (FALSE) BTFSS Bit Test f, Skip if Set Syntax: [ label] BTFSS f,b Operands: O<f<31 O<b<7 Operation: skip if (f<b>) = 1 Status Affected: None Description: If bit 'b' in register f' is '1' then the next instruction is skipped. If bit 'b' is '1', then the next instruction fetched during the current instruction execution, is discarded and an NOP is executed instead, making this a 2 cycle instruction. Words: 1 Cycles: 1(2) Example: HERE BTFSS FLAG,1 FALSE GOTO TRUE e PROCESS CODE Before Instruction PC = address (HERE) After Instruction IfFLAG<i> = 0, PC = address (FALSE); ifFLAG<1> = 1, PC address (TRUE) DS40139D-page 42 1998 Microchip Technology Inc.PIC12C5XX CALL Subroutine Call Syntax: [/abel] CALL k Operands: 0<k<255 Operation: (PC) + 1 Top of Stack; k + PC<7:0>; Status Affected: Encoding: Description: Words: Cycles: Example: (STATUS<6:5>) > PC<10:9>; 0 > PC<8> None 1001 kkkk kkkk Subroutine call. First, return address (PC+1) is pushed onto the stack. The eight bit immediate address is loaded into PC bits <7:0>. The upper bits PC<10:9> are loaded from STA- TUS<6:5>, PC<8> is cleared. CALLisa two cycle instruction. 1 2 HERE CALL THERE Before Instruction PC = address (HERE) After Instruction PC = address (THERE) TOS = address (HERE + 1) CLRF Clear f Syntax: [label] CLRF f Operands: O<f<31 Operation: 00h > (f); 1>Z Status Affected: Z Description: The contents of register 'f' are cleared and the Z bit is set. Words: 1 Cycles: 1 Example: CLRF FLAG REG Before Instruction FLAG_REG = = Ox5A After Instruction FLAG_REG = 0x00 Z = 1 CLRW Clear W Syntax: [ labei/] CLRW Operands: None Operation: 00h > (W); 135Z Status Affected: Z Description: The W register is cleared. Zero bit (Z) is set. Words: 1 Cycles: 1 Example: CLRW Before Instruction W = Ox5A After Instruction W = 0x00 Z = 1 CLRWDT Clear Watchdog Timer Syntax: [ label] CLRWDT Operands: None Operation: 00h > WDT; 0 + WDT prescaler (if assigned); 1 >TO; 15PD Status Affected: TO, PD Description: The CLRWDT instruction resets the WDT. It also resets the prescaler, if the prescaler is assigned to the WDT and not TimerO. Status bits TO and PD are set. Words: 1 Cycles: 1 Example: CLRWDT Before Instruction WDT counter = 2? After Instruction WDT counter = 0x00 WDT prescale= 0 TO = 1 PD = 1 1998 Microchip Technology Inc. DS40139D-page 43PIC12C5XX COMF Complement f Syntax: [label] COMF f,d Operands: O<f<31 de [0,1] Operation: (f} > (dest) Status Affected: Z Description: The contents of register 'f are comple- mented. If 'd' is 0 the result is stored in the W register. If 'd is 1 the result is stored back in register 'f'. Words: 1 Cycles: 1 Example: COMF REG1, 0 Before Instruction REG1 = 0x13 After Instruction REG1 = 0x13 WwW = OxEC DECF Decrement f Syntax: [label] DECF f,d Operands: O<f<31 de [0,1] Operation: (f) - 1 (dest) Status Affected: Z Description: Decrement register f. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f. Words: 1 Cycles: 1 Example: DECE CNT, 1 Before Instruction CNT = 0x01 Z = 0 After Instruction CNT = 0x00 Z = 1 DECFSZ Decrement f, Skip if 0 Syntax: [ label] DECFSZ fd Operands: O<f<31 de [0,1] Operation: (f)-1d; skip if result = 0 Status Affected: None Description: The contents of register 'f' are decre- mented. If 'd' is 0 the result is placed in the W register. If 'd is 1 the result is placed back in register 'f. If the result is 0, the next instruction, which is already fetched, is discarded and an NOP is executed instead mak- ing it a two cycle instruction. Words: 1 Cycles: 1(2) Example: HERE DECFSZ CNT, 1 GOTO LOOP CONTINUE Before Instruction PC = address (HERE) After Instruction CNT = CNT-1; ifCNT = 0, PC = address (CONTINUE); ifCNT # 0, PC = address (HERE+1) GOTO Unconditional Branch Syntax: [label] GOTO k Operands: O0<k<511 Operation: k > PC<8:0>; STATUS<6:5> > PC<10:9> Status Affected: None Description: GOTO is an unconditional branch. The 9-bit immediate value is loaded into PC bits <8:0>. The upper bits of PC are loaded from STATUS<6:5>. GoTO is a two cycle instruction. Words: 1 Cycles: 2 Example: GOTO THERE After Instruction PC = address (THERE) DS40139D-page 44 1998 Microchip Technology Inc.PIC12C5XX INCF Increment f Syntax: [label] INCF fd Operands: O<f<31 de [0,1] Operation: (f) + 1 (dest) Status Affected: Z Description: The contents of register f' are incre- mented. If 'd is 0 the result is placed in the W register. If 'd is 1 the result is placed back in register f'. Words: 1 Cycles: 1 Example: INCF CNT, 1 Before Instruction CNT = OxFF Z = 0 After Instruction CNT = 0x00 Z = 1 INCFSZ Increment f, Skip if 0 Syntax: [label] INCFSZ f,d Operands: O<f<31 de [0,1] Operation: (f) + 1 (dest), skip if result = 0 Status Affected: None Description: The contents of register f' are incre- mented. If 'd is 0 the result is placed in the W register. If 'd is 1 the result is placed back in register f'. If the result is 0, then the next instruc- tion, which is already fetched, is dis- carded and an NOP is executed instead making it a two cycle instruc- tion. Words: 1 Cycles: 1(2) Example: HERE INCFSZ CNT, 1 GOTO LOOP CONTINUE Before Instruction PC = address (HERE) After Instruction CNT if CNT PC if CNT PC = CNT+1; 0, address (CONTINUE); 0, address (HERE +1) tow oo IORLW Inclusive OR literal with W Syntax: [/abel] IORLW k Operands: 0<k<255 Operation: (W) .OR. (k) > (W) Status Affected: Z Description: The contents of the W register are ORed with the eight bit literal 'k'. The result is placed in the W register. Words: 1 Cycles: 1 Example: IORLW 0x35 Before Instruction W = Ox9A After Instruction W = OxBF Z = 0 IORWF Inclusive OR W with f Syntax: [label] IORWF fd Operands: O<f<31 de [0,1] Operation: (W).OR. (f) (dest) Status Affected: Z Description: Inclusive OR the W register with regis- ter 'f'. If 'd' is 0 the result is placed in the W register. If 'd is 1 the result is placed back in register 'f. Words: 1 Cycles: 1 Example: IORWE RESULT, 0 Before Instruction RESULT = 0x13 Ww = 0x91 After Instruction RESULT = 0x13 Ww = 0x93 Z 0 1998 Microchip Technology Inc. DS40139D-page 45PIC12C5XX MOVF Move f Syntax: [label] MOVF fd Operands: O<f<31 de [0,1] Operation: (f) (dest) Status Affected: Z Encoding: Description: Words: Cycles: Example: 0010 O0dft ffff The contents of register 'f' is moved to destination 'd. If 'd' is 0, destination is the W register. If 'd' is 1, the destination is file register 'f'. 'd is 1 is useful to test a file register since status flag Z is affected. 1 1 MOVE FSR, 0 After Instruction W = _ value in FSR register MOVLW Move Literal to W Syntax: [/abel] MOVLW k Operands: 0<k<255 Operation: k > (W) Status Affected: None Encoding: Description: Words: Cycles: Example: 1100 kkkk kkkk The eight bit literal 'k' is loaded into the W register. The dont cares will assem- ble as Os. { { MOVLW OxSA After Instruction W = Ox5A MOVWF Move W to f Syntax: [label] MOVWF f Operands: O<f<31 Operation: (W) > (f) Status Affected: None Description: Move data from the W register to regis- ter f. Words: 1 Cycles: 1 Example: MOVWF TEMP REG Before Instruction TEMP_REG = = OxFF WwW = Ox4F After Instruction TEMP_REG = = Ox4F WwW = Ox4F NOP No Operation Syntax: [label] NOP Operands: None Operation: No operation Status Affected: None Description: No operation. Words: 1 Cycles: 1 Example: NOP DS40139D-page 46 1998 Microchip Technology Inc.PIC12C5XX OPTION Load OPTION Register Syntax: [ label] OPTION Operands: None Operation: (W) OPTION Status Affected: None Description: The content of the W register is loaded into the OPTION register. Words: 1 Cycles: 1 Example OPTION Before Instruction Ww = 0x07 After Instruction OPTION = 0x07 RETLW Return with Literal in W Syntax: [label] RETLW k Operands: 0<k<255 Operation: k > (W); TOS > PC Status Affected: None Description: The W register is loaded with the eight bit literal 'k'. The program counter is loaded from the top of the stack (the return address). This is a two cycle instruction. Words: 1 Cycles: 2 Example: CALL TABLE ;W contains j;table offset ;value. . ;W now has table . jvalue. TABLE ADDWE PC ;W = offset RETLW kl ;Begin table RETLW k2 i RETLW kn ; End of table Before Instruction W = 0x07 After Instruction W = value of k8 RLF Rotate Left f through Carry Syntax: [label] RLF fd Operands: 0<f<31 de [0,1] Operation: See description below Status Affected: C Description: The contents of register 'f are rotated one bit to the left through the Carry Flag. If 'd' is O the result is placed in the W register. If 'd is 1 the result is stored back in register 'f'. easter F_| Words: 1 Cycles: 1 Example: RLF REG1, 0 Before Instruction REG1 = 1110 0110 Cc = 0 After Instruction REG1 = 1110 0110 Ww = 1100 1100 Cc 1 RRF Rotate Right f through Carry Syntax: [labe!] RRF fd Operands: O<f<31 de [0,1] Operation: See description below Status Affected: C Description: The contents of register 'f are rotated one bit to the right through the Carry Flag. If 'd' is 0 the result is placed in the W register. If 'd is 1 the result is placed back in register 'f'. Words: 1 Cycles: 1 Example: RRE REG1, 0 Before Instruction REG1 = 1110 0110 Cc = 0 After Instruction REG1 = 1110 0110 Ww = 0111 0011 Cc 0 1998 Microchip Technology Inc. DS40139D-page 47PIC12C5XX SLEEP Enter SLEEP Mode Syntax: [label SLEEP Operands: None Operation: 00h > WDT; 0 WDT prescaler; 13TO; 0> PD Status Affected: TO, PD, GPWUF Description: Time-out status bit (TO) is set. The power down status bit (PD) is cleared. GPWUF is unaffected. The WDT and its prescaler are cleared. The processor is put into SLEEP mode with the oscillator stopped. See sec- tion on SLEEP for more details. Words: 1 Cycles: 1 Example: SLEEP SUBWF Subtract W from f Syntax: [label SUBWF fd Operands: O<f<31 de [0,1] Operation: (f) - (W) > (dest) Status Affected: C, DC, Z Description: Subtract (2's complement method) the W register from register 'f. If 'd is 0 the result is stored in the W register. If 'd is 1 the result is stored back in register 'f. Words: 1 Cycles: 1 Example 1: SUBWF REG, 1 Before Instruction REG1 = 38 Ww = 2 Cc 2? After Instruction REG1 = 1 Ww = 2 Cc 1 ; result is positive Example 2: Before Instruction REG1 = 2 Ww = 2 Cc 2? After Instruction REG1 = 0O Ww = 2 Cc 1 ; result is zero Example 3: Before Instruction REG1 = 1 Ww = 2 Cc 2? After Instruction REG1 = FF Ww = 2 Cc 0 ; result is negative DS40139D-page 48 1998 Microchip Technology Inc.PIC12C5XX SWAPF Swap Nibbles in f Syntax: [label] SWAPF fd Operands: O<f<31 de [0,1] Operation: (f<3:0>) > (dest<7:4>); (f<7:4>) > (dest<3:0>) Status Affected: None Description: The upper and lower nibbles of register 'f' are exchanged. If 'd is 0 the result is placed in W register. If 'd' is 1 the result is placed in register 'f'. Words: 1 Cycles: 1 Example SWAPF REG1, 0 Before Instruction REG1 = OxA5 After Instruction REG1 = OxA5 WwW = OX5A TRIS Load TRIS Register Syntax: [label] TRIS f Operands: f=6 Operation: (W) > TRIS register f Status Affected: None Description: TRIS register 'f' (f = 6) is loaded with the contents of the W register Words: 1 Cycles: 1 Example TRIS GPIO Before Instruction Ww = OXA5 After Instruction TRIS = OXA5 Note: f= 6 for PIC12C5XX only. XORLW Exclusive OR literal with W Syntax: [label] XORLW k Operands: 0<k<255 Operation: (W) .XOR. k > (W) Status Affected: Z Description: The contents of the W register are XORed with the eight bit literal 'k. The result is placed in the W register. Words: 1 Cycles: 1 Example: XORLW OxAF Before Instruction W = OxBd5 After Instruction W = OxtA XORWF Exclusive OR W with f Syntax: [label] XORWF _ f,d Operands: 0<f<31 de [0,1] Operation: (W) .XOR. (f) > (dest) Status Affected: Z Description: Exclusive OR the contents of the W register with register 'f'. If 'd' is 0 the result is stored in the W register. If 'd is 1 the result is stored back in register 'f. Words: 1 Cycles: 1 Example XORWF REG, 1 Before Instruction REG = OxAF WwW = OxB5 After Instruction REG = OxiA WwW = OxB5 1998 Microchip Technology Inc. DS40139D-page 49PIC12C5XX NOTES: DS40139D-page 50 1998 Microchip Technology Inc.PIC12C5XX 9.0 DEVELOPMENT SUPPORT 9.1 Development Tools The PlCmicro microcontrollers are supported with a full range of hardware and software development tools: MPLAB-ICE Real-Time In-Circuit Emulator ICEPIC Low-Cost PIC16C5X and PIC16CXXX In-Circuit Emulator * PRO MATE II Universal Programmer * PICSTART Plus Entry-Level Prototype Programmer * SIMICE * PICDEM-1 Low-Cost Demonstration Board * PICDEM-2 Low-Cost Demonstration Board * PICDEM-3 Low-Cost Demonstration Board * MPASM Assembler * MPLAB SIM Software Simulator * MPLAB-C17 (C Compiler) + Fuzzy Logic Development System (fuzzyTECH-MP) * KEELOQ Evaluation Kits and Programmer 9.2 MPLAB-ICE: High Performance Universal In-Circuit Emulator with MPLAB IDE The MPLAB-ICE Universal In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PiCmicro microcontrollers (MCUs). MPLAB-ICE is sup- plied with the MPLAB Integrated Development Environ- ment (IDE), which allows editing, make and download, and source debugging from a single envi- ronment. Interchangeable processor modules allow the system to be easily reconfigured for emulation of different pro- cessors. The universal architecture of the MPLAB-ICE allows expansion to support all new Microchip micro- controllers. The MPLAB-ICE Emulator System has been designed as a real-time emulation system with advanced fea- tures that are generally found on more expensive development tools. The PC compatible 386 (and higher) machine platform and Microsoft Windows 3.x or Windows 95 environment were chosen to best make these features available to you, the end user. MPLAB-ICE is available in two _ versions. MPLAB-ICE 1000 is a basic, low-cost emulator system with simple trace capabilities. It shares processor mod- ules with the MPLAB-ICE 2000. This is a full-featured emulator system with enhanced trace, trigger, and data monitoring features. Both systems will operate across the entire operating speed reange of the PlCmicro MCU. 9.3 ICEPIC: Low-Cost PiCmicro In-Circuit Emulator ICEPIC is a low-cost in-circuit emulator solution for the Microchip PIC12CXXX, PIC16C5X and PIC16CXXX families of 8-bit OTP microcontrollers. ICEPIC is designed to operate on PC-compatible machines ranging from 386 through Pentium based machines under Windows 3.x, Windows 95, or Win- dows NT environment. ICEPIC features real time, non- intrusive emulation. 9.4 PRO MATE Il: Universal Programmer The PRO MATE II Universal Programmer is a full-fea- tured programmer capable of operating in stand-alone mode as well as PC-hosted mode. PRO MATE Il is CE compliant. The PRO MATE II has programmable VDD and VPP supplies which allows it to verify programmed memory at VDD min and VDD max for maximum reliability. It has an LCD display for displaying error messages, keys to enter commands and a modular detachable socket assembly to support various package types. In stand- alone mode the PRO MATE II can read, verify or pro- gram PIC12CXXX, PIC14C000, PIC16C5X, PIC16CXXX and PIC17CXX devices. It can also set configuration and code-protect bits in this mode. 9.5 PICSTART Plus Entry Level Development System The PICSTART programmer is an easy-to-use, low- cost prototype programmer. It connects to the PC via one of the COM (RS-232) ports. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. PICSTART Plus is not recommended for production programming. PICSTART Plus supports all PIC12CXXX, PIC14C000, PIC16C5X, PIC16CXXX and PIC17CXX devices with up to 40 pins. Larger pin count devices such as the PIC16C923, PIC16C924 and PIC17C756 may be sup- ported with an adapter socket. PICSTART Plus is CE compliant. 1998 Microchip Technology Inc. DS40139D-page 51PIC12C5XX 9.6 SIMICE Entry-Level Hardware Simulator SIMICE is an entry-level hardware development sys- tem designed to operate in a PC-based environment with Microchips simulator MPLAB-SIM. Both SIM- ICE and MPLAB-SIM run under Microchip Technol- ogys MPLAB Integrated Development Environment (IDE) software. Specifically, SIMICE provides hardware simulation for Microchips PIC12C5XX, PIC12CE5XxX, and PIC16C5X families of PICmicro 8-bit microcon- trollers. SIMICE works in conjunction with MPLAB-SIM to provide non-real-time I/O port emulation. SIMICE enables a developer to run simulator code for driving the target system. In addition, the target system can provide input to the simulator code. This capability allows for simple and interactive debugging without having to manually generate MPLAB-SIM stimulus files. SIMICE is a valuable debugging tool for entry- level system development. 9.7 PICDEM-1 Low-Cost PlCmicro Demonstration Board The PICDEM-1 is a simple board which demonstrates the capabilities of several of Microchips microcontrol- lers. The microcontrollers supported are: PIC16C5X (PIC16C54 to PICI6C58A), PIC16C61, PIC16C62x, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44, All necessary hardware and software is included to run basic demo programs. The users can program the sample microcontrollers provided with the PICDEM-1 board, on a PROMATE Ill or PICSTART-Plus programmer, and easily test firm- ware. The user can also connect the PICDEM-1 board to the MPLAB-ICE emulator and download the firmware to the emulator for testing. Additional proto- type area is available for the user to build some addi- tional hardware and connect it to the microcontroller socket(s). Some of the features include an RS-232 interface, a potentiometer for simulated analog input, push-button switches and eight LEDs connected to PORTB. 9.8 PICDEM-2 Low-Cost PIC16CXX Demonstration Board The PICDEM-2 is a simple demonstration board that supports the PIC16C62, PIC16C64, PIC16C65, PIC16C73 and PIC16C74 microcontrollers. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM-2 board, on a PRO MATE II pro- grammer or PICSTART-Plus, and easily test firmware. The MPLAB-ICE emulator may also be used with the PICDEM-2 board to test firmware. Additional prototype area has been provided to the user for adding addi- tional hardware and connecting it to the microcontroller socket(s). Some of the features include a RS-232 inter- face, push-button switches, a potentiometer for simu- lated analog input, a Serial EEPROM to demonstrate usage of the C bus and separate headers for connec- tion to an LCD module and a keypad. 9.9 PICDEM-3 Low-Cost PIC16CXXX Demonstration Board The PICDEM-3 is a simple demonstration board that supports the PIC16C923 and PIC16C924 in the PLCC package. It will also support future 44-pin PLCC microcontrollers with a LCD Module. All the neces- sary hardware and software is included to run the basic demonstration programs. The user can pro- gram the sample microcontrollers provided with the PICDEM-3 board, on a PRO MATE II program- mer or PICSTART Plus with an adapter socket, and easily test firmware. The MPLAB-ICE emulator may also be used with the PICDEM-3 board to test firm- ware. Additional prototype area has been provided to the user for adding hardware and connecting it to the microcontroller socket(s). Some of the features include an RS-232 interface, push-button switches, a potenti- ometer for simulated analog input, a thermistor and separate headers for connection to an external LCD module and a keypad. Also provided on the PICDEM-3 board is an LCD panel, with 4 commons and 12 seg- ments, that is capable of displaying time, temperature and day of the week. The PICDEM-3 provides an addi- tional RS-232 interface and Windows 3.1 software for showing the demultiplexed LCD signals on a PC. A sim- ple serial interface allows the user to construct a hard- ware demultiplexer for the LCD signals. DS40139D-page 52 1998 Microchip Technology Inc.PIC12C5XX 9.10 MPLAB Integrated Development Environment Software The MPLAB IDE Software brings an ease of software development previously unseen in the 8-bit microcon- troller market. MPLAB is a windows based application which contains: * A full featured editor * Three operating modes - editor - emulator - simulator * Aproject manager * Customizable tool bar and key mapping * Astatus bar with project information * Extensive on-line help MPLAB allows you to: * Edit your source files (either assembly or C) * One touch assemble (or compile) and download to PlCmicro tools (automatically updates all project information) * Debug using: - source files - absolute listing file The ability to use MPLAB with Microchips simulator allows a consistent platform and the ability to easily switch from the low cost simulator to the full featured emulator with minimal retraining due to development tools. 9.11 Assembler (MPASM) The MPASM Universal Macro Assembler is a PC- hosted symbolic assembler. It supports all microcon- troller series including the PIC12C5XxX, PIC14000, PIC16C5X, PIC16CXXX, and PIC17CXX families. MPASM offers full featured Macro capabilities, condi- tional assembly, and several source and listing formats. It generates various object code formats to support Microchip's development tools as well as third party programmers. MPASM allows full symbolic debugging from MPLAB- ICE, Microchips Universal Emulator System. MPASM has the following features to assist in develop- ing software for specific use applications. * Provides translation of Assembler source code to object code for all Microchip microcontrollers. * Macro assembly capability. * Produces all the files (Object, Listing, Symbol, and special) required for symbolic debug with Microchips emulator systems. * Supports Hex (default), Decimal and Octal source and listing formats. MPASM provides a rich directive language to support programming of the PlCmicro. Directives are helpful in making the development of your assemble source code shorter and more maintainable. 9.12 Software Simulator (MPLAB-SIM) The MPLAB-SIM Software Simulator allows code development in a PC host environment. It allows the user to simulate the PICmicro series microcontrollers on an instruction level. On any given instruction, the user may examine or modify any of the data areas or provide external stimulus to any of the pins. The input/ output radix can be set by the user and the execution can be performed in; single step, execute until break, or in a trace mode. MPLAB-SIM fully supports symbolic debugging using MPLAB-C17 and MPASM. The Software Simulator offers the low cost flexibility to develop and debug code outside of the laboratory environment making it an excellent multi-project software development tool. 9.13 MPLAB-C17 Compiler The MPLAB-C17 Code Development System is a complete ANSI C compiler and integrated develop- ment environment for Microchips PIC17CXXxX family of microcontrollers. The compiler provides powerful inte- gration capabilities and ease of use not found with other compilers. For easier source level debugging, the compiler pro- vides symbol information that is compatible with the MPLAB IDE memory display. 9.14 Fuzzy Logic Development System (fuzzyTECH-MP) fuzzyTECH-MP fuzzy logic development tool is avail- able in two versions - a low cost introductory version, MP Explorer, for designers to gain a comprehensive working knowledge of fuzzy logic system design; and a full-featured version, fuzzyTECH-MP, Edition for imple- menting more complex systems. Both versions include Microchips fuzzy_LAB demon- stration board for hands-on experience with fuzzy logic systems implementation. 9.15 SEEVAL Evaluation and Programming System The SEEVAL SEEPROM Designer's Kit supports all Microchip 2-wire and 3-wire Serial EEPROMs. The kit includes everything necessary to read, write, erase or program special features of any Microchip SEEPROM product including Smart Serials and secure serials. The Total Endurance Disk is included to aid in trade- off analysis and reliability calculations. The total kit can significantly reduce time-to-market and result in an optimized system. 1998 Microchip Technology Inc. DS40139D-page 53PIC12C5XX 9.16 KEELo@ Evaluation and Programming Tools KEELOQG evaluation and programming tools support Microchips HCS Secure Data Products. The HCS eval- uation kit includes an LCD display to show changing codes, a decoder to decode transmissions, and a pro- gramming interface to program test transmitters. DS40139D-page 54 1998 Microchip Technology Inc.Wy 49puodsuelL 007444 Wy UOReNjeag @00133y -WAddid -WaAddid b-IN3d9Id Vvl-WAddid PIC12C5XX JSOINIS iy sisuBblseg @ IWAAAS sawuwesboid @0OTS4 sawuwesboid Jesaaaiun Il ga LVIN Od Wy Aaq [essai 1S09-MO] SNidoLYVLSOld JPpoW aeMYyos w20UPINPUY [e}OL Joo, "Aeq o16o7 Azzny uolpy/saiojdxy dW-gHOsLAzznj s9Idwo5 ZbLO wV1da yuswUOsJAUy juswidojaAcg po}e169}u| wi VIdW 4oje/NwWy YNI15D-u] 1SO9-MO7 widld3adl DEVELOPMENT TOOLS FROM MICROCHIP OOOPLDld | XXSO?b3ld XXZOLLOld] XPOLLOid | XX6D9LOIid| XBD9LDid | XXZO9LOIid} X9D9LDId |XXX99b3Id TABLE 9-1: d0l-wdVIida DS40139D-page 55 ESE TIT] ole) spieog owaqg S|00] JeEMYOS Sel eee ye | 1998 Microchip Technology Inc.PIC12C5XX NOTES: DS40139D-page 56 1998 Microchip Technology Inc.PIC12C5XX 10.0 ELECTRICAL CHARACTERISTICS - PIC12C508/PIC12C509/ PIC12LC508/PIC12LC509 Absolute Maximum Ratingst Ambient Temperature Under DIAS 2000... ee eeeeceeennee eee eeeenneeeeenaeeeeneeeesaeeeeeaaeeeseneeeesaeeeenaaeeesnnaeeesieeeennaneeennaes 40C to +125C Storage TEMPerature......ecccecessececseeeeesneeeeenneeeceeeeeeeeeeeeeeeeecaeeeeeeeeeeeaeeecaeeeeeaaeeeeeaaeeceneeeessaeeesenaeeesneeees 65C to +150C Voltage On VDD with respect tO VSS oes ee eee ee entre eee ae rene sete aeeeeeaaee ea aeeee ea aeeeeeaaeeeeeeeseaeeeeeaeessneeeennaeeeeea 0t0 +7.5V Voltage on MCLR with respect to VSS......cccccssscsesesssscsescsssscecscsssecesessesesesassesesesasseacsesssecsesssesecseaesesecaeaeentecseaeens Oto +14V Voltage on all other pins with respect tO VSS ooo. eee cece ee eeee ee ernee ee eaeeeeneeeeeaeeeeeaeeeeneeeeenaeeeeeas 0.6 V to (VDD + 0.6 V) Total Power Dissipation) eee eee eee eee eee eee ee eee ee ee ae eee ea eae ae ence ae eee eee eee ee ea eaeae eee eee eeesaaaaeaeeeeseseeaeeeeeeseegaeeees 700 mW Max. Current OUt Of VSS Pil... eeeeeee eter eter enter eee cnet eee nee ene ee tae etna eee eee tae eee eae edness ee caae seeds ee ee naaeseeeeeaeseeee seat 200 mA Max. Current intO VDD PII... eee eeeeeeeeeneeeeeneeeeeee eter nese ena ae ee een ae eee seen nese eeaae ee cneeeeenaeeeeeeaeeesneeeeeseeeeneaeeesgneeeenneeenes 150 mA Input Clamp Current, IK (VI < 0 OF VI> VDD) oe eeceeeeeecnenecersetssenscnsessenssscssnecessenssarssasessesasssnenasesssnscenssnseanesasessenanes +20 mA Output Clamp Current, lOK (VO <0 OF VO > VDD) ue cteescettesceenscsssctsnsescsenecensesssenecsseereasscnsnscesisnseanssnsessesasesnensensees +20 mA Max. Output Current sunk by any I/O Dit oo... eee eeeeeeenne ee cee ee eenaeeeeeaaeeeeeneeeesaeeeeneaeeeseneeeecaeeeeeeaeeeenneeeecnaeeesenatessaes 25 mA Max. Output Current sourced by any I/O Pit... eceeeesneeeeeeee tener eeeeeaeeeseeeeeesaeeeeneaeeesneeeeeceeeeeeaeeeeeneeeesneeeeenaeessaes 25 mA Max. Output Current sourced by I/O port (GPIO).... eee censeeeeneeeeenne ee een ae ee eneee seen ee eenaeeesneeeseeaeeeeeeaeeeeneeeenieeeees 100 mA Max. Output Current sunk by I/O port (GPIO ) ooo... ee eeeee essere renner ener eee aee ee ea gee eeeaaeeeaeeeesaaeeeeeaaeeenneaeesaeeesenaeeesnas 100 mA Note 1: Power Dissipation is calculated as follows: PDIS = VDD x {IDD - IOH} + {(VDD-VOH) x IOH} + S(VOL x IOL) TNOTICE: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 1998 Microchip Technology Inc. DS40139D-page 57PIC12C5XX 10.1 DC CHARACTERISTICS: PIC12C508/509 (Commercial, Industrial, Extended) Standard Operating Conditions (unless otherwise specified) DC Characteristics Operating Temperature 0C < TAS +70C (commercial) Power Supply Pins 40C < TA < +85C (industrial) 40C < TAS +125C (extended) Characteristic Sym | Min | Typ) | Max | Units Conditions Supply Voltage VDD 2.5 5.5 Vv Fosc = DC to 4 MHz (Commercial/ Industrial) 3.0 5.5 Vv Fosc = DC to 4 MHz (Extended) RAM Data Retention VDR 1.5 Vv Device in SLEEP mode Voltage) VbpD Start Voltage to ensure | VPOR Vss Vv See section on Power-on Reset for details Power-on Reset VppD Rise Rate to ensure SvDD_ | 0.05% V/ms_ | See section on Power-on Reset for details Power-on Reset Supply Current) IDD 1.8 2.4 mA | XT and EXTRC options (Note 4) Fosc = 4 MHz, VDD = 5.5V 1.8 2.4 mA | INTRC Option Fosc = 4 MHz, VDD = 5.5V _ 15 27 uA | LP OPTION, Commercial Temperature Fosc = 32 kHz, VDD = 3.0V, WDT disabled 19 35 HA LP OPTION, Industrial Temperature Fosc = 32 kHz, VDD = 3.0V, WDT disabled _ 19 35 HA LP OPTION, Extended Temperature FOsc = 32 kHz, VDD = 3.0V, WDT disabled- AIWDT | _ 3.75 8 HA | VDD = 3.0V, Commercial _ 3.75 9 HA | VDD = 3.0V, Industrial _ 3.75 4 HA | VDD = 3.0V, Extended Power-Down Current () IPD 0.25 4 uA | VDD = 3.0V, Commercial _ 0.25 5 HA | VDD = 3.0V, Industrial 2 18 HA | VDD = 3.0V, Extended These parameters are characterized but not tested. Note 1: 2: 3: Data in the Typical (Typ) column is based on characterization results at 25C. This data is for design guid- ance only and is not tested. This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on the current consumption. a) The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to Vss, TOCKI = Vpop, MCLR = Vpp; WDT enabled/disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode. Does not include current through Rext. The current through the resistor can be estimated by the formula: IR = VDD/2Rext (mA) with Rext in kKOhm. The power down current in SLEEP mode does not depend on the oscillator type. Power down current is mea- sured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or Vss. DS40139D-page 58 1998 Microchip Technology Inc.PIC12C5XX 10.2 DC CHARACTERISTICS: PIC12C508/509 (Commercial, Industrial, Extended) Standard Operating Conditions (unless otherwise specified) Operating temperature 0C <TAS<+70C (commercial) 40C < TA < +85C (industrial DC CHARACTERISTICS 40C < TAS +1 25C (extended) Operating voltage VDD range as described in DC spec Section 10.1 and Section 10.2. Param Characteristic Sym Min Typ| Max | Units Conditions No. T Input Low Voltage I/O ports VIL D030 with TTL buffer Vss - 0.5V Vv D031 with Schmitt Trigger buffer Vss - |0.2VDD} V DO32 = |MCLR, GP2/TOCKI/AN2/INT Vss - |0.2VDD]} V (in EXTRC mode) D033 |OSC1 (in XT, HS and LP) Vss - |0.3VDD} V_ |Notet1 Input High Voltage I/O ports VIH - DO40 with TTL buffer 2.0 - VDD V |45<Vpp<5.5V DO40A 0.8VDD - VDD V_ |For VbD > 5.5V or VbD < 4.5V D041 with Schmitt Trigger buffer 0.8VDD - VDD V_ |For entire VDD range D042 = =|MCLR, GP2/TOCKI/AN2/INT 0.8VDD - VDD Vv DO42A |OSC1 (XT, HS and LP) 0.7VDD - VDD V_ |Note1 D043. = |OSC1 (in EXTRC mode) 0.9VDD - VDD Vv DO70 |GPIO weak pull-up current IPUR 50 250} 400 HA |VDD = 5V, VPIN = Vss Input Leakage Current (Notes 2, 3) DO60 I/O ports IL - - +1 HA |Vss < VPIN < VDD, Pin at hi- impedance DO61 |MCLR, GP2/TOCKI - - | 456) | HA |Vss < VPIN < VDD DO63 =|OSC1 - - +5 HA |Vss < VPIN < VDD, XT, HS and LP osc configuration Output Low Voltage DO80 {I/O ports/CLKOUT VOL - - 0.6 V_jloL = 8.5 mA, VDD = 4.5V, 40C to +85C DO80A - - 0.6 V_ {lot = 7.0 mA, VDD = 4.5V, 40C to +125C DO83 |OSC2 - - 0.6 V_jloL = 1.6 mA, VDD = 4.5V, 40C to +85C DO83A - - 0.6 V_jloL = 1.2 mA, VDD = 4.5V, 40C to +125C t+ Data in Typ column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC12C5XX be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as coming out of the pin. 4: Extended operating range is Advance Information for this device. 5: When configured as external reset, the input leakage current is the weak pulll-up current of -10mA minimum. This pull-up is weaker than the standard I/O pull-up. 1998 Microchip Technology Inc. DS40139D-page 59PIC12C5XX Standard Operating Conditions (unless otherwise specified) Operating temperature 0C <TAS<+70C (commercial) 40C < TA < +85C (industrial) DC CHARACTERISTICS 40C < TAS +125C (extended) Operating voltage VDD range as described in DC spec Section 10.1 and Section 10.2. Param Characteristic Sym Min Typ| Max | Units Conditions No. T Output High Voltage DO90_ {I/O ports/CLKOUT (Note 3) VOH | VDD -0.7] - - V_JIOH = -3.0 mA, VDD = 4.5V, 40C to +85C DOS0A VDD -0.7| - - V_|IOH = -2.5 mA, VDD = 4.5V, 40C to +125C Dog2. _ |OSC2 VDD -0.7] - - V_ |IOH = -1.3 mA, VDD = 4.5V, 40C to +85C DO92A VDD -0.7| - - V_|IOH = -1.0 mA, VDD = 4.5V, 40C to +125C Capacitive Loading Specs on Output Pins D100 = |OSC2 pin Cosce2 - - 15 pF {In XT, HS and LP modes when external clock is used to drive OSC1. D101 |All /O pins and OSC2 Clo - - 50 pF t+ Data in Typ column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC12C5XX be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as coming out of the pin. Extended operating range is Advance Information for this device. When configured as external reset, the input leakage current is the weak pulll-up current of -10mA minimum. This pull-up is weaker than the standard I/O pull-up. aA Po DS40139D-page 60 1998 Microchip Technology Inc.PIC12C5XX 10.3 DC CHARACTERISTICS: PIC12LC508/509 (Commercial, Industrial) a Standard Operating Conditions (unless otherwise specified) Pena acteristics Operating Temperature 0C < TAS +70C (commercial) PPly -40C < TA < 485C (industrial) Characteristic Sym | Min | Typ) | Max | Units Conditions Supply Voltage VDD 2.5 5.5 Vv Fosc = DC to 4 MHz (Commercial/ Industrial) 3.0 5.5 Vv Fosc = DC to 4 MHz (Extended) RAM Data Retention VDR 1.5 Vv Device in SLEEP mode Voltage) VbpD Start Voltage to ensure | VPOR Vss Vv See section on Power-on Reset for details Power-on Reset VbD Rise Rate to ensure SVDD | 0.05 V/ms_ | See section on Power-on Reset for details Power-on Reset Supply Current) IDD 1.8 2.4 mA | XT and EXTRC options (Note 4) Fosc = 4 MHz, VDD = 5.5V 1.8 2.4 mA | INTRC Option Fosc = 4 MHz, VDD = 5.5V 15 27 HA LP OPTION, Commercial Temperature Fosc = 32 kHz, VDD = 3.0V, WDT disabled 19 35 HA LP OPTION, Industrial Temperature Fosc = 32 kHz, VDD = 3.0V, WDT disabled _ 19 35 HA LP OPTION, Extended Temperature FOsc = 32 kHz, VDD = 3.0V, WDT disabled- AIWDT | _ 3.75 8 HA | VDD = 3.0V, Commercial _ 3.75 9 HA | VDD = 3.0V, Industrial _ 3.75 4 HA | VDD = 3.0V, Extended Power-Down Current () IPD 0.25 4 uA | VDD = 3.0V, Commercial 0.25 5 HA | VDD = 3.0V, Industrial _ 2 18 HA | VDD = 3.0V, Extended These parameters are characterized but not tested. Note 1: 2: 3: Data in the Typical (Typ) column is based on characterization results at 25C. This data is for design guid- ance only and is not tested. This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on the current consumption. a) The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to Vss, TOCKI = Vpop, MCLR = Vpp; WDT enabled/disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode. Does not include current through Rext. The current through the resistor can be estimated by the formula: IR = VDD/2Rext (mA) with Rext in kKOhm. The power down current in SLEEP mode does not depend on the oscillator type. Power down current is mea- sured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or Vss. 1998 Microchip Technology Inc. DS40139D-page 61PIC12C5XX 10.4 DC CHARACTERISTICS: PIC12LC508/509 (Commercial, Industrial) Standard Operating Conditions (unless otherwise specified) Operating temperature 0C <TAS<+70C (commercial) DC CHARACTERISTICS 40C < TA < +85C (industrial) Operating voltage VDD range as described in DC spec Section 10.1 and Section 10.2. Param Characteristic Sym Min Typ| Max | Units Conditions No. T Input Low Voltage I/O ports VIL D030 with TTL buffer Vss - | 0.5V Vv D031 with Schmitt Trigger buffer Vss - |0.2VDD} V DO32 = |MCLR, GP2/TOCKI/AN2/INT Vss - |0.2VDD]} V (in EXTRC mode) D033 |OSC1 (in XT, HS and LP) Vss - |0.3VDD} V_ |Notet1 Input High Voltage I/O ports VIH - DO40 with TTL buffer 2.0 - VDD V |45<Vpp<5.5V DO40A 0.8VDD | - VDD V_ |For VbD > 5.5V or VbD < 4.5V D041 with Schmitt Trigger buffer 0.8VDD - VDD V_ |For entire VDD range D042 = =|MCLR, GP2/TOCKI/AN2/INT 0.8VDD | - VDD Vv DO42A |OSC1 (XT, HS and LP) 0.7VDD | - VDD V_ |Note1 D043. = |OSC1 (in EXTRC mode) O.9VDD | - VDD Vv DO70 |GPIO weak pull-up current IPUR 50 250} 400 HA |VDD = 5V, VPIN = Vss Input Leakage Current (Notes 2, 3) DO60 I/O ports IL - - +1 HA |Vss < VPIN < VDD, Pin at hi- impedance DO61 |MCLR, GP2/TOCKI - - | 456) | HA |Vss < VPIN < VDD DO63 =|OSC1 - - +5 HA |Vss < VPIN < VDD, XT, HS and LP osc configuration Output Low Voltage DO80 {I/O ports/CLKOUT VOL - - 0.6 V_jloL = 8.5 mA, VDD = 4.5V, 40C to +85C DO80A - - 0.6 V_|loL = 7.0 mA, VDD = 4.5V, 40C to +125C DO83 |OSC2 - - 0.6 V_ jlo = 1.6 mA, VDD = 4.5V, 40C to +85C DO83A - - 0.6 V_jloL = 1.2 mA, VDD = 4.5V, 40C to +125C t+ Data in Typ column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC12C5XX be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as coming out of the pin. 4: Extended operating range is Advance Information for this device. 5: When configured as external reset, the input leakage current is the weak pulll-up current of -10mA minimum. This pull-up is weaker than the standard I/O pull-up. DS40139D-page 62 1998 Microchip Technology Inc.PIC12C5XX Standard Operating Conditions (unless otherwise specified) Operating temperature 0C <TAS<+70C (commercial) DC CHARACTERISTICS 40C < TA < +85C (industrial) Operating voltage VDD range as described in DC spec Section 10.1 and Section 10.2. Param Characteristic Sym Min Typ| Max | Units Conditions No. T Output High Voltage DO90_ {I/O ports/CLKOUT (Note 3) VOH | VDD -0.7] - - V_JIOH = -3.0 mA, VDD = 4.5V, 40C to +85C DOS0A VDD -0.7| - - V_|IOH = -2.5 mA, VDD = 4.5V, 40C to +125C Dog2 =|OSC2 VDD -0.7| - - V_ |IOH =-1.3 mA, VDD = 4.5V, 40C to +85C DO92A Vpp-0.7] - - V_ JIOH = -1.0 mA, VDD = 4.5V, 40C to +125C Capacitive Loading Specs on Output Pins D100 = |OSC2 pin Cosce2 - - 15 pF {In XT, HS and LP modes when external clock is used to drive OSC1. D101 |All /O pins and OSC2 Clo - - 50 pF t+ Data in Typ column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC12C5XX be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as coming out of the pin. 4: Extended operating range is Advance Information for this device. 5: When configured as external reset, the input leakage current is the weak pulll-up current of -10mA minimum. This pull-up is weaker than the standard I/O pull-up. 1998 Microchip Technology Inc. DS40139D-page 63PIC12C5XX TABLE 10-1: PULL-UP RESISTOR RANGES - PIC12C508/C509 VbD (Volts) Temperature (C) Min Typ Max Units GPO/GP1 2.5 -40 38K 42K 63K Q 25 42K 48K 63K Q 85 42K 49K 63K Q 125 50K 55K 63K Q 5.5 -40 15K 17K 20K Q 25 18K 20K 23K Q 85 19K 22K 25K Q 125 22K 24K 28K Q GP3 2.5 -40 285K 346K 417K Q 25 343K 414K 532K Q 85 368K 457K 532K Q 125 431K 504K 593K Q 5.5 -40 247K 292K 360K Q 25 288K 341K 437K Q 85 306K 371K 448K Q 125 351K 407K 500K Q * These parameters are characterized but not tested. DS40139D-page 64 1998 Microchip Technology Inc.PIC12C5XX 10.5 Timing Parameter Symbology and Load Conditions - PIC12C508/C509 The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2. Tpps T F Frequency T Time Lowercase subscripts (pp) and their meanings: Pp 2 to me MCLR ck CLKOUT osc oscillator cy cycle time os OSC1 drt device reset timer tO TOCKI io I/O port wat watchdog timer Uppercase letters and their meanings: Ss F Fall P Period High R Rise | Invalid (Hi-impedance) Vv Valid L Low Z Hi-impedance FIGURE 10-1: LOAD CONDITIONS - PIC12C508/C509 Pin X<t_ CL = 50pF forall pins except OSC2 CL 15 pF for OSC2 in XT, HS or LP Vv modes when external clock Vss is used to drive OSC 1 1998 Microchip Technology Inc. DS40139D-page 65PIC12C5XX 10.6 Timing Diagrams and Specifications FIGURE 10-2: EXTERNAL CLOCK TIMING - PIC12C508/C509 a4 Q1 Q2 Q1 Osc TABLE 10-2: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC12C508/C509 AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C < TAS +70C (commercial), 40C < TA < +85C (industrial), 40C < TAS +125C (extended) Operating Voltage VDD range is described in Section 10.1 Paremeter Sym Characteristic Min | Typ) | Max | Units Conditions Fosc External CLKIN Frequency?) DC _ 4 MHz |XT osc mode DC _ 200 kHz |LP osc mode Oscillator Frequency(?) 0.1 _ 4 MHz |XT osc mode DC _ 200 kHz |LP osc mode 1 Tosc External CLKIN Period2) 250 _ _ ns |EXTRC osc mode 250 _ _ ns |XT osc mode 5 _ _ ms |LP osc mode Oscillator Period) 250 _ _ ns |EXTRC osc mode 250 10,000} ns |XT osc mode 5 _ _ ms |LP osc mode 2 Tey Instruction Cycle Time) |4/Fosc| _ 3 TosL, TosH |Clock in (OSC1) Low or High Time 50* _ _ ns_ {XT oscillator 2* _ _ ms_ |LP oscillator 4 TosR, TosF |Clock in (OSC1) Rise or Fall Time _ _ 25* ns_ {XT oscillator _ _ 50* ns_ {LP oscillator * These parameters are characterized but not tested. Note 1: Data in the Typical (Typ) column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 2: All specified values are based on characterization data for that particular oscillator type under standard oper- ating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. When an external clock input is used, the max cycle time limit is DC (no clock) for all devices. 3: Instruction cycle period (TCY) equals four times the input oscillator time base period. DS40139D-page 66 1998 Microchip Technology Inc.PIC12C5XX TABLE 10-3: CALIBRATED INTERNAL RC FREQUENCIES - PIC12C508/C509 AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C < TAS +70C (commercial), 40C < TA < +85C (industrial), 40C < TAS +125C (extended) Operating Voltage VDD range is described in Section 10.1 Parameter Sym Characteristic Min* | Typ | Max* | Units Conditions Internal Calibrated RC Frequency 3.64 | 4.00 4.32 | MHz |VpDD = 5.0V Internal Calibrated RC Frequency 3.51 | 4.00 4.26 | MHz |VbDD = 2.5V * These parameters are characterized but not tested. Note 1: Data in the Typical (Typ) column is at 5V, 25C unless guidance only and are not tested. FIGURE 10-3: /O TIMING - PIC12C508/C509 otherwise stated. These parameters are for design OSC1 I/O Pin (input) I/O Pin (output) Q4 at Q2 Q3 CM a | 7 19 KUM _ Sw Old Value New Value Note: All tests must be done with specified capacitive loads (see data sheet) 50 pF on I/O pins and CLKOUT. 1998 Microchip Technology Inc. DS40139D-page 67PIC12C5XX TABLE 10-4: TIMING REQUIREMENTS - PIC12C508/C509 AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C < TAS +70C (commercial) 40C < TA < +85C (industrial) 40C < TAS +125C (extended) Operating Voltage VDD range is described in Section 10.1 Parameter No. Sym Characteristic Min Typ Max Units 17 TosH2ioV | QSC1T (Q1 cycle) to Port out valid) 100 ns 18 TosH2iol OSC1T (Q2 cycle) to Port input invalid TBD _ _ ns (I/O in hold time) 19 TioV20sH Port input valid to OSC1T TBD _ _ ns (I/O in setup time) 20 TioR Port output rise time) _ 10 2s5" ns 21 TioF Port output fall time) _ 10 2s5" ns * These parameters are characterized but not tested. These parameters are design targets and are not tested. No characterization data available at this time. Note 1: Data in the Typical (Typ) column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 2: Measurements are taken in EXTRC mode. 3: See Figure 10-1 for loading conditions. FIGURE 10-4: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER TIMING - PIC12C508/C509 ; Vpo 4 ' ? MCLR = 30 Internal POR 32 ' ' 32 =F" _ DRT ; % Timeout ' 1 (Note 2) Internal RESET Watchdog 1 1 < ' Timer RESET (Note 1) ' ' : Note 1: I/O pins must be taken out of hi-impedance mode by enabling the output drivers in software. 2: Runs in MCLR or WDT reset only in XT and LP modes. DS40139D-page 68 1998 Microchip Technology Inc.PIC12C5XX TABLE 10-5: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC12C508/C509 AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C < TAs +70C (commercial) 40C < TA < +85C (industrial) 40C < TA< +125C (extended) Operating Voltage VDD range is described in Section 10.1 Parameter No. Sym_ |Characteristic Min Typ Max | Units Conditions 30 TmeL |MCLR Pulse Width (low) 2000*| _ ns |VDD=5V 31 Twdt |Watchdog Timer Time-out Period 9* 18" 30* ms |VDD=5V (Commercial) (No Prescaler) 32 TDRT |Device Reset Timer Period?) 9* 18" 30* ms |VDD=5V (Commercial) 34 Tioz |I/O Hi-impedance from MCLR Low | |2000*| ns * These parameters are characterized but not tested. Note 1: Data in the Typical (Typ) column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. TABLE 10-6: DRT (DEVICE RESET TIMER PERIOD - PIC12C508/C509) Oscillator Configuration POR Reset Subsequent Resets IntRC & ExtRC 18 ms (typical) 300 us (typical) XT & LP 18 ms (typical) 18 ms (typical) 1998 Microchip Technology Inc. DS40139D-page 69PIC12C5XX FIGURE 10-5: TIMERO CLOCK TIMINGS - PIC12C508/C509 42 TABLE 10-7: TIMERO CLOCK REQUIREMENTS - PIC12C508/C509 AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C < TAS +70C (commercial) 40C < TA < +85C (industrial) 40C < TA< +125C (extended) Operating Voltage VDD range is described in Section 10.1. Parameter Sym | Characteristic Min Typ Max | Units | Conditions 40 TtOH |TOCKI High Pulse Width - No Prescaler 0.5 Tcy + 20 _ _ ns - With Prescaler 10* _ _ ns 41 TtOL | TOCKI Low Pulse Width - No Prescaler 0.5 Tcy + 20 _ _ ns - With Prescaler 10* _ _ ns 42 TtOP |TOCKI Period 20 or Toy + 40*] _ ns_|Whichever is greater. N N= Prescale Value (1, 2, 4,..., 256) * These parameters are characterized but not tested. Note 1: Data in the Typical (Typ) column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. DS40139D-page 70 1998 Microchip Technology Inc.PIC12C5XX NOTES: 1998 Microchip Technology Inc. DS40139D-page 71PIC12C5XX DS40139D-page 72 1998 Microchip Technology Inc.