MT46V128M4TH-8 - Micron - Datasheet.Directory

512Mb: x4, x8, x16 DDR SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE‡

‡ PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE

SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S

PRODUCTION DATA SHEET SPECIFICATIONS.

DOUBLE DATA RATE

(DDR) SDRAM MT46V128M4 – 32 Meg x 4 x 4 banks

MT46V64M8 – 16 Meg x 8 x 4 banks

MT46V32M16 – 8 Meg x 16 x 4 banks

For the latest data sheet revisions, please refer to the Micron

Web site: www.micronsemi.com/datasheets/ddrsdramds.html

PIN ASSIGNMENT (TOP VIEW)

66-Pin TSOP

FEATURES

•VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V

• Bidirectional data strobe (DQS) transmitted/

received with data, i.e., source-synchronous data

capture (x16 has two – one per byte)

• Internal, pipelined double-data-rate (DDR)

architecture; two data accesses per clock cycle

• Differential clock inputs (CK and CK#)

• Commands entered on each positive CK edge

• DQS edge-aligned with data for READs; center-

aligned with data for WRITEs

• DLL to align DQ and DQS transitions with CK

• Four internal banks for concurrent operation

• Data mask (DM) for masking write data (x16 has

two – one per byte)

• Programmable burst lengths: 2, 4, or 8

• Auto precharge option

• Auto Refresh and Self Refresh Modes

• Longer lead TSOP for improved reliability (OCPL)

• 2.5V I/O (SSTL_2 compatible)

OPTIONS MARKING

• Configuration

128 Meg x 4 (32 Meg x 4 x 4 banks) 128M4

64 Meg x 8 (16 Meg x 8 x 4 banks) 64M8

32 Meg x 16 (8 Meg x 16 x 4 banks) 32M16

• x16 IOL / IOH Drive

Full Drive Only D1

Reduced Drive Only D2

Programmable full or reduced drive D3

• Plastic Package – OCPL

66-pin TSOP (standard 22.3mm length) TG

66-pin TSOP (extended 27mm length) TH

(400 mil width, 0.65mm pin pitch)

• Timing – Cycle Time

7.5ns @ CL = 2 (DDR266A+)1-7

7.5ns @ CL = 2.5 (DDR266B)2-75

10ns @ CL = 2 (DDR200)3-8

• Self Refresh

Standard none

Low Power L

NOTE: 1. Supports PC2100 modules with 2-2-2 timing

2. Supports PC2100 modules with 2.5-3-3 timing

3. Supports PC1600 modules with 2-2-2 timing

128 Meg x 4 64 Meg x 8 32 Meg x 16

Configuration 32 Meg x 4 x 4 banks 16 Meg x 8 x 4 banks 8 Meg x 16 x 4 banks

Refresh Count 8K 8K 8K

Row Addressing 8K (A0–A12) 8K (A0–A12) 8K (A0–A12)

Bank Addressing 4 (BA0, BA1) 4 (BA0, BA1) 4 (BA0, BA1)

Column Addressing 4K (A0–A9, A11, A12) 2K (A0–A9, A11) 1K (A0–A9)

KEY TIMING PARAMETERS

SPEED CLOCK RATE DATA-OUT ACCESS DQS-DQ

GRADE CL = 2** CL = 2.5** WINDOW* WINDOW SKEW

-7 133 MHz 143 MHz 2.5ns ±0.75ns +0.5ns

-75 100 MHz 133 MHz 2.5ns ±0.75ns +0.5ns

-8 100 MHz 125 MHz 3.4ns ±0.8ns +0.6ns

*Minimum clock rate @ CL = 2 (-7, -8) and CL = 2.5 (-75)

**CL = CAS (Read) Latency

VSS

DQ15

VSSQ

DQ14

DQ13

VDDQ

DQ12

DQ11

VSSQ

DQ10

DQ9

VDDQ

DQ8

VSSQ

UDQS

DNU

VREF

VSS

UDM

CK#

CKE

A12

A11

VSS

x16

VDD

DQ0

VDDQ

DQ1

DQ2

VssQ

DQ3

DQ4

VDDQ

DQ5

DQ6

VssQ

DQ7

VDDQ

LDQS

VDD

DNU

LDM

WE#

CAS#

RAS#

CS#

BA0

BA1

A10/AP

VDD

x16

VSS

DQ7

VSSQ

DQ6

VDDQ

DQ5

VSSQ

DQ4

VDDQ

VSSQ

DQS

DNU

VREF

VSS

CK#

CKE

A12

A11

VSS

x8 x4

VSS

VSSQ

DQ3

VDDQ

VSSQ

DQ2

VDDQ

VSSQ

DQS

DNU

VREF

VSS

CK#

CKE

A12

A11

VSS

VDD

DQ0

VDDQ

DQ1

VSSQ

DQ2

VDDQ

DQ3

VSSQ

VDDQ

VDD

DNU

WE#

CAS#

RAS#

CS#

BA0

BA1

A10/AP

VDD

x8x4

VDD

VDDQ

DQ0

VSSQ

VDDQ

DQ1

VSSQ

VDDQ

VDD

DNU

WE#

CAS#

RAS#

CS#

BA0

BA1

A10/AP

VDD

TH Package

TG Package

512Mb: x4, x8, x16 DDR SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

GENERAL DESCRIPTION

The 512Mb DDR SDRAM is a high-speed CMOS,

dynamic random-access memory containing

536,870,912 bits. It is internally configured as a quad-

bank DRAM.

The 512Mb DDR SDRAM uses a double data rate

architecture to achieve high-speed operation. The

double data rate architecture is essentially a 2n-prefetch

architecture with an interface designed to transfer two

data words per clock cycle at the I/O pins. A single read

or write access for the 512Mb DDR SDRAM effectively

consists of a single 2n-bit wide, one-clock-cycle data

transfer at the internal DRAM core and two corre-

sponding n-bit wide, one-half-clock-cycle data trans-

fers at the I/O pins.

A bidirectional data strobe (DQS) is transmitted

externally, along with data, for use in data capture at

the receiver. DQS is a strobe transmitted by the DDR

SDRAM during READs and by the memory controller

during WRITEs. DQS is edge-aligned with data for

READs and center-aligned with data for WRITEs. The

x16 offering has two data strobes, one for the lower

byte and one for the upper byte.

The 512Mb DDR SDRAM operates from a differen-

tial clock (CK and CK#); the crossing of CK going HIGH

and CK# going LOW will be referred to as the positive

edge of CK. Commands (address and control signals)

are registered at every positive edge of CK. Input data

is registered on both edges of DQS, and output data is

referenced to both edges of DQS, as well as to both

edges of CK.

Read and write accesses to the DDR SDRAM are

burst oriented; accesses start at a selected location and

continue for a programmed number of locations in a

programmed sequence. Accesses begin with the regis-

tration of an ACTIVE command, which is then fol-

lowed by a READ or WRITE command. The address

bits registered coincident with the ACTIVE command

are used to select the bank and row to be accessed. The

address bits registered coincident with the READ or

WRITE command are used to select the bank and the

starting column location for the burst access.

The DDR SDRAM provides for programmable READ

or WRITE burst lengths of 2, 4, or 8 locations. An auto

precharge function may be enabled to provide a self-

timed row precharge that is initiated at the end of the

burst access.

As with standard SDR SDRAMs, the pipelined,

multibank architecture of DDR SDRAMs allows for

concurrent operation, thereby providing high effective

bandwidth by hiding row precharge and activation

time.

An auto refresh mode is provided, along with a

power-saving power-down mode. All inputs are com-

patible with the JEDEC Standard for SSTL_2. All full

drive strength outputs are SSTL_2, Class II compatible.

NOTE: 1. The functionality and the timing specifications

discussed in this data sheet are for the DLL-enabled

mode of operation.

2. Throughout the data sheet, the various figures and

text refer to DQs as “DQ.” The DQ term is to be

interpreted as any and all DQ collectively, unless

specifically stated otherwise. Additionally, the x16

is divided in to two bytes—the lower byte and upper

byte. For the lower byte (DQ0 through DQ7) DM

refers to LDM and DQS refers to LDQS; and for the

upper byte (DQ8 through DQ15) DM refers to UDM

and DQS refers to UDQS.

(Note: xx= 7, 75, or 8)

256Mb DDR SDRAM PART NUMBERS

PART NUMBER CONFIGURATION I/O DRIVE LEVEL REFRESH OPTION PACKAGE

MT46V128M4TH-xx 128 Meg x 4 Full Drive Standard 66-pin TSOP (27mm)

MT46V128M4TH-xxL 128 Meg x 4 Full Drive Low Power 66-pin TSOP (27mm)

MT46V64M8TH-xx 64 Meg x 8 Full Drive Standard 66-pin TSOP (27mm)

MT46V64M8TH-xxL 64 Meg x 8 Full Drive Low Power 66-pin TSOP (27mm)

MT46V32M16D1TH-xx 32 Meg x 16 Full Drive Standard 66-pin TSOP (27mm)

MT46V32M16D1TH-xxL 32 Meg x 16 Full Drive Low Power 66-pin TSOP (27mm)

MT46V32M16D2TH-xx 32 Meg x 16 Reduced Drive Standard 66-pin TSOP (27mm)

MT46V32M16D2TH-xxL 32 Meg x 16 Reduced Drive Low Power 66-pin TSOP (27mm)

MT46V32M16D3TH-xx 32 Meg x 16 Programmable Drive Standard 66-pin TSOP (27mm)

MT46V32M16D3TH-xxL 32 Meg x 16 Programmable Drive Low Power 66-pin TSOP (27mm)

512Mb: x4, x8, x16 DDR SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

TABLE OF CONTENTS

Functional Block Diagram – 128 Meg x 4 ............. 4

Functional Block Diagram – 64 Meg x 8 ............... 5

Functional Block Diagram – 32 Meg x 16 ............. 6

Pin Descriptions ...................................................... 7

Functional Description ......................................... 9

Initialization ...................................................... 9

Mode Register ............................................... 9

Burst Length ............................................ 9

Burst Type ................................................ 10

Read Latency ........................................... 11

Operating Mode ...................................... 11

Extended Mode Register ............................... 12

DLL Enable/Disable ................................. 12

Commands............................................................ 13

Truth Table 1 (Commands) ....................................... 13

Truth Table 1A (DM Operation) ................................. 13

Deselect .............................................................. 14

No Operation (NOP) .......................................... 14

Load Mode Register ........................................... 14

Active ................................................................ 14

Read ................................................................ 14

Write ................................................................ 14

Precharge ........................................................... 14

Auto Precharge .................................................. 14

Burst Terminate ................................................. 14

Auto Refresh ...................................................... 15

Self Refresh ......................................................... 15

Operation.............................................................. 16

Bank/Row Activation ....................................... 16

Reads ................................................................ 17

Read Burst .................................................... 18

Consecutive Read Bursts .............................. 19

Nonconsecutive Read Bursts ....................... 20

Random Read Accesses ................................ 21

Terminating a Read Burst ............................ 23

Read to Write ............................................... 24

Read to Precharge ......................................... 25

Writes ................................................................ 26

Write Burst .................................................... 27

Consecutive Write to Write ......................... 28

Nonconsecutive Write to Write .................. 29

Random Writes ............................................ 30

Write to Read – Uninterrupting .................. 31

Write to Read – Interrupting ....................... 32

Write to Read – Odd, Interrupting ............. 33

Write to Precharge – Uninterrupting .......... 34

Write to Precharge – Interrupting ............... 35

Write to Precharge – Odd, Interrupting ...... 36

Precharge ........................................................... 37

Power-Down ..................................................... 37

Truth Table 2 (CKE) ................................................. 38

Truth Table 3 (Current State, Same Bank) ..................... 39

Truth Table 4 (Current State, Different Bank) ................. 41

Operating Conditions

Absolute Maximum Ratings .................................... 43

DC Electrical and Operating Conditions ..................... 43

AC Input Operating Conditions ............................. 43

Capacitance – x4, x8 .............................................. 44

IDD Specifications and Conditions – x4, x8 ........... 45

Capacitance – x16 .................................................. 46

IDD Specifications and Conditions – x16 ............... 47

AC Electrical Characteristics (Timing Table) .......... 48

Slew Rate Derating Table ....................................... 49

Data Valid Window Derating ............................... 51

Voltage and Timing Waveforms

Nominal Output Drive Curves ......................... 54

Reduced Output Drive Curves (x16 only) ........ 55

Output Timing – tDQSQ and tQH - x4, x8 ...... 56

Output Timing – tDQSQ and tQH - x16 .......... 57

Output Timing – tAC and tDQSCK ................. 58

Input Timing ..................................................... 58

Input Voltage .................................................... 59

Initialize and Load Mode Registers .................. 60

Power-Down Mode .......................................... 61

Auto Refresh Mode ........................................... 62

Self Refresh Mode ............................................. 63

Reads

Bank Read - Without Auto Precharge ........ 64

Bank Read - With Auto Precharge .............. 65

Writes

Bank Write – Without Auto Precharge ....... 66

Bank Write – With Auto Precharge ............. 67

Write – DM Operation ................................ 68

66-pin TSOP (TH) dimensions ............................... 69

66-pin TSOP (TG) dimensions ............................... 70

512Mb: x4, x8, x16 DDR SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

FUNCTIONAL BLOCK DIAGRAM

128 Meg x 4

RAS#

CAS#

ROW-

ADDRESS

MUX

CS#

WE#

CK#

CONTROL

LOGIC

COLUMN-

ADDRESS

COUNTER/

LATCH

MODE REGISTERS

COMMAND

DECODE

A0-A12,

BA0, BA1

CKE

ADDRESS

2048

(x8)

8192

I/O GATING

DM MASK LOGIC

COLUMN

DECODER

BANK0

MEMORY

ARRAY

(8,192 x 2,048 x 8)

BANK0

ROW-

ADDRESS

LATCH

DECODER

8192

SENSE AMPLIFIERS

BANK

CONTROL

LOGIC

BANK1

BANK2

BANK3

REFRESH

COUNTER

INPUT

REGISTERS

RCVRS

out

DATA

DQS

MASK

DATA

COL0

DRVRS

DLL

MUX

DQS

GENERATOR

DQ0 -

DQ3, DM

DQS

READ

LATCH

WRITE

FIFO

DRIVERS

512Mb: x4, x8, x16 DDR SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

FUNCTIONAL BLOCK DIAGRAM

64 Meg x 8

RAS#

CAS#

ROW-

ADDRESS

MUX

CS#

WE#

CK#

CONTROL

LOGIC

COLUMN-

ADDRESS

COUNTER/

LATCH

MODE REGISTERS

COMMAND

DECODE

A0-A12,

BA0, BA1

CKE

ADDRESS

1024

(x16)

8192

I/O GATING

DM MASK LOGIC

COLUMN

DECODER

BANK0

MEMORY

ARRAY

(8192 x 1024 x 16)

BANK0

ROW-

ADDRESS

LATCH

DECODER

8192

SENSE AMPLIFIERS

BANK

CONTROL

LOGIC

BANK1

BANK2

BANK3

REFRESH

COUNTER

INPUT

REGISTERS

RCVRS

out

DATA

DQS

MASK

DATA

DRVRS

DLL

MUX

DQS

GENERATOR

DQ0 -

DQ7, DM

DQS

READ

LATCH

WRITE

FIFO

DRIVERS

512Mb: x4, x8, x16 DDR SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

FUNCTIONAL BLOCK DIAGRAM

32 Meg x 16

RAS#

CAS#

ROW-

ADDRESS

MUX

CS#

WE#

CK#

CONTROL

LOGIC

COLUMN-

ADDRESS

COUNTER/

LATCH

MODE REGISTERS

COMMAND

DECODE

A0-A12,

BA0, BA1

CKE

ADDRESS

512

(x32)

8192

I/O GATING

DM MASK LOGIC

COLUMN

DECODER

BANK0

MEMORY

ARRAY

(8,192 x 512 x 32)

BANK0

ROW-

ADDRESS

LATCH

DECODER

8192

SENSE AMPLIFIERS

BANK

CONTROL

LOGIC

BANK1

BANK2

BANK3

REFRESH

COUNTER

INPUT

REGISTERS

RCVRS

out

DATA

DQS

MASK

DATA

DRVRS

DLL

MUX

DQS

GENERATOR

DQ0 -

DQ15,

LDM,

UDM

LDQS

UDQS

READ

LATCH

WRITE

FIFO

DRIVERS

512Mb: x4, x8, x16 DDR SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

PIN DESCRIPTIONS

TSOP PIN NUMBERS SYMBOL TYPE DESCRIPTION

45, 46 CK, CK# Input Clock: CK and CK# are differential clock inputs. All address and

control input signals are sampled on the crossing of the positive

edge of CK and negative edge of CK#. Output data (DQs and

DQS) is referenced to the crossings of CK and CK#.

44 CKE Input Clock Enable: CKE HIGH activates and CKE LOW deactivates the

internal clock, input buffers and output drivers. Taking CKE LOW

provides PRECHARGE POWER-DOWN and SELF REFRESH

operations (all banks idle), or ACTIVE POWER-DOWN (row

ACTIVE in any bank). CKE is synchronous for POWER-DOWN

entry and exit, and for SELF REFRESH entry. CKE is asynchronous

for SELF REFRESH exit and for disabling the outputs. CKE must be

maintained HIGH throughout read and write accesses. Input

buffers (excluding CK, CK# and CKE) are disabled during POWER-

DOWN. Input buffers (excluding CKE) are disabled during SELF

REFRESH. CKE is an SSTL_2 input but will detect an LVCMOS

LOW level after V

is applied.

24 CS# Input Chip Select: CS# enables (registered LOW) and disables (regis-

tered HIGH) the command decoder. All commands are masked

when CS# is registered HIGH. CS# provides for external bank

selection on systems with multiple banks. CS# is considered part

of the command code.

23, 22, 21 RAS#, CAS#, Input Command Inputs: RAS#, CAS#, and WE# (along with CS#) define the

WE# command being entered.

47 DM Input Input Data Mask: DM is an input mask signal for write data. Input

20, 47 LDM, UDM data is masked when DM is sampled HIGH along with that input data

during a WRITE access. DM is sampled on both edges of DQS.

Although DM pins are input-only, the DM loading is designed to

match that of DQ and DQS pins. For the x16 , LDM is DM for DQ0-

DQ7 and UDM is DM for DQ8-DQ15. Pin 20 is a NC on x4 and x8

26, 27 BA0, BA1 Input Bank Address Inputs: BA0 and BA1 define to which bank an

ACTIVE, READ, WRITE, or PRECHARGE command is being applied.

29-32, 35-40, A0–A12 Input Address Inputs: Provide the row address for ACTIVE commands, and

28, 41, 42 the column address and auto precharge bit (A10) for READ/WRITE

commands, to select one location out of the memory array in the

respective bank. A10 sampled during a PRECHARGE command

determines whether the PRECHARGE applies to one bank (A10 LOW,

bank selected by BA0, BA1) or all banks (A10 HIGH). The address

inputs also provide the op-code during a MODE REGISTER SET

command. BA0 and BA1 define which mode register (mode register

or extended mode register) is loaded during the LOAD MODE

2, 4, 5, 7, 8, 10, 11, 13, DQ0–15 I/O Data Input/Output: Data bus for x16 (4, 7, 10, 13, 54, 57, 60, and 63

54, 56, 57, 59, 60, 62, are NC for x8), (2, 4, 7, 8,10, 13, 54, 57, 59, 60, 63, and 65 for x4).

63, 65

(continued on next page)

512Mb: x4, x8, x16 DDR SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

PIN DESCRIPTIONS (continued)

TSOP PIN NUMBERS SYMBOL TYPE DESCRIPTION

RESERVED NC PINS1

TSOP PIN NUMBERS SYMBOL TYPE DESCRIPTION

17 A13 I Address input for 1Gb devices.

NOTE: 1. NC pins not listed may also be reserved for other uses now or in the future. This table simply defines specific NC pins

deemed to be of importance.

2, 5, 8, 11, 56, 59, 62, 65 DQ0-7 I/O Data Input/Output: Data bus for x8 (2, 8, 59 and 65 are NC for x4).

5, 11, 56, 62 DQ0-3 I/O Data Input/Output: Data bus for x4.

51 DQS I/O Data Strobe: Output with read data, input with write data. DQS is

16, 51 LDQS, UDQS edge-aligned with read data, centered in write data. It is used to

capture data. For the x16 , LDQS is DQS for DQ0-DQ7 and UDQS is

DQS for DQ8-DQ15. Pin 16 is NC on x4 and x8.

50 DNU –Do Not Use: Must float to minimize noise.

3, 9, 15, 55, 61 VDDQ Supply DQ Power Supply: +2.5V ±0.2V. Isolated on the die for improved

noise immunity.

6, 12, 52, 58, 64 VSSQ Supply DQ Ground. Isolated on the die for improved noise immunity.

1, 18, 33 VDD Supply Power Supply: +2.5V ±0.2V.

34, 48, 66 VSS Supply Ground.

49 VREF Supply SSTL_2 reference voltage.

14, 17, 19, 25, 43, 53 NC –No Connect: These pins should be left unconnected.

512Mb: x4, x8, x16 DDR SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

FUNCTIONAL DESCRIPTION

The 512Mb DDR SDRAM is a high-speed CMOS,

dynamic random-access memory containing

536,870,912 bits. The 512Mb DDR SDRAM is internally

configured as a quad-bank DRAM.

The 512Mb DDR SDRAM uses a double data rate

architecture to achieve high-speed operation. The

double data rate architecture is essentially a 2n-prefetch

architecture, with an interface designed to transfer two

data words per clock cycle at the I/O pins. A single read

or write access for the 512Mb DDR SDRAM consists of

a single 2n-bit wide, one-clock-cycle data transfer at the

internal DRAM core and two corresponding n-bit wide,

one-half-clock-cycle data transfers at the I/O pins.

Read and write accesses to the DDR SDRAM are

burst oriented; accesses start at a selected location and

continue for a programmed number of locations in a

programmed sequence. Accesses begin with the regis-

tration of an ACTIVE command, which is then fol-

lowed by a READ or WRITE command. The address

bits registered coincident with the ACTIVE command

are used to select the bank and row to be accessed (BA0,

BA1 select the bank; A0-A12 select the row). The ad-

dress bits registered coincident with the READ or WRITE

command are used to select the starting column loca-

tion for the burst access.

Prior to normal operation, the DDR SDRAM must

be initialized. The following sections provide detailed

information covering device initialization, register defi-

nition, command descriptions and device operation.

Initialization

DDR SDRAMs must be powered up and initialized

in a predefined manner. Operational procedures other

than those specified may result in undefined opera-

tion. Power must first be applied to VDD and VDDQ

simultaneously, and then to VREF (and to the system

VTT). VTT must be applied after VDDQ to avoid device

latch-up, which may cause permanent damage to the

device. VREF can be applied any time after VDDQ but is

expected to be nominally coincident with VTT. Except

for CKE, inputs are not recognized as valid until after

VREF is applied. CKE is an SSTL_2 input but will detect

an LVCMOS LOW level after VDD is applied. Maintain-

ing an LVCMOS LOW level on CKE during power-up

is required to ensure that the DQ and DQS outputs

will be in the High-Z state, where they will remain until

driven in normal operation (by a read access). After all

power supply and reference voltages are stable, and the

clock is stable, the DDR SDRAM requires a 200µs delay

prior to applying an executable command.

Once the 200µs delay has been satisfied, a DESE-

LECT or NOP command should be applied, and CKE

should be brought HIGH. Following the NOP com-

mand, a PRECHARGE ALL command should be ap-

plied. Next a LOAD MODE REGISTER command

should be issued for the extended mode register (BA1

LOW and BA0 HIGH) to enable the DLL, followed by

another LOAD MODE REGISTER command to the

mode register (BA0/BA1 both LOW) to reset the DLL

and to program the operating parameters. Two-hun-

dred clock cycles are required between the DLL reset

and any READ command. A PRECHARGE ALL com-

mand should then be applied, placing the device in the

all banks idle state.

Once in the idle state, two AUTO REFRESH cycles

must be performed (tRFC must be satisfied.) Addition-

ally, a LOAD MODE REGISTER command for the

mode register with the reset DLL bit deactivated (i.e., to

program operating parameters without resetting the

DLL) is required. Following these requirements, the

DDR SDRAM is ready for normal operation.

MODE REGISTER

The mode register is used to define the specific mode

of operation of the DDR SDRAM. This definition

includes the selection of a burst length, a burst type, a

CAS latency and an operating mode, as shown in

Figure 1. The mode register is programmed via the

MODE REGISTER SET command (with BA0 = 0 and

BA1 = 0) and will retain the stored information until it

is programmed again or the device loses power (except

for bit A8, which is self-clearing).

Reprogramming the mode register will not alter the

contents of the memory, provided it is performed

correctly. The mode register must be loaded (reloaded)

when all banks are idle and no bursts are in progress,

and the controller must wait the specified time before

initiating the subsequent operation. Violating either of

these requirements will result in unspecified operation.

Mode register bits A0-A2 specify the burst length, A3

specifies the type of burst (sequential or interleaved),

A4-A6 specify the CAS latency, and A7-A12 specify the

operating mode.

Burst Length

Read and write accesses to the DDR SDRAM are

burst oriented, with the burst length being program-

mable, as shown in Figure 1. The burst length deter-

mines the maximum number of column locations that

can be accessed for a given READ or WRITE command.

Burst lengths of 2, 4, or 8 locations are available for

both the sequential and the interleaved burst types.

512Mb: x4, x8, x16 DDR SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

Figure 1

Mode Register Definition

Reserved states should not be used, as unknown

operation or incompatibility with future versions may

result.

When a READ or WRITE command is issued, a

block of columns equal to the burst length is effectively

selected. All accesses for that burst take place within this

block, meaning that the burst will wrap within the

block if a boundary is reached. The block is uniquely

selected by A1-Ai when the burst length is set to two, by

A2-Ai when the burst length is set to four and by A3-Ai

when the burst length is set to eight (where Ai is the

most significant column address bit for a given con-

figuration). The remaining (least significant) address

Table 1

Burst Definition

Burst Starting Column Order of Accesses Within a Burst

Length Address Type = Sequential Type = Interleaved

20 0-1 0-1

1 1-0 1-0

A1 A0

0 0 0-1-2-3 0-1-2-3

40 1 1-2-3-0 1-0-3-2

1 0 2-3-0-1 2-3-0-1

1 1 3-0-1-2 3-2-1-0

A2 A1 A0

0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7

0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6

0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5

80 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4

1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3

1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2

1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1

1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0

NOTE: 1. For a burst length of two, A1-Ai select the two-

data-element block; A0 selects the first access

within the block.

2. For a burst length of four, A2-Ai select the four-

data-element block; A0-A1 select the first access

within the block.

3. For a burst length of eight, A3-Ai select the eight-

data-element block; A0-A2 select the first access

within the block.

4. Whenever a boundary of the block is reached

within a given sequence above, the following

access wraps within the block.

bit(s) is (are) used to select the starting location within

the block. The programmed burst length applies to

both READ and WRITE bursts.

Burst Type

Accesses within a given burst may be programmed

to be either sequential or interleaved; this is referred to

as the burst type and is selected via bit M3.

The ordering of accesses within a burst is deter-

mined by the burst length, the burst type and the

starting column address, as shown in Table 1.

M3 = 0

Reserved

M3 = 1

Reserved

Operating Mode

Normal Operation

Normal Operation/Reset DLL

All other states reserved

Valid

Burst Type

Sequential

Interleaved

CAS Latency

Reserved

2.5

Reserved

Burst Length

Burst LengthCAS Latency BT0*

A9 A7 A6 A5 A4 A3

A8 A2 A1 A0

Mode Register (Mx)

Address Bus

976543

8210

M6-M0

M8 M7

Operating Mode

A10

A12 A11

BA1

BA0

* M14 and M13 (BA0 and BA1)

must be “0, 0” to select the

base mode register (vs. the

extended mode register).

M9M10M12 M11

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DDR SDRAM

ADVANCE

Table 2

CAS Latency (CL)

Read Latency

The READ latency is the delay, in clock cycles,

between the registration of a READ command and the

availability of the first bit of output data. The latency

can be set to 2, or 2.5 clocks, as shown in Figure 2.

If a READ command is registered at clock edge n,

and the latency is m clocks, the data will be available

nominally coincident with clock edge n + m. Table 2

indicates the operating frequencies at which each CAS

latency setting can be used.

Reserved states should not be used as unknown

operation or incompatibility with future versions may

result.

Figure 2

CAS Latency

Operating Mode

The normal operating mode is selected by issuing a

MODE REGISTER SET command with bits A7-A12

each set to zero, and bits A0-A6 set to the desired values.

A DLL reset is initiated by issuing a MODE REGISTER

SET command with bits A7 and A9-A12 each set to

zero, bit A8 set to one, and bits A0-A6 set to the desired

values. Although not required by the Micron device,

JEDEC specifications recommend when a LOAD MODE

should always be followed by a LOAD MODE REGIS-

TER command to select normal operating mode.

All other combinations of values for A7-A12 are

reserved for future use and/or test modes. Test modes

and reserved states should not be used because un-

known operation or incompatibility with future ver-

sions may result.

CK#

COMMAND

DQS

CL = 2

READ NOP NOP NOP

Burst Length = 4 in the cases shown

Shown with nominal tAC and nominal tDSDQ

CK#

COMMAND

DQS

CL = 2.5

T0 T1 T2 T2n T3 T3n

DON’T CARETRANSITIONING DATA

ALLOWABLE OPERATING

FREQUENCY (MHz)

SPEED CL = 2 CL = 2.5

-7 83 ≤ f ≤ 133 83 ≤ f ≤ 143

-75 83 ≤ f ≤ 100 83 ≤ f ≤133

-8 83 ≤ f ≤ 100 83 ≤ f ≤125

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Figure 3

Extended Mode Register Definition

EXTENDED MODE REGISTER

The extended mode register controls functions be-

yond those controlled by the mode register; these

additional functions are DLL enable/disable and

output drive strength. These functions are controlled

via the bits shown in Figure 3. The extended mode

TER command to the mode register (with BA0 = 1 and

BA1 = 0) and will retain the stored information until it

is programmed again or the device loses power. The

enabling of the DLL should always be followed by a

LOAD MODE REGISTER command to the mode regis-

ter (BA0/BA1 both LOW) to reset the DLL.

The extended mode register must be loaded when

all banks are idle and no bursts are in progress, and the

controller must wait the specified time before initiating

any subsequent operation. Violating either of these

requirements could result in unspecified operation.

Output Drive Strength

The normal drive strength for all outputs are speci-

fied to be SSTL2, Class II. The x16 supports an option

for reduced drive. This option is intended for the

support of the lighter load and/or point-to-point

environments. The selection of the reduced drive

strength will alter the DQs and DQSs from SSTL2, Class

II drive strength to a reduced drive strength, which is

approximately 54% of the SSTL2, Class II drive strength.

Micron will support these x16 options: 1) Full drive

strength only (not programmable), 2) Reduced drive

strength only (not programable), and 3) Program-

mable full or reduced drive strength.

DLL Enable/Disable

The DLL must be enabled for normal operation.

DLL enable is required during power-up initialization

and upon returning to normal operation after having

disabled the DLL for the purpose of debug or evalua-

tion. (When the device exits self refresh mode, the DLL

is enabled automatically.) Any time the DLL is enabled,

200 clock cycles must occur before a READ command

can be issued.

Operating Mode

Reserved

–

Valid

–

DLL

Enable

Disable

DLL

A9 A7 A6 A5 A4 A3

A8 A2 A1 A0

Extended Mode

Address Bus

976543

8210

Drive Strength

Normal

Reduced

E12

–

QFC Function

Disabled

Reserved

E1,

Operating Mode

A10

A11A12

BA0 BA1

1314

NOTE: 1. E14 and E13 (BA0 and BA1) must be “1, 0” to select the

Extended Mode Register (vs. the base Mode Register).

2. The reduced drive strength option is not supported on

the x4 and x8 versions: and is only available on the D3 version

of the x16 device.

3. The QFC# option is not supported.

E2,E3E4

–

E6 E5

E7E8E9

–

E10E11

–

E12

DSQFC

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appear following the Operation section; these tables

provide current state/next state information.

COMMANDS

Truth Table 1 provides a quick reference of avail-

able commands. This is followed by a verbal descrip-

tion of each command. Two additional Truth Tables

NOTE: 1. CKE is HIGH for all commands shown except SELF REFRESH.

2. BA0-BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register;

BA0 = 1, BA1 = 0 select extended mode register; other combinations of BA0-BA1 are reserved). A0-A12 provide the op-

code to be written to the selected mode register.

3. BA0-BA1 provide bank address and A0-A12 provide row address.

4. BA0-BA1 provide bank address; A0-Ai provide column address (where i = 9 for x16, 9,11 for x8, and 9, 11, 12 for x4);

A10 HIGH enables the auto precharge feature (nonpersistent), and A10 LOW disables the auto precharge feature.

5. A10 LOW: BA0-BA1 determine which bank is precharged.

A10 HIGH: all banks are precharged and BA0-BA1 are “Don’t Care.”

6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.

7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.

8. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for READ

bursts with auto precharge enabled and for WRITE bursts.

9. DESELECT and NOP are functionally interchangeable.

10. Used to mask write data; provided coincident with the corresponding data.

TRUTH TABLE 1 – COMMANDS

(Note: 1)

NAME (FUNCTION) CS# RAS# CAS# WE# ADDR NOTES

DESELECT (NOP) H X X X X 9

NO OPERATION (NOP) L H H H X 9

ACTIVE (Select bank and activate row) L L H H Bank/Row 3

READ (Select bank and column, and start READ burst) L H L H Bank/Col 4

WRITE (Select bank and column, and start WRITE burst) L H L L Bank/Col 4

BURST TERMINATE L H H L X 8

PRECHARGE (Deactivate row in bank or banks) L L H L Code 5

AUTO REFRESH or SELF REFRESH L L L H X 6, 7

(Enter self refresh mode)

LOAD MODE REGISTER L L L L Op-Code 2

TRUTH TABLE 1A – DM OPERATION

(Note: 10)

NAME (FUNCTION) DM DQs NOTES

Write Enable L Valid

Write Inhibit HX

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DESELECT

The DESELECT function (CS# HIGH) prevents new

commands from being executed by the DDR SDRAM.

The DDR SDRAM is effectively deselected. Operations

already in progress are not affected.

NO OPERATION (NOP)

The NO OPERATION (NOP) command is used to

instruct the selected DDR SDRAM to perform a NOP

(CS# LOW). This prevents unwanted commands from

being registered during idle or wait states. Operations

already in progress are not affected.

LOAD MODE REGISTER

The mode registers are loaded via inputs A0–A12.

See mode register descriptions in the Register Defini-

tion section. The LOAD MODE REGISTER command

can only be issued when all banks are idle, and a

subsequent executable command cannot be issued until

tMRD is met.

ACTIVE

The ACTIVE command is used to open (or activate)

a row in a particular bank for a subsequent access. The

value on the BA0, BA1 inputs selects the bank, and the

address provided on inputs A0–A12 selects the row.

This row remains active (or open) for accesses until a

PRECHARGE command is issued to that bank.

A PRECHARGE command must be issued before open-

ing a different row in the same bank.

READ

The READ command is used to initiate a burst read

access to an active row. The value on the BA0, BA1

inputs selects the bank, and the address provided on

inputs A0–Ai (where i = 9 for x16; 9, 11 for x8; or 9, 11,

and 12 for x4) selects the starting column location. The

value on input A10 determines whether or not auto

precharge is used. If auto precharge is selected, the row

being accessed will be precharged at the end of the

READ burst; if auto precharge is not selected, the row

will remain open for subsequent accesses.

WRITE

The WRITE command is used to initiate a burst write

access to an active row. The value on the BA0, BA1

inputs selects the bank, and the address provided on

inputs A0–Ai (where i = 9 for x16; 9 and 11 for x8; or 9,

11, and 12 for x4) selects the starting column location.

The value on input A10 determines whether or not auto

precharge is used. If auto precharge is selected, the row

being accessed will be precharged at the end of the

WRITE burst; if auto precharge is not selected, the row

will remain open for subsequent accesses. Input data

appearing on the DQs is written to the memory array

subject to the DM input logic level appearing coincident

with the data. If a given DM signal is registered LOW, the

corresponding data will be written to memory; if the

DM signal is registered HIGH, the corresponding data

inputs will be ignored, and a WRITE will not be executed

to that byte/column location.

PRECHARGE

The PRECHARGE command is used to deactivate the

open row in a particular bank or the open row in all

banks. The bank(s) will be available for a subsequent row

access a specified time (tRP) after the PRECHARGE com-

mand is issued. Input A10 determines whether one or all

banks are to be precharged, and in the case where only

one bank is to be precharged, inputs BA0, BA1 select the

bank. Otherwise BA0, BA1 are treated as “Don’t Care.”

Once a bank has been precharged, it is in the idle state

and must be activated prior to any READ or WRITE

commands being issued to that bank. A PRECHARGE

command will be treated as a NOP if there is no open

row in that bank (idle state), or if the previously open

row is already in the process of precharging.

AUTO PRECHARGE

Auto precharge is a feature which performs the

same individual-bank precharge function described

above, but without requiring an explicit command.

This is accomplished by using A10 to enable auto

precharge in conjunction with a specific READ or

WRITE command. A precharge of the bank/row that is

addressed with the READ or WRITE command is auto-

matically performed upon completion of the READ or

WRITE burst. Auto precharge is nonpersistent in that it

is either enabled or disabled for each individual READ

or WRITE command.

Auto precharge ensures that the precharge is initi-

ated at the earliest valid stage within a burst. This

“earliest valid stage” is determined as if an explicit

PRECHARGE command was issued at the earliest pos-

sible time, without violating tRAS (MIN), as described

for each burst type in the Operation section of this data

sheet. The user must not issue another command to the

same bank until the precharge time (tRP) is completed.

BURST TERMINATE

The BURST TERMINATE command is used to trun-

cate READ bursts (with auto precharge disabled). The

most recently registered READ command prior to the

BURST TERMINATE command will be truncated, as

shown in the Operation section of this data sheet. The

open page which the READ burst was terminated from

remains open.

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AUTO REFRESH

AUTO REFRESH is used during normal operation

of the DDR SDRAM and is analogous to CAS#-BE-

FORE-RAS# (CBR) REFRESH in FPM/EDO DRAMs.

This command is nonpersistent, so it must be issued

each time a refresh is required.

The addressing is generated by the internal refresh

controller. This makes the address bits a “Don’t Care”

during an AUTO REFRESH command. The 512Mb

DDR SDRAM requires AUTO REFRESH cycles at an

average interval of 7.8125µs (maximum).

To allow for improved efficiency in scheduling and

switching between tasks, some flexibility in the abso-

lute refresh interval is provided. A maximum of eight

AUTO REFRESH command can be posted to any given

DDR SDRAM, meaning that the maximum absolute

interval between any AUTO REFRESH command and

the next AUTO REFRESH command is 9 × 7.8125µs

(70.3µs). This maximum absolute interval is to allow

future support for DLL updates internal to the DDR

SDRAM to be restricted to AUTO REFRESH cycles,

without allowing excessive drift in tAC between up-

dates.

Although not a JEDEC requirement, to provide for

future functionality features, CKE must be active (High)

during the AUTO REFRESH period. The AUTO RE-

FRESH period begins when the AUTO REFRESH com-

mand is registered and ends tRFC latter.

SELF REFRESH

The SELF REFRESH command can be used to retain

data in the DDR SDRAM, even if the rest of the system

is powered down. When in the self refresh mode, the

DDR SDRAM retains data without external clocking.

The SELF REFRESH command is initiated like an AUTO

REFRESH command except CKE is disabled (LOW).

The DLL is automatically disabled upon entering SELF

REFRESH and is automatically enabled upon exiting

SELF REFRESH (200 clock cycles must then occur before

a READ command can be issued). Input signals except

CKE are “Don’t Care” during SELF REFRESH.

The procedure for exiting self refresh requires a

sequence of commands. First, CK must be stable prior

to CKE going back HIGH. Once CKE is HIGH, the DDR

SDRAM must have NOP commands issued for tXSNR

because time is required for the completion of any

internal refresh in progress. A simple algorithm for

meeting both refresh and DLL requirements is to apply

NOPs for 200 clock cycles before applying any other

command.

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ADVANCE

Operations

BANK/ROW ACTIVATION

Before any READ or WRITE commands can be

issued to a bank within the DDR SDRAM, a row in that

bank must be “opened.” This is accomplished via the

ACTIVE command, which selects both the bank and

the row to be activated, as shown in Figure 4.

After a row is opened with an ACTIVE command,

a READ or WRITE command may be issued to that

row, subject to the tRCD specification. tRCD (MIN)

should be divided by the clock period and rounded up

to the next whole number to determine the earliest

clock edge after the ACTIVE command on which a

READ or WRITE command can be entered. For ex-

ample, a tRCD specification of 20ns with a 133 MHz

clock (7.5ns period) results in 2.7 clocks rounded to 3.

This is reflected in Figure 5, which covers any case where

2 < tRCD (MIN)/tCK ≤ 3. (Figure 5 also shows the same

case for tRCD; the same procedure is used to convert

other specification limits from time units to clock

cycles).

A subsequent ACTIVE command to a different row

in the same bank can only be issued after the previous

active row has been “closed” (precharged). The mini-

mum time interval between successive ACTIVE com-

mands to the same bank is defined by tRC.

A subsequent ACTIVE command to another bank

can be issued while the first bank is being accessed,

which results in a reduction of total row-access over-

head. The minimum time interval between successive

ACTIVE commands to different banks is defined by

tRRD.

Figure 5

Example: Meeting tRCD (tRRD) MIN When 2 < tRCD (tRRD) MIN/tCK ≤≤

≤≤

≤ 3

Figure 4

Activating a Specific Row in

a Specific Bank

CS#

WE#

CAS#

RAS#

CKE

A0-A12 RA

RA = Row Address

BA = Bank Address

HIGH

BA0,1 BA

CK#

COMMAND

BA0, BA1

ACT ACT

NOP

RRD t

RCD

CK#

Bank x Bank y

A0-A12

Row Row

NOP RD/WR

NOP

Bank y

Col

NOP

T0 T1 T2 T3 T4 T5 T6 T7

DON’T CARE

NOP

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ADVANCE

READs

READ bursts are initiated with a READ command,

as shown in Figure 6.

The starting column and bank addresses are pro-

vided with the READ command and auto precharge is

either enabled or disabled for that burst access. If auto

precharge is enabled, the row being accessed is

precharged at the completion of the burst. For the

generic READ commands used in the following illus-

trations, auto precharge is disabled.

During READ bursts, the valid data-out element

from the starting column address will be available

following the CAS latency after the READ command.

Each subsequent data-out element will be valid nomi-

nally at the next positive or negative clock edge (i.e., at

the next crossing of CK and CK#). Figure 7 shows

general timing for each possible CAS latency setting.

DQS is driven by the DDR SDRAM along with output

data. The initial LOW state on DQS is known as the

read preamble; the LOW state coincident with the last

data-out element is known as the read postamble.

Upon completion of a burst, assuming no other

commands have been initiated, the DQs will go

High-Z. A detailed explanation of tDQSQ (valid data-

out skew), tQH (data-out window hold), the valid

data window are depicted in Figure 27. A detailed

explanation of tDQSCK (DQS transition skew to CK)

and tAC (data-out transition skew to CK) is depicted in

Figure 28.

Data from any READ burst may be concatenated

with or truncated with data from a subsequent READ

command. In either case, a continuous flow of data

can be maintained. The first data element from the new

burst follows either the last element of a completed

burst or the last desired data element of a longer burst

which is being truncated. The new READ command

should be issued x cycles after the first READ command,

where x equals the number of desired data element

pairs (pairs are required by the 2n-prefetch architec-

ture). This is shown in Figure 8. A READ command can

be initiated on any clock cycle following a previous

READ command. Nonconsecutive read data is shown

for illustration in Figure 9. Full-speed random read

accesses within a page (or pages) can be performed as

shown in Figure 10.

Figure 6

READ Command

CS#

WE#

CAS#

RAS#

CKE

x4: A0-A9, A11, A12

x8: A0-A9, A11

x16: A0-A9

A10

BA0,1

HIGH

EN AP

DIS AP

x8: A12

x16: A11, A12

CK#

CA = Column Address

BA = Bank Address

EN AP = Enable Auto Precharge

DIS AP = Disable Auto Precharge

DON’T CARE

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Figure 7

READ Burst

CK#

COMMAND

READ NOP NOP NOP NOP NOP

ADDRESS

Bank a,

Col n

READ NOP NOP NOP NOP NOP

Bank a,

Col n

CL = 2

NOTE: 1. DO n = data-out from column n.

2. Burst length = 4.

3. Three subsequent elements of data-out appear in the programmed order following DO n.

4. Shown with nominal tAC, tDQSCK, and tDQSQ.

CK#

COMMAND

ADDRESS

DQS

CL = 2.5

DQS

T0 T1 T2 T3T2n T3n T4 T5

DON’T CARE TRANSITIONING DATA

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Figure 8

Consecutive READ Bursts

CK#

COMMAND READ NOP READ NOP NOP NOP

ADDRESS Bank,

Col n

Bank,

Col b

COMMAND READ NOP READ NOP NOP NOP

ADDRESS Bank,

Col n

Bank,

Col b

CL = 2

CK#

COMMAND

ADDRESS

DQS

CL = 2.5

DQS

T0 T1 T2 T3T2n T3n T4 T5T4n T5n

NOTE: 1. DO n (or b) = data-out from column n (or column b).

2. Burst length = 4 or 8 (if 4, the bursts are concatenated; if 8, the second burst interrupts the first).

3. Three subsequent elements of data-out appear in the programmed order following DO n.

4. Three (or seven) subsequent elements of data-out appear in the programmed order following DO b.

5. Shown with nominal tAC, tDQSCK, and tDQSQ.

6. Example applies only when READ commands are issued to same device.

DON’T CARE TRANSITIONING DATA

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Figure 9

Nonconsecutive READ Bursts

CK#

COMMAND READ NOP NOP NOP NOP NOP

ADDRESS Bank,

Col n

READ

Bank,

Col b

COMMAND

ADDRESS

CL = 2

CK#

COMMAND

ADDRESS

DQS

CL = 2.5

DQS

T0 T1 T2 T3T2n T3n T4 T5 T5n T6

NOTE: 1. DO n (or b) = data-out from column n (or column b).

2. Burst length = 4 or 8 (if 4, the bursts are concatenated; if 8, the second burst interrupts the first).

3. Three subsequent elements of data-out appear in the programmed order following DO n.

4. Three (or seven) subsequent elements of data-out appear in the programmed order following DO b.

5. Shown with nominal tAC, tDQSCK, and tDQSQ.

6. Example applies when READ commands are issued to different devices or nonconsecutive READs.

READ NOP NOP NOP NOP NOP

Bank,

Col n

READ

Bank,

Col b

T0 T1 T2 T3T2n T3n T4 T5 T5n T6

DON’T CARE TRANSITIONING DATA

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Figure 10

Random READ Accesses

CK#

COMMAND READ READ READ NOP NOP

ADDRESS Bank,

Col n

Bank,

Col x

Bank,

Col b

Bank,

Col x

Bank,

Col b

READ

Bank,

Col g

COMMAND

ADDRESS

CL = 2

CK#

COMMAND

ADDRESS

DQS

CL = 2.5

DQS

T0 T1 T2 T3T2n T3n T4 T5T4n T5n

NOTE: 1. DO n (or x or b or g) = data-out from column n (or column x or column b or column g).

2. Burst length = 2 or 4 or 8 (if 4 or 8, the following burst interrupts the previous).

3. n' or x' or b' or g' indicates the next data-out following DO n or DO x or DO b or DO g, respectively.

4. READs are to an active row in any bank.

5. Shown with nominal

AC,

DQSCK, and

DQSQ.

READ READ READ NOP NOP

Bank,

Col n

READ

Bank,

Col g

T0 T1 T2 T3T2n T3n T4 T5T4n T5n

DON’T CARE TRANSITIONING DATA

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DDR SDRAM

ADVANCE

Data from any READ burst may be truncated with

a BURST TERMINATE command, as shown in Figure

11. The BURST TERMINATE latency is equal to the

READ (CAS) latency, i.e., the BURST TERMINATE

command should be issued x cycles after the READ

command, where x equals the number of desired data

element pairs (pairs are required by the 2n-prefetch

architecture).

Data from any READ burst must be completed or

truncated before a subsequent WRITE command can

be issued. If truncation is necessary, the BURST TERMI-

NATE command must be used, as shown in Figure 12.

The tDQSS (MIN) case is shown; the tDQSS (MAX) case

has a longer bus idle time. (tDQSS [MIN] and tDQSS

[MAX] are defined in the section on WRITEs.)

A READ burst may be followed by, or truncated

with, a PRECHARGE command to the same bank

provided that auto precharge was not activated. The

PRECHARGE command should be issued x cycles after

the READ command, where x equals the number of

desired data element pairs (pairs are required by the 2n-

prefetch architecture). This is shown in Figure 13.

Following the PRECHARGE command, a subsequent

command to the same bank cannot be issued until tRP

is met. Note that part of the row precharge time is

hidden during the access of the last data elements.

READs (continued)

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DDR SDRAM

ADVANCE

Figure 11

Terminating a READ Burst

CK#

COMMAND

READ BST

NOP NOP NOP NOP

ADDRESS

Bank a,

Col n

READ BST

NOP NOP NOP NOP

Bank a,

Col n

CL = 2

NOTE: 1. DO n = data-out from column n.

2. Burst length = 4.

3. Subsequent element of data-out appears in the programmed order following DO n.

4. Shown with nominal tAC, tDQSCK, and tDQSQ.

5. BST = BURST TERMINATE command, page remains open.

CK#

COMMAND

ADDRESS

DQS

CL = 2.5

DQS

T0 T1 T2 T3T2n T4 T5

DON’T CARE TRANSITIONING DATA

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512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

Figure 12

READ to WRITE

CK#

COMMAND READ BST7NOP NOP NOP

ADDRESS Bank,

Col n

WRITE

Bank,

Col b

T0 T1 T2 T3T2n T4 T5T4n T5n

NOTE: 1. DO n = data-out from column n.

2. DI b = data-in from column b.

3. Burst length = 4 in the cases shown (applies for bursts of 8 as well; if the burst length is 2,

the BST command shown can be NOP).

4. One subsequent element of data-out appears in the programmed order following DO n.

5. Data-in elements are applied following DI b in the programmed order.

6. Shown with nominal tAC, tDQSCK, and tDQSQ.

7. BST = BURST TERMINATE command, page remains open.

CL = 2

DQS

(MIN)

DQSS

CK#

COMMAND READ BST7NOP WRITE NOP

ADDRESS Bank a,

Col n

NOP

T0 T1 T2 T3T2n T4 T5 T5n

CL = 2.5

DQS

(MIN)

DQSS

DON’T CARE TRANSITIONING DATA

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DDR SDRAM

ADVANCE

Figure 13

READ to PRECHARGE

CK#

COMMAND

READ NOP PRE NOP NOP ACT

ADDRESS Bank a,

Col n

Bank a,

(a or all)

Bank a,

Row

READ NOP PRE NOP NOP ACT

Bank a,

Col n

CL = 2 tRP

tRP

NOTE: 1. DO n = data-out from column n.

2. Burst length = 4, or an interrupted burst of 8.

3. Three subsequent elements of data-out appear in the programmed order following DO n.

4. Shown with nominal tAC, tDQSCK, and tDQSQ.

5. READ to PRECHARGE equals two clocks, which allows two data pairs of data-out.

6. PRE = PRECHARGE command; ACT = ACTIVE command.

CK#

COMMAND

ADDRESS

DQS

CL = 2.5

DQS

T0 T1 T2 T3T2n T3n T4 T5

Bank a,

(a or all)

Bank a,

Row

DON’T CARE TRANSITIONING DATA

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512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

WRITEs

WRITE bursts are initiated with a WRITE com-

mand, as shown in Figure 14.

The starting column and bank addresses are pro-

vided with the WRITE command, and auto precharge

is either enabled or disabled for that access. If auto

precharge is enabled, the row being accessed is

precharged at the completion of the burst. For the

generic WRITE commands used in the following illus-

trations, auto precharge is disabled.

During WRITE bursts, the first valid data-in element

will be registered on the first rising edge of DQS follow-

ing the WRITE command, and subsequent data ele-

ments will be registered on successive edges of DQS. The

LOW state on DQS between the WRITE command and

the first rising edge is known as the write preamble; the

LOW state on DQS following the last data-in element

is known as the write postamble.

The time between the WRITE command and the

first corresponding rising edge of DQS (tDQSS) is

specified with a relatively wide range (from 75 percent

to 125 percent of one clock cycle). All of the WRITE

diagrams show the nominal case, and where the two

extreme cases (i.e., tDQSS [MIN] and tDQSS [MAX])

might not be intuitive, they have also been included.

Figure 15 shows the nominal case and the extremes of

tDQSS for a burst of 4. Upon completion of a burst,

assuming no other commands have been initiated, the

DQs will remain High-Z and any additional input data

will be ignored.

Data for any WRITE burst may be concatenated

with or truncated with a subsequent WRITE com-

mand. In either case, a continuous flow of input data

can be maintained. The new WRITE command can be

issued on any positive edge of clock following the

previous WRITE command. The first data element

from the new burst is applied after either the last

element of a completed burst or the last desired data

element of a longer burst which is being truncated. The

new WRITE command should be issued x cycles after

the first WRITE command, where x equals the number

of desired data element pairs (pairs are required by the

2n-prefetch architecture).

Figure 16 shows concatenated bursts of 4. An ex-

ample of nonconsecutive WRITEs is shown in Figure

17. Full-speed random write accesses within a page or

pages can be performed as shown in Figure 18.

Data for any WRITE burst may be followed by a

subsequent READ command. To follow a WRITE with-

out truncating the WRITE burst, tWTR should be met

as shown in Figure 19.

Data for any WRITE burst may be truncated by a

subsequent READ command, as shown in Figure 20.

Note that only the data-in pairs that are registered

Figure 14

WRITE Command

prior to the tWTR period are written to the internal

array, and any subsequent data-in should be masked

with DM as shown in Figure 21.

Data for any WRITE burst may be followed by a

subsequent PRECHARGE command. To follow a

WRITE without truncating the WRITE burst, tWR

should be met as shown in Figure 22.

Data for any WRITE burst may be truncated by a

subsequent PRECHARGE command, as shown in Fig-

ures 23 and 24. Note that only the data-in pairs that are

registered prior to the tWR period are written to the

internal array, and any subsequent data-in should be

masked with DM as shown in Figures 23 and 24. After

the PRECHARGE command, a subsequent command

to the same bank cannot be issued until tRP is met.

CS#

WE#

CAS#

RAS#

CKE

A10

BA0,1

HIGH

EN AP

DIS AP

CK#

CA = Column Address

BA = Bank Address

EN AP = Enable Auto Precharge

DIS AP = Disable Auto Precharg

DON’T CARE

x4: A0–A9, A11, A12

x8: A0-A9, A11

x16: A0–A9

x8: A12

x16:A11, A12

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DDR SDRAM

ADVANCE

Figure 15

WRITE Burst

DQS

NOTE: 1. DI b = data-in for column b.

2. Three subsequent elements of data-in are applied in the programmed

order following DI b.

3. An uninterrupted burst of 4 is shown.

4. A10 is LOW with the WRITE command (auto precharge is disabled).

DQSS (MAX)

DQSS (NOM)

DQSS (MIN)

tDQSS

CK#

COMMAND

WRITE NOP NOP

ADDRESS

Bank a,

Col b

NOP

T0 T1 T2 T3T2n

DQS

tDQSS

DQS

tDQSS

DON’T CARE TRANSITIONING DATA

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DDR SDRAM

ADVANCE

Figure 16

Consecutive WRITE to WRITE

CK#

COMMAND

WRITE NOP WRITE NOP NOP

ADDRESS

Bank,

Col b

NOP

Bank,

Col n

T0 T1 T2 T3T2n T4 T5T4n

NOTE: 1. DI b, etc. = data-in for column b, etc.

2. Three subsequent elements of data-in are applied in the programmed order following DI b.

3. Three subsequent elements of data-in are applied in the programmed order following DI n.

4. An uninterrupted burst of 4 is shown.

5. Each WRITE command may be to any bank.

T3nT1n

DQS

DON’T CARE TRANSITIONING DATA

DQSS

DQSS (NOM)

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DDR SDRAM

ADVANCE

FIGURE 17

Nonconsecutive WRITE to WRITE

CK#

COMMAND

WRITE NOP NOP NOP NOP

ADDRESS

Bank,

Col b

WRITE

Bank,

Col n

T0 T1 T2 T3T2n T4 T5T4n

NOTE: 1. DI b, etc. = data-in for column b, etc.

2. Three subsequent elements of data-in are applied in the programmed order following DI b.

3. Three subsequent elements of data-in are applied in the programmed order following DI n.

4. An uninterrupted burst of 4 is shown.

5. Each WRITE command may be to any bank.

T1n T5n

DQS

tDQSS (NOM) tDQSS

DON’T CARE TRANSITIONING DATA

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512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

Figure 18

Random WRITE Cycles

DQSS (NOM)

CK#

COMMAND

WRITE WRITE WRITE WRITE NOP

ADDRESS

Bank,

Col b

Bank,

Col x

Bank,

Col n

Bank,

Col g

WRITE

Bank,

Col a

T0 T1 T2 T3T2n T4 T5T4n

NOTE: 1. DI b, etc. = data-in for column b, etc.

2. b', etc. = the next data-in following DI b, etc., according to the programmed burst order.

3. Programmed burst length = 2, 4, or 8 in cases shown.

4. Each WRITE command may be to any bank.

T1n T3n T5n

DQS

gDI

DON’T CARE TRANSITIONING DATA

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512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

Figure 19

WRITE to READ – Uninterrupting

DQSS (NOM)

CK#

COMMAND

WRITE NOP NOP READ NOP NOP

ADDRESS

Bank a,

Col b

Bank a,

Col n

NOP

T0 T1 T2 T3T2n T4 T5

NOTE: 1. DI b = data-in for column b.

2. Three subsequent elements of data-in are applied in the programmed order following DI b.

3. An uninterrupted burst of 4 is shown.

4. tWTR is referenced from the first positive CK edge after the last data-in pair.

5. The READ and WRITE commands are to the same bank. However, the READ and WRITE commands may be

to different devices, in which case tWTR is not required and the READ command could be applied earlier.

6. A10 is LOW with the WRITE command (auto precharge is disabled).

T1n T6 T6n

WTR

CL = 2

DQS

DQSS

DQSS (MIN) CL = 2

DQS

DQSS

DQSS (MAX) CL = 2

DQS

DQSS

DON’T CARE TRANSITIONING DATA

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512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

Figure 20

WRITE to READ – Interrupting

DQSS (NOM)

CK#

COMMAND

WRITE NOP NOP NOP NOP NOP

ADDRESS

Bank a,

Col b

Bank a,

Col n

READ

T0 T1 T2 T3T2n T4 T5 T5n

NOTE: 1. DI b = data-in for column b.

2. An interrupted burst of 4 or 8 is shown; two data elements are written.

3. One subsequent element of data-in is applied in the programmed order following DI b.

4. tWTR is referenced from the first positive CK edge after the last data-in pair.

5. A10 is LOW with the WRITE command (auto precharge is disabled).

6. DQS is required at T2 and T2n (nominal case) to register DM.

7. If the burst of 8 was used, DM would not be required at T3 -T4n because the READ command would

mask the last two data elements.

T1n T6 T6n

WTR

CL = 2

DQS

DQSS (MIN) CL = 2

DQS

DQSS (MAX) CL = 2

DQS

DON’T CARE TRANSITIONING DATA

DQSS

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512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

Figure 21

WRITE to READ – Odd Number of Data, Interrupting

DQSS (NOM)

CK#

COMMAND

WRITE NOP NOP NOP NOP NOP

ADDRESS

Bank a,

Col b

Bank a,

Col n

READ

T0 T1 T2 T3T2n T4 T5

NOTE: 1. DI b = data-in for column b.

2. An interrupted burst of 4 is shown; one data element is written.

3. tWTR is referenced from the first positive CK edge after the last desired data-in pair (not the last two data elements).

4. A10 is LOW with the WRITE command (auto precharge is disabled).

5. DQS is required at T1n, T2, and T2n (nominal case) to register DM.

6. If the burst of 8 was used, DM would not be required at T3 -T4n because the READ command would mask the last

four data elements.

T1n T6 T6nT5n

WTR

CL = 2

DQS

DQSS (MIN) CL = 2

DQS

DQSS (MAX) CL = 2

DQS

DON’T CARE TRANSITIONING DATA

DQSS

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DDR SDRAM

ADVANCE

Figure 22

WRITE to PRECHARGE – Uninterrupting

tDQSS (NOM)

CK#

COMMAND WRITE NOP NOP NOP PRE7NOP

ADDRESS Bank a,

Col b

Bank,

(a or all)

NOP

T0 T1 T2 T3T2n T4 T5

NOTE: 1. DI b = data-in for column b.

2. Three subsequent elements of data-in are applied in the programmed order following DI b.

3. An uninterrupted burst of 4 is shown.

4. tWR is referenced from the first positive CK edge after the last data-in pair.

5. The PRECHARGE and WRITE commands are to the same bank. However, the PRECHARGE and WRITE commands may

be to different devices, in which case tWR is not required and the PRECHARGE command could be applied earlier.

6. A10 is LOW with the WRITE command (auto precharge is disabled).

7. PRE = PRECHARGE command.

T1n T6

tWR tRP

DQS

tDQSS (MIN)

DQS

tDQSS (MAX)

DQS

DON’T CARE TRANSITIONING DATA

tDQSS

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DDR SDRAM

ADVANCE

Figure 23

WRITE to Precharge – Interrupting

DQSS

DQSS (NOM)

CK#

COMMAND WRITE NOP NOP PRE

NOP NOP

ADDRESS Bank a,

Col b

Bank,

(a or all)

NOP

T0 T1 T2 T3T2n T4 T5

NOTE: 1. DI b = data-in for column b.

2. Subsequent element of data-in is applied in the programmed order following DI b.

3. An interrupted burst of 4 is shown; two data elements are written.

4. tWR is referenced from the first positive CK edge after the last data-in pair.

5. The PRECHARGE and WRITE commands are to the same bank.

6. A10 is LOW with the WRITE command (auto precharge is disabled).

7. DQS is required at T2 and T2n (nominal case) to register DM.

8. If the burst of 8 was used, DM would be required at T3 and T3n and not at T4 and T4n because the PRECHARGE

command would mask the last two data elements.

9. PRE = PRECHARGE command.

T1n T6

DQS

DQSS

DQSS (MIN)

DQS

DQSS

DQSS (MAX)

DQS

DON’T CARE TRANSITIONING DATA

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512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

Figure 24

WRITE to PRECHARGE

Odd Number of Data, Interrupting

tDQSS

tDQSS (NOM)

CK#

COMMAND

WRITE NOP NOP PRE9NOP NOP

ADDRESS

Bank a,

Col b

Bank,

(a or all)

NOP

T0 T1 T2 T3T2n T4 T5

NOTE: 1. DI b = data-in for column b.

2. Subsequent element of data-in is applied in the programmed order following DI b.

3. An interrupted burst of 4 is shown; one data element is written.

4. tWR is referenced from the first positive CK edge after the last data-in pair.

5. The PRECHARGE and WRITE commands are to the same bank.

6. A10 is LOW with the WRITE command (auto precharge is disabled).

7. DQS is required at T1n, T2 and T2n (nominal case) to register DM.

8. If the burst of 8 was used, DM would be required at T3 and T3n and not at T4 and T4n because the PRECHARGE

command would mask the last two data elements.

9. PRE = PRECHARGE command.

T1n T6

tWR tRP

DQS

tDQSS

tDQSS (MIN)

DQS

tDQSS

tDQSS (MAX)

DQS

DON’T CARE TRANSITIONING DATA

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512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

Figure 25

PRECHARGE Command

PRECHARGE

The PRECHARGE command (Figure 25) is used to

deactivate the open row in a particular bank or the

open row in all banks. The bank(s) will be available for

a subsequent row access some specified time (tRP) after

the PRECHARGE command is issued. Input A10 deter-

No READ/WRITE

access in progress Exit power-down mode

Enter power-down mode

CKE

CK#

COMMAND NOP

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

NOP VALID

T0 T1 T2 Ta0 Ta1 Ta2

VALID

DON’T CARE

mines whether one or all banks are to be precharged,

and in the case where only one bank is to be precharged,

inputs BA0, BA1 select the bank. When all banks are to

be precharged, inputs BA0, BA1 are treated as “Don’t

Care.” Once a bank has been precharged, it is in the idle

state and must be activated prior to any READ or

WRITE commands being issued to that bank.

POWER-DOWN (CKE NOT ACTIVE)

Unlike SDR SDRAMs, DDR SDRAMs require CKE to

be active at all times an access is in progress: from the

issuing of a READ or WRITE command until comple-

tion of the burst. Thus a clock suspend is not sup-

ported. For READs, a burst completion is defined when

the Read Postamble is satisfied; For WRITEs, a burst

completion is defined when the Write Postamble is

satisfied.

Power-down (Figure 26) is entered when CKE is

registered LOW. If power-down occurs when all banks

are idle, this mode is referred to as precharge power-

down; if power-down occurs when there is a row active

in any bank, this mode is referred to as active power-

down. Entering power-down deactivates the input

and output buffers, excluding CK, CK#, and CKE. For

maximum power savings, the DLL is frozen. Exiting

power-down requires the device to be at the same.

voltage and frequency as when it entered power-down.

However, power-down duration is limited by the

refresh requirements of the device (tREFC).

While in power-down, CKE LOW and a stable clock

signal must be maintained at the inputs of the DDR

SDRAM, while all other input signals are “Don’t Care.”

The power-down state is synchronously exited when

CKE is registered HIGH (in conjunction with a NOP or

DESELECT command). A valid executable command

may be applied one clock cycle later.

Figure 26

Power-Down

CS#

WE#

CAS#

RAS#

CKE

A10

BA0,1

HIGH

ALL BANKS

ONE BANK

A0–A9, A11, A12

CK#

BA = Bank Address (if A10 is LOW;

otherwise “Don’t Care”)

DON’T CARE

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512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

TRUTH TABLE 2 – CKE

(Notes: 1-4)

CKEn-1 CKEnCURRENT STATE COMMANDnACTIONnNOTES

L L Power-Down X Maintain Power-Down

Self Refresh X Maintain Self Refresh

L H Power-Down DESELECT or NOP Exit Power-Down

Self Refresh DESELECT or NOP Exit Self Refresh 5

H L All Banks Idle DESELECT or NOP Precharge Power-Down Entry

Bank(s) Active DESELECT or NOP Active Power-Down Entry

All Banks Idle AUTO REFRESH Self Refresh Entry

H H See Truth Table 3

NOTE: 1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge.

2. Current state is the state of the DDR SDRAM immediately prior to clock edge n.

3. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of COMMANDn.

4. All states and sequences not shown are illegal or reserved.

5. DESELECT or NOP commands should be issued on any clock edges occurring during the tXSR period. A minimum of 200

clock cycles is needed before applying a READ command for the DLL to lock.

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DDR SDRAM

ADVANCE

TRUTH TABLE 3 – CURRENT STATE BANK n - COMMAND TO BANK n

(Notes: 1-6; notes appear below and on next page)

CURRENT STATE CS# RAS# CAS# WE# COMMAND/ACTION NOTES

Any H X X X DESELECT (NOP/continue previous operation)

L H H H NO OPERATION (NOP/continue previous operation)

L L H H ACTIVE (select and activate row)

Idle L L L H AUTO REFRESH 7

LLLLLOAD MODE REGISTER 7

L H L H READ (select column and start READ burst) 10

Row Active L H L L WRITE (select column and start WRITE burst) 10

L L H L PRECHARGE (deactivate row in bank or banks) 8

Read L H L H READ (select column and start new READ burst) 10

(Auto- L H L L WRITE (select column and start WRITE burst) 10, 12

Precharge L L H L PRECHARGE (truncate READ burst, start PRECHARGE) 8

Disabled) L H H L BURST TERMINATE 9

Write L H L H READ (select column and start READ burst) 10, 11

(Auto- L H L L WRITE (select column and start new WRITE burst) 10

Precharge L L H L PRECHARGE (truncate WRITE burst, start PRECHARGE) 8, 11

Disabled)

NOTE:

1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Truth Table 2) and after tXSNR has been

met (if the previous state was self refresh).

2. This table is bank-specific, except where noted (i.e., the current state is for a specific bank and the com-

mands shown are those allowed to be issued to that bank when in that state). Exceptions are covered in

the notes below.

3. Current state definitions:

Idle: The bank has been precharged, and tRP has been met.

Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses

and no register accesses are in progress.

Read: A READ burst has been initiated, with auto precharge disabled, and has not yet

terminated or been terminated.

Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet

terminated or been terminated.

4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT

or NOP commands, or allowable commands to the other bank should be issued on any clock edge occur-

ring during these states. Allowable commands to the other bank are determined by its current state and

Truth Table 3, and according to Truth Table 4.

Precharging: Starts with registration of a PRECHARGE command and ends when tRP is met. Once

tRP is met, the bank will be in the idle state.

Row Activating: Starts with registration of an ACTIVE command and ends when tRCD is met.

Once tRCD is met, the bank will be in the “row active” state.

Read w/Auto-

Precharge Enabled: Starts with registration of a READ command with auto precharge enabled and ends

when tRP has been met. Once tRP is met, the bank will be in the idle state.

Write w/Auto-

Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled and ends

when tRP has been met. Once tRP is met, the bank will be in the idle state.

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512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

NOTE (continued):

5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP

commands must be applied on each positive clock edge during these states.

Refreshing: Starts with registration of an AUTO REFRESH command and ends when tRC is met.

Once tRC is met, the DDR SDRAM will be in the all banks idle state.

Accessing Mode

has been met. Once tMRD is met, the DDR SDRAM will be in the all banks idle state.

Precharging All: Starts with registration of a PRECHARGE ALL command and ends when tRP is met.

Once tRP is met, all banks will be in the idle state.

6. All states and sequences not shown are illegal or reserved.

7. Not bank-specific; requires that all banks are idle, and bursts are not in progress.

8. May or may not be bank-specific; if multiple banks are to be precharged, each must be in a valid state for

precharging.

9. Not bank-specific; BURST TERMINATE affects the most recent READ burst, regardless of bank.

10. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto precharge

enabled and READs or WRITEs with auto precharge disabled.

11. Requires appropriate DM masking.

12. A WRITE command may be applied after the completion of the READ burst; otherwise, a BURST TERMI-

NATE must be used to end the READ burst prior to asserting a WRITE command.

512Mb: x4, x8, x16 DDR SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

TRUTH TABLE 4 – CURRENT STATE BANK n - COMMAND TO BANK m

(Notes: 1-6; notes appear below and on next page)

CURRENT STATE CS # RAS # CAS# WE# COMMAND/ACTION NOTES

Any H X X X DESELECT (NOP/continue previous operation)

L H H H NO OPERATION (NOP/continue previous operation)

Idle XXXXAny Command Otherwise Allowed to Bank m

Row L L H H ACTIVE (select and activate row)

Activating, L H L H READ (select column and start READ burst) 7

Active, or L H L L WRITE (select column and start WRITE burst) 7

Precharging L L H L PRECHARGE

Read L L H H ACTIVE (select and activate row)

(Auto- L H L H READ (select column and start new READ burst) 7

Precharge L H L L WRITE (select column and start WRITE burst) 7, 9

Disabled) L L H L PRECHARGE

Write L L H H ACTIVE (select and activate row)

(Auto- L H L H READ (select column and start READ burst) 7, 8

Precharge L H L L WRITE (select column and start new WRITE burst) 7

Disabled) L L H L PRECHARGE

Read L L H H ACTIVE (select and activate row)

(With Auto- L H L H READ (select column and start new READ burst) 7, 3a

Precharge) L H L L WRITE (select column and start WRITE burst) 7, 9, 3a

L L H L PRECHARGE

Write L L H H ACTIVE (select and activate row)

(With Auto- L H L H READ (select column and start READ burst) 7, 3a

Precharge) L H L L WRITE (select column and start new WRITE burst) 7, 3a

L L H L PRECHARGE

NOTE:

1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Truth Table 2) and after tXSNR has been

met (if the previous state was self refresh).

2. This table describes alternate bank operation, except where noted (i.e., the current state is for bank n and

the commands shown are those allowed to be issued to bank m, assuming that bank m is in such a state that the

given command is allowable). Exceptions are covered in the notes below.

(Notes continued on next page)

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512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

NOTE (continued):

3.Current state definitions:

Idle: The bank has been precharged, and tRP has been met.

Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses

and no register accesses are in progress.

Read: A READ burst has been initiated, with auto precharge disabled, and has not yet

terminated or been terminated.

Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet

terminated or been terminated.

Read with Auto

Precharge Enabled: See following text – 3a

Write with Auto

Precharge Enabled: See following text – 3a

3a. The read with auto precharge enabled or write with auto precharge enabled states can each be

broken into two parts: the access period and the precharge period. For read with auto precharge,

the precharge period is defined as if the same burst was executed with auto precharge disabled and

then followed with the earliest possible PRECHARGE command that still accesses all of the data in

the burst. For write with auto precharge, the precharge period begins when tWR ends, with tWR

measured as if auto precharge was disabled. The access period starts with registration of the

command and ends where the precharge period (or tRP) begins.

During the precharge period of the read with auto precharge enabled or write with auto precharge

enabled states, ACTIVE, PRECHARGE, READ and WRITE commands to the other bank may be

applied; during the access period, only ACTIVE and PRECHARGE commands to the other bank may

be applied. In either case, all other related limitations apply (e.g., contention between read data

and write data must be avoided).

This means concurrent auto precharge is not supported.

4. AUTO REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle.

5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by

the current state only.

6. All states and sequences not shown are illegal or reserved.

7. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto precharge

enabled and READs or WRITEs with auto precharge disabled.

8. Requires appropriate DM masking.

9. A WRITE command may be applied after the completion of the READ burst; otherwise, a BURST TERMI-

NATE must be used to end the READ burst prior to asserting a WRITE command.

512Mb: x4, x8, x16 DDR SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

ABSOLUTE MAXIMUM RATINGS*

VDD Supply Voltage Relative to VSS ........-1V to +3.6V

VDDQ Supply Voltage Relative to VSS .....-1V to +3.6V

VREF and Inputs Voltage Relative to VSS ... -1V to +3.6V

I/O Pins Voltage Relative to VSS .. -0.5V to VDDQ +0.5V

Operating Temperature, TA (ambient) .. 0°C to +70°C

Storage Temperature (plastic) ........... -55°C to +150°C

Power Dissipation ................................................... 1W

Short Circuit Output Current ............................ 50mA

*Stresses greater than those listed under “Absolute

Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only, and functional

operation of the device at these or any other condi-

tions above those indicated in the operational sections

of this specification is not implied. Exposure to abso-

lute maximum rating conditions for extended periods

may affect reliability.

DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS

(Notes: 1–5, 16; notes appear on pages 50–53) (0°C ≤ TA ≤ +70°C; VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V)

PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES

Supply Voltage VDD 2.3 2.7 V 41

I/O Supply Voltage VDDQ 2.3 2.7 V 41, 44

I/O Reference Voltage VREF 0.49 x VDDQ 0.51 x VDDQ V 6, 44

I/O Termination Voltage (system) VTT VREF - 0.04 VREF + 0.04 V 7, 44

Input High (Logic 1) Voltage VIH(DC)VREF + 0.15 VDD + 0.3 V 28

Input Low (Logic 0) Voltage VIL(DC) -0.3 VREF - 0.15 V 28

Clock Input Voltage Level; CK and CK# VIN -0.3 VDDQ + 0.3 V

Clock Input Differential Voltage; CK and CK# VID 0.36 VDDQ + 0.6 V 8

Clock Input Crossing Point Voltage; CK and CK# VIX 1.15 1.35 V 9

INPUT LEAKAGE CURRENT

Any input 0V ≤ VIN ≤ VDD, VREF pin 0V ≤ VIN ≤ 1.35V II-2 2 µA

(All other pins not under test = 0V)

OUTPUT LEAKAGE CURRENT IOZ -5 5 µA

(DQs are disabled; 0V ≤ VOUT ≤ VDDQ)

OUTPUT LEVELS: Full drive option - x4, x8, x16

High Current (VOUT = VDDQ-0.373V, minimum VREF, minimum VTT)IOH -16.8 –mA 37, 39

Low Current (VOUT = 0.373V, maximum VREF, maximum VTT)IOL 16.8 –mA

OUTPUT LEVELS: Reduced drive option - x16 only

High Current (VOUT = VDDQ-0.763V, minimum VREF, minimum VTT)IOHR -9 –mA 38, 39

Low Current (VOUT = 0.763V, maximum VREF, maximum VTT)IOLR 9–mA

AC INPUT OPERATING CONDITIONS

(Notes: 1–5, 14, 16; notes appear on pages 50–53) (0°C ≤ TA ≤ +70°C; VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V)

PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES

Input High (Logic 1) Voltage VIH(AC)VREF + 0.310 –V 14, 28, 40

Input Low (Logic 0) Voltage VIL(AC)–VREF - 0.310 V 14, 28, 40

Clock Input Differential Voltage; CK and CK# VID(AC) 0.7 VDDQ + 0.6 V 8

Clock Input Crossing Point Voltage; CK and CK# VIX(AC) 0.5 x VDDQ - 0.2 0.5 x VDDQ + 0.2 V 9

I/O Reference Voltage VREF(AC) 0.49 x VDDQ 0.51 x VDDQV 6

512Mb: x4, x8, x16 DDR SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

CAPACITANCE (x4, x8)

(Note: 13; notes appear on pages 50–53)

PARAMETER SYMBOL MIN MAX UNITS NOTES

Delta Input/Output Capacitance: DQs, DQS, DM DCIO –0.50 pF 24

Delta Input Capacitance: Command and Address DCI1–0.50 pF 29

Delta Input Capacitance: CK, CK# DCI2–0.25 pF 29

Input/Output Capacitance: DQs, DQS, DM CIO 4.0 5.0 pF

Input Capacitance: Command and Address CI12.0 3.0 pF

Input Capacitance: CK, CK# CI22.0 3.0 pF

Input Capacitance: CKE CI32.0 3.0 pF

512Mb: x4, x8, x16 DDR SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

IDD SPECIFICATIONS AND CONDITIONS (x4, x8)

(Notes: 1–5, 10, 12, 14; notes appear on pages 50–53) (0°C ≤ TA ≤ +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V)

PARAMETER/CONDITION SYMBOL -7

-75

-8 UNITS NOTES

OPERATING CURRENT: One bank; Active-Precharge; IDD0TBD TBD TBD mA 22, 48

tRC = tRC(MIN); t

CK = tCK(MIN); DQ, DM, and DQS inputs

changing once per clock cyle; Address and control inputs

changing once every two clock cycles;

OPERATING CURRENT: One bank; Active-Read-Precharge; IDD1TBD TBD TBD mA 22, 48

Burst = 2; tRC = tRC(MIN); tCK = tCK(MIN); IOUT = 0mA;

Address and control inputs changing once per clock cycle

PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle; IDD2P 3 3 3 mA 23, 32

Power-down mode; tCK = tCK(MIN); CKE = LOW; 50

IDLE STANDBY CURRENT: CS# = HIGH; All banks idle; IDD2F 35 35 30 mA 51

CK = tCK(MIN); CKE = HIGH; Address and other control inputs

changing once per clock cycle.

VIN

VREF

for DQ, DQS, and DM

ACTIVE POWER-DOWN STANDBY CURRENT: One bank active; IDD3P 3 3 3 mA 23, 32

Power-down mode; tCK = tCK(MIN); CKE = LOW 50

ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; IDD3N 35 35 30 mA 22

One bank; Active-Precharge; t

RC = tRAS(MAX); tCK = tCK(MIN);

DQ, DM, and DQS inputs changing twice per clock cycle;

Address and other control inputs changing once per clock cycle

OPERATING CURRENT: Burst = 2; Reads; Continuous burst; IDD4R TBD TBD TBD mA 22, 48

One bank active; Address and control inputs changing once per

clock cycle; tCK = tCK(MIN); IOUT = 0mA

OPERATING CURRENT: Burst = 2; Writes; Continuous burst; IDD4W TBD TBD TBD mA 22

One bank active; Address and control inputs changing once per

clock cycle; tCK = tCK(MIN); DQ, DM, and DQS inputs

changing twice per clock cycle

AUTO REFRESH CURRENT tRC = t

RFC(MIN) IDD5TBD TBD TBD mA 22,50

tRC = 7.8125µs IDD66 6 6 mA 27,50

SELF REFRESH CURRENT: CKE ≤ 0.2V Standard IDD7TBD TBD TBD mA 11

Low power (L) IDD7TBD TBD TBD mA 11

OPERATING CURRENT: Four bank interleaving READs (BL=4) with I

8TBD TBD TBD mA 22, 49

auto precharge,

RC =

(MIN)

;

CK =

(MIN)

; Address and

control inputs change only during Active READ, or WRITE commands.

MAX

512Mb: x4, x8, x16 DDR SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

CAPACITANCE (x16)

(Note: 13; notes appear on pages 50–53)

PARAMETER SYMBOL MIN MAX UNITS NOTES

Delta Input/Output Capacitance: DQ0-DQ7, LDQS, LDM DCIOL –0.50 pF 24

Delta Input/Output Capacitance: DQ8-DQ15, UDQS, UDM DCIOU –0.50 pF 24

Delta Input Capacitance: Command and Address DCI1–0.50 pF 29

Delta Input Capacitance: CK, CK# DCI2–0.25 pF 29

Input/Output Capacitance: DQs, LDQS, UDQS, LDM, UDM CIO 4.0 5.0 pF

Input Capacitance: Command and Address CI12.0 3.0 pF

Input Capacitance: CK, CK# CI22.0 3.0 pF

Input Capacitance: CKE CI32.0 3.0 pF

512Mb: x4, x8, x16 DDR SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

IDD SPECIFICATIONS AND CONDITIONS (x16)

(Notes: 1–5, 10, 12, 14; notes appear on pages 50–53) (0°C ≤ TA ≤ +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V)

PARAMETER/CONDITION SYMBOL -7 -75 -8 UNITS NOTES

OPERATING CURRENT: One bank; Active-Precharge;

RC =

(MIN)

;

IDD0 TBD TBD TBD mA 22, 48

CK =

(MIN)

; DQ, DM, and DQS inputs changing once per clock

cyle; Address and control inputs changing once every two clock cycles;

OPERATING CURRENT: One bank; Active-Read-Precharge; IDD1TBD TBD TBD mA 22, 48

Burst = 2; tRC = tRC(MIN); tCK = tCK(MIN); IOUT = 0mA;

Address and control inputs changing once per clock cycle

PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle; IDD2P 3 3 3 mA 23, 32

Power-down mode; tCK = tCK(MIN); CKE = LOW; 50

IDLE STANDBY CURRENT: CS# = HIGH; All banks idle;

CK =

(MIN)

;

IDD2F 40 40 35 mA 51

CKE = HIGH; Address and other control inputs changing once per

clock cycle.

VIN

VREF

for DQ, DQS, and DM

ACTIVE POWER-DOWN STANDBY CURRENT: One bank active; IDD3P 3 3 3 mA 23, 32

Power-down mode; tCK = tCK(MIN); CKE = LOW 50

ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; IDD3N 35 35 30 mA 22

One bank; Active-Precharge; t

RC = tRAS(MAX); tCK = tCK(MIN);

DQ, DM, and DQS inputs changing twice per clock cycle; Address

and other control inputs changing once per clock cycle

OPERATING CURRENT: Burst = 2; Reads; Continuous burst; IDD4R TBD TBD TBD mA 22, 48

One bank active; Address and control inputs changing once per

clock cycle; tCK = tCK(MIN); IOUT = 0mA

OPERATING CURRENT: Burst = 2; Writes; Continuous burst; IDD4W TBD TBD TBD mA 22

One bank active; Address and control inputs changing once per

clock cycle; tCK = tCK(MIN); DQ, DM, and DQS inputs

changing twice per clock cycle

AUTO REFRESH CURRENT tRC = t

RFC(MIN) IDD5TBD TBD TBD mA 22,50

tRC = 7.8125µs IDD66 6 6 mA 27,50

SELF REFRESH CURRENT: CKE ≤ 0.2V Standard IDD7TBD TBD TBD mA 11

Low power (L) IDD7TBD TBD TBD mA 11

OPERATING CURRENT: Four bank interleaving READs (BL=4) with I

8TBD TBD TBD mA 22, 49

auto precharge with ,

RC =

(MIN)

;

CK =

(MIN)

; Address and

control inputs change only during Active READ, or WRITE commands.

MAX

512Mb: x4, x8, x16 DDR SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

(continued on following page)

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS

(Notes: 1–5, 14-17, 33; notes appear on pages 50–53) (0°C ≤ TA ≤ +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V)

AC CHARACTERISTICS -7 -75 -8

PARAMETER SYMBOL MIN MAX MIN MAX MIN MAX UNITS NOTES

Access window of DQs from CK/CK# tAC -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns

CK high-level width tCH 0.45 0.55 0.45 0.55 0.45 0.55 tCK 30

CK low-level width tCL 0.45 0.55 0.45 0.55 0.45 0.55 tCK 30

Clock cycle time CL = 2.5 tCK(2.5) 7 12 7.5 12 8 12 ns 52

CL = 2 tCK(2) 7.5 12 10 12 10 12 ns 52

DQ and DM input hold time relative to DQS tDH 0.5 0.5 0.6 ns 26, 31

DQ and DM input setup time relative to DQS tDS 0.5 0.5 0.6 ns 26, 31

DQ and DM input pulse width (for each input) tDIPW 1.75 1.75 2 ns 31

Access window of DQS from CK/CK# tDQSCK -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns

DQS input high pulse width tDQSH 0.35 0.35 0.35 tCK

DQS input low pulse width tDQSL 0.35 0.35 0.35 tCK

DQS-DQ skew, DQS to last DQ valid, per group, per access tDQSQ 0.5 0.5 0.6 ns 25, 26

DQS-DQ skew, first DQS to last DQ valid, per access tDQSQA 0.7 0.7 0.8 ns 36

Write command to first DQS latching transition tDQSS 0.75 1.25 0.75 1.25 0.75 1.25 tCK

DQS falling edge to CK rising - setup time tDSS 0.2 0.2 0.2 tCK

DQS falling edge from CK rising - hold time tDSH 0.2 0.2 0.2 tCK

Half clock period tHP tCH,tCL tCH,tCL tCH,tCL ns 34

Data-out high-impedance window from CK/CK# tHZ -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns 18

Data-out low-impedance window from CK/CK# tLZ -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns 18

Address and control input hold time (fast slew rate) tIHF.90 .90 1.1 ns 14

Address and control input setup time (fast slew rate) tISF.90 .90 1.1 ns 14

Address and control input hold time (slow slew rate) tIHS1 1 1.1 ns 14

Address and control input setup time (slow slew rate) tIHS1 1 1.1 ns 14

Address and control input pulse width tIPW 2.2 2.2 2.5 ns

LOAD MODE REGISTER command cycle time tMRD 15 15 16 ns

DQ-DQS hold, DQS to first DQ to go non-valid, per access tQH tHP tHP tHP ns 25, 26,

- tQHS - tQHS - tQHS 34

Data hold skew factor tQHS 0.75 0.75 1 ns

ACTIVE to PRECHARGE command tRAS 45 120,000 45 120,000 50 120,000 ns 35

ACTIVE to READ with Auto precharge command tRAP 15 20 20 ns

ACTIVE to ACTIVE/AUTO REFRESH command period tRC 60 65 70 ns

AUTO REFRESH command period tRFC 67 75 80 ns 50

ACTIVE to READ or WRITE delay tRCD 15 20 20 ns

PRECHARGE command period tRP 15 20 20 ns

DQS read preamble tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 tCK 42

DQS read postamble tRPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK

ACTIVE bank a to ACTIVE bank b command tRRD 2 2 2 tCK

512Mb: x4, x8, x16 DDR SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

DQS write preamble tWPRE 0.25 0.25 0.25 tCK

DQS write preamble setup time tWPRES 0 0 0 ns 20, 21

DQS write postamble tWPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK 19

Write recovery time tWR 15 15 15 ns

Internal WRITE to READ command delay tWTR 1 1 1 tCK

Data valid output window (DVW) na tQH - tDQSQ tQH - tDQSQ tQH - tDQSQ ns 25

REFRESH to REFRESH command interval tREFC 70.3 70.3 70.3 µs 23

Average periodic refresh interval tREFI 7.8 7.8 7.8 µs 23

Terminating voltage delay to VDD tVTD 0 0 0 ns

Exit SELF REFRESH to non-READ command tXSNR 75 75 80 ns

Exit SELF REFRESH to READ command tXSRD 200 200 200 tCK

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS

(Notes: 1–5, 14-17, 33; notes appear on pages 50–53) (0°C ≤ TA ≤ +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V)

AC CHARACTERISTICS - Continued -7 -75 -8

PARAMETER SYMBOL MIN MAX MIN MAX MIN MAX UNITS NOTES

SLEW RATE DERATING VALUES

(Note: 14; notes appear on pages 50–53) (0°C ≤ TA ≤ +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V)

ADDRESS / COMMAND

SPEED SLEW RATE tIS tIH UNITS

-7, -75 0.500V / ns 1 1 ns

-7, -75 0.400V / ns 1.05 1 ns

-7, -75 0.300V / ns 1.10 1 ns

-7, -75 0.200V / ns 1.15 1 ns

-8 0.500V / ns 1.1 1.1 ns

-8 0.400V / ns 1.15 1.1 ns

-8 0.300V / ns 1.20 1.1 ns

-8 0.200V / ns 1.25 1.1 ns

SLEW RATE DERATING VALUES

(Note: 31; notes appear on pages 50–53) (0°C ≤ TA ≤ +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V)

Data, DM, DQS

SPEED SLEW RATE tDS tDH UNITS

-7, -75 0.500V / ns 0.50 0.50 ns

-7, -75 0.400V / ns 0.55 0.55 ns

-7, -75 0.300V / ns 0.60 0.60 ns

-7, -75 0.200V / ns 0.65 0.65 ns

-8 0.500V / ns 0.60 0.60 ns

-8 0.400V / ns 0.65 0.65 ns

-8 0.300V / ns 0.70 0.70 ns

-8 0.200V / ns 0.75 0.75 ns

512Mb: x4, x8, x16 DDR SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

4. AC timing and IDD tests may use a VIL-to-VIH

swing of up to 1.5V in the test environment, but

input timing is still referenced to VREF (or to the

crossing point for CK/CK#), and parameter

specifications are guaranteed for the specified

AC input levels under normal use conditions.

The minimum slew rate for the input signals

used to test the device is 1V/ns in the range

between VIL(AC) and VIH(AC).

5. The AC and DC input level specifications are as

defined in the SSTL_2 Standard (i.e., the receiver

will effectively switch as a result of the signal

crossing the AC input level, and will remain in

that state as long as the signal does not ring back

above [below] the DC input LOW [HIGH] level).

6. VREF is expected to equal VDDQ/2 of the transmit-

ting device and to track variations in the DC

level of the same. Peak-to-peak noise (non-

common mode) on VREF may not exceed ±2

percent of the DC value. Thus, from VDDQ/2,

VREF is allowed ±25mV for DC error and an

additional ±25mV for AC noise.

7. VTT is not applied directly to the device. VTT is a

system supply for signal termination resistors, is

expected to be set equal to VREF and must track

variations in the DC level of VREF.

8. VID is the magnitude of the difference between the

input level on CK and the input level on CK#.

9. The value of VIX is expected to equal VDDQ/2 of

the transmitting device and must track varia-

tions in the DC level of the same.

10. IDD is dependent on output loading and cycle

rates. Specified values are obtained with

minimum cycle time at CL = 2 for -7 and -8,

CL = 2.5 for -75 with the outputs open.

11. Enables on-chip refresh and address counters.

NOTES

1. All voltages referenced to VSS.

2. Tests for AC timing, IDD, and electrical AC and

DC characteristics may be conducted at nominal

reference/supply voltage levels, but the related

specifications and device operation are guaran-

teed for the full voltage range specified.

3. Outputs measured with equivalent load:

12. IDD specifications are tested after the device is

properly initialized, and is averaged at the

defined cycle rate.

13. This parameter is sampled. VDD = +2.5V ±0.2V,

VDDQ = +2.5V ±0.2V, VREF = VSS, f = 100 MHz,

TA = 25°C, VOUT(DC) = VDDQ/2, VOUT (peak to

peak) = 0.2V. DM input is grouped with I/O

pins, reflecting the fact that they are matched in

14. Command/Address input slew rate = 0.5V/ns.

For -7 and -75 with slew rates 1V/ns and faster,

tIS and tIH are reduced to 900ps. If the slew rate

is less than 0.5V/ns, timing must be derated: tIS

has an additional 50ps per each 100mV/ns

reduction in slew rate from the 500mV/ns. tIH

has 0ps added, that is, it remains constant. If the

slew rate exceeds 4.5V/ns, functionality is

uncertain.

15. The CK/CK# input reference level (for timing

referenced to CK/CK#) is the point at which CK

and CK# cross; the input reference level for

signals other than CK/CK# is VREF.

16. Inputs are not recognized as valid until VREF

stabilizes. Exception: during the period before

VREF stabilizes, CKE ≤ 0.3 x VDDQ is recognized as

LOW.

17. The output timing reference level, as measured at the

timing reference point indicated in Note 3, is VTT.

18. tHZ and tLZ transitions occur in the same access

time windows as valid data transitions. These

parameters are not referenced to a specific

voltage level, but specify when the device output

is no longer driving (HZ) or begins driving (LZ).

19. The maximum limit for this parameter is not a

device limit. The device will operate with a

greater value for this parameter, but system

performance (bus turnaround) will degrade

accordingly.

20. This is not a device limit. The device will operate

with a negative value, but system performance

could be degraded due to bus turnaround.

21. It is recommended that DQS be valid (HIGH or

LOW) on or before the WRITE command. The

case shown (DQS going from High-Z to logic

LOW) applies when no WRITEs were previously

in progress on the bus. If a previous WRITE was

in progress, DQS could be HIGH during this

time, depending on tDQSS.

22. MIN (tRC or tRFC) for IDD measurements is the

smallest multiple of tCK that meets the minimum

absolute value for the respective parameter.

tRAS(MAX) for IDD measurements is the largest

multiple of tCK that meets the maximum

absolute value for tRAS.

Output

OUT

)

Reference

Point

Ω

30pF

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512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

23. The refresh period 64ms. This equates to an

average refresh rate of 7.8125µs. However, an

AUTO REFRESH command must be asserted at

least once every 70.3µs; burst refreshing or

posting by the DRAM controller greater than

eight refresh cycles is not allowed.

24. The I/O capacitance per DQS and DQ byte/

group will not differ by more than this maxi-

mum amount for any given device.

25. The valid data window is derived by achieving

other specifications - tHP (tCK/2), tDQSQ, and

tQH (tHP - tQHS). The data valid window

derates directly porportional with the clock duty

cycle and a practical data valid window can be

derived. The clock is allowed a maximum duty

cycle variation of 45/55. Functionality is

uncertain when operating beyond a 45/55 ratio.

The data valid window derating curves are

provided below for duty cycles ranging between

50/50 and 45/55.

26. Referenced to each output group: x4 = DQS with

DQ0-DQ3; x8 = DQS with DQ0-DQ7; x16 =

LDQS with DQ0-DQ7; and UDQS with DQ8-

DQ15.

NOTES (continued) 27. This limit is actually a nominal value and does

not result in a fail value. CKE is HIGH during

REFRESH command period (tRFC [MIN]) else

CKE is LOW (i.e., during standby).

28. To maintain a valid level, the transitioning edge

of the input must:

a) Sustain a constant slew rate from the current

AC level through to the target AC level, VIL(AC)

or VIH(AC).

b) Reach at least the target AC level.

c) After the AC target level is reached, continue

to maintain at least the target DC level, VIL(DC)

or VIH(DC).

29. The Input capacitance per pin group will not

differ by more than this maximum amount for

any given device.

30. CK and CK# input slew rate must be ≥ 1V/ns.

31. DQ and DM input slew rates must not deviate

from DQS by more than 10%. If the DQ/DM/

DQS slew rate is less than 0.5V/ns, timing must

be derated: 50ps must be added to tDS and tDH

for each 100mv/ns reduction in slew rate. If slew

rate exceeds 4V/ns, functionality is uncertain.

DER ATING DATA VALID WINDOW

(tQH - tDQSQ)

3.750 3.700 3.650 3.600

3.550

3.500 3.450

3.400 3.350 3.300

3.250

3.400 3.350 3.300

3.250

3.200 3.150

3.100 3.050

3.000 2.950 2.900

2.500 2.463 2.425 2.388 2.350 2.313 2.275 2.238 2.200 2.163 2.125

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

50/50 49.5/50.5 49/51 48.5/52.5 48/52 47.5/53.5 47/53 46.5/54.5 46/54 45.5/55.5 45/55

Clock Duty Cyc le

-7,-75 @ tCK = 10ns

-8 @ tCK = 10ns

-7, -75 @ tCK = 7. 5ns

-8 @ tCK = 8ns

-7 @ tCK = 7ns

512Mb: x4, x8, x16 DDR SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

NOTES (continued)

32. VDD must not vary more than 4% if CKE is not

active while any bank is active.

33. The clock is allowed up to ±150ps of jitter. Each

timing parameter is allowed to vary by the same

amount.

34. tHPmin is the lesser of tCL minimum and tCH

minimum actually applied to the device CK and

CK/ inputs, collectively during bank active.

35. READs and WRITEs with autoprecharge are not

allowed to be issued until tRAS(MIN) can be

satisfied prior to the internal precharge com-

mand being issued.

36. Applies to x16 only. First DQS (LDQS or UDQS)

to transition to last DQ (DQ0-DQ15) to

transition valid. Initial JEDEC specifications

suggested this to be same as tDQSQ.

37.Normal Output Drive Curves:

a) The full variation in driver pull-down current from

minimum to maximum process, temperature and

voltage will lie within the outer bounding lines of

the V-I curve of Figure A.

b) The variation in driver pull-down current

within nominal limits of voltage and tempera-

ture is expected, but not guaranteed, to lie

within the inner bounding lines of the V-I

curve of Figure A.

c) The full variation in driver pull-up current

from minimum to maximum process,

temperature and voltage will lie within the

outer bounding lines of the V-I curve of Figure

d) The variation in driver pull-up current within

nominal limits of voltage and temperature is

expected, but not guaranteed, to lie within

the inner bounding lines of the V-I curve of

Figure B.

e) The full variation in the ratio of the maximum

to minimum pull-up and pull-down current

should be between .71 and 1.4, for device

drain-to-source voltages from 0.1V to 1.0

Volt, and at the same voltage and tempera-

ture.

f) The full variation in the ratio of the nominal

pull-up to pull-down current should be unity

±10%, for device drain-to-source voltages

from 0.1V to 1.0 volt.

Figure A

Pull-Down Characteristics

100

120

140

160

0.0 0.5 1.0 1.5 2.0 2.5

VOUT (V)

OUT

(mA)

Figure B

Pull-Up Characteristics

-200

-180

-160

-140

-120

-100

-80

-60

-40

-20

0.00.51.01.52.02.5

VDDQ - VOUT (V)

OUT

(mA)

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512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

NOTES (continued)

38.Reduced Output Drive Curves:

a) The full variation in driver pull-down current from

minimum to maximum process, temperature and

voltage will lie within the outer bounding lines of

the V-I curve of Figure C.

b) The variation in driver pull-down current

within nominal limits of voltage and tempera-

ture is expected, but not guaranteed, to lie

within the inner bounding lines of the V-I

curve of Figure C.

c) The full variation in driver pull-up current from

minimum to maximum process, temperature and

voltage will lie within the outer bounding lines of

the V-I curve of Figure D.

d) The variation in driver pull-up current within

nominal limits of voltage and temperature is

expected, but not guaranteed, to lie within

the inner bounding lines of the V-I curve of

Figure D.

e) The full variation in the ratio of the maximum

to minimum pull-up and pull-down current

should be between .71 and 1.4 for device

drain-to-source voltages from 0.1V to 1.0

Volt, and at the same voltage and tempera-

ture.

f) The full variation in the ratio of the nominal

pull-up to pull-down current should be unity

±10%, for device drain-to-source voltages

from 0.1V to 1.0 Volt.

39. The voltage levels used are derived from the

refernced test load. In practice, the voltage levels

obtained from a properly terminated bus will

provide significantly different voltage values.

40. VIH overshoot: VIH(MAX) = VDDQ+1.5V for a

pulse width ≤ 3ns and the pulse width can not

be greater than 1/3 of the cycle rate.

Figure C

Pull-Down Characteristics

0.0 0.5 1.0 1.5 2.0 2.5

VOUT (V)

OUT

(mA)

Figure D

Pull-Up Characteristics

-50

-45

-40

-35

-30

-25

-20

-15

-10

-5

0.0 0.2 0.4 0.6 0.8 1.0

VDDQ - VOUT (V)

OUT

(mA)

VIL undershoot: VIL(MIN) = -1.5V for a pulse

width ≤ 3ns and the pulse width can not be

greater than 1/3 of the cycle rate.

41. VDD and VDDQ must track each other.

42. Note 42 is not used.

43. Note 43 is not used.

4 4. During initialization, VDDQ, VTT, and VREF must be

equal to or less than VDD + 0.3V. Alternatively,

VTT may be 1.35V maximum during power up,

even if VDD/VDDQ are 0 volts, provided a

minimum of 42 ohms of series resistance is used

between the VTT supply and the input pin.

45. Note 45 is not used.

46. Note 46 is not used.

47. Note 47 is not used.

48. Random addressing changing 50% of data

changing at every transfer.

49. Random addressing changing 100% of data

changing at every transfer.

50. CKE must be active (high) during the entire time

a refresh command is executed. That is, from the

time the AUTO REFRESH command is registered,

CKE must be active at each rising clock edge,

until tREF later.

51. IDD2N specifies the DQ, DQS, and DM to be

driven to a valid high or low logic level. IDD2Q

is similar to IDD2F except IDD2Q specifies the

address and control inputs to remain stable.

Although IDD2F, IDD2N, and IDD2Q are

similar, IDD2F is “worst case.”

52. Whenever the operating frequency is altered, not

including jitter, the DLL is required to be reset,

and followed by 200 clock cycles.

512Mb: x4, x8, x16 DDR SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

NOTE: The above characteristics are specified under best, worst, and nominal process variation/conditions.

NORMAL OUTPUT DRIVE CHARACTERISTICS

PULL-DOWN CURRENT (mA) PULL-UP CURRENT (mA)

VOLTAGE NOMINAL NOMINAL NOMINAL NOMINAL

(V) LOW HIGH MINIMUM MAXIMUM LOW HIGH MINIMUM MAXIMUM

0.1 6.0 6.8 4.6 9.6 -6.1 -7.6 -4.6 -10.0

0.2 12.2 13.5 9.2 18.2 -12.2 -14.5 -9.2 -20.0

0.3 18.1 20.1 13.8 26.0 -18.1 -21.2 -13.8 -29.8

0.4 24.1 26.6 18.4 33.9 -24.0 -27.7 -18.4 -38.8

0.5 29.8 33.0 23.0 41.8 -29.8 -34.1 -23.0 -46.8

0.6 34.6 39.1 27.7 49.4 -34.3 -40.5 -27.7 -54.4

0.7 39.4 44.2 32.2 56.8 -38.1 -46.9 -32.2 -61.8

0.8 43.7 49.8 36.8 63.2 -41.1 -53.1 -36.0 -69.5

0.9 47.5 55.2 39.6 69.9 -43.8 -59.4 -38.2 -77.3

1.0 51.3 60.3 42.6 76.3 -46.0 -65.5 -38.7 -85.2

1.1 54.1 65.2 44.8 82.5 -47.8 -71.6 -39.0 -93.0

1.2 56.2 69.9 46.2 88.3 -49.2 -77.6 -39.2 -100.6

1.3 57.9 74.2 47.1 93.8 -50.0 -83.6 -39.4 -108.1

1.4 59.3 78.4 47.4 99.1 -50.5 -89.7 -39.6 -115.5

1.5 60.1 82.3 47.7 103.8 -50.7 -95.5 -39.9 -123.0

1.6 60.5 85.9 48.0 108.4 -51.0 -101.3 -40.1 -130.4

1.7 61.0 89.1 48.4 112.1 -51.1 -107.1 -40.2 -136.7

1.8 61.5 92.2 48.9 115.9 -51.3 -112.4 -40.3 -144.2

1.9 62.0 95.3 49.1 119.6 -51.5 -118.7 -40.4 -150.5

2.0 62.5 97.2 49.4 123.3 -51.6 -124.0 -40.5 -156.9

2.1 62.8 99.1 49.6 126.5 -51.8 -129.3 -40.6 -163.2

2.2 63.3 100.9 49.8 129.5 -52.0 -134.6 -40.7 -169.6

2.3 63.8 101.9 49.9 132.4 -52.2 -139.9 -40.8 -176.0

2.4 64.1 102.8 50.0 135.0 -52.3 -145.2 -40.9 -181.3

2.5 64.6 103.8 50.2 137.3 -52.5 -150.5 -41.0 -187.6

2.6 64.8 104.6 50.4 139.2 -52.7 -155.3 -41.1 -192.9

2.7 65.0 105.4 50.5 140.8 -52.8 -160.1 -41.2 -198.2

512Mb: x4, x8, x16 DDR SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

NOTE: The above characteristics are specified under best, worst, and nominal process variation/conditions.

REDUCED OUTPUT DRIVE CHARACTERISTICS

PULL-DOWN CURRENT (mA) PULL-UP CURRENT (mA)

VOLTAGE NOMINAL NOMINAL NOMINAL NOMINAL

(V) LOW HIGH MINIMUM MAXIMUM LOW HIGH MINIMUM MAXIMUM

0.1 3.4 3.8 2.6 5.0 -3.5 -4.3 -2.6 -5.0

0.2 6.9 7.6 5.2 9.9 -6.9 -7.8 -5.2 -9.9

0.3 10.3 11.4 7.8 14.6 -10.3 -12.0 -7.8 -14.6

0.4 13.6 15.1 10.4 19.2 -13.6 -15.7 -10.4 -19.2

0.5 16.9 18.7 13.0 23.6 -16.9 -19.3 -13.0 -23.6

0.6 19.9 22.1 15.7 28.0 -19.4 -22.9 -15.7 -28.0

0.7 22.3 25.0 18.2 32.2 -21.5 -26.5 -18.2 -32.2

0.8 24.7 28.2 20.8 35.8 -23.3 -30.1 -20.4 -35.8

0.9 26.9 31.3 22.4 39.5 -24.8 -33.6 -21.6 -39.5

1.0 29.0 34.1 24.1 43.2 -26.0 -37.1 -21.9 -43.2

1.1 30.6 36.9 25.4 46.7 -27.1 -40.3 -22.1 -46.7

1.2 31.8 39.5 26.2 50.0 -27.8 -43.1 -22.2 -50.0

1.3 32.8 42.0 26.6 53.1 -28.3 -45.8 -22.3 -53.1

1.4 33.5 44.4 26.8 56.1 -28.6 -48.4 -22.4 -56.1

1.5 34.0 46.6 27.0 58.7 -28.7 -50.7 -22.6 -58.7

1.6 34.3 48.6 27.2 61.4 -28.9 -52.9 -22.7 -61.4

1.7 34.5 50.5 27.4 63.5 -28.9 -55.0 -22.7 -63.5

1.8 34.8 52.2 27.7 65.6 -29.0 -56.8 -22.8 -65.6

1.9 35.1 53.9 27.8 67.7 -29.2 -58.7 -22.9 -67.7

2.0 35.4 55.0 28.0 69.8 -29.2 -60.0 -22.9 -69.8

2.1 35.6 56.1 28.1 71.6 -29.3 -61.2 -23.0 -71.6

2.2 35.8 57.1 28.2 73.3 -29.5 -62.4 -23.0 -73.3

2.3 36.1 57.7 28.3 74.9 -29.5 -63.1 -23.1 -74.9

2.4 36.3 58.2 28.3 76.4 -29.6 -63.8 -23.2 -76.4

2.5 36.5 58.7 28.4 77.7 -29.7 -64.4 -23.2 -77.7

2.6 36.7 59.2 28.5 78.8 -29.8 -65.1 -23.3 -78.8

2.7 36.8 59.6 28.6 79.7 -29.9 -65.8 -23.3 -79.7

512Mb: x4, x8, x16 DDR SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

Figure 27

x4, x8 Data Output Timing – tDQSQ, tQH and Data Valid Window

DQ (Last data valid)

DQ2

DQS1

DQ (Last data valid)

DQ (First data no longer valid)

All DQs and DQS, collectively6

NOTE: 1. DQs transitioning after DQS transition define tDQSQ window. DQS transitions at T2 and at T2n are an “early DQS,”

at T3 is a “nominal DQS,” and at T3n is a "late DQS"

2. For a x4, only two DQs apply.

3. tDQSQ is derived at each DQS clock edge and is not cumulative over time and begins with DQS transition and

ends with the last valid transition of DQs .

4. tQH is derived from tHP : tQH = tHP - tQHS.

5. tHP is the lesser of tCL or tCH clock transition collectively when a bank is active.

6. The data valid window is derived for each DQS transitions and is defined as tQH minus tDQSQ.

Earliest signal transition

Latest signal transition

T2n

T3n

CK#

T1 T2 T3 T4T2n T3n

tQH

tHP

tQH

tHP

tQH

tDQSQ

Data

Valid

window

Data

Valid

window

Data

Valid

window

Data

Valid

window

QFC#

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512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

Figure 27 A

x16 Data Output Timing – tDQSQ, tQH and Data Valid Window

DQ (Last data valid)

LDQS

DQ (Last data valid)

DQ (First data no longer valid)

DQ0 - DQ7 and LDQS, collectively

NOTE: 1. DQs transitioning after DQS transition define tDQSQ

window. LDQS defines the lower byte and

UDQS defines the upper byte.

2. DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, or DQ7.

3. tDQSQ is derived at each DQS clock edge and is not

cumulative over time and begins with DQS transition

and ends with the last valid transition of DQs .

T2n

T3n

CK#

T1 T2 T3 T4T2n T3n

tQH

tDQSQ

Data Valid

window

Data Valid

window

DQ (Last data valid)

UDQS

DQ (Last data valid)

DQ (First data no longer valid)

DQ8 - DQ15 and UDQS, collectively

T2n

T3n

tQH

tDQSQ

tDQSQA

tHP

tQH

Data Valid

window

Data Valid

window Data Valid

window

Data Valid

window

Data Valid

window

4. tQH is derived from tHP: tQH = tHP - tQHS.

5. tHP is the lesser of tCL or tCH clock transition

collectively when a bank is active.

6. The data valid window is derived for each

DQS transition and is tQH minus tDQSQ.

7. DQ8, DQ9, DQ10, D11, DQ12, DQ13, DQ14, or DQ15.

Upper Byte

Lower Byte

Data Valid

window

512Mb: x4, x8, x16 DDR SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

Figure 29

Data Input Timing

Figure 28

Data Output Timing - tAC and tDQSCK

CK#

DQS, or LDQS/UDQS

T1 T2 T3 T4 T5

T2n T3n T4n T5n T6

NOTE: 1. tDQSCK is the DQS output window relative to CK and is the“long term” component of DQS skew.

DQs transitioning after DQS transition define tDQSQ window.

3. All DQs must transition by tDQSQ after DQS transitions, regardless of tAC.

4. tAC is the DQ output window relative to CK, and is the“long term” component of DQ skew.

5. tLZ

(MIN)

, tAC

(MIN)

, and tHZ

(MIN)

are the first valid signal transition.

6. tLZ

(MAX)

, tAC

(MAX)

, and tHZ

(MAX)

are the latest valid signal transition.

7. READ command with CL = 2 issued at T0.

tRPST

tLZ

(MAX)

tLZ

(MIN)

tDQSCK

(MAX)

tDQSCK

(MIN)

tDQSCK

(MAX)

tDQSCK

(MIN)

tHZ

(MAX)

tHZ

(MIN)

tRPRE

DQ (Last data valid)

DQ (First data valid)

All DQs collectively

tAC

(MIN)

tAC

(MAX)

tLZ

(MAX)

tLZ

(MIN)

tHZ

(MAX)

tHZ

(MIN)

T2n T3n T4n T5n

T2n

T3n

T4n

T5n

T2 T3 T4 T5

DQS

tDQSS

tDQSH tWPST

tDH

tDS

tDQSL

tDSS2tDSH1

tDSH1tDSS2

CK#

T1 T1n T2 T2n T3

NOTE: 1. tDSH

(

MIN) generally occurs during tDQSS

(

MIN).

2. tDSS

(

MIN) generally occurs during tDQSS

(

MAX).

3. WRITE command issued at T0.

4. For x16, LDQS controls the lower byte and UDQS controls the upper byte.

DON’T CARE

TRANSITIONING DATA

WPRE

WPRES

512Mb: x4, x8, x16 DDR SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

Figure 30

Input Voltage Waveform

0.940V

1.100V

1.200V

1.225V

1.250V

1.275V

1.300V

1.400V

1.560V

REF

-AC Noise

REF

-DC Error

REF

+DC Error

REF

+AC Noise

OH(MIN)

(1.670V1 for SSTL2 termination)

AC - Provides margin

between V

(MAX) and V

ILAC

Q (2.3V minimum)

(MAX) (0.83V2 for

SSTL2 termination)

System Noise Margin (Power/Ground,

Crosstalk, Signal Integrity Attenuation)

NOTE: 1. V

(MIN) with test load is 1.927V

2. V

(MAX) with test load is 0.373V

3. Numbers in diagram reflect nomimal

values utilizing circuit below.

Reference

Point

Ω

Transmitter

Receiver

512Mb: x4, x8, x16 DDR SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

TIMING PARAMETERS

-7 -75 -8

SYMBOL MIN MAX MIN MAX MIN MAX UNITS

tCH 0.45 0.55 0.45 0.55 0.45 0.55 tCK

tCL 0.45 0.55 0.45 0.55 0.45 0.55 tCK

tCK (2.5) 7 12 7.5 12 8 12 ns

tCK (2) 7.5 12 10 2 10 12 ns

tIH 1 1 1.1 ns

INITIALIZE AND LOAD MODE REGISTERS

-7 -75 -8

SYMBOL MIN MAX MIN MAX MIN MAX UNITS

tIS 1 1 1.1 ns

tMRD151516ns

tRFC 67 75 80 ns

tRP 15 20 20 ns

tVTD 0 0 0 ns

VTD

CKE

LVCMOS

LOW LEVEL

BA0, BA1

200 cycles of CK

Load Extended

Mode Register

Load Mode

tMRD tMRD tRP tRFC tRFC

Power-up:

and

CK stable

T = 200µs

High-Z

(

)(

)

(

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(

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(

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(

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(

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(

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(

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(

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(

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(

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(

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(

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(

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(

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(

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(

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(

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(

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(

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(

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)

(

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)

(

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)

(

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)

(

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)

(

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(

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(

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(

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(

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(

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(

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(

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(

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(

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(

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(

)(

)

DQS

High-Z

A0-A9, A11, A12

A10

ALL BANKS

CK#

TT1

REF

COMMAND6

LMRNOP PRELMR AR

(

)(

)

(

)(

)

AR ACT

tIS tIH

BA0 = H,

BA1 = L

tIS tIH

BA0 = L,

BA1 = L

tIS tIH

(

)(

)

(

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(

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(

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(

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(

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(

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(

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(

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CODE CODE

tIS tIH

CODE CODE

(

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(

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)

PRE

ALL BANKS

tIS tIH

NOTE: 1. V

is not applied directly to the device; however, tVTD should be greater than or equal to zero to avoid device latch-up. V

Q, V

and V

REF

must be equal to or less than V

+ 0.3V. Alternatively, V

may be 1.35V maximum during power up, even if

Q are 0 volts, provided a minimum of 42 ohms of series resistance is used between the V

supply and the input pin.

2. Although not required by the Micron device, JEDEC specifies resetting the DLL with A8 = H.

3. tMRD is required before any command can be applied, and 200 cycles of CK are required before a READ command can be issued.

4. The two AUTO REFRESH commands at Tc0 and Td0 may be applied after the LOAD MODE REGISTER (LMR) command at Ta0.

5. Although not required by the Micron device, JEDEC specifies issuing another LMR command (A8 = L) prior to activating any bank.

6. PRE = PRECHARGE command, LMR = LOAD MODE REGISTER command, AR = AUTO REFRESH command, ACT = ACTIVE command,

RA = Row Address, Bank Address

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T0 T1 T2 Ta0 Tb0 Tc0 Td0 Te0

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tRP

512Mb: x4, x8, x16 DDR SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

POWER-DOWN MODE

CK#

COMMAND

VALID1NOP

ADDR

CKE

NOTE: 1. If this command is a PRECHARGE (or if the device is already in the idle state), then the

power-down mode shown is precharge power-down. If this command is an ACTIVE (or if

at least one row is already active), then the power-down mode shown is active power-down.

2. No column accesses are allowed to be in progress at the time power-down is entered.

DQS

VALID

tCK tCH tCL

tIS

tIH

tIS

tIS tIH

tIH tIS

Enter 2

Power-Down

Mode

Exit

Power-Down

Mode

tREFC

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T0 T1 Ta0 Ta1 Ta2T2

NOP

DON’T CARE

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VALIDVALID

TIMING PARAMETERS

-7 -75 -8

SYMBOL MIN MAX MIN MAX MIN MAX UNITS

tCH 0.45 0.55 0.45 0.55 0.45 0.55 tCK

tCL 0.45 0.55 0.45 0.55 0.45 0.55 tCK

tCK (2.5) 7 12 7.5 12 8 12 ns

-7 -75 -8

SYMBOL MIN MAX MIN MAX MIN MAX UNITS

tCK (2 ) 7.5 12 10 12 10 12 ns

tIH 1 1 1.1 ns

tIS 1 1 1.1 ns

512Mb: x4, x8, x16 DDR SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

AUTO REFRESH MODE

TIMING PARAMETERS

-7 -75 -8

SYMBOL MIN MAX MIN MAX MIN MAX UNITS

tCH 0.45 0.55 0.45 0.55 0.45 0.55 tCK

tCL 0.45 0.55 0.45 0.55 0.45 0.55 tCK

tCK (2.5) 7 12 7.5 12 8 12 ns

tCK ( 2) 7.5 12 10 12 10 12 ns

-7 -75 -8

SYMBOL MIN MAX MIN MAX MIN MAX UNITS

tIH 1 1 1.1 ns

tIS 1 1 1.1 ns

tRFC 67 75 80 ns

tRP 15 20 20 ns

CK#

COMMAND1NOP2

VALID VALID

NOP 2NOP2

PRE

CKE

A0-A9,

A11, A121

A101

BA0, BA11Bank(s)3BA

NOTE: 1. PRE = PRECHARGE, ACT = ACTIVE, AR = AUTO REFRESH, RA = Row Address, BA = Bank Address.

2. NOP commands are shown for ease of illustration; other valid commands may be possible at these times.

CKE must be active during clock positive transitions.

3. “Don’t Care” if A10 is HIGH at this point; A10 must be HIGH if more than one bank is active (i.e.,

must precharge all active banks).

4. DM, DQ, and DQS signals are all “Don’t Care”/High-Z for operations shown.

5. The second AUTO REFRESH is not required and is only shown as an example of two back-to-back

AUTO REFRESH commands.

AR NOP2AR5NOP2ACTNOP2

ONE BANK

ALL BANKS

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DQ4

DM4

DQS4

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tRFC

tRP tRFC

T0 T1 T2 T3 T4 Ta0 Tb0

Ta1 Tb1 Tb2

DON’T CARE

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512Mb: x4, x8, x16 DDR SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

SELF REFRESH MODE

TIMING PARAMETERS

-7 -75 -8

SYMBOL MIN MAX MIN MAX MIN MAX UNITS

tCH 0.45 0.55 0.45 0.55 0.45 0.55 tCK

tCL 0.45 0.55 0.45 0.55 0.45 0.55 tCK

tCK (2.5) 7 12 7.5 12 8 12 ns

tCK ( 2) 7.5 12 10 12 10 12 ns

tIH 1 1 1.1 ns

-7 -75 -8

SYMBOL MIN MAX MIN MAX MIN MAX UNITS

tIS 1 1 1.1 ns

tRP 15 20 20 ns

tXSNR 75 75 80 ns

tXSRD 200 200 200 tCK

CK1

CK#

COMMAND4NOP AR

ADDR

CKE1

VALID

DQS

VALIDNOP

NOTE: 1. Clock must be stable before exiting self refresh mode. That is, the clock must be cycling within

specifications by Ta0.

2. Device must be in the all banks idle state prior to entering self refresh mode.

XSNR is required before any non-READ command can be applied, and

XSRD (200 cycles of CK)

is required before a READ command can be applied.

4. AR = AUTO REFRESH command.

CL tCK

tXSNR/

tXSRD

tIS tIH

IH tIS

Enter Self Refresh Mode Exit Self Refresh Mode

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T0 T1 Tb0Ta1

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DON’T CARE

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Ta0

512Mb: x4, x8, x16 DDR SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

BANK READ – WITHOUT AUTO PRECHARGE

CK#

CKE

A10

BA0, BA1

RCD

RAS7

CL = 2

T0 T1 T2 T3 T4 T5 T5n T6nT6 T7 T8

DQS

Case 1:

(

MIN)

and

DQSCK

(

MIN)

Case 2:

(

MAX)

and

DQSCK

(

MAX)

DQS

RPRE

RPST

DQSCK

(

MIN)

DQSCK

(

MAX)

(

MIN)

(

MAX)

(

MIN)

(

MIN)

(

MAX)

(

MAX)

(

MAX)

NOP6

COMMAND

ACT

Col n

READ2PRE

Bank x

Bank xBank x4

ACT

Bank x

NOP6NOP6NOP6

(

MIN)

NOTE: 1. DO n = data-out from column n; subsequent elements are provided in the programmed order.

2. Burst length = 4 in the case shown.

3. Disable auto precharge.

4. “Don’t Care” if A10 is HIGH at T5.

5. PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address.

6. NOP commands are shown for ease of illustration; other commands may be valid at these times.

7. The PRECHARGE command can only be applied at T5 if

RAS minimum is met.

8. Refer to figure 27, 27A, and 28 for detailed DQS and DQ timing.

ONE BANK

ALL BANKS

DON’T CARE

TRANSITIONING DATA

x4: A0-A9, A11, A12

x8: A0-A11

x16: A0-A9

x8: A12

x16: A11, A12

512Mb: x4, x8, x16 DDR SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

BANK READ – WITH AUTO PRECHARGE

CK#

CKE

A10

BA0, BA1

IS IH

CL = 2

T0 T1 T2 T3 T4 T5 T5n T6nT6 T7 T8

DQ1

DQS

Case 1: tAC

(MIN)

and tDQSCK

(MIN)

Case 2: tAC

(MAX)

and tDQSCK

(MAX)

DQ1

DQS

RPRE

RPST

tDQSCK

(MIN)

tDQSCK

(MAX)

AC(MIN)

LZ(MIN)

HZ(MAX)

AC(MAX)

LZ(MAX)

NOP5

COMMAND4

ACT

Col n

READ2,6 NOP5

Bank x

ACT

Bank x

NOP5NOP5NOP5

HZ(MIN)

NOTE: 1. DO n = data-out from column n; subsequent elements are provided in the programmed order.

2. Burst length = 4 in the case shown.

3. Enable auto precharge.

4. ACT = ACTIVE, RA = Row Address, BA = Bank Address.

5. NOP commands are shown for ease of illustration; other commands may be valid at these times.

6. The READ command can only be applied at T3 if

RAP is satisfied at T3

7. Refer to figure 27, 27A, and 28 for detailed DQS and DQ timing.

DON’T CARE

TRANSITIONING DATA

x4: A0-A9, A11,A12

x8: A0-A9, A11

x16: A0-A9

x8: A12

x16: A11, A12

RAS

(MIN)

(MAX)

RCD,

RAP6

512Mb: x4, x8, x16 DDR SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

BANK WRITE – WITHOUT AUTO PRECHARGE

TIMING PARAMETERS

-7 -75 -8

SYMBOL MIN MAX MIN MAX MIN MAX UNITS

tCH 0.45 0.55 0.45 0.55 0.45 0.55 tCK

tCL 0.45 0.55 0.45 0.55 0.45 0.55 tCK

tCK (2.5) 7 12 7.5 12 8 12 ns

tCK ( 2) 7.5 12 10 12 10 12 ns

tDH 0.5 0.5 0.6 ns

tDS 0.5 0.5 0.6 ns

tDQSH 0.35 0.35 0.35 tCK

tDQSL 0.35 0.35 0.35 tCK

tDQSS 0.75 1.25 0.75 1.25 0.75 1.25 tCK

tDSS 0.2 0.2 0.2 tCK

-7 -75 -8

SYMBOL MIN MAX MIN MAX MIN MAX UNITS

tDSH 0.2 0.2 0.2 tCK

tIH 1 1 1.1 ns

tIS 1 1 1.1 ns

tRAS 45 120,000 45 120,000 50 120,000 ns

tRCD 15 20 20 ns

tRP 15 20 20 ns

tWPRE 0.25 0.25 0.25 tCK

tWPRES 0 0 0 ns

tWPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK

tWR 15 15 15 n s

CK#

CKE

A10

BA0, BA1

tCK tCH tCL

tIS

tIH

tIS

tIH

tIS tIH

tRCD

tRAS tRP

tWR

T0 T1 T2 T3 T4 T5 T5n T6 T7 T8T4n

NOTE: 1. DI n = data-out from column n; subsequent elements are provided in the programmed order.

2. Burst length = 4 in the case shown.

3. Disable auto precharge.

4. “Don’t Care” if A10 is HIGH at T8.

5. PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address.

6. NOP commands are shown for ease of illustration; other commands may be valid at these times.

7.tDSH is applicable during tDQSS(MIN) and is referenced from CK T4 or T5.

8.tDSS is applicable during tDQSS(MAX) and is referenced from CK T5 or T6.

NOP6

COMMAND

ACT

Col n

WRITE2NOP6

ONE BANK

ALL BANKS

Bank x

PRE

Bank x

NOP6NOP6NOP6

tDQSL tDQSH tWPST

Bank x4

DQS

tDS tDH

DON’T CARE

TRANSITIONING DATA

tDQSS(NOM)

WPRE

WPRES

x4: A0-A9, A11, A12

x8: A0-A9, A11

x16: A0-A9

x8: A12

x16: A11, A12

512Mb: x4, x8, x16 DDR SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

BANK WRITE – WITH AUTO PRECHARGE

TIMING PARAMETERS

-7 -75 -8

SYMBOL MIN MAX MIN MAX MIN MAX UNITS

tCH 0.45 0.55 0.45 0.55 0.45 0.55 tCK

tCL 0.45 0.55 0.45 0.55 0.45 0.55 tCK

tCK (2.5) 7 12 7.5 12 8 12 ns

tCK ( 2) 7.5 12 10 12 10 12 ns

tDH 0.5 0.5 0.6 ns

tDS 0.5 0.5 0.6 ns

tDQSH 0.35 0.35 0.35 tCK

tDQSL 0.35 0.35 0.35 tCK

tDQSS 0.75 1.25 0.75 1.25 0.75 1.25 tCK

tDSS 0.2 0.2 0.2 tCK

-7 -75 -8

SYMBOL MIN MAX MIN MAX MIN MAX UNITS

tDSH 0.2 0.2 0.2 tCK

tIH 1 1 1.1 ns

tIS 1 1 1.1 ns

tRAS 45 120,000 45 120,000 50 120,000 ns

tRCD 15 20 20 ns

tRP 15 20 20 ns

tWPRE 0.25 0.25 0.25 tCK

tWPRES 0 0 0 ns

tWPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK

tWR 15 15 15 n s

CK#

CKE

A10

BA0, BA1

CH tCL

RCD

RAS

T0 T1 T2 T3 T4 T5 T5n T6 T7 T8T4n

NOTE: 1. DI n = data-out from column n; subsequent elements are provided in the programmed order.

2. Burst length = 4 in the case shown.

3. Enable auto precharge.

4. ACT = ACTIVE, RA = Row Address, BA = Bank Address.

5. NOP commands are shown for ease of illustration; other commands may be valid at these times.

6.tDSH is applicable during tDQSS

(MIN)

and is referenced from CK T4 or T5.

7.tDSS is applicable during tDQSS

(MAX)

and is referenced from CK T5 or T6.

NOP5

COMMAND

ACT

Col n

WRITE2NOP5

Bank x

NOP5

Bank x

NOP5NOP5NOP5

DQSL

DQSH

WPST

DQS

tDS tDH

DQSS

(NOM)

DON’T CARE

TRANSITIONING DATA

WPRES

WPRE

x4: A0-A9, A11

x8: A0-A9

x16: A0-A8

x4: A12

x8: A11, A12

x16: A9, A11, A12

512Mb: x4, x8, x16 DDR SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

WRITE – DM OPERATION

TIMING PARAMETERS

-7 -75 -8

SYMBOL MIN MAX MIN MAX MIN MAX UNITS

tCH 0.45 0.55 0.45 0.55 0.45 0.55 tCK

tCL 0.45 0.55 0.45 0.55 0.45 0.55 tCK

tCK (2.5) 7 12 7.5 12 8 12 ns

tCK ( 2) 7.5 12 10 12 10 12 ns

tDH 0.5 0.5 0.6 ns

tDS 0.5 0.5 0.6 ns

tDQSH 0.35 0.35 0.35 tCK

tDQSL 0.35 0.35 0.35 tCK

tDQSS 0.75 1.25 0.75 1.25 0.75 1.25 tCK

tDSS 0.2 0.2 0.2 tCK

-7 -75 -8

SYMBOL MIN MAX MIN MAX MIN MAX UNITS

tDSH 0.2 0.2 0.2 tCK

tIH 1 1 1.1 ns

tIS 1 1 1.1 ns

tRAS 45 120,000 45 120,000 50 120,000 ns

tRCD 15 20 20 ns

tRP 15 20 20 ns

tWPRE 0.25 0.25 0.25 tCK

tWPRES 0 0 0 ns

tWPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK

tWR 15 15 15 n s

CK#

CKE

A10

BA0, BA1

RCD

RAS tRP

tWR

T0 T1 T2 T3 T4 T5 T5n T6 T7 T8T4n

NOTE: 1. DI n = data-out from column n; subsequent elements are provided in the programmed order.

2. Burst length = 4 in the case shown.

3. Disable auto precharge.

4. “Don’t Care” if A10 is HIGH at T8.

5. PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address.

6. NOP commands are shown for ease of illustration; other commands may be valid at these times.

7.tDSH is applicable during tDQSS(MIN) and is referenced from CK T4 or T5.

8.tDSS is applicable during tDQSS(MAX) and is referenced from CK T5 or T6.

NOP6

COMMAND

ACT

Col n

WRITE2NOP6

ONE BANK

ALL BANKS

Bank x

PRE

Bank x

NOP6NOP6NOP6

DQSL

DQSH

WPST

Bank x4

DQS

DON’T CARE

TRANSITIONING DATA

DQSS

(NOM)

WPRES

WPRE

x4: A0-A9, A11

x8: A0-A9

x16: A0-A8

x4: A12

x8: A11, A12

x16: A9, A11, A12

512Mb: x4, x8, x16 DDR SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

(TH) OPTION

66-PIN PLASTIC TSOP (400 MIL)

NOTE: 1. All dimensions in millimeters MAX or typical here noted.

MIN

2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per

side.

SEE DETAIL A

0.10

0.65 TYP 3.10

10.16 ±0.08

0.15

0.50 ±0.10

PIN #1 ID

DETAIL A

27.00 ± 0.08

0.32 ±0.075 TYP

+0.03

-0.02

+0.10

-0.05

1.20 MAX

0.10

0.25

11.76 ±0.10

0.80 TYP

GAGE PLANE

512Mb: x4, x8, x16 DDR SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

(TG) OPTION

66-PIN PLASTIC TSOP (400 MIL)

NOTE: 1. All dimensions in millimeters MAX or typical here noted.

MIN

2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per

side.

SEE DETAIL A

0.10

0.65 TYP

0.71

10.16 ±0.08

0.15

0.50 ±0.10

PIN #1 ID

DETAIL A

22.22 ± 0.08

0.32 ± .075 TYP

+0.03

-0.02

+0.10

-0.05

1.20 MAX

0.10

0.25

11.76 ±0.10

0.80 TYP

0.10 (2X)

GAGE PLANE

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail: prodmktg@micronsemi.com, Internet: http://www.micronsemi.com, Customer Comment Line: 800-932-4992

Micron is a registered trademark of Micron Technology, Inc.