April 2003
Preliminary
Copyright © 2003 Alliance Semiconductor. All rights reserved.
®AS7C31024B
3.3V 128K X 8 CMOS SRAM
3/31/03, V 032003 Alliance Semiconductor P. 1 of 9
Features
• Industrial and commercia l temp erat ures
• Organization: 131,072 words x 8 bits
•High speed
- 8/10/12/15/20 ns ad dress access time
- 5, 5, 6, 7, 8 ns output enabl e acc e ss time
• Low power consumption: ACTIVE
- 270 mW / max @ 8 ns
• Low power consumption: STANDBY
- 18 mW / max CMOS
• Latest 6T 0.18u CMOS technology
• Easy memory expansion with CE1, CE2, OE inputs
• TTL/LVTTL-compatible, three-state I/O
• 32-pin JEDEC standard packages
- 300 mil SOJ
- 400 mil SOJ
-8 × 20mm TSOP 1
- 8 x 13.4mm sTSOP 1
• ESD protection ≥ 2000 volts
• Latch-up cu rrent ≥ 200 mA
Logic block diagram
512 x 256 x 8
Array
(1,048,576)
Sense amp
Input buffer
A10
A11
A12
A13
A14
A15
A16
I/O0
I/O7
OE
CE1
WE
Column decoder
Row decoder
Control
circuit
A9
A0
A1
A2
A3
A4
A5
A6
A7
V
CC
GND
A8
CE2
Pin arrangement
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
AS7C31024B
32-pin SOJ (300 mil)
VCC
A15
CE2
WE
A13
A8
A9
A11 OE
A10
CE1
I/O7
I/O6
I/O4
NC
A16
A14
A12
A7
A6
A5
A4 A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
I/O5
I/O3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
32
31
30
29
28
27
26
25
24
23
22
21
AS7C31024B
20
19
15
16 18
17
32-pin (8 x 20mm) TSOP I
32-pin SOJ (400 mil)
32-pin (8 x 13.4mm) sTSOP1
Selection guide -8 -10 -12 -15 -20 Unit
Maximum address access time 8 10 12 15 20 ns
Maximum output enable access time55678ns
Maximum operating current 7570656055mA
Maximum CMOS standby current55555mA
AS7C31024B
3/31/03, V 032003 Alliance Semiconductor P. 2 of 9
®
Functional description
The AS7C31024B is a high performance CMOS 1,048,576-bit Static Random Access M emor y (SRAM) device organized as 131,072 words x 8
bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired.
Equal address access and cycle times (tAA, tRC, tWC) of 8/10/12/15/20 ns with output enable access times (tOE) of 5, 5, 6, 7, 8 ns are ideal for
high performance applications. Active high and low chip enables (CE1, CE2) permit easy memory expansion with multiple-bank systems.
When CE1 is high or CE2 is low, the device enters standby mode. If inputs are still toggling, the device will consume ISB power. If the bus is
static, then full standby po wer is reached (ISB1). F or example , the AS7C31024B is guaranteed not to exceed 18 mW under nominal full standby
conditions. All devices in this family will retain data when VCC is reduced as low as 2.0 V.
A writ e cycle is accomplished by asserting write enable (WE) and both ch ip en ables (CE1, CE2). Data on the input pins I/O0 through I/O7 is
written on the rising edge of WE (write cycle 1) or the activ e-to-inactiv e edge of CE1 or CE2 (write cycle 2). To a v oid bus contention, external
devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output ena ble (OE) and both chip enables (CE1, CE2), with write enab le (W E) high. The chip drives
I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is active,
output drivers stay in high-impedance mode.
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional oper-
ation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
Key: X = don’t care, L = low, H = high
Absolute maximum ratings
Parameter Symbol Min Max Unit
Voltage on VCC relative to GND Vt1 -0.50 +5.0 V
Voltage on any pin relative to GND Vt2 –0.50 VCC +0.50 V
P ower dissipation PD–1.0W
Storage temperature (plastic) Tstg –65 +150 °C
Ambient temperature with VCC applied Tbias –55 +125 °C
DC current into outputs (low) IOUT –20mA
Truth table
CE1
CE2
WE OE
Data Mode
HXXX High Z Standby (I
SB, ISB1)
XLXX High Z Standby (I
SB, ISB1)
L H H H High Z Output disable (ICC)
LHHL D
OUT Read (ICC)
LHLX D
IN Write (ICC)
AS7C31024B
3/31/03, V 032003 Alliance Semiconductor P. 3 of 9
®
Recommended operating conditions
Parameter Symbol Min Nominal Max Unit
Supply voltage VCC 3.0 3.3 3.6 V
Input voltage VIH 2.0 – VCC + 0.5 V
VIL1–0.5 – 0.8 V
Ambient operating temperature commercial TA0–70
°C
industrial TA–40 – 85 °C
1 VILmin. = –3.0V for pulse width less than tRC/2.
DC operating characteristics (over the operating range)
Parameter Sym Test con d itio n s -8 -10 -12 -15 -20 Unit
Min Max Min Max Min Max Min Max Min Max
Inp u t l ea k ag e
current |ILI|V
CC = Max, VIN = GND to VCC –1–1–1–1–1µA
Output leakage
current |ILO|VCC = Max, CE1 = VIH or
CE2 = VIL, VOUT = GND to VCC –1–1–1–1–1µA
Operating
po wer supply
current ICC VCC = Max, CE1 = VIL,
CE2 = VIH, f = fMax,
IOUT = 0 mA –75–70–65–60–55
mA
Standby po wer
supply current
ISB VCC = Max, CE1 ≥ V IH and/or
CE2 ≤ VIL, VIN = VIH or VIL,
f = fMax, IOUT = 0 mA –30–30–25–20–20
mA
ISB1 VCC = Max, CE1 ≥ VCC–0.3V
VIN ≤ G N D + 0.2V or
VIN ≥ V CC –0 .3V, f = 0 –5–5–5–5–5
Output voltage VOL IOL = 8 mA, VCC = Min –0.4–0.4–0.4–0.4–0.4V
VOH IOH = –4 m A, VCC = Min 2.4–2.4–2.4–2.4–2.4– V
Capacitance (f = 1 MHz, Ta = 25 °C, VCC = NOMINAL)2
Parameter Symbol Signals Test conditions Max Unit
Input capacitance CIN A, CE1, CE2, WE, OE VIN = 0V 5 pF
I/O capacitance CI/O I/O VIN = VOUT = 0V 7 pF
AS7C31024B
3/31/03, V 032003 Alliance Semiconductor P. 4 of 9
®
Key to switching waveforms
Read waveform 1 (address controlled)
Read waveform 2 (CE1, CE2, and OE controlled)
Read cycle (over the opera ting range)
Parameter Symbol -8 -10 -12 -15 -20 Unit NotesMin Max Min Max Min Max Min Max Min Max
Read cycle time tRC 8 – 10 – 12 – 15 – 20 ns
Address access time tAA – 8 – 10 – 12 – 15 – 20 ns 3
Chip enable (CE1) access
time tACE1 – 8 – 10 – 12 – 15 – 20 ns 3, 12
Chip enable (CE2) access
time tACE2 – 8 – 10 – 12 – 15 – 20 ns 3, 12
Output enable (OE) access
time tOE –5–5–6–7–8ns
Output hold from address
change tOH 3–3–3–3–3–ns5
CE1 low to output in low Z tCLZ1 3 – 3 – 3 – 3 – 3 – ns 4, 5, 12
CE2 high to output in low Z tCLZ2 3 – 3 – 3 – 3 – 3 – ns 4, 5, 12
CE1 high to output in high Z tCHZ1 – 3 – 3 – 3 – 4 – 5 ns 4, 5, 12
CE2 low to output in high Z tCHZ2 – 3 – 3 – 3 – 4 – 5 ns 4, 5, 12
OE low to output in low Z tOLZ 0–0–0–0–0–ns4, 5
OE high to output in high Z tOHZ –4–5–6–7–8ns4, 5
P ower up time tPU 0 0–0–0–0–ns4, 5, 12
Power down time tPD – 8 – 10 – 12 – 15 – 20 ns 4, 5, 12
Undefined / don’t careFalling in pu tRising input
Address
DOUT Data va lid
tOH
tAA
tRC
Supply
current
CE2
OE
DOUT
tOE
tOLZ
tACE1, tACE2 tCHZ1, tCHZ2
tCLZ1, tCLZ2
tPU
t
PD
ICC
ISB
50% 50%
Data valid
tRC1
CE1
tOHZ
AS7C31024B
3/31/03, V 032003 Alliance Semiconductor P. 5 of 9
®
Write waveform 1 (WE controlled)
Write cycle (over the operating range)
Parameter Symbol –8 -10 -12 -15 -20 Unit Not
es
Min Max Min Max Min Max Min Max Min Max
Write cycle time tWC 8 –10–12–15–20–ns
Chip enable (CE1) to write end tCW1 7–8–9–10–12–ns12
Chip enable (CE2) to write end tCW2 7–8–9–10–12–ns12
Address setup to write end tAW 7–8–9–10–12–ns
Address setup time tAS 0–0–0–0–0–ns12
Write pulse width tWP 6–7–8–9–12–ns
Write recovery time tWR 0–0–0–0–0–ns
Address hold from end of write tAH 0–0–0–0–0–ns
Data valid to write end tDW 5–5–6–8–10–ns
Data hold time tDH 0–0–0–0–0–ns4, 5
Write enable to output in high Z tWZ –4–5–6–7–8ns4, 5
Output active from write end tOW 1–1–1–1–1–ns4, 5
tAW tAH
tWC
Address
WE
DOUT
tDH
tOW
tDW
tWZ
tWP
tAS
Data valid
DIN
tWR
AS7C31024B
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®
Write waveform 2 (CE1 and CE2 controlled)
AC test conditions
Notes
1During V
CC power-up, a pull-up resistor to VCC on CE1 is required to meet ISB specification.
2 This parameter is sampled and not 100% tested.
3 For test conditions, see AC Test Conditions, Figures A, B, and C.
4t
CLZ and tCHZ are specified with CL = 5pF, as in Figure C. Transition is measured ±500 mV from steady-state voltage.
5 This parameter is guaranteed, but not 100% tested.
6WE
is high for read cycle.
7CE1
and OE are low and CE2 is high for read cycle.
8 Address valid prior to or coincident with CE1 transition Low.
9 All read cycle timings are referenced from the last valid address to the first transitioning address.
10 CE1 or WE must be high or CE2 low during address transitions. Either CE1 or WE asserting high terminates a write cycle.
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 CE1 and CE2 have identical timing.
13 C = 30 pF, except all high Z and low Z parameters where C = 5 pF.
14 2 V data retention applies to commercial temperature operating range only.
tAW
Address
CE1
WE
DOUT
tCW1, tCW2
tWP
tDW tDH
tAH
tWC
tAS
CE2
Data valid
DIN
tWR
tWZ
255Ω
– Output load: see Figure B or Figure C.
– I nput pulse level: GND to 3.0V. See Figure A.
– I nput rise and fall times: 2 ns. See Figure A.
– I nput and output timing reference levels: 1.5V.
C13
320Ω
DOUT
GND
+3.3V
168Ω
Thevenin equivalent:
DOUT +1.728V (5V and 3.3V)
Figure C: 3.3V Output load
255ΩC13
480Ω
DOUT
GND
+5V
Figure B: 5V Output load
10%
90%
10%
90%
GND
+3.0V
Figure A: Input pu lse
2 ns
AS7C31024B
3/31/03, V 032003 Alliance Semiconductor P. 7 of 9
®
Typical DC and AC Characteristcs
Supply voltage (V)
MIN MAX
NOMINAL
0.0
0.2
0.6
0.8
0.4
1.0
1.2
1.4
Normalized I
CC
, I
SB
Normalized su pply c u rren t I
CC
, I
SB
Ambient temperature (°C)
–55 80 125
35–10
0.0
0.2
0.6
0.8
0.4
1.0
1.2
1.4
Normalized I
CC
, I
SB
Normalized supply current I
CC
, I
SB
vs. ambient temperature T
a
vs. su pply voltage V
CC
I
CC
I
SB
I
CC
I
SB
Ambient temperature (°C)
-55 80 125
35-10
0.2
1
0.04
5
25
625
Normalized ISB1 (log scale)
Normalized supply current I
SB1
vs. ambient temperature T
a
VCC = VCC(NOMINAL)
Supply voltage (V)
MIN MAX
NOMINAL
0.8
0.9
1.1
1.2
1.0
1.3
1.4
1.5
Normalized access time
Normalized access time t
AA
Ambient temperature (°C)
–55 80 125
35–10
0.8
0.9
1.1
1.2
1.0
1.3
1.4
1.5
Normalized access time
Normalized access time t
AA
Cycle frequency (MHz)
075
100
5025
0.0
0.2
0.6
0.8
0.4
1.0
1.2
1.4
Normalized ICC
Normalized supply current I
CC
vs. ambient temperature T
a
vs. cycle frequency 1/t
RC
, 1/t
WC
vs. su pply voltage V
CC
Ta = 25° C
VCC = VCC(NOMINAL)
VCC = VCC(NOMINAL)
Ta = 25° C
Output voltage (V) V
CC
0
20
60
80
40
100
120
140
Output source current (mA)
Output source current I
OH
Output voltage (V) V
CC
Output sink current (mA)
Output sink current I
OL
vs. ou tp ut voltage V
OL
vs. outpu t volta ge V
OH
0
20
60
80
40
100
120
140
Capacitance (pF)
0750 1000
500250
0
5
15
20
10
25
30
35
Change in t
AA
(ns)
Typical access time change
∆
t
AA
vs. output ca pacitive loading
00
VCC = VCC(NOMINAL)
Ta = 25° C
VCC = VCC(NOMINAL)
Ta = 25° C
VCC = VCC(NOMINAL)
AS7C31024B
3/31/03, V 032003 Alliance Semiconductor P. 8 of 9
®
Package dimensions
Seating
Plane
e
b
E
Hd
D
α
c
LA1AA2
pin 1 pin 32
pin 16 pin 17
Pin 1
D
e
E1E2
A1
B
b
A
A2
E
c
32-pin SOJ 300
mil 32-pin SOJ 400
mil
Min Max Min Max
A - 0.145 - 0.145
A1 0.025 - 0.025 -
A2 0.086 0.105 0.086 0.115
B 0.026 0.032 0.026 0.032
b 0.014 0.020 0.015 0.020
c 0.006 0.013 0.007 0.013
D 0.820 0.830 0.820 0.830
E 0.250 0.275 0.360 0.380
E1 0.292 0.305 0.395 0.405
E2 0.330 0.340 0.435 0.445
e 0.050 BSC 0.050 BSC
32-pin TSOP 8×20 mm
Min Max
A – 1.20
A1 0.05 0.15
A2 0.95 1.05
b 0.17 0.27
c 0.10 0.21
D 18.20 18.60
e 0.50 nominal
E 7.80 8.20
Hd 19.80 20.20
L 0.50 0.70
α0° 5°
AS7C31024B
© C o py rig h t A llia nc e S emicon d uc tor C or po ra tion . A ll r ig hts r eser v ed . O u r thr ee -p oin t lo go , o ur na m e an d I nte lliw a tt are trad emark s or re giste re d tra d emark s of A llian ce . A ll o the r b ra nd an d
p
ro du c t na m es m a y b e th e tr ad emark s of the ir re spe ctiv e c ompa nie s. A llia nc e re ser ve s th e rig h t to make ch an g es to thi s do cu m e n t an d its p ro d u cts at a n y time w ith ou t n ot ice . A llia n ce assu mes no
responsibility for any errors that m ay appear in this docum ent. T he data contained herein represents A lliance’s best data and/or estim ates at the tim e o f issuance. A lliance re serves the righ t to
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against all claim s arising from such use.
3/31/03, V 032003 Alliance Semiconductor P. 9 of 9
®
Ordering codes
Package \ Access
time Temp 8 ns 10 ns 12 ns 15 ns 20 ns
Plastic SOJ, 300 mil Commercial AS7C31024B-
8TJC AS7C31024B-
10TJC AS7C31024B-
12TJC AS7C31024B-
15TJC AS7C31024B-
20TJC
Industrial –AS7C31024B-
10TJI AS7C31024B-
12TJI AS7C31024B-
15TJI AS7C31024B-
20TJI
Plastic SOJ, 400 mil Commercial AS7C31024B-
8JC AS7C31024B-
10JC AS7C31024B-
12JC AS7C31024B-
15JC AS7C31024B-
20JC
Industrial –AS7C31024B-
10JI AS7C31024B-
12JI AS7C31024B-
15JI AS7C31024B-
20JI
TSOP1 8×20 mm Commercial AS7C31024B-
8TC AS7C31024B-
10TC AS7C31024B-
12TC AS7C31024B-
15TC AS7C31024B-
20TC
Industrial –AS7C31024B-
10TI AS7C31024B-
12TI AS7C31024B-
15TI AS7C31024B-
20TI
sTSOP1
8 x 13.4mm
Commercial AS7C31024B-
8STC AS7C31024B-
10STC AS7C31024B-
12STC AS7C31024B-
15STC AS7C31024B-
20STC
Industrial –AS7C31024B-
10STI AS7C31024B-
12STI AS7C31024B-
15STI AS7C31024B-
20STI
Part numbering system
AS7C X1024B –XX X X
SRAM
prefix 3 = 3.3 V CMOS Device
number Access
time
Package:
T = TSOP1 8×20 mm
ST = sTSOP1 8 x 13.4 mm
J = SOJ 400 mil
TJ = SOJ 300 mil
Te mperature ra nge
C = Commercial, 0° C to 70° C
I = Industrial, -40° C to 85° C
