2011 Microchip Technology Inc. DS22067J-page 1
11AA010/11LC010 11AA080/11LC080
11AA020/11LC020 11AA160/11LC160
11AA040/11LC040 11AA161/11LC161
Features:
• Single I/O, UNI/O® Serial Interface Bus
• Low-Power CMOS Technology:
- 1 mA active current , typical
- 1 µA standby current (max.) (I-temp)
• 128 x 8 through 2,048 x 8 Bit Organizations
• Schmitt Trigger Inputs for Noise Suppression
• Output Slop e C o ntro l t o El im ina te Gro und Bounce
• 100 kbps Max. Bit Rate – Equivalent to 100 kHz
Clock Frequency
• Self-Timed Write Cycle ( including Auto-Erase )
• Page-Write Buffer for up to 16 Bytes
• STATUS Register for Added Control:
- Write enable latch bit
- Write-In-Progress bit
• Block Write Protection:
- Protect none, 1/4, 1/2 or all of array
• Built -in W ri te Prot ection:
- Power-on/off data protection circuitry
- Write enable latch
• High Reliability:
- Endurance: 1,000,000 erase/write cycles
- Data retention: > 200 years
- ESD protection: > 4,000V
• 3-lead SOT-23 and TO-92 Packages
• 4-lead Chip Scale Package
• 8-lead PDIP, SOIC, MSOP, TDFN Packages
• Pb-Free and RoHS Compliant
• Available Temperature Ranges:
Pin Function Table
Description:
The Microchip Technology Inc. 11AAXXX/11LCXXX
(11XX*) devices are a family of 1 Kbit through 16 Kbit
Serial Electrically Erasable PROMs. The devices are
organized in blocks of x8-bit memory and support the
patented** single I/O UNI/O® serial bus. By using
Manchester encoding techniques, the clock and data
are combined into a single, serial bit stream (SCIO),
where the clock signal is extracted by the receiver to
corr ectly deco de the timing an d value of each bit.
Low-voltage d esign permit s operation down to 1.8V (for
11AAXXX devic es), with st andby and active c urrents of
only 1 uA and 1 mA, respectively.
The 11XX family is available in standard packages
including 8-lead PDIP and SOIC, and advanced pack-
aging including 3-lead SOT-23, 3-lead TO-92, 4-lead
Chip Scale, 8-lead TDFN, and 8-lead MSOP.
Package Types (not to scale)
- Industrial (I): -40°C to +85°C
- Automotive (E): -40°C to +125°C
Name Function
SCIO Serial Clock, Data Input/Output
VSS Ground
VCC Supply Voltage
NC
NC
NC
Vss
1
2
3
4
8
7
6
5
VCC
NC
NC
SCIO
PDIP/SOIC
(P, SN)
NC
NC
NC
V
SS
1
2
3
4
8
7
6
5
VCC
NC
NC
SCIO
(MS)
TDFN
NC
NC
NC
VSS
NC
NC
SCIO
5
6
7
8
4
3
2
1VCC
(MN)
MSOP
SOT23
2
3
1SCIO
VCC
VSS
(TT)
Vcc
TO-92
SCIO
(TO) 12
34
VCC VSS
NC
SCIO
(Top down view,
balls not visible
)
Note 1: Availa ble in I-temp, “AA” o n ly.
Vss
CS (Chip Scale)(1)
1K-16K UNI/O® Serial EEPROM Family Data Sheet
* 11XX is used in this document as a generic part number for the 11 series devices.
** Microchip’s UNI/O® Bus products are covered by some or all of the following patents issued in the U.S.A.: 7,376,020 & 7,788,430.
11XX
DS22067J-page 2 2011 Microchip Technology Inc.
DEVICE SELECTION TABLE
Part Number Density
(bits) Organization VCC Range Page Size
(Bytes) Temp.
Ranges Device
Address Packages
11LC010 1K 128 x 8 2.5-5.5V 16 I,E 0xA0 P, SN, MS, MN, TO, TT
11AA010 1K 128 x 8 1.8-5.5V 16 I 0xA0 P, S N , MS, M N , TO, TT, CS
11LC020 2K 256 x 8 2.5-5.5V 16 I,E 0xA0 P, SN, MS, MN, TO, TT
11AA020 2K 256 x 8 1.8-5.5V 16 I 0xA0 P, S N , MS, M N , TO, TT, CS
11LC040 4K 512 x 8 2.5-5.5V 16 I,E 0xA0 P, SN, MS, MN, TO, TT
11AA040 4K 512 x 8 1.8-5.5V 16 I 0xA0 P, S N , MS, M N , TO, TT, CS
11LC080 8K 1,024 x 8 2.5-5.5V 16 I,E 0xA0 P, SN, MS, MN, T O, TT
11AA080 8K 1,024 x 8 1.8-5.5V 16 I 0xA0 P, SN , MS, MN, TO, TT, CS
11LC160 16K 2,048 x 8 2.5-5.5V 16 I,E 0xA0 P, SN, MS, MN, TO, TT
11AA160 16K 2,048 x 8 1.8-5.5V 16 I 0xA0 P, SN, MS, MN, TO, TT,CS
11LC161 16K 2,048 x 8 2.5-5.5V 16 I, E 0xA1 P, SN, MS, MN, TO, TT
11AA161 16K 2,048 x 8 1.8-5.5V 16 I 0xA1 P, SN, MS, MN, TO, TT, CS
2011 Microchip Technology Inc. DS22067J-page 3
11XX
1.0 ELECTRICAL CHARAC TERISTICS
Absolute Maximum Ratings (†)
VCC.............................................................................................................................................................................6.5V
SCIO w.r.t. VSS.....................................................................................................................................-0.6V to VCC+1.0V
Storage temperature .................................................................................................................................-65°C to 150°C
Ambient temperature under bias...............................................................................................................-40°C to 125°C
ESD protection on all pins..........................................................................................................................................4 kV
TABLE 1-1: DC CHARACTERISTICS
† NOTICE: Stresses above those listed under ‘Absolute Maximum Ratings’ may cause permanent damage to the
device . Th is is a st ress r ating o nly a nd fun ctiona l ope ration of t he devic e at thos e or an y oth er cond itions abov e thos e
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an
extended period of time may affect device reliability.
DC CHARACTERISTICS
Electrical Characteristics :
Industrial (I): VCC = 2.5V to 5.5V TA = -40°C to +85°C
VCC = 1.8V to 2.5V TA = -20°C to +85°C
Automotive (E): VCC = 2.5V to 5.5V TA = -40°C to +125°C
Param.
No. Sym. Characteristic Min. Max. Units Test Conditions
D1 VIH High-level input
voltage 0.7*VCC VCC+1 V
D2 VIL Low-level input
voltage -0.3
-0.3 0.3*VCC
0.2*VCC V
VVCC2.5V
VCC < 2.5V
D3 VHYS Hysteresis of Schmitt
Trigger i npu ts (SCIO) 0.05*Vcc — V VCC2.5V (Note 1)
D4 VOH High-level output
voltage VCC -0.5
VCC -0.5 —
—V
VIOH = -300 A, VCC = 5.5V
IOH = -200 A, Vcc = 2.5V
D5 VOL Low-level output
voltage —
—0.4
0.4 V
VIOI = 300 A, VCC = 5.5V
IOI = 200 A, Vcc = 2.5V
D6 IOOutput curr ent lim it
(Note 2) —
—±4
±3 mA
mA VCC = 5.5V (Note 1)
Vcc = 2.5V (Note 1)
D7 ILI Input leakage current
(SCIO) —±1AVIN = VSS or VCC
D8 CINT Internal Capa ci t anc e
(all inputs and
outputs)
—7pFT
A = 25°C, FCLK = 1 MHz,
VCC = 5.0V (Note 1)
D9 ICC Read Read Operating
Current —
—3
1mA
mA VCC=5.5V; FBUS=100 kHz, CB=1 00 pF
VCC=2.5V; FBUS=100 kHz, CB=1 00 pF
D10 ICC Write W rite Opera tin g
Current —
—5
3mA
mA VCC = 5.5V
VCC = 2.5V
D11 Iccs Standby Current —
—
5
1
A
A
VCC = 5.5V
TA = 125°C
VCC = 5.5V
TA = 85°C
D12 ICCI Idle Mode Current — 50 AVCC = 5.5V
Note 1: This parameter is periodically sampled and not 100% tested.
2: The SCIO output driver impedance will vary to ensure IO is not exceeded.
11XX
DS22067J-page 4 2011 Microchip Technology Inc.
TABLE 1-3: AC TEST CONDITIONS
TABLE 1-2: AC CHARACTERISTICS
AC CHARACTERISTICS
Electrical Characteristics:
Industri al (I): VCC = 2.5V to 5.5V TA = -40°C to +85°C
VCC = 1.8V to 2.5V TA = -20°C to +85°C
Automotive (E): VCC = 2.5V to 5.5V TA = -40°C to +125°C
Param.
No. Sym. Characteristic Min. Max. Units Test Conditions
1F
BUS Serial bus freque nc y 10 100 kHz —
2T
EBit period 10 100 µs —
3TIJIT Input edge jitter tolerance — ±0.06 UI (Note 3)
4FDRIFT Serial bus frequency drift
rate tolerance — ±0.50 % per byte —
5F
DEV Serial bus frequency drift
limit —±5% per
command —
6T
OJIT Output edge jitter — ±0.25 UI (Note 3)
7T
RSCIO input rise time
(Note 1)— 100 ns —
8T
FSCIO input fall time
(Note 1)— 100 ns —
9T
STBY Standby pulse time 600 — µs —
10 TSS Start header setup time 10 — µs —
11 THDR Start header low pulse
time 5—µs—
12 TSP Input filter spike
suppression (SCIO) —50ns(Note 1)
13 TWC Write cy cl e time
(byte or page) —
—5
10 ms
ms Write, WRSR commands
ERAL, SETAL commands
14 — Endurance (per page) 1M — cycles 25°C, VCC = 5.5V (Note 2)
Note 1: This parameter is periodically sampled and not 100% tested.
2: This parameter is not tested but ensured by characterization . For enduranc e estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained on Microchip’s web site:
www.microchip.com.
3: A Unit Interval (UI) is equal to 1-bit period (TE) at the current bus frequency.
AC Waveform:
VLO = 0.2V
VHI = VCC - 0.2V
CL = 100 pF
Timing Measurement Refere nce Lev el
Input 0.5 VCC
Output 0.5 VCC
2011 Microchip Technology Inc. DS22067J-page 5
11XX
FIGURE 1-1: BUS TIMING – ST ART HEADER
FIGURE 1-2: BUS TIMING – DATA
FIGURE 1-3: BUS TIMING – STANDBY PULSE
FIGURE 1-4: BUS TIMING – JITTER
SCIO
2
Data ‘0’Data ‘1’Data ‘0’Data ‘1’Data ‘0’Data ‘1’Data ‘0’Data ‘1’MAK bit NoSAK bit
1110
2
SCIO
7 8
Data ‘0’Data ‘1’Data ‘1’Data ‘0’
12
SCIO 9
Standby
Mode
Ideal Edge
323 6 6
26 6
Ideal Edge Ideal Edge Ideal Edge
from Master from Master from Slave from Slave
11XX
DS22067J-page 6 2011 Microchip Technology Inc.
2.0 FUNCTIONAL DESCRIPTION
2.1 Principles of Operation
The 11XX family of serial EEPROMs support the
UNI/O® protocol. They can be interfaced with
microcontrollers, including Microchip’s PIC® mic rocon-
trollers, ASICs, or any other device with an available
discrete I/O line that can be configured properly to
match the UNI / O prot oco l.
The 11XX devices contain an 8-bit instruction register.
The devices are accessed via the SCIO pin.
Table 4-1 contains a list of the possible instruction
bytes and format for device operation. All instructions,
addresses, and data are transferred MSb first, LSb
last.
Data is embedded into the I/O stream through
Manchester encoding. The bus is controlled by a
master de vic e whi ch de term in es the clo ck perio d, co n-
trols the bus access and initiates all operations, while
the 11XX works as slave. Both master and slave can
operate as transmitter or receiver, but the master
device determines which mode is active.
FIGURE 2-1: BLOCK DIAGRAM
SCIO
STATUS
Register
I/O Contro l Memory
Control
Logic
X
Dec
HV Generator
EEPROM
Array
Page Latches
Y Decoder
Sense Amp.
R/W Control
Logic
Vcc
Vss
Current-
Limited
Slope
Control
2011 Microchip Technology Inc. DS22067J-page 7
11XX
3.0 BUS CHARACTERISTICS
3.1 Standby Pulse
When the m as ter h as co ntro l of SCIO, a standby pulse
can be generated by holding SCIO high for TSTBY. At
this time, the 11XX will reset and return to Standby
mode. Subsequently, a high-to-low transition on SCIO
(the first low pulse of the header) will return the device
to the active state.
Once a command is terminated satisfactorily (i.e., via
a NoMAK/SAK combination during the Acknowledge
sequence), performing a standby pulse is not required
to begin a new command as long as the device to be
selected is the same device selected during the previ-
ous command. However, a period of TSS must be
observe d a fter the en d o f th e c om m and an d b efo re th e
beginning of the start header. After TSS, the start
header (including THDR low pulse) can be transmitted
in order to begin the new command.
If a com mand i s termina ted in a ny ma nner ot her t han a
NoMAK/SAK combination, then the master must per-
form a standby pulse before beginning a new com-
mand, regardless of which device is to be selected.
An exampl e of two con secutiv e comm ands is shown in
Figure 3-1. Note that the device address is the same
for both commands, indicating that the same device is
being selected both times.
A standby pulse cannot be generated while the slave
has control of SCIO. In this situation, the master must
wait for the slave to finish transmitting and to release
SCIO before the pulse can be generated.
If, at any point during a command, an error is detected
by the master, a standby pulse should be generated
and the command should be performed again.
FIGURE 3-1: CONSECUT IV E COMMAN D S EXA MPLE
3.2 Start Data Transfer
All ope rations mu st be p recede d by a s tar t head er. The
start header consists of holding SCIO low for a period
of THDR, followed by trans mi tti ng an 8- bit ‘01010101’
code. This code is used to synchronize the slave’s
internal clock period with the master’s clock period, so
accurate timing is very important.
When a standby pulse is not required (i.e., between
successive commands to the same device), a period of
TSS must be observed after the end of the command
and before the beginning of the start header.
Figure 3-2 shows the waveform for the start header,
including the required Acknowledge sequence at the
end of the byte.
FIGURE 3-2: START HEADER
Note: After a POR/BOR event occurs, a low-
to-high tra nsitio n on SCIO mus t be gen-
erated before proceeding with commu-
nication , including a standby pulse.
11010100
Start Heade r
SCIO
Devi ce A ddress
MAK
00001010
MAK
NoSAK
SAK
Standby Pulse(1)
11010100
Start Header
SCIO
Device Address
MAK
00001010
MAK
NoSAK
SAK
NoMAK
SAK
TSS
Note 1: After a POR/BOR event, a low-to-high transition on SCIO is required to occur before the first
standby pulse.
SCIO
Data ‘0’Data ‘1’Data ‘0’Data ‘1’Data ‘0’Data ‘1’Data ‘0’Data ‘1’MAK NoSAKTSS THDR
11XX
DS22067J-page 8 2011 Microchip Technology Inc.
3.3 Acknowledge
An Acknowledge routine occurs after each byte is
transmitted, including the start header. This routine
consists of two bits. The first bit is transmitted by the
master, and the second bit is transmitted by the slave.
The Master Acknowl edge, or MAK, is signified by trans-
mitting a ‘1’, and informs the slave that the current
operation is to be continued. Conversely, a Not
Acknowledge, or NoMAK, is signified by transmitting a
‘0’, and is used to end the current opera tion (and initia te
the write cycle for write operations).
The slave Acknowledge, or SAK, is also signified by
transmitting a ‘1’, and con firm s proper co mm uni ca tio n.
However, unlike the No MAK, the NoSAK is sign ified b y
the lack of a middle edge during the bit period.
A NoSAK will occur for the following events:
• Following the start header
• Following the device address, if no slave on the
bus matches the transmitted address
• Following the command byte, if the command is
invalid, including Read, CRRD, Write, WRSR,
SETAL, and ERAL during a write cycle.
• If the slave becomes out of sync with the master
• If a command is terminated prematurely by using
a NoMAK, with the exception of immediatel y after
the device address.
See Figure 3.3 and Figure 3-4 for details.
If a NoSAK is received from the slave after any byte
(except the start header), an error has occurred. The
master sh ould then perfor m a stan dby pul se and begi n
the desired command again.
FIGURE 3-3: ACKNOWLEDGE
ROUTINE
FIGURE 3-4: ACKNOWLEDGE BITS
3.4 Device Addressing
A devic e address byte is the first byte received from th e
master device following the start header. The device
address byte consists of a four-bit family code, for the
11XX this is set as ‘1010’. The last four bits of the
device address byte are the device code, which is
hardwi red to ‘0000’ on the 11XXXX0 devices.
The device code on 11XXXX1 devices is hardwired to
‘0001’. This allows both 11XXXX0 and 11XXXX1
devices to be used on the same bus without address
conflicts.
FIGURE 3-5: DEVICE ADDRESS BYTE
ALLOCATION
3.5 Bus Conflict Protection
To help guard against high current conditions arising
from bus conflicts, the 11XX features a current-limited
output driver. The IOL and IOH specifications describe
the maximum current that can be sunk or sourced,
respectively, by the SCIO pin. The 11XX will vary the
output driver impedance to ensure that the maximum
current level is not exceeded.
Note: A MAK must always be transmitted
following the start header.
Note: When a NoMAK is used to end a
WRITE or WRSR instruction, the write
cycle is not initiated if no bytes of data
have been received.
Note: In order to guard against bus conten-
tion, a NoSAK will occur after the start
header.
Master Slave
MAK SAK
MAK (‘1’)
NoMAK (‘0’)
SAK (‘1’)
NoSAK(1)
Note 1: valid SAK.
A NoSAK is defined as any sequen ce that is not a
1010000
MAK
SLAVE ADDRESS
0(1)
SAK
Note 1: This bit is a ‘1’ on the 11XXXX1.
2011 Microchip Technology Inc. DS22067J-page 9
11XX
3.6 Device Standby
The 11XX fe atures a low-po wer Stand by mode du ring
which the device is waiting to begin a new command.
A high-to-low transition on SCIO will exit low-power
mode and prepare the device for receiving the start
header.
Standby mode will be entered upon the following
conditions:
• A NoMAK followed by a SAK (i.e., valid termina-
tion of a command)
• Reception of a standby pulse
3.7 Device Idle
The 11XX features an Idle m ode du ring w hi ch all s eria l
data is ignored until a standby pulse occ urs . Idle mod e
will be entered upon the following conditions:
• Invalid device address
• Invalid command byte, including Read, CRRD,
Write, WRSR, SETAL and ERAL during a write
cycle.
• Missed edge transition
• Reception of a MAK following a WREN, WRDI,
SETAL, or ERAL command byte
• Reception of a MAK following the data byte of a
WRSR command
An invalid start header will indirectly cause the device
to enter Idle mode. Whether or not the start header is
invalid cannot be detected by the slave, but will
prevent the slave from synchronizing properly with the
master. If the slave is not synchronized with the
master, a n e dge t r ans iti on will be mi ss ed , th us c au sin g
the device to enter Idle mode.
3.8 Synchronization
At the beginning of every command, the 11XX utilizes
the start header to determine the master’s bus clock
period. This period is then used as a reference for all
subsequent communication within that command.
The 11XX features re-synchronization circuitry which
will monitor the position of the middle data edge during
each MAK bi t and subs equently adju st the internal tim e
reference in order to remain synchronized with the
master.
There are two variables which can cause the 11XX to
lose synchronization. The first is frequency drift,
defined as a ch ange i n the bit period, TE. The second is
edge jitter, which is a single occurrence change in the
position of an edge within a bit period, while the bit
period itself remains constant.
3.8.1 FREQUENCY DRIFT
With in a syst em, th ere is a p ossibi lity that fr equen cies
can drift due to changes in voltage, temperature, etc.
The re-synchronization circuitry provides some toler-
ance for such frequency drift. The tolerance range is
specified by two parameters, FDRIFT and FDEV. FDRIFT
specifies the maximum tolerable change in bus fre-
quency per byte. FDEV specifies the overall limit in fre-
quency deviation within an operati on (i.e., from the en d
of the start header until communication is terminated
for that o pera tion). T he sta rt head er at th e begi nning of
the next operation will reset the re-synchronization cir-
cuitr y an d a l low fo r an o t her FDEV amount of frequency
drift.
3.8.2 EDGE JITTER
Ensuring that edge transitions from the master always
occur exactly in the middle or end of the bi t period is not
alwa ys po s si bl e. T h er ef or e, t he re - sy nc hro ni z at i on cir -
cuitry is designed to provide some tolerance for edge
jitter.
The 11XX adjusts its phase every MAK bit, so TIJIT
specifies the maximum allowable peak-to-peak jitter
relative to the previous MAK bit. Since the position of
the previous MAK bit would be difficult to measure by
the maste r , the m inimum and maximum jitte r values for
a system should be considered the worst-case. These
values will be based on the execution time for different
branch paths in software, jitter due to thermal noise,
etc.
The difference between the minimum and maximum
values , as a percent age of the b it period, should be cal-
culated and then compared against TIJIT to determine
jitter compliance.
Note: In the case of the WRITE, WRSR, SETAL,
or ERAL commands, the write cycle is initi-
ated upon receipt of the NoMAK, assuming
all other w rite requi rem en ts have been met.
Note: Because the 11XX only re-synchronizes
during the MAK bit, the overall ability to
remain synchronized depends on a combi-
nation o f frequency d r if t and ed ge j itter (i.e.,
if the MAK bit e dge is experien cing the max-
imum allowable edge jitter, then there is no
room for frequency drift). Conversely, if the
frequency has drifted to the maximum
amount tolerable within a byte, then no
edge jitter can be present.
11XX
DS22067J-page 10 2011 Microchip Technology Inc.
4.0 DEVICE COMMANDS
After the device address byte, a command byte must
be sent by the master to indicate the type of operation
to be performed. Th e c ode for ea ch ins truc ti on is listed
in Table 4-1.
TABLE 4-1: INSTRUCTION SET
4.1 Read Instruction
The Read command allows the master to access any
memory location in a random manner. After the READ
instruction has been sent to the slave, the two bytes of
the Word Address are transmitted, with an Acknowl-
edge se quence being performed af ter each byte. The n,
the sla ve sends the first data byte to the mast er . If more
data is to be read, the master sends a MAK, indicating
that the slave should output the next data byte. This
continu es until t he master se nds a NoMAK, w hich ends
the operation.
To provide sequential reads in this manner, the 11XX
contains an internal Address Pointer which is incre-
mented by one after the transmission of each byte. This
Address Pointer allows the entire memory contents to
be serially read during one operation. When the highest
address is reached, the Address Pointer rolls over to
address ‘0x000’ if the master chooses to continue the
operation by providing a MAK.
FIGURE 4-1: READ COMMAND SEQUENCE
Instruction Name Instruction Code Hex Code Description
READ 0000 0011 0x03 Read data from memory array beginning at specified address
CRRD 0000 0110 0x06 Read data from current location in memory array
WRITE 0110 1100 0x6C Write data to memory array beginning at specified address
WREN 1001 0110 0x96 Set the write enable latch (enable write operations)
WRDI 1001 0001 0x91 Reset the write enable latch (disable write operations)
RDSR 0000 0101 0x05 Read STATUS register
WRSR 0110 1110 0x6E Write STATUS re gister
ERAL 0110 1101 0x6D Write ‘0x00’ to entire array
SETAL 0110 0111 0x67 Write ‘0xFF’ to entire array
7654
Data Byte 1
32107654
Data Byte 2
32107654
Data Byte n
3210
SCIO
MAK
MAK
NoMAK
11010100
Start Heade r
SCIO
Device Address
MAK
00
(1)
001010
MAK
Command
01000001
MAK
NoSAK
SAK
Standby Pulse
SCIO
SAK
15 14 13 12
Word Address M SB
11 10 9 8
MAK
SAK
7654
Word Address LSB
3210
MAK
SAK
SAK
SAK
SAK
Note 1: For the 11XXXX1, this bit must be a ‘1’.
2011 Microchip Technology Inc. DS22067J-page 11
11XX
4.2 Current Address Read (CRRD)
Instruction
The internal address counter featured on the 11XX
maintains the address of the last memory array loca-
tion accessed. The CRRD instruction allows the mas-
ter to read data back beginning from this current
location. Consequently, no word address is provided
upon issuing this command.
Note that, except for the initial word address, the
READ and CRRD instructions are identical, including
the ability to continue requesting data through the use
of MAKs in order to sequentially read from the array.
As with the READ instruction, the CRRD instruction is
termina ted by transmitting a NoMAK.
Table 4-2 lists the events upon which the internal
address counter is modified.
TABLE 4-2: INTERNAL ADDRESS
COUNTER
FIGURE 4-2: CRRD COMMAND SEQUEN CE
Command Event Action
— Power-on Reset Counter is undefined
READ or
WRITE MAK edge fol-
lowing each
Address byt e
Counter is updated
with newly received
value
READ,
WRITE, or
CRRD
MAK/NoMAK
edge following
each data byte
Counter is incre-
mented by 1
Note: If, following each data byte in a READ,
WRITE, or CRRD instruction, neither a
MAK nor a NoMAK edge is received
(i.e., if a standby pulse occurs instead),
the internal address counter will not be
incremented.
Note: During a Write command, once the last
data byte for a page has been loaded,
the internal Addre ss Poi nter w i ll ro ll ove r
to the beginning of the selected page.
7654
Data Byte 1
32107654
Data Byte 2
3210
7654
Data Byte n
3210
SCIO
MAK
MAK
NoMAK
11010100
Start Head er
SCIO
Device Address
MAK
00
(1)
001010
MAK
Command
10000001
MAK
NoSAK
SAK
Standby Pulse
SCIO
SAK
SAK
SAK
SAK
Note 1: For the 11XXXX1, this bit must be a ‘1’.
11XX
DS22067J-page 12 2011 Microchip Technology Inc.
4.3 Wr ite Instruction
Prior to a ny att em pt t o wri te data to the 11XX, the wri te
enable latch must be set by issuing the WREN
instruction (see Section 4.4 “Write Enable (WREN)
and Write Disable (WRDI) Instructions”).
Once the write enable latch is set, the user may pro-
ceed with issuing a WRITE instruction (including the
header a nd device ad dress bytes) fo llowed by t he MSB
and LSB of the Word Address. Once the la st Acknowl-
edge sequence has been performed, the master
transmits the data byte to be written.
The 11XX features a 16-byt e page bu ffer, meaning th at
up to 16 byt es can be writt en at one time . To utilize thi s
feature, the master can transmit up to 16 data bytes to
the 11XX, which are tem porarily s tored in the page b uf-
fer . Af ter each dat a byte, the m aster sends a MAK, indi-
cating whether or not another data byte is to follow. A
NoMAK in dicate s that no mo re dat a is to follo w, and as
such will initiate the internal write cycle.
Upon receipt of each word, the four lower-order
Address Po inter bit s are internal ly incremen ted by one.
The higher-order bits of the word address remain con-
stan t. If the mas ter shoul d transmit data p ast the e nd of
the page, the address counter will roll over to the begin-
ning of the page, where further received data will be
written.
FIGURE 4-3: WRITE COMMAND SEQUENCE
Note: If a NoMAK is generated before any
data has been provided, or if a standby
puls e oc cu r s be for e th e N oMA K is gen -
erated, the 11XX will be reset, and the
write cyc l e will not be in itiated.
Note: Page write operations are limited to writ-
ing bytes within a single physical page,
regardless of the numb er of bytes actu-
ally bei ng writ ten. Phys ical p age bo und -
aries start at addresses that are integer
multip les of the page size (16 bytes) and
end at addresses that are integer multi-
ples of the page size minus 1. As an
example, the page that begins at
address 0x30 ends at ad dress 0x3F. If a
page Write command attempts to write
across a physical page boundary, the
result is that the data wraps around to
the beginning of th e cu rrent p age ( ove r-
writing data previously stored there),
instea d of b eing w ritte n to th e nex t p age
as might be expected. It is therefore
necessary for the application software
to prevent page write operations that
would attempt to cross a page bound-
ary.
7654
Data Byte 1
32107654
Data Byte 2
32107654
Data Byte n
3210
SCIO
MAK
MAK
No MAK
11010100
Start Header
SCIO
Device Address
MAK
00
(1)
001010
MAK
Command
10101100
MAK
NoSAK
SAK
Standby Pulse
SCIO
SAK
15 14 13 12
Word Addre ss MSB
11 10 9 8
MAK
SAK
7654
Word Address LSB
3210
MAK
SAK
SAK
SAK
SAK
Twc
Note 1: For the 11XXXX1, this bit must be a ‘1’.
2011 Microchip Technology Inc. DS22067J-page 13
11XX
4.4 Wr ite Enable (WREN) and Write
Disable (WRDI) Instr uctions
The 11XX contains a write enable latch. See Table 6-1
for the Write-Protect Functionality Matrix. This latch
must be set before any write operation will be com-
pleted internally. The WREN instruction will set the
latch, and the WRDI instruction will reset the latch.
The following is a list of conditions under which the
write enab le latc h wi ll be reset:
• Power-up
•WRDI instruction successfully executed
•WRSR instruction successfully executed
•WRITE instruction successfully executed
•ERAL instruction successfully executed
•SETAL instruction successfully executed
FIGURE 4-4: WRITE ENABLE COMMAND SEQUENCE
FIGURE 4-5: WRITE DISABLE COMMAND SEQUEN CE
Note: The WREN and WRDI instruct ions must
be terminated with a NoMAK following
the command byte. If a NoMAK is not
received at this point, the command will
be considered invalid, and the device
will go into Idle mode without respond-
ing with a SAK or executing the com-
mand.
11010100
Start Header
SCIO
Devi ce A ddre ss
MAK
00
(1)
001010
MAK
Command
10010011
NoMAK
NoSAK
SAK
Standby Pulse
SCIO
SAK
Note 1: For the 11XXXX1, this bit must be a ‘1’.
11010100
Start Header
SCIO
Devi ce A ddre ss
MAK
00
(1)
001010
MAK
Command
01010010
NoMAK
NoSAK
SAK
Standby Pulse
SCIO
SAK
Note 1: For the 11XXXX1, this bit must be a ‘1’.
11XX
DS22067J-page 14 2011 Microchip Technology Inc.
4.5 Read Sta tus Regist er (RDSR)
Instruction
The RDSR instruction provides access to the STATUS
register. The ST ATUS register ma y be read at any time,
even during a write cycle. The STATUS register is
formatted as follows:
The Write-In-Process (WIP) bit indicates whether the
11XX is busy with a write operation. When set to a ‘1’,
a write is in progress, when set to a ‘0’, no write is in
progress. This bit is read-only.
The Write Enable La tch (WEL) bit indi cat es the st atu s
of the write enable latch. When set to a ‘1’, the latch
allows writes to the array, when set to a ‘0’, the latch
prohibits writes to the array. This bit is set and cleared
using the WREN and WRDI instructions, respectively.
This bit is read-only for any other instruction.
The Block Protection (BP0 and BP1) bits indicate
which blocks are currently write-protected. These bits
are set by the user through the WRSR instruction.
These bits are nonvolatile.
The WIP and WEL bits will update dynamically (asyn-
chronous to issuing the RDSR instruction). Further-
more, after the STATUS register data is received, the
master can provide a MAK during the Acknowledge
sequence to request that the data be tra nsmitted again.
This allows the master to continuously monitor the WIP
and WEL bits without the need to issue another full
command.
Once the master is finished, it provides a NoMAK to
end the operation.
FIGURE 4-6: READ STATUS REGISTER COMMAND SEQUENCE
7654 3 2 1 0
XXXXBP1 BP0 WEL WIP
Note: Bit s 4-7 are don ’t cares, and will read as ‘0’.
Note: If Read Status Register command is
initiated while the 11XX is currently
exec utin g an int erna l wri te cyc le on the
STATUS register, the new Block
Protection bit values will be read during
the entire command.
Note: The current drawn for a Read Status
Register command during a write cycle
is a co mbination of the ICC Read and ICC
Write operating currents.
11010100
Start Header
SCIO
Device Address
MAK
00
(1)
001010
MAK
Command
11000000
MAK
NoSAK
SAK
Standby Pulse
SCIO
SAK
STATUS Register Data
3210
NoMAK
SAK
The STATUS register data can continuously be read, or polled, by transmitting a MAK in place of the NoMAK.Note 2:
0000
Note 1: For the 11XXXX1, this bit must be a ‘1’.
2011 Microchip Technology Inc. DS22067J-page 15
11XX
4.6 Wr it e Status Register (WRSR)
Instruction
The WRSR instruction allows the user to select one of
four levels of protection for the array by writing to the
appropriate bits in the STATUS register. The array is
divided up into four segments. The user has the ability
to write-protect none, one, two, or all four of the seg-
ments of the array. The partitioning is controlled as
illustrated in Table 4-3.
Aft er transmitting the ST ATUS register dat a, the mast er
must transmit a NoMAK during the Acknowledge
sequence in order to initiate the internal write cycle.
TABLE 4-3: ARRAY PROTECTION
TABLE 4-4: PROTECTED ARRAY ADDRESS LOCATIONS
FIGURE 4-7: WRITE STATUS REGISTER COMMAND SEQUENCE
Note: The WRSR instruction must be termi-
nated with a NoMAK following the data
byte. If a NoMAK is not received at this
point, the command will be considered
invalid, and the device will go into Idle
mode without responding with a SAK or
executing th e command.
BP1 BP0 Address Ranges Write-Protected Address Ranges Unprotected
00 None All
01 Upper 1/4 Lower 3/4
10 Upper 1/2 Lower 1/2
11 All None
Density Upper 1/4 Upper 1/2 All Sectors
1K 60h-7Fh 40h-7Fh 00h-7Fh
2K C0h-FFh 80h-FFh 00h-FFh
4K 180h-1FFh 100h-1FFh 000h-1FFh
8K 300h-3FFh 200h-3FFh 000h-3FFh
16K 600h-7FFh 400h-7FFh 000h-7FFh
11010100
Start Header
SCIO
Devi ce A ddre ss
MAK
00
(1)
001010
MAK
Command
10101101
MAK
NoSAK
SAK
Standby Puls e
SCIO
SAK
7654
Status Register Data
3210
NoMAK
SAK
Twc
Note 1: For the 11XXXX1, this bit must be a ‘1’.
11XX
DS22067J-page 16 2011 Microchip Technology Inc.
4.7 Erase All (ERAL) Instruct ion
The ERAL instruction allows the user to write ‘0x00’ to
the entire memory array with one command. Note that
the write enab le latch (WEL) must first be set by issuing
the WREN instruction.
Once the write enable latch is set, the user may pro-
ceed with issuing a ERAL instruction (including the
header and device address bytes). Immediately after
the No MAK bit has been tra nsmi tted by the maste r, the
internal write cycle is initiated, during which time all
words of the memory array are written to ‘0x00’.
The ERAL instruction is ignored if either of the Block
Protect bits (BP0, BP1) are not 0, meaning 1/4, 1/2, or
all of the array is protected.
FIGURE 4-8: ERASE ALL COMMAND SEQUENCE
4.8 Set All (SETAL) Instruction
The SETAL instruction allows the user to write ‘0xFF’
to the entire memory array with one command. Note
that the write enable latch (WEL) must first be set by
issuing the WREN instru cti on.
Once the write enable latch is set, the user may pro-
ceed with issuing a SETAL instruction (including the
header and device address bytes). Immediately after
the No MAK bit has been tra nsmi tted by the maste r, the
internal write cycle is initiated, during which time all
words of the memory array are written to ‘0xFF’.
The SETAL instruction is ignored if either of the Block
Protect bits (BP0, BP1) are not 0, meaning 1/4, 1/2, or
all of the array is protected.
FIGURE 4-9: SET ALL COMMAND SEQUENCE
Note: The ERAL instruction must be termi-
nated with a NoMAK following the com-
mand by te. If a NoMAK is not received
at this point, the command will be con-
sidered invalid, and the device will go
into Idle mode without responding with a
SAK or executing the command.
11010100
Start Header
SCIO
Devi ce A ddre ss
MAK
00
(1)
001010
MAK
Command
11101100
NoMAK
NoSAK
SAK
Standby Pulse
SCIO
SAK
Twc
Note 1: For the 11XXXX1, this bit must be a ‘1’.
Note: The SETAL instruction must be termi-
nated with a NoMAK following the com-
mand by te. If a NoMAK is not received
at this point, the command will be con-
sidered invalid, and the device will go
into Idle mode without responding with a
SAK or executing the command.
11010100
Start Header
SCIO
Device Address
MAK
00
(1)
001010
MAK
Command
11001101
NoMAK
NoSAK
SAK
Standby Pulse
SCIO
SAK
Twc
Note 1: For the 11XXXX1, this bit must be a ‘1’.
2011 Microchip Technology Inc. DS22067J-page 17
11XX
5.0 DATA PROTECTIO N
The following protection has been implemented to
prevent ina dv erte nt wri tes to the array:
• The Write Enable Latch (WEL) is reset on power-
up
•A Write Enable (
WREN) instructi on must be issued
to set the write enable latch
• After a write , ERAL , SETAL, or WRSR command ,
the write enable latch is reset
• Commands to access the array or write to the
stat us register are ig nored during an internal write
cycl e and programming is not affected
6.0 POWER-ON STATE
The 11XX powers on in the following state:
• The devi ce is in low -po wer Shutdown mode,
requiring a l ow-to -high transit ion o n SCIO to e nter
Idle mode
• The Write Enable Latch (WEL) is reset
• The internal Address Pointer is undefined
• A low- to -hig h tra ns iti on, standb y pul se and subse-
quent high-to-low transition on SCIO (the first low
pulse of the header) are required to enter the
active state
.
TABLE 6-1: WRITE PROTECT FUNCTIONALITY MATRIX
WEL Protected Blocks Unprotected Blocks Status Register
0Protected Protected Protected
1Protected Writable Writable
11XX
DS22067J-page 18 2011 Microchip Technology Inc.
7.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 7-1.
TABLE 7-1: PIN FUNCTION TABLE
7.1 Serial Clock, Data Input/Output
(SCIO)
SCIO is a bidirectional pin used to transfer commands
and addresses in to, as well as data into a nd o ut o f, the
device. The serial clock is embedded into the data
stream through Manchester encoding. Each bit is
represented by a signal transition at the middle of the
bit period.
Name 3-pin SOT-23 3-pin TO-92 4-pin CS 8-pin PDIP/SOIC/
MSOP/TDFN Description
SCIO 1 2 3 5 Serial Clock, Data Input/Output
VCC 2 3 1 8 Supply Voltage
VSS 3 1 2 4 Ground
NC — — 4 1,2,3,6,7 No Internal Connection
2011 Microchip Technology Inc. DS22067J-page 19
11XX
8.0 PACKAGING INFORMATION
8.1 Package Marking Information
T/XXXNNN
XXXXXXXX
YYWW
8-Lead PDIP
I/P 1L7
11AA160
0828
Example:
3
e
8-Lead PDIP Package Marking (Pb-Free)
Device Line 1 Marking Device Line 1 Marking
11AA010 11AA010 11LC010 11LC010
11AA020 11AA020 11LC020 11LC020
11AA040 11AA040 11LC040 11LC040
11AA080 11AA080 11LC080 11LC080
11AA160 11AA160 11LC160 11LC160
11AA161 11AA161 11LC161 11LC161
Note: T = Temperature Grade (I, E)
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-fr ee. The Pb- fre e JED EC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full M icroc hip p art numb er cann ot be mark ed on one line, it wil l
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e