Sample & Buy Product Folder Support & Community Tools & Software Technical Documents OPA348-Q1, OPA2348-Q1, OPA4348-Q1 SBOS465C - JANUARY 2009 - REVISED JANUARY 2016 OPAx348-Q1 1-MHz 45-A CMOS Rail-to-Rail Operational Amplifier 1 Features 3 Description * * The OPAx348-Q1 series of devices are single-supply, low-power CMOS operational amplifiers. Featuring an extended bandwidth of 1 MHz and a supply current of 45 A, the OPAx348-Q1 family of devices is useful for low-power applications on single supplies of 2.1 V to 5.5 V. 1 * * * * * * Qualified for Automotive Applications AEC-Q100 Qualified With the Following Results: - Device Temperature Grade 1: -40C to +125C Ambient Operating Temperature Range - Device HBM ESD Classification Level 2 - Device CDM ESD Classification Level C4B Low Quiescent Current (IQ): 45 A (Typ) Low Cost Rail-to-Rail Input and Output Single Supply: 2.1 V to 5.5 V Input Bias Current: 0.5 pA (Typ) High Speed: Power With Bandwidth: 1 MHz Low supply current of 45 A and an input bias current of 0.5 pA make the OPAx348-Q1 family of devices an optimal candidate for low-power, high-impedance applications such as smoke detectors and other sensors. The OPA348-Q1 device is available in both the SOT23-5 (DBV) and the SOIC (D) packages. The OPA2348-Q1 device is available in the SOIC-8 (D) package. The OPA4348-Q1 device is available in the TSSOP-14 (PW) package. The automotive temperature range of -40C to +125C over all supply voltages offers additional design flexibility. 2 Applications * * * * * * * Portable Equipment Battery-Powered Equipment Smoke Alarms CO Detectors HEV/EV and Power Train Infotainment and Cluster Medical Instrumentation Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) SOT-23 (5) 2.90 mm x 1.60 mm SOIC (8) 4.90 mm x 3.91 mm OPA2348-Q1 SOIC (8) 4.90 mm x 3.91 mm OPA4348-Q1 TSSOP (14) 5.00 mm x 4.40 mm OPA348-Q1 (1) For all available packages, see the orderable addendum at the end of the datasheet. Noninverting Configuration Driving ADS7822 5V 0.1 F 8 V+ 1/2 OPA2348-Q1 500 0.1 F 1 VREF DCLOCK +IN ADS7822 12-Bit A/D 2 VIN 3300 pF -IN 3 DOUT CS/SHDN 7 6 5 Serial Interface GND 4 VIN = 0 V to 5 V for 0-V to 5-V output. RC network filters high-frequency noise. 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. OPA348-Q1, OPA2348-Q1, OPA4348-Q1 SBOS465C - JANUARY 2009 - REVISED JANUARY 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 5 6.1 6.2 6.3 6.4 6.5 6.6 6.7 5 5 5 6 6 7 8 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information: OPA348-Q1 ............................ Thermal Information: OPA2348-Q1, OPA4348-Q1... Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description ............................................ 11 7.1 Overview ................................................................. 11 7.2 Functional Block Diagram ....................................... 11 7.3 Feature Description................................................. 12 7.4 Device Functional Modes........................................ 15 8 Application and Implementation ........................ 16 8.1 Application Information............................................ 16 8.2 Typical Application ................................................. 17 9 Power Supply Recommendations...................... 19 10 Layout................................................................... 20 10.1 Layout Guidelines ................................................. 20 10.2 Layout Example .................................................... 20 11 Device and Documentation Support ................. 21 11.1 11.2 11.3 11.4 11.5 11.6 Documentation Support ........................................ Related Links ........................................................ Community Resource............................................ Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 21 21 21 21 21 21 12 Mechanical, Packaging, and Orderable Information ........................................................... 21 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (December 2014) to Revision C * Page Added the OPA348-Q1 SOIC (D) package option to document ............................................................................................ 1 Changes from Revision A (January 2009) to Revision B Page * Added two new applications to the Applications section ....................................................................................................... 1 * Added the ESD Ratings table, Feature Description section, Device Functional Modes section, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ............................................................... 1 * Added the OPA348-Q1 device to the data sheet .................................................................................................................. 1 * Changed the name for pin 3 in the PW (TSSOP) package drawing ...................................................................................... 4 2 Submit Documentation Feedback Copyright (c) 2009-2016, Texas Instruments Incorporated Product Folder Links: OPA348-Q1 OPA2348-Q1 OPA4348-Q1 OPA348-Q1, OPA2348-Q1, OPA4348-Q1 www.ti.com SBOS465C - JANUARY 2009 - REVISED JANUARY 2016 5 Pin Configuration and Functions DBV Package: OPA348-Q1 5-Pin SOT-23 Top View Out 1 V- 2 +In 3 5 4 D Package: OPA348-Q1 8-Pin SOIC Top View V+ -In NC 1 -In 2 +In 3 V- 4 8 NC - 7 V+ + 6 OUT 5 nc Pin Functions: OPA348-Q1 PIN NO. NAME I/O DESCRIPTION SOT-23 SOIC +IN 3 3 I Noninverting input -IN 4 2 I Inverting input OUT 1 6 O Output V+ 5 7 -- Positive (highest) supply V- 2 4 -- Negative (lowest) supply -- Do not connect 1 NC -- 5 8 D Package: OPA2348-Q1 8-Pin SOIC Top View Out A 1 -In A 2 A +In A 3 V- B 4 8 V+ 7 Out B 6 -In B 5 +In B Pin Functions: OPA2348-Q1 PIN I/O DESCRIPTION NAME NO +IN A 3 I Noninverting input, Channel A -IN A 2 I Inverting input, Channel A +IN B 5 I Noninverting input, Channel B -IN B 6 I Inverting input, Channel B OUT A 1 O Output, Channel A OUT B 7 O Output, Channel B V+ 8 -- Positive (highest) supply V- 4 -- Negative (lowest) supply Copyright (c) 2009-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: OPA348-Q1 OPA2348-Q1 OPA4348-Q1 3 OPA348-Q1, OPA2348-Q1, OPA4348-Q1 SBOS465C - JANUARY 2009 - REVISED JANUARY 2016 www.ti.com PW Package: OPA4348-Q1 14-Pin TSSOP Top View 14 Out D 13 -In D 3 12 +In D V+ 4 11 V- +In B 5 10 +In C Out A 1 -In A 2 +In A A B D C -In B 6 9 -In C Out B 7 8 Out C Pin Functions: OPA4348-Q1 PIN I/O DESCRIPTION NAME NO. +IN A 3 I Noninverting input, Channel A -IN A 2 I Inverting input, Channel A +IN B 5 I Noninverting input, Channel B -IN B 6 I Inverting input, Channel B +IN C 10 I Noninverting input, Channel C -IN C 9 I Inverting input, Channel C +IN D 12 I Noninverting input, Channel D -IN D 13 I Inverting input, Channel D OUT A 1 O Output, Channel A OUT B 7 O Output, Channel B OUT C 8 O Output, Channel C OUT D 14 O Output, Channel D V+ 4 -- Positive (highest) supply V- 11 -- Negative (lowest) supply 4 Submit Documentation Feedback Copyright (c) 2009-2016, Texas Instruments Incorporated Product Folder Links: OPA348-Q1 OPA2348-Q1 OPA4348-Q1 OPA348-Q1, OPA2348-Q1, OPA4348-Q1 www.ti.com SBOS465C - JANUARY 2009 - REVISED JANUARY 2016 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN Supply voltage, VS V- to V+ Input voltage, VIN Signal input terminals (2) Input current, IIN Signal input terminals (2) (V-) - 0.5 V Output short-circuit duration (3) V 10 mA 150 C 150 C 150 C -40 Storage temperature, Tstg (3) V (V+) + 0.5 V Operating virtual-junction temperature, TJ (2) UNIT 7.5 Continuous Operating free-air temperature, TA (1) MAX -65 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails should be current-limited to 10 mA or less. Short-circuit to ground, one amplifier per package. 6.2 ESD Ratings VALUE Human-body model (HBM), per AEC Q100-002 (1) V(ESD) (1) Electrostatic discharge Charged-device model (CDM), per AEC Q100-011 UNIT 2000 All pins 500 Corner pins (1, 7, 8, and 14) 750 V AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VS Supply voltage, V- to V+ 2.1 5.5 V TA Operating free-air temperature -40 125 C Copyright (c) 2009-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: OPA348-Q1 OPA2348-Q1 OPA4348-Q1 5 OPA348-Q1, OPA2348-Q1, OPA4348-Q1 SBOS465C - JANUARY 2009 - REVISED JANUARY 2016 www.ti.com 6.4 Thermal Information: OPA348-Q1 OPA348-Q1 THERMAL METRIC (1) DBV (SOT-23) D (SOIC) 5 PINS 8 PINS UNIT RJA Junction-to-ambient thermal resistance 228.5 142.0 C/W RJC(top) Junction-to-case (top) thermal resistance 99.1 90.2 C/W RJB Junction-to-board thermal resistance 54.6 82.5 C/W JT Junction-to-top characterization parameter 7.7 39.4 C/W JB Junction-to-board characterization parameter 53.8 82.0 C/W RJC(bottom) Junction-to-case (bottom) thermal resistance n/a n/a C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. 6.5 Thermal Information: OPA2348-Q1, OPA4348-Q1 THERMAL METRIC (1) OPA2348-Q1 OPA4348-Q1 D (SOIC) PW (TSSOP) 8 PINS 14 PINS UNIT RJA Junction-to-ambient thermal resistance 138.4 121 C/W RJC(top) Junction-to-case (top) thermal resistance 89.5 49.4 C/W RJB Junction-to-board thermal resistance 78.6 62.8 C/W JT Junction-to-top characterization parameter 29.9 5.9 C/W JB Junction-to-board characterization parameter 78.1 62.2 C/W RJC(bottom) Junction-to-case (bottom) thermal resistance n/a n/a C/W (1) 6 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright (c) 2009-2016, Texas Instruments Incorporated Product Folder Links: OPA348-Q1 OPA2348-Q1 OPA4348-Q1 OPA348-Q1, OPA2348-Q1, OPA4348-Q1 www.ti.com SBOS465C - JANUARY 2009 - REVISED JANUARY 2016 6.6 Electrical Characteristics At VS = 2.5 V to 5.5 V, RL = 100 k connected to VS / 2, VOUT = VS / 2 (unless otherwise noted). PARAMETER TEST CONDITIONS VOS Input offset voltage VOS/T Offset voltage drift over temperature PSRR VS = 5 V, VCM = (V-) + 0.8 V Offset voltage drift vs power supply Channel separation VCM VS = 2.5 V to 5.5 V, VCM < (V+) - 1.7 V TA (1) MIN 25C TYP MAX 1 5 Full range Full range 4 25C 60 Full range V/C 175 V/V 300 25C 0.2 f = 1 kHz 25C 134 (V-) - 0.2 V < VCM < (V+) - 1.7 V mV 6 dc Input common-mode voltage range UNIT 25C (V-) - 0.2 25C 70 Full range 66 25C 60 Full range 56 V/V dB (V+) + 0.2 V 82 CMRR Input common-mode rejection ratio IB Input bias current 25C 0.5 10 pA IOS Input offset current 25C 0.5 10 pA VS = 5.5 V, (V-) - 0.2 V < VCM < (V+) + 0.2 V VS = 5.5 V, (V-) < VCM < (V+) 1013|| 3 Differential ZI Input impedance dB 71 25C || pF 1013|| 3 Common-mode Input voltage noise VCM < (V+) - 1.7 V, f = 0.1 Hz to 10 Hz 25C 10 VPP Vn Input voltage noise density VCM < (V+) - 1.7 V, f = 1 kHz 25C 35 nV/Hz In Input current noise density VCM < (V+) - 1.7 V, f = 1 kHz 25C 4 fA/Hz VS = 5 V, RL = 100 k, 0.025 V < VO < 4.975 V 25C 94 Full range 90 25C 90 Full range 88 AOL Open-loop voltage gain VS = 5V, RL = 5 k, 0.125 V < VO < 4.875 V RL = 100 k, AOL > 94 dB Voltage output swing from rail RL = 5 k, AOL > 90 dB 25C Capacitive load drive See the Typical Characteristics section 25C GBW Gain-bandwidth product CL = 100 pF SR Slew rate CL = 100 pF, G = +1 Settling time 100 mV mV 10 mA 25C 1 MHz 25C 0.5 V/s 5 CL = 100 pF, VS = 5.5 V, 2V- step, G = +1 25C Overload recovery time VIN x Gain > VS 25C 1.6 THD+N Total harmonic distortion plus noise CL = 100 pF, VS = 5.5 V, VO = 3 VPP, G = +1, f = 1 kHz 25C 0.0023% IQ Quiescent current Per amplifier 25C 45 (1) 125 125 25C 0.01% 25 25 25C Output short-circuit current ts 18 Full range CLOAD dB 98 Full range ISC 0.1% 108 s 7 Full range s 65 75 A Full range TA = -40C to +125C. Copyright (c) 2009-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: OPA348-Q1 OPA2348-Q1 OPA4348-Q1 7 OPA348-Q1, OPA2348-Q1, OPA4348-Q1 SBOS465C - JANUARY 2009 - REVISED JANUARY 2016 www.ti.com 6.7 Typical Characteristics At TA = 25C, RL = 100 k connected to VS / 2, VOUT = VS / 2 (unless otherwise noted). 140 100 0 80 100 80 Gain 60 -90 Phase 40 20 -135 PSRR, CMRR (dB) -45 Phase () Open-Loop Gain (dB) 120 CMRR 60 40 PSRR 20 0 -20 1 0.1 10 100 1k 10k 100k 1M 0 -180 10M 10 100 1k Figure 1. Open-Loop Gain and Phase vs Frequency 6 10k 100k 1M 10M Frequency (Hz) Frequency (Hz) Figure 2. PSRR and CMRR vs Frequency 140 V S = 5.5 V Channel Separation (dB) Output Voltage (Vp-p) 5 VS = 5 V 4 3 2 V S = 2.5 V 120 100 80 1 60 0 1k 10k 100k 1M 10 10M 100 1k 2 10 45 7 IQ 35 4 Output Voltage Swing (V) 55 Short-Circuit Current (mA) ISC +125C 1 3 3.5 4 10M 4.5 5 5.5 Supply Voltage (V) +25C 1.5 -40C 1 Sourcing Current 0.5 0 -0.5 -1 Sinking Current -1.5 -40C +25C -2 25 2.5 1M 2.5 13 2 100k Figure 4. Channel Separation vs Frequency Figure 3. Maximum Output Voltage vs Frequency 65 Quiescent Current ( A) 10k Frequency (Hz) Frequency (Hz) +125C -2.5 0 5 10 15 20 Output Current (mA) VS = 2.5V Figure 5. Quiescent and Short-Circuit Current vs Supply Voltage 8 Submit Documentation Feedback Figure 6. Output Voltage Swing vs Output Current Copyright (c) 2009-2016, Texas Instruments Incorporated Product Folder Links: OPA348-Q1 OPA2348-Q1 OPA4348-Q1 OPA348-Q1, OPA2348-Q1, OPA4348-Q1 www.ti.com SBOS465C - JANUARY 2009 - REVISED JANUARY 2016 Typical Characteristics (continued) At TA = 25C, RL = 100 k connected to VS / 2, VOUT = VS / 2 (unless otherwise noted). 100 130 90 Open-Loop Gain and Power Supply Rejection (dB) Common-Mode Rejection (dB) AOL , R L = 100 k 120 V- < VCM < (V+) - 1.7 V 80 V- < VCM < V+ 70 60 50 AOL , R L = 5 k 110 100 90 80 PSRR 70 60 -50 -75 -25 0 25 50 75 100 125 150 -50 -75 -25 0 Temperature (C) Figure 7. Common-Mode Rejection vs Temperature 75 55 12 45 10 IQ 35 8 25 6 15 4 0 25 50 100 125 150 1k Input Bias Current (pA) 14 ISC -25 75 Figure 8. Open-Loop Gain and PSRR vs Temperature Short-Circuit Current (mA) Quiescent Current ( A) 65 -50 50 10k 16 -75 25 Temperature (C) 75 100 125 100 10 1 0.1 150 -75 -50 -25 0 25 50 75 100 125 150 Temperature (C) Temperature (C) Figure 9. Quiescent and Short-Circuit Current vs Temperature Figure 10. Input Bias (IB) Current vs Temperature 25 20 Percentage of Amplifiers (%) 18 Percent of Amplifiers (%) 16 14 12 10 8 6 4 20 15 10 5 2 0 0 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 Offset Voltage (mV) Typical production distribution of packaged units. Figure 11. Offset Voltage Production Distribution Copyright (c) 2009-2016, Texas Instruments Incorporated 1 2 3 4 5 6 7 8 9 10 11 12 Offset Voltage Drift (V/C) Typical production distribution of packaged units. Figure 12. Offset Voltage Drift Magnitude Production Distribution Submit Documentation Feedback Product Folder Links: OPA348-Q1 OPA2348-Q1 OPA4348-Q1 9 OPA348-Q1, OPA2348-Q1, OPA4348-Q1 SBOS465C - JANUARY 2009 - REVISED JANUARY 2016 www.ti.com Typical Characteristics (continued) At TA = 25C, RL = 100 k connected to VS / 2, VOUT = VS / 2 (unless otherwise noted). 60 60 50 50 40 40 Overshoot (%) Small-Signal Overshoot (%) G = -1 V/V, R FB = 100 kW 30 G = +1 V/V, RL = 100 kW 20 30 20 G = -1 V/V, RFB = 5 kW 10 10 0 0 10 100 1k 10k 10 100 Load Capacitance (pF) 1k 10k Load Capacitance (pF) G = 5 V/V, RFB = 100 k Figure 13. Small-Signal Overshoot vs Load Capacitance 20 mV/div 500 mV/div Figure 14. Percent Overshoot vs Load Capacitance 10 s/div 2 s/div G = 1 V/V RL = 100 k CL = 100 pF G = 1 V/V Figure 16. Large-Signal Step Response 1k 1k 100 IN VN 10 10 1 1 10 100 1k 10k 100k Total Harmonic Distortion + Noise (%) 10k 100 0.100 0.010 0.001 10 100 Figure 17. Input Current and Voltage Noise Spectral Density vs Frequency Submit Documentation Feedback 1k 10k 100k Frequency (Hz) Frequency (Hz) 10 CL = 100 pF 1.000 Current Noise (fAHz) Voltage Noise (nV/Hz) Figure 15. Small-Signal Step Response RL = 100 k Figure 18. Total Harmonic Distortion + Noise vs Frequency Copyright (c) 2009-2016, Texas Instruments Incorporated Product Folder Links: OPA348-Q1 OPA2348-Q1 OPA4348-Q1 OPA348-Q1, OPA2348-Q1, OPA4348-Q1 www.ti.com SBOS465C - JANUARY 2009 - REVISED JANUARY 2016 7 Detailed Description 7.1 Overview The OPAx348-Q1 family of devices is a low-power, rail-to-rail input and output operational amplifier. These devices operate from 1.8 V to 5.5 V, are unity-gain stable, and are suitable for a wide range of general-purpose applications. The class AB output stage is capable of driving 10-k loads connected to any point between V+ and ground. The input common-mode voltage range includes both rails and allows the OPAx348-Q1 family of devices to be used in virtually any single-supply application. Rail-to-rail input and output swing significantly increases dynamic range, especially in low-supply applications, and makes them ideal for driving sampling analog-to-digital converters (ADCs). 7.2 Functional Block Diagram OPA348-Q1 V+ Reference Current VIN+ VIN VBIAS1 Class AB Control Circuitry Vo VBIAS2 V (Ground) Copyright (c) 2009-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: OPA348-Q1 OPA2348-Q1 OPA4348-Q1 11 OPA348-Q1, OPA2348-Q1, OPA4348-Q1 SBOS465C - JANUARY 2009 - REVISED JANUARY 2016 www.ti.com 7.3 Feature Description 7.3.1 Operating Voltage The OPAx348-Q1 op amp is fully specified and ensured for operation from 1.8 V to 5.5 V. In addition, many specifications apply from -40C to +125C. Parameters that vary significantly with operating voltages or temperature are shown in the Typical Characteristics graphs. Power-supply pins should be bypassed with 0.01-F ceramic capacitors. 7.3.2 Rail-to-Rail Input The input common-mode voltage range of the OPAx348-Q1 family of devices extends 200 mV beyond the supply rails. This performance is achieved with a complementary input stage: an N-channel input differential pair in parallel with a P-channel differential pair. The N-channel pair is active for input voltages close to the positive rail, typically (V+) - 1.3 V to 200 mV above the positive supply. The P-channel pair is on for inputs from 200 mV below the negative supply to approximately (V+) - 1.3 V. A small transition region exists, typically (V+) - 1.4 V to (V+) - 1.2 V, in which both pairs are on. This 200-mV transition region can vary up to 300 mV with process variation. Thus, the transition region (both stages on) can range from (V+) - 1.7 V to (V+) - 1.5 V on the low end, up to (V+) - 1.1 V to (V+) - 0.9 V on the high end. Within this transition region, PSRR, CMRR, offset voltage, offset drift, and THD may be degraded compared to device operation outside this region. 7.3.3 Rail-to-Rail Input The input common-mode range extends from (V-) - 0.2 V to (V+) + 0.2 V. For normal operation, the inputs should be limited to this range. The absolute maximum input voltage is 500 mV beyond the supplies. Inputs greater than the input common-mode range but less than the maximum input voltage, while not valid, do not cause any damage to the op amp. Unlike some other op amps, if the input current is limited, the inputs may go beyond the power supplies without phase inversion, as shown in Figure 19. VIN G = +1V/V, V S = +5V 5V 1V/div VOUT 0V 10s/div Figure 19. No Phase Inversion with Inputs Greater Than Power-Supply Voltage Normally, input currents are 0.5 pA. However, large inputs (greater than 500 mV beyond the supply rails) can cause excessive current to flow in or out of the input pins. Therefore, limiting the input current to less than 10 mA is important as well as keeping the input voltage below the maximum rating. This limiting is easily accomplished with an input voltage resistor, as shown in Figure 20. +5V IOVERLOAD 10mA max 1/2 OPA2348 VOUT VIN 5kW Figure 20. Input Current Protection for Voltages Exceeding the Supply Voltage 12 Submit Documentation Feedback Copyright (c) 2009-2016, Texas Instruments Incorporated Product Folder Links: OPA348-Q1 OPA2348-Q1 OPA4348-Q1 OPA348-Q1, OPA2348-Q1, OPA4348-Q1 www.ti.com SBOS465C - JANUARY 2009 - REVISED JANUARY 2016 Feature Description (continued) 7.3.4 Input and ESD Protection The OPAx348-Q1 family of devices incorporates internal electrostatic discharge (ESD) protection circuits on all pins. In the case of input and output pins, this protection primarily consists of current-steering diodes connected between the input and power-supply pins. These ESD protection diodes also provide in-circuit, input overdrive protection, as long as the current is limited to 10 mA as stated in the Absolute Maximum Ratings table. Figure 21 shows how a series input resistor can be added to the driven input to limit the input current. The added resistor contributes thermal noise at the amplifier input and the value should be kept to a minimum in noise-sensitive applications. V+ IOVERLOAD 10-mA max VOUT Device VIN 5 kW Figure 21. Input Current Protection 7.3.5 Common-Mode Rejection Ratio (CMRR) CMRR for the OPAx348-Q1 family of devices is specified in several ways so the best match for a given application may be used; see the Electrical Characteristics table. First, the CMRR of the device in the commonmode range below the transition region [VCM < (V+) - 1.3 V] is given. This specification is the best indicator of the capability of the device when the application requires use of one of the differential input pairs. Second, the CMRR over the entire common-mode range is specified at (VCM = -0.2 V to 5.7 V). This last value includes the variations seen through the transition region (see Figure 22). 7.3.6 Common-Mode Voltage Range The input common-mode voltage range of the OPAx348-Q1 device extends 200 mV beyond the supply rails. This extended range is achieved with a complementary input stage--an N-channel input differential pair in parallel with a P-channel differential pair. The N-channel pair is active for input voltages close to the positive rail, typically (V+) - 1.2 V to 300 mV above the positive supply, while the P-channel pair is on for inputs from 300 mV below the negative supply to approximately (V+) - 1.4 V. A small transition region exists, typically (V+) - 1.4 V to (V+) - 1.2 V, in which both pairs are on. This 200-mV transition region, shown in Figure 22, can vary 300 mV with process variation. Thus, the transition region (both stages on) can range from (V+) - 1.7 V to (V+) - 1.5 V on the low end, up to (V+) - 1.1 V to (V+) - 0.9 V on the high end. Within the 200-mV transition region, PSRR, CMRR, offset voltage, offset drift, and THD may be degraded compared to operation outside this region. OFFSET VOLTAGE vs FULL COMMON-MODE VOLTAGE RANGE 2 Offset Voltage (mV) 1.5 1 0.5 0 -0.5 -1 V- V+ -1.5 -2 -0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Common-Mode Voltage (V) Figure 22. Behavior of Typical Transition Region at Room Temperature Copyright (c) 2009-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: OPA348-Q1 OPA2348-Q1 OPA4348-Q1 13 OPA348-Q1, OPA2348-Q1, OPA4348-Q1 SBOS465C - JANUARY 2009 - REVISED JANUARY 2016 www.ti.com Feature Description (continued) 7.3.7 EMI Susceptibility and Input Filtering Op amps vary with regard to the susceptibility of the device to electromagnetic interference (EMI). If conducted EMI enters the op amp, the dc offset observed at the amplifier output may shift from the nominal value while EMI is present. This shift is a result of signal rectification associated with the internal semiconductor junctions. While all op amp pin functions can be affected by EMI, the signal input pins are likely to be the most susceptible. The OPAx348-Q1 family of devices incorporates an internal input, low-pass filter that reduces the amplifier response to EMI. Both common-mode and differential mode filtering are provided by this filter. The filter is designed for a cutoff frequency of approximately 80 MHz (-3 dB), with a roll-off of 20 dB per decade. Texas Instruments has developed the ability to accurately measure and quantify the immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz. The EMI rejection ratio (EMIRR) metric allows op amps to be directly compared by the EMI immunity. Detailed information can also be found in the application report, EMI Rejection Ratio of Operational Amplifiers (SBOA128), available for download from www.ti.com. 7.3.8 Rail-to-Rail Output Designed as a micro-power, low-noise operational amplifier, the OPAx348-Q1 family of devices delivers a robust output drive capability. A class AB output stage with common-source transistors is used to achieve full rail-to-rail output swing capability. For resistive loads up to 10 k, the output swings typically to within 5 mV of either supply rail regardless of the power-supply voltage applied. Different load conditions change the ability of the amplifier to swing close to the rails; refer to the graph, Output Voltage Swing vs Output Current. A class AB output stage with common-source transistors is used to achieve rail-to-rail output. This output stage is capable of driving 5-k loads connected to any potential between V+ and ground. For light resistive loads (>100 k), the output voltage can typically swing to within 18 mV from supply rail. With moderate resistive loads (10 k to 50 k), the output voltage can typically swing to within 100 mV of the supply rails while maintaining high open-loop gain (see Figure 6 in the Typical Characteristics section). G = +1V/V, VS = +5V Output (Inverted on Scope) 1V/div 5V 0V 20s/div Figure 23. Rail-to-Rail I/O 14 Submit Documentation Feedback Copyright (c) 2009-2016, Texas Instruments Incorporated Product Folder Links: OPA348-Q1 OPA2348-Q1 OPA4348-Q1 OPA348-Q1, OPA2348-Q1, OPA4348-Q1 www.ti.com SBOS465C - JANUARY 2009 - REVISED JANUARY 2016 Feature Description (continued) 7.3.9 Capacitive Load and Stability The OPAx348-Q1 family of devices in a unity-gain configuration can directly drive up to 250-pF pure capacitive load. Increasing the gain enhances the ability of the amplifier to drive greater capacitive loads (see Figure 13 in the Typical Characteristics section). In unity-gain configurations, capacitive load drive can be improved by inserting a small (10- to 20-) resistor, RS, in series with the output, as shown in Figure 24. This resistor significantly reduces ringing while maintaining dc performance for purely capacitive loads. However, if a resistive load exists in parallel with the capacitive load, a voltage divider is created, introducing a direct current (dc) error at the output and slightly reducing the output swing. The error introduced is proportional to the ratio RS/RL and is generally negligible. V+ RS 1/2 OPA2348 VOUT 10W to 20W VIN RL CL Figure 24. Series Resistor in Unity-Gain Buffer Configuration Improves Capacitive Load Drive In unity-gain inverter configuration, the phase margin can be reduced by the reaction between the capacitance at the op amp input and the gain setting resistors, thus degrading capacitive load drive. The best performance is achieved by using small-valued resistors. For example, when driving a 500-pF load, reducing the resistor values from 100 k to 5 k decreases overshoot from 55% to 13% (see Figure 13 in the Typical Characteristics section). However, when large-valued resistors cannot be avoided, a small (4-pF to 6-pF) capacitor, CFB, can be inserted in the feedback loop, as shown in Figure 25. This small capacitor significantly reduces overshoot by compensating the effect of capacitance, CIN, which includes the input capacitance of the amplifier and printed circuit board (PCB) parasitic capacitance. CFB RF RI VIN 1/2 OPA2348 VOUT CIN CL Figure 25. Improving Capacitive Load Drive 7.4 Device Functional Modes The OPAx348-Q1 family of devices is powered on when the supply is connected. The device can be operated as a single-supply operational amplifier or a dual-supply amplifier, depending on the application. Copyright (c) 2009-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: OPA348-Q1 OPA2348-Q1 OPA4348-Q1 15 OPA348-Q1, OPA2348-Q1, OPA4348-Q1 SBOS465C - JANUARY 2009 - REVISED JANUARY 2016 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The OPAx348-Q1 operational amplifiers (op amps) are unity-gain stable and suitable for a wide range of generalpurpose applications. The OPAx348-Q1 device features wide bandwidth and unity-gain stability with rail-to-rail input and output for increased dynamic range. Figure 23 shows the input and output waveforms for the OPAx348-Q1 device in unitygain configuration. Operation is from a single 5-V supply with a 100-k load connected to VS / 2. The input is a 5-VPP sinusoid. Output voltage is approximately 4.98 VPP. The power-supply pins should be bypassed with 0.01-F ceramic capacitors. 8.1.1 Driving Analog-to-Digital Converters (ADCs) The OPAx348-Q1 op amps are optimized for driving medium-speed sampling ADCs. The OPAx348-Q1 op amps buffer the ADC input capacitance and resulting charge injection while providing signal gain. Figure 26 shows the OPA2348 in a basic noninverting configuration driving the ADS7822 device. The ADS7822 device is a 12-bit, micropower sampling converter in the MSOP-8 package. When used with the low-power miniature packages of the OPAx348-Q1 family of devices, the combination is ideal for space-limited, low-power applications. In this configuration, an RC network at the ADC input can be used to provide for anti-aliasing filtering and charge injection current. 5V 0.1 F 8 V+ 1/2 OPA2348-Q1 500 0.1 F 1 VREF DCLOCK +IN ADS7822 12-Bit A/D 2 VIN 3300 pF -IN 3 DOUT CS/SHDN 7 6 5 Serial Interface GND 4 VIN = 0 V to 5 V for 0-V to 5-V output. RC network filters high-frequency noise. A/D input = 0 V to VREF Figure 26. Noninverting Configuration Driving ADS7822 The OPAx348-Q1 family of devices can also be used in noninverting configuration to drive the ADS7822 device in limited low-power applications. In this configuration, an RC network at the ADC input can be used to provide for anti-aliasing filtering and charge injection current. See Figure 26 for the OPAx348-Q1 driving an ADS7822 device in a speech bandpass filtered data acquisition system. This small, low-cost solution provides the necessary amplification and signal conditioning to interface directly with an electret microphone. This circuit operates with VS = 2.7 V to 5 V with less than 250-A typical quiescent current. 16 Submit Documentation Feedback Copyright (c) 2009-2016, Texas Instruments Incorporated Product Folder Links: OPA348-Q1 OPA2348-Q1 OPA4348-Q1 OPA348-Q1, OPA2348-Q1, OPA4348-Q1 www.ti.com SBOS465C - JANUARY 2009 - REVISED JANUARY 2016 Application Information (continued) V+ = 2.7 V to 5 V Passband 300 Hz to 3 kHz R9 510 k R1 1.5 k R4 20 k R2 1 M C1 1000 pF 1/2 C3 33 pF R7 51 k R8 150 k VREF 1 8 V+ 7 OPA2348-Q1 +IN 1/2 R3 1 M Electret Microphone(1) R6 100 k OPA2348-Q1 C2 2 -IN 1000 pF DCLOCK ADS7822 6 12-Bit A/D 5 DOUT CS/SHDN Serial Interface 3 4 R5 20 k (1) G = 100 GND Electret microphone powered by R1. Figure 27. Speech Bandpass Filtered Data Acquisition System 8.2 Typical Application Some applications require differential signals. Figure 28 shows a simple circuit to convert a single-ended input of 0.1 V to 2.4 V into a differential output of 2.3 V on a single 2.7-V supply. The output range is intentionally limited to maximize linearity. The circuit is composed of two amplifiers. One amplifier functions as a buffer and creates a voltage, VOUT+. The second amplifier inverts the input and adds a reference voltage to generate VOUT-. Both VOUT+ and VOUT- range from 0.1 V to 2.4 V. The difference, VDIFF, is the difference between VOUT+ and VOUT-. This configuration makes the differential output voltage range to be 2.3 V. R2 2.7 V R1 VOUT + Device R3 + VREF 2.5 V R4 V VDIFF + 2.7 V VOUT+ + Device + + VIN Figure 28. Schematic for a Single-Ended Input to Differential Output Conversion Copyright (c) 2009-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: OPA348-Q1 OPA2348-Q1 OPA4348-Q1 17 OPA348-Q1, OPA2348-Q1, OPA4348-Q1 SBOS465C - JANUARY 2009 - REVISED JANUARY 2016 www.ti.com Typical Application (continued) 8.2.1 Design Requirements The design requirements are as follows: * Supply voltage: 2.7 V * Reference voltage: 2.5 V * Input: 0.1 V to 2.4 V * Output differential: 2.3 V * Output common-mode voltage: 1.25 V * Small-signal bandwidth: 1 MHz 8.2.2 Detailed Design Procedure The circuit in Figure 28 takes a single-ended input signal, VIN, and generates two output signals, VOUT+ and VOUT- using two amplifiers and a reference voltage, VREF. VOUT+ is the output of the first amplifier and is a buffered version of the input signal, VIN (as shown in Equation 1). VOUT- is the output of the second amplifier which uses VREF to add an offset voltage to VIN and feedback to add inverting gain. The transfer function for VOUT- is given in Equation 2. VOUT VIN (1) V287 R 4 * R2 * R2 V5() u u 1 V,1 u R R R R1 4 (c) 1 (c) 3 (2) The differential output signal, VDIFF, is the difference between the two single-ended output signals, VOUT+ and VOUT-. Equation 3 shows the transfer function for VDIFF. By applying the conditions that R1 = R2 and R3 = R4, the transfer function is simplified into Equation 6. Using this configuration, the maximum input signal is equal to the reference voltage and the maximum output of each amplifier is equal to VREF. The differential output range is 2 x VREF. Furthermore, the common-mode voltage (VCM) is one half of VREF (see Equation 7). V',)) V287 VOUT VIN V287 V5() V287 R 4 * R2 * R2 * V,1 u 1 u 1 V5() u R1 R1 (c) (c) R3 R 4 (c) (3) (4) V,1 VDIFF 2 u VIN VREF VCM V287 * V287 2 (c) (5) (6) 1 VREF 2 (7) 8.2.2.1 Amplifier Selection Linearity over the input range is key for good dc accuracy. The common-mode input range and output swing limitations determine the linearity. In general, an amplifier with rail-to-rail input and output swing is required. Bandwidth is a key concern for this design, so the OPAx348-Q1 family of devices is selected because its bandwidth is greater than the target of 1 MHz. The bandwidth and power ratio makes this device power-efficient, and the low offset and drift ensure good accuracy for moderate precision applications. 8.2.2.2 Passive Component Selection Because the transfer function of VOUT- relies heavily upon resistors (R1, R2, R3, and R4), use resistors with low tolerances to maximize performance and minimize error. This design uses resistors with resistance values of 49.9 k and tolerances of 0.1%. However, if the noise of the system is a key parameter, smaller resistance values (6 k or lower) can be selected to keep the overall system noise low. This technique ensures that the noise from the resistors is lower than the amplifier noise. 18 Submit Documentation Feedback Copyright (c) 2009-2016, Texas Instruments Incorporated Product Folder Links: OPA348-Q1 OPA2348-Q1 OPA4348-Q1 OPA348-Q1, OPA2348-Q1, OPA4348-Q1 www.ti.com SBOS465C - JANUARY 2009 - REVISED JANUARY 2016 Typical Application (continued) 2.50 2.50 2.00 2.00 1.50 1.50 Vout- (V) Vout+ (V) 8.2.3 Application Curves 1.00 0.50 0.00 0.00 1.00 0.50 0.50 1.00 1.50 2.00 0.00 0.00 2.50 Input voltage (V) 0.50 1.00 1.50 2.00 Input voltage (V) C027 Figure 29. VOUT+ vs Input Voltage 2.50 C027 Figure 30. VOUT- vs Input Voltage 2.50 2.00 1.50 Vdiff (V) 1.00 0.50 0.00 -0.50 -1.00 -1.50 -2.00 -2.50 0.00 0.50 1.00 1.50 2.00 Input voltage (V) 2.50 C027 Figure 31. VDIFF vs Input Voltage 9 Power Supply Recommendations The OPAx348-Q1 family of devices is specified for operation from 1.8 V to 5.5 V (0.9 V to 2.75 V); many specifications apply from -40C to 125C. The Typical Characteristics presents parameters that can exhibit significant variance with regard to operating voltage or temperature. CAUTION Supply voltages larger than 7 V can permanently damage the device (see the Absolute Maximum Ratings). Place 0.1-F bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or highimpedance power supplies. For more detailed information on bypass capacitor placement, refer to the Layout Guidelines section. Copyright (c) 2009-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: OPA348-Q1 OPA2348-Q1 OPA4348-Q1 19 OPA348-Q1, OPA2348-Q1, OPA4348-Q1 SBOS465C - JANUARY 2009 - REVISED JANUARY 2016 www.ti.com 10 Layout 10.1 Layout Guidelines For best operational performance of the device, use good PCB layout practices, including: * Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing lowimpedance power sources local to the analog circuitry. - Connect low-ESR, 0.1-F ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications. * Separate grounding for analog and digital portions of the circuitry is one of the simplest and most effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital and analog grounds, paying attention to the flow of the ground current. For more detailed information, refer to Circuit Board Layout Techniques, SLOA089. * To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicularly is much better than crossing in parallel with the noisy trace. * Place the external components as close to the device as possible. Keep RF and RG close to the inverting input to minimize parasitic capacitance, as shown in Figure 32. * Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitive part of the circuit. * Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce leakage currents from nearby traces that are at different potentials. 10.2 Layout Example + VIN VOUT RG RF (Schematic Representation) Run the input traces as far away from the supply lines as possible Place components close to device and to each other to reduce parasitic errors VS+ RF N/C N/C GND IN V+ VIN +IN OUTPUT V N/C RG Use low-ESR, ceramic bypass capacitor GND GND Use low-ESR, ceramic bypass capacitor VOUT VS Ground (GND) plane on another layer Figure 32. Operational Amplifier Board Layout for Noninverting Configuration 20 Submit Documentation Feedback Copyright (c) 2009-2016, Texas Instruments Incorporated Product Folder Links: OPA348-Q1 OPA2348-Q1 OPA4348-Q1 OPA348-Q1, OPA2348-Q1, OPA4348-Q1 www.ti.com SBOS465C - JANUARY 2009 - REVISED JANUARY 2016 11 Device and Documentation Support 11.1 Documentation Support 11.1.1 Related Documentation For related documentation see the following: * ADS7822: 12-Bit, 200kHz, microPower Sampling Analog-to-Digital Converter, SBAS062 * Application report: Circuit Board Layout Techniques, SLOA089 * Application report: EMI Rejection Ratio of Operational Amplifiers, SBOA128 11.2 Related Links Table 1 lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 1. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY OPA348-Q1 Click here Click here Click here Click here Click here OPA2348-Q1 Click here Click here Click here Click here Click here OPA4348-Q1 Click here Click here Click here Click here Click here 11.3 Community Resource The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.4 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.6 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright (c) 2009-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: OPA348-Q1 OPA2348-Q1 OPA4348-Q1 21 PACKAGE OPTION ADDENDUM www.ti.com 16-Dec-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) OPA2348AQDRQ1 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 OPA 2348Q OPA348AQDBVRQ1 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 A48 OPA348AQDRQ1 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 348Q1 OPA4348AQPWRQ1 ACTIVE TSSOP PW 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 OP4348Q (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 16-Dec-2015 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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OTHER QUALIFIED VERSIONS OF OPA2348-Q1, OPA348-Q1, OPA4348-Q1 : * Catalog: OPA2348, OPA348, OPA4348 NOTE: Qualified Version Definitions: * Catalog - TI's standard catalog product Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 17-Dec-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) OPA2348AQDRQ1 SOIC D 8 2500 330.0 OPA348AQDBVRQ1 SOT-23 DBV 5 3000 OPA348AQDRQ1 SOIC D 8 2500 OPA4348AQPWRQ1 TSSOP PW 14 2500 B0 (mm) K0 (mm) P1 (mm) 12.4 6.4 5.2 2.1 8.0 178.0 9.0 3.3 3.2 1.4 330.0 12.4 6.4 5.2 2.1 330.0 12.4 6.9 5.6 1.6 Pack Materials-Page 1 W Pin1 (mm) Quadrant 12.0 Q1 4.0 8.0 Q3 8.0 12.0 Q1 8.0 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 17-Dec-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) OPA2348AQDRQ1 SOIC D 8 2500 367.0 367.0 35.0 OPA348AQDBVRQ1 SOT-23 DBV 5 3000 180.0 180.0 18.0 OPA348AQDRQ1 SOIC D 8 2500 367.0 367.0 35.0 OPA4348AQPWRQ1 TSSOP PW 14 2500 367.0 367.0 35.0 Pack Materials-Page 2 PACKAGE OUTLINE DBV0005A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 1.75 1.45 PIN 1 INDEX AREA 1 0.1 C B A 5 2X 0.95 1.9 1.45 MAX 3.05 2.75 1.9 2 4 0.5 5X 0.3 0.2 3 (1.1) C A B 0.15 TYP 0.00 0.25 GAGE PLANE 8 TYP 0 0.22 TYP 0.08 0.6 TYP 0.3 SEATING PLANE 4214839/C 04/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. www.ti.com EXAMPLE BOARD LAYOUT DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MIN ARROUND 0.07 MAX ARROUND NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS 4214839/C 04/2017 NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X(0.95) 4 3 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214839/C 04/2017 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. www.ti.com PACKAGE OUTLINE DBV0005A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 1.75 1.45 PIN 1 INDEX AREA 1 0.1 C B A 5 2X 0.95 1.9 1.45 MAX 3.05 2.75 1.9 2 4 0.5 5X 0.3 0.2 3 (1.1) C A B 0.15 TYP 0.00 0.25 GAGE PLANE 8 TYP 0 0.22 TYP 0.08 0.6 TYP 0.3 SEATING PLANE 4214839/C 04/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. www.ti.com EXAMPLE BOARD LAYOUT DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MIN ARROUND 0.07 MAX ARROUND NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS 4214839/C 04/2017 NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X(0.95) 4 3 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214839/C 04/2017 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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