ADS7822
12-Bit A/D
DCLOCK
DOUT
CS/SHDN
1/2
OPA2348-Q1
5 V
VIN
V+
2
+IN
3
–IN
VREF
8
4GND
Serial
Interface
1
0.1 µF 0.1 µF
7
6
5
VIN = 0 V to 5 V for
0-V to 5-V output.
RC network filters high-frequency noise.
500 Ω
3300 pF
Product
Folder
Sample &
Buy
Technical
Documents
Tools &
Software
Support &
Community
OPA348-Q1
,
OPA2348-Q1
,
OPA4348-Q1
SBOS465C –JANUARY 2009–REVISED JANUARY 2016
OPAx348-Q1 1-MHz 45-µA CMOS Rail-to-Rail Operational Amplifier
1 Features 3 Description
The OPAx348-Q1 series of devices are single-supply,
1• Qualified for Automotive Applications low-power CMOS operational amplifiers. Featuring an
• AEC-Q100 Qualified With the Following Results: extended bandwidth of 1 MHz and a supply current of
– Device Temperature Grade 1: –40°C to 45 µA, the OPAx348-Q1 family of devices is useful
+125°C Ambient Operating Temperature for low-power applications on single supplies of 2.1 V
to 5.5 V.
Range
– Device HBM ESD Classification Level 2 Low supply current of 45 µA and an input bias current
of 0.5 pA make the OPAx348-Q1 family of devices an
– Device CDM ESD Classification Level C4B optimal candidate for low-power, high-impedance
• Low Quiescent Current (IQ): 45 µA (Typ) applications such as smoke detectors and other
• Low Cost sensors.
• Rail-to-Rail Input and Output The OPA348-Q1 device is available in both the
• Single Supply: 2.1 V to 5.5 V SOT23-5 (DBV) and the SOIC (D) packages. The
OPA2348-Q1 device is available in the SOIC-8 (D)
• Input Bias Current: 0.5 pA (Typ) package. The OPA4348-Q1 device is available in the
• High Speed: Power With Bandwidth: 1 MHz TSSOP-14 (PW) package. The automotive
temperature range of –40°C to +125°C over all
2 Applications supply voltages offers additional design flexibility.
• Portable Equipment Device Information(1)
• Battery-Powered Equipment PART NUMBER PACKAGE BODY SIZE (NOM)
• Smoke Alarms SOT-23 (5) 2.90 mm × 1.60 mm
• CO Detectors OPA348-Q1 SOIC (8) 4.90 mm × 3.91 mm
• HEV/EV and Power Train OPA2348-Q1 SOIC (8) 4.90 mm × 3.91 mm
• Infotainment and Cluster OPA4348-Q1 TSSOP (14) 5.00 mm × 4.40 mm
• Medical Instrumentation (1) For all available packages, see the orderable addendum at
the end of the datasheet.
Noninverting Configuration Driving ADS7822
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA348-Q1
,
OPA2348-Q1
,
OPA4348-Q1
SBOS465C –JANUARY 2009–REVISED JANUARY 2016
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Table of Contents
7.4 Device Functional Modes........................................ 15
1 Features.................................................................. 18 Application and Implementation ........................ 16
2 Applications ........................................................... 18.1 Application Information............................................ 16
3 Description............................................................. 18.2 Typical Application ................................................. 17
4 Revision History..................................................... 29 Power Supply Recommendations...................... 19
5 Pin Configuration and Functions......................... 310 Layout................................................................... 20
6 Specifications......................................................... 510.1 Layout Guidelines ................................................. 20
6.1 Absolute Maximum Ratings ...................................... 510.2 Layout Example .................................................... 20
6.2 ESD Ratings.............................................................. 511 Device and Documentation Support................. 21
6.3 Recommended Operating Conditions....................... 511.1 Documentation Support ........................................ 21
6.4 Thermal Information: OPA348-Q1 ............................ 611.2 Related Links ........................................................ 21
6.5 Thermal Information: OPA2348-Q1, OPA4348-Q1... 611.3 Community Resource............................................ 21
6.6 Electrical Characteristics........................................... 711.4 Trademarks........................................................... 21
6.7 Typical Characteristics.............................................. 811.5 Electrostatic Discharge Caution............................ 21
7 Detailed Description............................................ 11 11.6 Glossary................................................................ 21
7.1 Overview................................................................. 11 12 Mechanical, Packaging, and Orderable
7.2 Functional Block Diagram....................................... 11 Information ........................................................... 21
7.3 Feature Description................................................. 12
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (December 2014) to Revision C Page
• Added the OPA348-Q1 SOIC (D) package option to document............................................................................................ 1
Changes from Revision A (January 2009) to Revision B Page
• Added two new applications to the Applications section ....................................................................................................... 1
• Added the ESD Ratings table, Feature Description section, Device Functional Modes section, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section ............................................................... 1
• Added the OPA348-Q1 device to the data sheet .................................................................................................................. 1
• Changed the name for pin 3 in the PW (TSSOP) package drawing...................................................................................... 4
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1
2
3
4
8
7
6
5
V+
Out B
-In B
+In B
Out A
-In A
+In A
V-
A
B
1
2
3
4
8
7
6
5
NC
V+
OUT
nc
NC
-In
+In
V-
––
+
1
2
3
5
4
V+
–In
Out
V–
+In
OPA348-Q1
,
OPA2348-Q1
,
OPA4348-Q1
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5 Pin Configuration and Functions
DBV Package: OPA348-Q1 D Package: OPA348-Q1
5-Pin SOT-23 8-Pin SOIC
Top View Top View
Pin Functions: OPA348-Q1
PIN
NO. I/O DESCRIPTION
NAME SOT-23 SOIC
+IN 3 3 I Noninverting input
–IN 4 2 I Inverting input
OUT 1 6 O Output
V+ 5 7 — Positive (highest) supply
V– 2 4 — Negative (lowest) supply
1
NC — 5 — Do not connect
8
D Package: OPA2348-Q1
8-Pin SOIC
Top View
Pin Functions: OPA2348-Q1
PIN I/O DESCRIPTION
NAME NO
+IN A 3 I Noninverting input, Channel A
–IN A 2 I Inverting input, Channel A
+IN B 5 I Noninverting input, Channel B
–IN B 6 I Inverting input, Channel B
OUT A 1 O Output, Channel A
OUT B 7 O Output, Channel B
V+ 8 — Positive (highest) supply
V– 4 — Negative (lowest) supply
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PW Package: OPA4348-Q1
14-Pin TSSOP
Top View
Pin Functions: OPA4348-Q1
PIN I/O DESCRIPTION
NAME NO.
+IN A 3 I Noninverting input, Channel A
–IN A 2 I Inverting input, Channel A
+IN B 5 I Noninverting input, Channel B
–IN B 6 I Inverting input, Channel B
+IN C 10 I Noninverting input, Channel C
–IN C 9 I Inverting input, Channel C
+IN D 12 I Noninverting input, Channel D
–IN D 13 I Inverting input, Channel D
OUT A 1 O Output, Channel A
OUT B 7 O Output, Channel B
OUT C 8 O Output, Channel C
OUT D 14 O Output, Channel D
V+ 4 — Positive (highest) supply
V– 11 — Negative (lowest) supply
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage, VSV– to V+ 7.5 V
Input voltage, VIN Signal input terminals(2) (V–) – 0.5 V (V+) + 0.5 V V
Input current, IIN Signal input terminals(2) 10 mA
Output short-circuit duration(3) Continuous
Operating free-air temperature, TA–40 150 °C
Operating virtual-junction temperature, TJ150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails should
be current-limited to 10 mA or less.
(3) Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings VALUE UNIT
Human-body model (HBM), per AEC Q100-002(1) ±2000
Electrostatic
V(ESD) All pins ±500 V
Charged-device model (CDM), per AEC
discharge Q100-011 Corner pins (1, 7, 8, and 14) ±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT
VSSupply voltage, V– to V+ 2.1 5.5 V
TAOperating free-air temperature –40 125 °C
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6.4 Thermal Information: OPA348-Q1 OPA348-Q1
THERMAL METRIC(1) DBV (SOT-23) D (SOIC) UNIT
5 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 228.5 142.0 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 99.1 90.2 °C/W
RθJB Junction-to-board thermal resistance 54.6 82.5 °C/W
ψJT Junction-to-top characterization parameter 7.7 39.4 °C/W
ψJB Junction-to-board characterization parameter 53.8 82.0 °C/W
RθJC(bottom) Junction-to-case (bottom) thermal resistance n/a n/a °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Thermal Information: OPA2348-Q1, OPA4348-Q1 OPA2348-Q1 OPA4348-Q1
THERMAL METRIC(1) D (SOIC) PW (TSSOP) UNIT
8 PINS 14 PINS
RθJA Junction-to-ambient thermal resistance 138.4 121 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 89.5 49.4 °C/W
RθJB Junction-to-board thermal resistance 78.6 62.8 °C/W
ψJT Junction-to-top characterization parameter 29.9 5.9 °C/W
ψJB Junction-to-board characterization parameter 78.1 62.2 °C/W
RθJC(bottom) Junction-to-case (bottom) thermal resistance n/a n/a °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.6 Electrical Characteristics
At VS= 2.5 V to 5.5 V, RL= 100 kΩconnected to VS/ 2, VOUT = VS/ 2 (unless otherwise noted).
PARAMETER TEST CONDITIONS TA(1) MIN TYP MAX UNIT
25°C 1 5
VOS Input offset voltage VS= 5 V, VCM = (V–) + 0.8 V mV
Full range 6
ΔVOS/ΔT Offset voltage drift over temperature Full range 4 µV/°C
25°C 60 175
PSRR Offset voltage drift vs power supply VS= 2.5 V to 5.5 V, VCM < (V+) – 1.7 V µV/V
Full range 300
dc 25°C 0.2 µV/V
Channel separation f = 1 kHz 25°C 134 dB
VCM Input common-mode voltage range 25°C (V–) – 0.2 (V+) + 0.2 V
25°C 70 82
(V–) – 0.2 V < VCM < (V+) – 1.7 V Full range 66
CMRR Input common-mode rejection ratio dB
VS= 5.5 V, (V–) – 0.2 V < VCM < (V+) + 0.2 V 25°C 60 71
VS= 5.5 V, (V–) < VCM < (V+) Full range 56
IBInput bias current 25°C ±0.5 ±10 pA
IOS Input offset current 25°C ±0.5 ±10 pA
Differential 1013|| 3
ZIInput impedance 25°C Ω|| pF
Common-mode 1013|| 3
Input voltage noise VCM < (V+) – 1.7 V, f = 0.1 Hz to 10 Hz 25°C 10 µVPP
VnInput voltage noise density VCM < (V+) – 1.7 V, f = 1 kHz 25°C 35 nV/√Hz
InInput current noise density VCM < (V+) – 1.7 V, f = 1 kHz 25°C 4 fA/√Hz
25°C 94 108
VS= 5 V, RL= 100 kΩ,
0.025 V < VO< 4.975 V Full range 90
AOL Open-loop voltage gain dB
25°C 90 98
VS= 5V, RL= 5 kΩ,
0.125 V < VO< 4.875 V Full range 88
25°C 18 25
RL = 100 kΩ, AOL > 94 dB mV
Full range 25
Voltage output swing from rail 25°C 100 125
RL = 5 kΩ, AOL > 90 dB mV
Full range 125
ISC Output short-circuit current 25°C ±10 mA
CLOAD Capacitive load drive See the Typical Characteristics section 25°C
GBW Gain-bandwidth product CL= 100 pF 25°C 1 MHz
SR Slew rate CL= 100 pF, G = +1 25°C 0.5 V/µs
0.1% 5
Settling
tsCL= 100 pF, VS= 5.5 V, 2V- step, G = +1 25°C µs
time 0.01% 7
Overload recovery time VIN × Gain > VS25°C 1.6 µs
CL= 100 pF, VS= 5.5 V, VO= 3 VPP,
THD+N Total harmonic distortion plus noise 25°C 0.0023%
G = +1, f = 1 kHz
25°C 45 65
IQQuiescent current Per amplifier µA
Full range 75
(1) Full range TA= –40°C to +125°C.
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2
Quiescent Current ( µA)
13
10
7
4
1
Short-Circuit Current (mA)
Supply Voltage (V)
2.5 3 3.5 4 4.5 5 5.5
65
55
45
35
25
IQ
ISC
0
Output Voltage Swing (V)
Output Current (mA)
5 10
–40°C
–40°C
+125°C
+125°C
+25°C
+25°C
15 20
2.5
2
1.5
1
0.5
0
–0.5
–1
–1.5
–2
–2.5
Sourcing Current
Sinking Current
Output Voltage (Vp-p)
Frequency (Hz)
1k 10k 1M100k 10M
6
5
4
3
2
1
0
V
S
= 5.5 V
V
S
= 5 V
V
S
= 2.5 V
10
Channel Separation (dB)
Frequency (Hz)
100 1k 10k 100k 1M 10M
140
120
100
80
60
0.1
Open-Loop Gain (dB)
0
–45
–90
–135
–180
Phase (°)
Frequency (Hz)
1 10010 10k1k 100k 1M 10M
140
120
100
80
60
40
20
0
–20
Gain
Phase
10
PSRR, CMRR (dB)
Frequency (Hz)
100 1k 10k 100k 1M 10M
100
80
60
40
20
0
PSRR
CMRR
OPA348-Q1
,
OPA2348-Q1
,
OPA4348-Q1
SBOS465C –JANUARY 2009–REVISED JANUARY 2016
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6.7 Typical Characteristics
At TA= 25°C, RL= 100 kΩconnected to VS/ 2, VOUT = VS/ 2 (unless otherwise noted).
Figure 1. Open-Loop Gain and Phase vs Frequency Figure 2. PSRR and CMRR vs Frequency
Figure 4. Channel Separation vs Frequency
Figure 3. Maximum Output Voltage vs Frequency
VS = ±2.5V
Figure 5. Quiescent and Short-Circuit Current Figure 6. Output Voltage Swing vs Output Current
vs Supply Voltage
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–6 –5 –4 –3 –2 –1 0 1 2 3 4 5 6
Offset Voltage (mV)
20
18
16
14
12
10
8
6
4
2
0
Percent of Amplifiers (%)
Percentage of Amplifiers (%)
Offset Voltage Drift (µV/°C)
1 2 3 4 5 6 7 8 9 10 11 12
25
20
15
10
5
0
Quiescent Current ( µA)
Temperature (°C)
ISC
IQ
75
65
55
45
35
25
15
Short-Circuit Current (mA)
16
14
12
10
8
6
4
–75 –50 –25 0 25 50 75 100 125 150
Input Bias Current (pA)
10k
1k
100
10
1
0.1
–75
Temperature (°C)
–50 –25 0 25 50 75 100 125 150
–75
Common-Mode Rejection (dB)
Temperature (°C)
–50 –25 0 25 50 75 100 125 150
100
90
80
70
60
50
V– < VCM < (V+) – 1.7 V
V– < VCM < V+
–75
Open-Loop Gain and
Power Supply Rejection (dB)
Temperature (°C)
–50 –25 0 25 50 75 100 125 150
130
120
110
100
90
80
70
60
A
OL
, R
L
= 100 kΩ
A
OL
, R
L
= 5 kΩ
PSRR
OPA348-Q1
,
OPA2348-Q1
,
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Typical Characteristics (continued)
At TA= 25°C, RL= 100 kΩconnected to VS/ 2, VOUT = VS/ 2 (unless otherwise noted).
Figure 7. Common-Mode Rejection vs Temperature Figure 8. Open-Loop Gain and PSRR vs Temperature
Figure 9. Quiescent and Short-Circuit Current Figure 10. Input Bias (IB) Current vs Temperature
vs Temperature
Typical production distribution of packaged units. Typical production distribution of packaged units.
Figure 11. Offset Voltage Production Distribution Figure 12. Offset Voltage Drift Magnitude
Production Distribution
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1
Voltage Noise (nV/ Hz)√
Current Noise (fA Hz)√
Frequency (Hz)
10 100 1k 10k 100k
10k
1k
100
10
1k
100
10
1
VN
IN
10
Total Harmonic Distortion + Noise (%)
Frequency (Hz)
100 1k 10k 100k
1.000
0.100
0.010
0.001
20 mV/div
2 µs/div
500 mV/div
10 µs/div
Overshoot (%)
Load Capacitance (pF)
10 100 1k 10k
60
50
40
30
20
10
0
10
Small-Signal Overshoot (%)
Load Capacitance (pF)
100 1k 10k
60
50
40
30
20
10
0
G = +1 V/V, RL= 100 kW
G = –1 V/V, RFB = 5 kW
G = –1 V/V, RFB = 100 kW
OPA348-Q1
,
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,
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Typical Characteristics (continued)
At TA= 25°C, RL= 100 kΩconnected to VS/ 2, VOUT = VS/ 2 (unless otherwise noted).
G = ±5 V/V, RFB = 100 kΩ
Figure 13. Small-Signal Overshoot vs Load Capacitance Figure 14. Percent Overshoot vs Load Capacitance
G = 1 V/V RL= 100 kΩCL= 100 pF G = 1 V/V RL= 100 kΩCL= 100 pF
Figure 15. Small-Signal Step Response Figure 16. Large-Signal Step Response
Figure 18. Total Harmonic Distortion + Noise vs Frequency
Figure 17. Input Current and Voltage Noise Spectral Density
vs Frequency
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OPA348-Q1
VBIAS1
VBIAS2
Class AB
Control Circuitry
V+
V±
(Ground)
VIN+ VIN±
Reference
Current
Vo
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,
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7 Detailed Description
7.1 Overview
The OPAx348-Q1 family of devices is a low-power, rail-to-rail input and output operational amplifier. These
devices operate from 1.8 V to 5.5 V, are unity-gain stable, and are suitable for a wide range of general-purpose
applications. The class AB output stage is capable of driving ≤10-kΩloads connected to any point between V+
and ground. The input common-mode voltage range includes both rails and allows the OPAx348-Q1 family of
devices to be used in virtually any single-supply application. Rail-to-rail input and output swing significantly
increases dynamic range, especially in low-supply applications, and makes them ideal for driving sampling
analog-to-digital converters (ADCs).
7.2 Functional Block Diagram
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5kW
1/2
OPA2348
10mA max
+5V
V
IN
V
OUT
I
OVERLOAD
5V
1V/div
0V
G = +1V/V, V S= +5V
10µs/div
VIN
VOUT
OPA348-Q1
,
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,
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7.3 Feature Description
7.3.1 Operating Voltage
The OPAx348-Q1 op amp is fully specified and ensured for operation from 1.8 V to 5.5 V. In addition, many
specifications apply from –40°C to +125°C. Parameters that vary significantly with operating voltages or
temperature are shown in the Typical Characteristics graphs. Power-supply pins should be bypassed with
0.01-μF ceramic capacitors.
7.3.2 Rail-to-Rail Input
The input common-mode voltage range of the OPAx348-Q1 family of devices extends 200 mV beyond the supply
rails. This performance is achieved with a complementary input stage: an N-channel input differential pair in
parallel with a P-channel differential pair. The N-channel pair is active for input voltages close to the positive rail,
typically (V+) – 1.3 V to 200 mV above the positive supply. The P-channel pair is on for inputs from 200 mV
below the negative supply to approximately (V+) – 1.3 V. A small transition region exists, typically (V+) – 1.4 V to
(V+) – 1.2 V, in which both pairs are on. This 200-mV transition region can vary up to 300 mV with process
variation. Thus, the transition region (both stages on) can range from (V+) – 1.7 V to (V+) – 1.5 V on the low end,
up to (V+) – 1.1 V to (V+) – 0.9 V on the high end. Within this transition region, PSRR, CMRR, offset voltage,
offset drift, and THD may be degraded compared to device operation outside this region.
7.3.3 Rail-to-Rail Input
The input common-mode range extends from (V–) – 0.2 V to (V+) + 0.2 V. For normal operation, the inputs
should be limited to this range. The absolute maximum input voltage is 500 mV beyond the supplies. Inputs
greater than the input common-mode range but less than the maximum input voltage, while not valid, do not
cause any damage to the op amp. Unlike some other op amps, if the input current is limited, the inputs may go
beyond the power supplies without phase inversion, as shown in Figure 19.
Figure 19. No Phase Inversion with Inputs Greater Than Power-Supply Voltage
Normally, input currents are 0.5 pA. However, large inputs (greater than 500 mV beyond the supply rails) can
cause excessive current to flow in or out of the input pins. Therefore, limiting the input current to less than 10 mA
is important as well as keeping the input voltage below the maximum rating. This limiting is easily accomplished
with an input voltage resistor, as shown in Figure 20.
Figure 20. Input Current Protection for Voltages Exceeding the Supply Voltage
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–0.5
Offset Voltage (mV)
Common-Mode Voltage (V)
OFFSET VOLTAGE
vs FULL COMMON-MODE VOLTAGE RANGE
0
V–
0.5 1.51 2.52 3.53 4.5 54 5.5
2
1.5
1
0.5
0
–0.5
–1
–1.5
–2
V+
5 kW
10-mA max
V+
VIN
VOUT
IOVERLOAD
Device
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,
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,
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Feature Description (continued)
7.3.4 Input and ESD Protection
The OPAx348-Q1 family of devices incorporates internal electrostatic discharge (ESD) protection circuits on all
pins. In the case of input and output pins, this protection primarily consists of current-steering diodes connected
between the input and power-supply pins. These ESD protection diodes also provide in-circuit, input overdrive
protection, as long as the current is limited to 10 mA as stated in the Absolute Maximum Ratings table. Figure 21
shows how a series input resistor can be added to the driven input to limit the input current. The added resistor
contributes thermal noise at the amplifier input and the value should be kept to a minimum in noise-sensitive
applications.
Figure 21. Input Current Protection
7.3.5 Common-Mode Rejection Ratio (CMRR)
CMRR for the OPAx348-Q1 family of devices is specified in several ways so the best match for a given
application may be used; see the Electrical Characteristics table. First, the CMRR of the device in the common-
mode range below the transition region [VCM < (V+) – 1.3 V] is given. This specification is the best indicator of
the capability of the device when the application requires use of one of the differential input pairs. Second, the
CMRR over the entire common-mode range is specified at (VCM = –0.2 V to 5.7 V). This last value includes the
variations seen through the transition region (see Figure 22).
7.3.6 Common-Mode Voltage Range
The input common-mode voltage range of the OPAx348-Q1 device extends 200 mV beyond the supply rails.
This extended range is achieved with a complementary input stage—an N-channel input differential pair in
parallel with a P-channel differential pair. The N-channel pair is active for input voltages close to the positive rail,
typically (V+) – 1.2 V to 300 mV above the positive supply, while the P-channel pair is on for inputs from 300 mV
below the negative supply to approximately (V+) – 1.4 V. A small transition region exists, typically (V+) – 1.4 V to
(V+) – 1.2 V, in which both pairs are on. This 200-mV transition region, shown in Figure 22, can vary ±300 mV
with process variation. Thus, the transition region (both stages on) can range from (V+) – 1.7 V to (V+) – 1.5 V
on the low end, up to (V+) – 1.1 V to (V+) – 0.9 V on the high end. Within the 200-mV transition region, PSRR,
CMRR, offset voltage, offset drift, and THD may be degraded compared to operation outside this region.
Figure 22. Behavior of Typical Transition Region at Room Temperature
Copyright © 2009–2016, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: OPA348-Q1 OPA2348-Q1 OPA4348-Q1
5V
1V/div
0V
G = +1V/V, V
S
= +5V
20µs/div
Output (Inverted on Scope)
OPA348-Q1
,
OPA2348-Q1
,
OPA4348-Q1
SBOS465C –JANUARY 2009–REVISED JANUARY 2016
www.ti.com
Feature Description (continued)
7.3.7 EMI Susceptibility and Input Filtering
Op amps vary with regard to the susceptibility of the device to electromagnetic interference (EMI). If conducted
EMI enters the op amp, the dc offset observed at the amplifier output may shift from the nominal value while EMI
is present. This shift is a result of signal rectification associated with the internal semiconductor junctions. While
all op amp pin functions can be affected by EMI, the signal input pins are likely to be the most susceptible. The
OPAx348-Q1 family of devices incorporates an internal input, low-pass filter that reduces the amplifier response
to EMI. Both common-mode and differential mode filtering are provided by this filter. The filter is designed for a
cutoff frequency of approximately 80 MHz (–3 dB), with a roll-off of 20 dB per decade.
Texas Instruments has developed the ability to accurately measure and quantify the immunity of an operational
amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz. The EMI rejection ratio (EMIRR)
metric allows op amps to be directly compared by the EMI immunity. Detailed information can also be found in
the application report, EMI Rejection Ratio of Operational Amplifiers (SBOA128), available for download from
www.ti.com.
7.3.8 Rail-to-Rail Output
Designed as a micro-power, low-noise operational amplifier, the OPAx348-Q1 family of devices delivers a robust
output drive capability. A class AB output stage with common-source transistors is used to achieve full rail-to-rail
output swing capability. For resistive loads up to 10 kΩ, the output swings typically to within 5 mV of either supply
rail regardless of the power-supply voltage applied. Different load conditions change the ability of the amplifier to
swing close to the rails; refer to the graph, Output Voltage Swing vs Output Current.
A class AB output stage with common-source transistors is used to achieve rail-to-rail output. This output stage is
capable of driving 5-kΩloads connected to any potential between V+ and ground. For light resistive loads
(>100 kΩ), the output voltage can typically swing to within 18 mV from supply rail. With moderate resistive loads
(10 kΩto 50 kΩ), the output voltage can typically swing to within 100 mV of the supply rails while maintaining
high open-loop gain (see Figure 6 in the Typical Characteristics section).
Figure 23. Rail-to-Rail I/O
14 Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated
Product Folder Links: OPA348-Q1 OPA2348-Q1 OPA4348-Q1
RI
1/2
OPA2348
VIN
VOUT
RF
CFB
CIN
CL
10 toW
20W
1/2
OPA2348
V+
V
IN
V
OUT
R
S
R
L
C
L
OPA348-Q1
,
OPA2348-Q1
,
OPA4348-Q1
www.ti.com
SBOS465C –JANUARY 2009–REVISED JANUARY 2016
Feature Description (continued)
7.3.9 Capacitive Load and Stability
The OPAx348-Q1 family of devices in a unity-gain configuration can directly drive up to 250-pF pure capacitive
load. Increasing the gain enhances the ability of the amplifier to drive greater capacitive loads (see Figure 13 in
the Typical Characteristics section). In unity-gain configurations, capacitive load drive can be improved by
inserting a small (10-Ωto 20-Ω) resistor, RS, in series with the output, as shown in Figure 24. This resistor
significantly reduces ringing while maintaining dc performance for purely capacitive loads. However, if a resistive
load exists in parallel with the capacitive load, a voltage divider is created, introducing a direct current (dc) error
at the output and slightly reducing the output swing. The error introduced is proportional to the ratio RS/RLand is
generally negligible.
Figure 24. Series Resistor in Unity-Gain Buffer Configuration Improves Capacitive Load Drive
In unity-gain inverter configuration, the phase margin can be reduced by the reaction between the capacitance at
the op amp input and the gain setting resistors, thus degrading capacitive load drive. The best performance is
achieved by using small-valued resistors. For example, when driving a 500-pF load, reducing the resistor values
from 100 kΩto 5 kΩdecreases overshoot from 55% to 13% (see Figure 13 in the Typical Characteristics
section). However, when large-valued resistors cannot be avoided, a small (4-pF to 6-pF) capacitor, CFB, can be
inserted in the feedback loop, as shown in Figure 25. This small capacitor significantly reduces overshoot by
compensating the effect of capacitance, CIN, which includes the input capacitance of the amplifier and printed
circuit board (PCB) parasitic capacitance.
Figure 25. Improving Capacitive Load Drive
7.4 Device Functional Modes
The OPAx348-Q1 family of devices is powered on when the supply is connected. The device can be operated as
a single-supply operational amplifier or a dual-supply amplifier, depending on the application.
Copyright © 2009–2016, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: OPA348-Q1 OPA2348-Q1 OPA4348-Q1
ADS7822
12-Bit A/D
DCLOCK
DOUT
CS/SHDN
1/2
OPA2348-Q1
5 V
VIN
V+
2
+IN
3
–IN
VREF
8
4GND
Serial
Interface
1
0.1 µF 0.1 µF
7
6
5
VIN = 0 V to 5 V for
0-V to 5-V output.
RC network filters high-frequency noise.
500 Ω
3300 pF
OPA348-Q1
,
OPA2348-Q1
,
OPA4348-Q1
SBOS465C –JANUARY 2009–REVISED JANUARY 2016
www.ti.com
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The OPAx348-Q1 operational amplifiers (op amps) are unity-gain stable and suitable for a wide range of general-
purpose applications.
The OPAx348-Q1 device features wide bandwidth and unity-gain stability with rail-to-rail input and output for
increased dynamic range. Figure 23 shows the input and output waveforms for the OPAx348-Q1 device in unity-
gain configuration. Operation is from a single 5-V supply with a 100-kΩload connected to VS/ 2. The input is a
5-VPP sinusoid. Output voltage is approximately 4.98 VPP.
The power-supply pins should be bypassed with 0.01-µF ceramic capacitors.
8.1.1 Driving Analog-to-Digital Converters (ADCs)
The OPAx348-Q1 op amps are optimized for driving medium-speed sampling ADCs. The OPAx348-Q1 op amps
buffer the ADC input capacitance and resulting charge injection while providing signal gain.
Figure 26 shows the OPA2348 in a basic noninverting configuration driving the ADS7822 device. The ADS7822
device is a 12-bit, micropower sampling converter in the MSOP-8 package. When used with the low-power
miniature packages of the OPAx348-Q1 family of devices, the combination is ideal for space-limited, low-power
applications. In this configuration, an RC network at the ADC input can be used to provide for anti-aliasing
filtering and charge injection current.
A/D input = 0 V to VREF
Figure 26. Noninverting Configuration Driving ADS7822
The OPAx348-Q1 family of devices can also be used in noninverting configuration to drive the ADS7822 device
in limited low-power applications. In this configuration, an RC network at the ADC input can be used to provide
for anti-aliasing filtering and charge injection current. See Figure 26 for the OPAx348-Q1 driving an ADS7822
device in a speech bandpass filtered data acquisition system. This small, low-cost solution provides the
necessary amplification and signal conditioning to interface directly with an electret microphone. This circuit
operates with VS= 2.7 V to 5 V with less than 250-µA typical quiescent current.
16 Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated
Product Folder Links: OPA348-Q1 OPA2348-Q1 OPA4348-Q1
2.7 V
2.7 V
R3
R4
R1
R2
VOUT+
VOUT±
V
+
VDIFF
VREF
2.5 V
+
VIN
+
±+
Device
+
±+
Device
C
3
33 pF
V+
GND
3
18
4
5
6
7
–IN
+IN
2
C
2
DCLOCK
Serial
Interface
1000 pF
R
1
1.5 kΩ
R
4
20 kΩ
R
5
20 kΩ
R
6
100 kΩ
R
8
150 kΩ
R
9
510 kΩ
R
7
51 kΩ
D
OUT
V
REF
V+ = 2.7 V to 5 V
CS/SHDN
C1
1000 pF
Electret
Microphone
(1)
G = 100
Passband 300 Hz to 3 kHz
R
3
1 MΩ
R
2
1 MΩ
ADS7822
12-Bit A/D
1/2
OPA2348-Q1
1/2
OPA2348-Q1
OPA348-Q1
,
OPA2348-Q1
,
OPA4348-Q1
www.ti.com
SBOS465C –JANUARY 2009–REVISED JANUARY 2016
Application Information (continued)
(1) Electret microphone powered by R1.
Figure 27. Speech Bandpass Filtered Data Acquisition System
8.2 Typical Application
Some applications require differential signals. Figure 28 shows a simple circuit to convert a single-ended input of
0.1 V to 2.4 V into a differential output of ±2.3 V on a single 2.7-V supply. The output range is intentionally limited
to maximize linearity. The circuit is composed of two amplifiers. One amplifier functions as a buffer and creates a
voltage, VOUT+. The second amplifier inverts the input and adds a reference voltage to generate VOUT–. Both
VOUT+ and VOUT– range from 0.1 V to 2.4 V. The difference, VDIFF, is the difference between VOUT+ and VOUT–.
This configuration makes the differential output voltage range to be 2.3 V.
Figure 28. Schematic for a Single-Ended Input to Differential Output Conversion
Copyright © 2009–2016, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: OPA348-Q1 OPA2348-Q1 OPA4348-Q1
287 287±
CM REF
V V 1
V V
2 2
§ ·
¨ ¸
© ¹
DIFF IN REF
V 2 V V u
287± 5() ,1
V V V
OUT IN
V V
2 4 2
',)) 287 287± ,1 5()
1 3 4 1
R R R
V V V V 1 V 1
R R R R
§ ·
§ · § ·
u u u
¨ ¸
¨ ¸ ¨ ¸
© ¹ © ¹
© ¹
4 2 2
287± 5() ,1
3 4 1 1
R R R
V V 1 V
R R R R
§ · § ·
u u u
¨ ¸ ¨ ¸
© ¹
© ¹
OUT IN
V V
OPA348-Q1
,
OPA2348-Q1
,
OPA4348-Q1
SBOS465C –JANUARY 2009–REVISED JANUARY 2016
www.ti.com
Typical Application (continued)
8.2.1 Design Requirements
The design requirements are as follows:
• Supply voltage: 2.7 V
• Reference voltage: 2.5 V
• Input: 0.1 V to 2.4 V
• Output differential: ±2.3 V
• Output common-mode voltage: 1.25 V
• Small-signal bandwidth: 1 MHz
8.2.2 Detailed Design Procedure
The circuit in Figure 28 takes a single-ended input signal, VIN, and generates two output signals, VOUT+ and
VOUT– using two amplifiers and a reference voltage, VREF. VOUT+ is the output of the first amplifier and is a
buffered version of the input signal, VIN (as shown in Equation 1). VOUT– is the output of the second amplifier
which uses VREF to add an offset voltage to VIN and feedback to add inverting gain. The transfer function for
VOUT– is given in Equation 2.
(1)
(2)
The differential output signal, VDIFF, is the difference between the two single-ended output signals, VOUT+ and
VOUT–.Equation 3 shows the transfer function for VDIFF. By applying the conditions that R1= R2and R3= R4, the
transfer function is simplified into Equation 6. Using this configuration, the maximum input signal is equal to the
reference voltage and the maximum output of each amplifier is equal to VREF. The differential output range is 2 ×
VREF. Furthermore, the common-mode voltage (VCM) is one half of VREF (see Equation 7).
(3)
(4)
(5)
(6)
(7)
8.2.2.1 Amplifier Selection
Linearity over the input range is key for good dc accuracy. The common-mode input range and output swing
limitations determine the linearity. In general, an amplifier with rail-to-rail input and output swing is required.
Bandwidth is a key concern for this design, so the OPAx348-Q1 family of devices is selected because its
bandwidth is greater than the target of 1 MHz. The bandwidth and power ratio makes this device power-efficient,
and the low offset and drift ensure good accuracy for moderate precision applications.
8.2.2.2 Passive Component Selection
Because the transfer function of VOUT– relies heavily upon resistors (R1, R2, R3, and R4), use resistors with low
tolerances to maximize performance and minimize error. This design uses resistors with resistance values of
49.9 kΩand tolerances of 0.1%. However, if the noise of the system is a key parameter, smaller resistance
values (6 kΩor lower) can be selected to keep the overall system noise low. This technique ensures that the
noise from the resistors is lower than the amplifier noise.
18 Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated
Product Folder Links: OPA348-Q1 OPA2348-Q1 OPA4348-Q1
-2.50
-2.00
-1.50
-1.00
-0.50
0.00
0.50
1.00
1.50
2.00
2.50
0.00 0.50 1.00 1.50 2.00 2.50
Vdiff (V)
Input voltage (V)
C027
0.00
0.50
1.00
1.50
2.00
2.50
0.00 0.50 1.00 1.50 2.00 2.50
Vout+ (V)
Input voltage (V)
C027
0.00
0.50
1.00
1.50
2.00
2.50
0.00 0.50 1.00 1.50 2.00 2.50
Vout- (V)
Input voltage (V)
C027
OPA348-Q1
,
OPA2348-Q1
,
OPA4348-Q1
www.ti.com
SBOS465C –JANUARY 2009–REVISED JANUARY 2016
Typical Application (continued)
8.2.3 Application Curves
Figure 29. VOUT+ vs Input Voltage Figure 30. VOUT– vs Input Voltage
Figure 31. VDIFF vs Input Voltage
9 Power Supply Recommendations
The OPAx348-Q1 family of devices is specified for operation from 1.8 V to 5.5 V (±0.9 V to ±2.75 V); many
specifications apply from –40°C to 125°C. The Typical Characteristics presents parameters that can exhibit
significant variance with regard to operating voltage or temperature.
CAUTION
Supply voltages larger than 7 V can permanently damage the device (see the Absolute
Maximum Ratings).
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-
impedance power supplies. For more detailed information on bypass capacitor placement, refer to the Layout
Guidelines section.
Copyright © 2009–2016, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: OPA348-Q1 OPA2348-Q1 OPA4348-Q1
N/C
±IN
+IN
V±
V+
OUTPUT
N/C
N/C
VS+
GND
VS±
GND Ground (GND) plane on another layer
VOUT
VIN
GND
Run the input traces
as far away from
the supply lines
as possible
Use low-ESR, ceramic
bypass capacitor
RF
RG
Place components
close to device and to
each other to reduce
parasitic errors
+
VIN VOUT
RG
RF
(Schematic Representation)
Use low-ESR,
ceramic bypass
capacitor
OPA348-Q1
,
OPA2348-Q1
,
OPA4348-Q1
SBOS465C –JANUARY 2009–REVISED JANUARY 2016
www.ti.com
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the
operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low-
impedance power sources local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
• Separate grounding for analog and digital portions of the circuitry is one of the simplest and most
effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to
ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to
physically separate digital and analog grounds, paying attention to the flow of the ground current. For
more detailed information, refer to Circuit Board Layout Techniques,SLOA089.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicularly is much
better than crossing in parallel with the noisy trace.
• Place the external components as close to the device as possible. Keep RF and RG close to the inverting
input to minimize parasitic capacitance, as shown in Figure 32.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly
reduce leakage currents from nearby traces that are at different potentials.
10.2 Layout Example
Figure 32. Operational Amplifier Board Layout for Noninverting Configuration
20 Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated
Product Folder Links: OPA348-Q1 OPA2348-Q1 OPA4348-Q1
OPA348-Q1
,
OPA2348-Q1
,
OPA4348-Q1
www.ti.com
SBOS465C –JANUARY 2009–REVISED JANUARY 2016
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• ADS7822: 12-Bit, 200kHz, microPower Sampling Analog-to-Digital Converter, SBAS062
• Application report: Circuit Board Layout Techniques,SLOA089
• Application report: EMI Rejection Ratio of Operational Amplifiers,SBOA128
11.2 Related Links
Table 1 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to sample or buy.
Table 1. Related Links
TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY DOCUMENTS SOFTWARE COMMUNITY
OPA348-Q1 Click here Click here Click here Click here Click here
OPA2348-Q1 Click here Click here Click here Click here Click here
OPA4348-Q1 Click here Click here Click here Click here Click here
11.3 Community Resource
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2009–2016, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Links: OPA348-Q1 OPA2348-Q1 OPA4348-Q1
PACKAGE OPTION ADDENDUM
www.ti.com 16-Dec-2015
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
OPA2348AQDRQ1 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 OPA
2348Q
OPA348AQDBVRQ1 ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 A48
OPA348AQDRQ1 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 348Q1
OPA4348AQPWRQ1 ACTIVE TSSOP PW 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 OP4348Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
PACKAGE OPTION ADDENDUM
www.ti.com 16-Dec-2015
Addendum-Page 2
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF OPA2348-Q1, OPA348-Q1, OPA4348-Q1 :
•Catalog: OPA2348, OPA348, OPA4348
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
OPA2348AQDRQ1 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
OPA348AQDBVRQ1 SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
OPA348AQDRQ1 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
OPA4348AQPWRQ1 TSSOP PW 14 2500 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 17-Dec-2015
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
OPA2348AQDRQ1 SOIC D 8 2500 367.0 367.0 35.0
OPA348AQDBVRQ1 SOT-23 DBV 5 3000 180.0 180.0 18.0
OPA348AQDRQ1 SOIC D 8 2500 367.0 367.0 35.0
OPA4348AQPWRQ1 TSSOP PW 14 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 17-Dec-2015
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
TYP
0.22
0.08
0.25
3.0
2.6
2X 0.95
1.9
1.45 MAX
TYP
0.15
0.00
5X 0.5
0.3
TYP
0.6
0.3
TYP
8
0
1.9
A
3.05
2.75
B
1.75
1.45
(1.1)
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/C 04/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
0.2 C A B
1
34
5
2
INDEX AREA
PIN 1
GAGE PLANE
SEATING PLANE
0.1 C
SCALE 4.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAX
ARROUND 0.07 MIN
ARROUND
5X (1.1)
5X (0.6)
(2.6)
(1.9)
2X (0.95)
(R0.05) TYP
4214839/C 04/2017
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
PKG
1
34
5
2
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
(2.6)
(1.9)
2X(0.95)
5X (1.1)
5X (0.6)
(R0.05) TYP
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/C 04/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
SYMM
PKG
1
34
5
2
www.ti.com
PACKAGE OUTLINE
C
TYP
0.22
0.08
0.25
3.0
2.6
2X 0.95
1.9
1.45 MAX
TYP
0.15
0.00
5X 0.5
0.3
TYP
0.6
0.3
TYP
8
0
1.9
A
3.05
2.75
B
1.75
1.45
(1.1)
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/C 04/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
0.2 C A B
1
34
5
2
INDEX AREA
PIN 1
GAGE PLANE
SEATING PLANE
0.1 C
SCALE 4.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAX
ARROUND 0.07 MIN
ARROUND
5X (1.1)
5X (0.6)
(2.6)
(1.9)
2X (0.95)
(R0.05) TYP
4214839/C 04/2017
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
PKG
1
34
5
2
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
(2.6)
(1.9)
2X(0.95)
5X (1.1)
5X (0.6)
(R0.05) TYP
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/C 04/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
SYMM
PKG
1
34
5
2
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