1
®HI5628
8-Bit, 125/60MSPS, Dual High Speed
CMOS D/A Converter
The HI5628 is an 8-bit, dual 125MSPS D/A converter which
is implemented in an advanced CMOS process. Operating
from a single +5V to +3V supply, the converter provides
20.48mA of full scale output current and includes an input
data register. Low glitch energy and excellent frequency
domain performance are achieved using a segmented
architecture. The single DAC version is the HI5660 while
10-bit versions exist in the HI5760 and HI5728.
Features
• Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . 125MSPS
• Low Power . . . . . . . . . . . . . 330mW at 5V, 170mW at 3V
• Integral Linearity Error . . . . . . . . . . . . . . . . . . . ±0.25 LSB
• Differential Linearity . . . . . . . . . . . . . . . . . . . . . ±0.25 LSB
• Channel Isolation (Typ) . . . . . . . . . . . . . . . . . . . . . . 80dB
• SFDR to Nyquist at 10MHz Output . . . . . . . . . . . . 60dBc
• Internal 1.2V Bandgap Voltage Reference
• Single Power Supply from +5V to +3V
• CMOS Compatible Inputs
• Excellent Spurious Free Dynamic Range
Applications
• Direct Digital Frequency Synthesis
• Wireless Communications
• Signal Reconstruction
• Arbitrary Waveform Generators
• Test Equipment
• High Resolution Imaging Systems
Pinout
HI5628 (LQFP)
TOP VIEW
Ordering Information
PART
NUMBER
TEMP.
RANGE
(oC) PACKAGE PKG. NO.
MAX
CLOCK
SPEED
HI5628IN -40 to 85 48 Ld LQFP Q48.7x7A 125MHz
HI5628/6IN -40 to 85 48 Ld LQFP Q48.7x7A 60MHz
HI5628EVAL1 25 Evaluation Platform 125MHz
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
2423222120191817
9
10
11
1213 14 15 16
33
34
35
36
373839404142434445464748 QD4
QD3
QD2
QD1
QD0 (LSB)
DGND
DGND
DV
DD
DGND
NC
AV
DD
AGND
ID4
ID3
ID2
ID1
ID0 (LSB )
SLEEP
DV
DD
DGND
NC
AV
DD
DGND
DGND
ID5
ID6
ID7 (MSB)
DV
DD
DGND
QCLK
DGND
DV
DD
QD7 (MSB)
QD6
QD5
ICLK
AGND
ICOMP1
REFLO
IOUTA
IOUTB
AGND
AGND
QOUTB
QOUTA
FSADJ
REFIO
QCOMP1
Data Sheet September 2000 FN4520.5
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
2
Typical Applications Circuit
NOTE: Recommended separate analog and digital ground planes, connected at a single point near the device. See AN9827.
IOUTBIOUTA
50Ω
+5V TO +3V (SUPPLY)
0.1µF
50Ω
10µF
50Ω
0.1µF
1.91kΩ
FERRITE
10µH+
BEAD
RSET
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
2423222120191817
9
10
11
1213 14 15 16
33
34
35
36
373839404142434445464748
AVDD
ID5
ID4
ID3
ID6
ID7 (MSB)
QD7 (MSB)
ID2
ID1
ID0 (LSB)
QD6
QD5
QD4
QD3
QD2
QD1
QD0 (LSB)
ICLK/QCLK
DVDD
0.1µF
DVDD
SLEEP
DVDD
0.1µF
DVDD
DGND
NC (GROUND)
AVDD
AGND
ICOMP1
0.1µF
0.1µF
AGND
QOUTAQOUTB
50Ω
50Ω
0.1µF
REFIO
QCOMP1
0.1µFAVDD
0.1µF
AVDD
AGND
AVDD
NC (GND) 0.1µF
DVDD
DGND
DVDD
DGND
DGND
DGND
DGND
ANALOG GROUND
PLANE
DIGITAL GROUND
PLANE
PLANE
AVDD
NOTE: ICOMP1 AND QCOMP1 PINS (24, 14)
MUST BE TIED TOGETHER EXTERNALLY
DVDD
10µF0.1µF
FERRITE
10µH
BEAD
+5V TO +3V
POWER SUPPLY
(POWER PLANE) (POWER PLANE)
HI5628
3
Functional Block Diagram
UPPER
VOLTAGE
REFERENCE
(LSB) ID0
ID1
ID2
ID3
ID4
ID5
ID6
ICLK
(MSB) ID7
5-BIT
DECODER
REFIO
LATCH
AVDD AGND DVDD DGND
LATCH
CASCODE
CURRENT
SOURCE
SWITCH
MATRIX
BIAS
GENERATION
INT/EXT
FSADJ
REFERENCE
INT/EXT
SELECT
REFLO
31
34 34
31 MSB
SEGMENTS
3 LSBs
+
ICOMP1
SLEEP
IOUTA IOUTB
UPPER
(LSB) QD0
QD1
QD2
QD3
QD4
QD5
QD6
QCLK
(MSB) QD7
5-BIT
DECODER
LATCH
LATCH
CASCODE
CURRENT
SOURCE
SWITCH
MATRIX
31
34 34
31 MSB
SEGMENTS
3 LSBs
+
QCOMP1
QOUTA QOUTB
HI5628
4
Absolute Maximum Ratings Thermal Information
Digital Supply Voltage DVDD to DCOM . . . . . . . . . . . . . . . . . . +5.5V
Analog Supply Voltage AVDD to ACOM. . . . . . . . . . . . . . . . . . +5.5V
Grounds, ACOM TO DCOM . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
Digital Input Voltages (D7-D0, CLK, SLEEP). . . . . . . . DVDD + 0.3V
Internal Reference Output Current. . . . . . . . . . . . . . . . . . . . . ±50µA
Reference Input Voltage Range. . . . . . . . . . . . . . . . . . AVDD + 0.3V
Analog Output Current (IOUT) . . . . . . . . . . . . . . . . . . . . . . . . . 24mA
Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
Thermal Resistance (Typical, Note 1) θJA(oC/W)
LQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other co nditions above those indicat ed in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications AVDD = +5V , DVDD = +5V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25oC for All Typical Values. Data given
is per channel except for ‘Power Supply Characteristics.’
PARAMETER TEST CONDITIONS
HI5628IN
TA = -40oC TO 85oC
UNITSMIN TYP MAX
SYSTEM PERFORMANCE (Per Channel)
Resolution 8 - - Bits
Integral Linearity Error, INL “Best Fit” Straight Line (Note 7) -0.5 ±0.25 +0.5 LSB
Differential Linearity Error, DNL (Note 7) -0.5 ±0.25 +0.5 LSB
Offset Error, IOS (Note 7) -0.025 -+0.025 % FSR
Offset Drift Coefficient (Note 7) -0.1 -ppm
FSR/oC
Full Scale Gain Error, FSE With External Reference (Notes 2, 7) -10 ±2+10 % FSR
With Internal Reference (Notes 2, 7) -10 ±1+10 % FSR
Full Scale Gain Drifta With External Reference (Note 7) -±50 -ppm
FSR/oC
With Internal Reference (Note 7) -±100 -ppm
FSR/oC
Gain Matching Between Channels -0.5 0.1 0.5 dB
I/Q Channel Isolation FOUT = 10MHz -80 -dB
Output Voltage Compliance Range (Note 3) -0.3 -1.25 V
Full Scale Output Current, IFS 2 - 20 mA
DYNAMIC CHARACTERISTICS (Per Channel)
Clock Rate, fCLK (Note 3, 9) 125 - - MHz
Output Settling Time, (tSETT) 0.8% (±1 LSB, equivalent to 7 Bits) (Note 7) - 5 - ns
0.4% (±1/2 LSB, equivalent to 8 Bits) (Note 7) -15 -ns
Singlet Glitch Area (Peak Glitch) RL = 25Ω (Note 7) - 5 - pV•s
Output Rise Time Full Scale Step -1.5 -ns
Output Fall Time Full Scale Step -1.5 -ns
Output Capacitance -10 -pF
Output Noise IOUTFS = 20mA -50 -pA/ √Hz
IOUTFS = 2mA -30 -pA/ √Hz
HI5628
5
AC CHARACTERISTICS - HI5628IN - 125MHz (Per Channel)
Spurious Free Dynamic Range,
SFDR Within a Window
fCLK = 125MSPS, fOUT = 32.9MHz, 10MHz Span (Notes 4, 7) -70 -dBc
fCLK = 100MSPS, fOUT = 5.04MHz, 4MHz Span (Notes 4, 7) -73 -dBc
Total Harmonic Distortion (THD) to Nyquist fCLK = 100MSPS, fOUT = 2.00MHz (Notes 4, 7) -67 -dBc
Spurious Free Dynamic Range,
SFDR to Nyquist
fCLK = 125MSPS, fOUT = 32.9MHz, 62.5MHz Span (Notes 4, 7) -51 -dBc
fCLK = 125MSPS, fOUT = 10.1MHz, 62.5MHz Span (Notes 4, 7) -61 -dBc
fCLK = 100MSPS, fOUT = 40.4MHz, 50MHz Span (Notes 4, 7) -48 -dBc
fCLK = 100MSPS, fOUT = 20.2MHz, 50MHz Span (Notes 4, 7) -56 -dBc
fCLK = 100MSPS, fOUT = 5.04MHz, 50MHz Span (Notes 4, 7) -68 -dBc
fCLK = 100MSPS, fOUT = 2.51MHz, 50MHz Span (Notes 4, 7) -68 -dBc
AC CHARACTERISTICS - HI5628/6IN - 60MHz (Per Channel)
Spurious Free Dynamic Range,
SFDR Within a Window
fCLK = 60MSPS, fOUT = 10.1MHz, 10MHz Span (Notes 4, 7) -70 -dBc
fCLK = 50MSPS, fOUT = 5.02MHz, 2MHz Span (Notes 4, 7) -73 -dBc
fCLK = 50MSPS, fOUT = 1.00MHz, 2MHz Span (Notes 4, 7) -74 -dBc
Total Harmonic Distortion (THD) to Nyquist fCLK = 50MSPS, fOUT = 2.00MHz (Notes 4, 7) -67 -dBc
fCLK = 50MSPS, fOUT = 1.00MHz (Notes 4, 7) -68 -dBc
Spurious Free Dynamic Range,
SFDR to Nyquist
fCLK = 60MSPS, fOUT = 20.2MHz, 30MHz Span (Notes 4, 7) -54 -dBc
fCLK = 60MSPS, fOUT = 10.1MHz, 30MHz Span (Notes 4, 7) -60 -dBc
fCLK = 50MSPS, fOUT = 20.2MHz, 25MHz Span (Notes 4, 7) -53 -dBc
fCLK = 50MSPS, fOUT = 5.02MHz, 25MHz Span (Notes 4, 7) -67 -dBc
fCLK = 50MSPS, fOUT = 2.51MHz, 25MHz Span (Notes 4, 7) -68 -dBc
fCLK = 50MSPS, fOUT = 1.00MHz, 25MHz Span (Notes 4, 7) -68 -dBc
fCLK = 25MSPS, fOUT = 5.02MHz, 25MHz Span (Notes 4, 7) -71 -dBc
VOLTAGE REFERENCE
Internal Reference Voltage, VFSADJ Voltage at Pin 22 with Internal Reference 1.04 1.16 1.28 V
Internal Reference Voltage Drift -±60 -ppm/oC
Internal Reference Output Current
Sink/Source Capability
-0.1 -µA
Reference Input Impedance - 1 - MΩ
Reference Input Multiplying Bandwidth (Note 7) -1.4 -MHz
DIGITAL INPUTS D7-D0, CLK (Per Channel)
Input Logic High Voltage with
5V Supply, VIH
(Note 3) 3.5 5 - V
Input Logic High Voltage with
3V Supply, VIH
(Note 3) 2.1 3 - V
Input Logic Low Voltage with
5V Supply, VIL
(Note 3) - 0 1.3 V
Input Logic Low Voltage with
3V Supply, VIL
(Note 3) - 0 0.9 V
Input Logic Current, IIH -10 -+10 µA
Input Logic Current, IIL -10 -+10 µA
Digital Input Capacitance, CIN - 5 - pF
TIMING CHARACTERISTICS (Per Channel)
Electrical Specifications AVDD = +5V , DVDD = +5V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25oC for All Typical Values. Data given
is per channel except for ‘Power Supply Characteristics.’ (Continued)
PARAMETER TEST CONDITIONS
HI5628IN
TA = -40oC TO 85oC
UNITSMIN TYP MAX
HI5628
6
Data Setup Time, tSU See Figure 3 (Note 3) 3 - - ns
Data Hold Time, tHLD See Figure 3 (Note 3) 3 - - ns
Propagation Delay Time, tPD See Figure 3 - 1 - ns
CLK Pulse Width, tPW1 , tPW2 See Figure 3 (Note 3) 4 - - ns
POWER SUPPLY CHARACTERISTICS
AVDD Power Supply (Note 8, 9) 2.7 5.0 5.5 V
DVDD Power Supply (Note 8, 9) 2.7 5.0 5.5 V
Analog Supply Current (IAVDD)5V or 3V, IOUTFS = 20mA -46 60 mA
5V or 3V, IOUTFS = 2mA - 8 - mA
Digital Supply Current (IDVDD)5V, IOUTFS = Don’t Care (Note 5) - 6 10 mA
3V, IOUTFS = Don’t Care (Note 5) - 3 - mA
Supply Current (IAVDD) Sleep Mode 5V or 3V, IOUTFS = Don’t Care) -3.2 6mA
Power Dissipation (Both Channels) 5V, IOUTFS = 20mA (Note 6) -330 -mW
5V, IOUTFS = 2mA (Notes 6) -140 -mW
3V, IOUTFS = 20mA (Note 6) -170 -mW
3V, IOUTFS = 2mA (Note 6) -54 -mW
5V, IOUTFS = 20mA (Note 10) -300 -mW
3.3V, IOUTFS = 20mA (Note 10) -150 -mW
3V, IOUTFS = 20mA (Note 10) -135 -mW
Power Supply Rejection Single Supply (Note 7) -0.2 -+0.2 %
FSR/V
NOTES:
2. Gain Error measured as the error in the ratio between the full scale output current and the current through RSET (typically 625µA). Ideally the
ratio should be 32.
3. Parameter guaranteed by design or characterization and not production tested.
4. Spectral measurements made with differential transformer coupled output and no filtering.
5. Measured with the clock at 50MSPS and the output frequency at 1MHz, both channels.
6. Measured with the clock at 100MSPS and the output frequency at 40MHz, both channels.
7. See ‘Definition of Specifications’.
8. For operation below 3V, it is recommended that the output current be reduced to 12mA or less to maintain optimum performance. DVDD and
AVDD do not have to be equal.
9. For operation above 125MHz, it is recommended that the power supply be 3.3V or greater. The part is functional with the clock above 125MSPS
and the power supply below 3.3V, but performance is degraded.
10. Measured with the clock at 60MSPS and the output frequency at 10MHz, both channels.
Electrical Specifications AVDD = +5V , DVDD = +5V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25oC for All Typical Values. Data given
is per channel except for ‘Power Supply Characteristics.’ (Continued)
PARAMETER TEST CONDITIONS
HI5628IN
TA = -40oC TO 85oC
UNITSMIN TYP MAX
HI5628
7
Timing Diagrams
FIGURE 1. OUTPUT SETTLING TIME DIAGRAM FIGURE 2. PEAK GLITCH AREA (SINGLET) MEASUREMENT
METHOD
FIGURE 3. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM
CLK
D7-D0
IOUT
50%
tSETT
1/2 LSB ERROR BAND
tPD
V
t(ps)
HEIGHT (H)
WIDTH (W)
GLITCH AREA = 1/2 (H x W)
CLK
D7-D0
IOUT
50%
tPW1 tPW2
tSU
tHLD
tSU tSU
tPD
tPD tPD
tHLD tHLD
tSETT
tSETT tSETT
HI5628
8
Definition of Specifications
Integral Linearity Error, INL, is the measure of the worst
case point that deviates from a best fit straight line of data
values along the transfer curve.
Differential Linearity Error, DNL, is the measure of the
step size output deviation from code to code. Ideally the step
size should be 1 LSB. A DNL specification of 1 LSB or less
guarantees monotonicity.
Output Settling Time, is the time required for the output
voltage to settle to within a specified error band measured
from the beginning of the output transition. The
measurement was done by switching from code 0 to 64, or
quarter scale. Termination impedance was 25Ω due to the
parallel resistance of the output 50Ω and the oscilloscope’s
50Ω input. This also aids the ability to resolve the specified
error band without overdriving the oscilloscope.
Singlet Glitch Area, is the switching transient appearing on
the output during a code transition. It is measured as the
area under the overshoot portion of the curve and is
expressed as a Volt-Time specification.
Full Scale Gain Error , is the error from an ideal ratio of 32
between the output current and the full scale adjust current
(through RSET).
Full Scale Gain Drift, is measured by setting the data inputs
to all ones and measuring the output voltage through a
known resistance as the temperature is varied from TMIN to
TMAX . It is defined as the maximum deviation from the value
measured at room temperature to the value measured at
either TMIN or TMAX . The units are ppm of FSR (Full Scale
Range) per degree C.
Total Harmonic Distortion, THD, is the ratio of the DAC output
fundamental to the RMS sum of the first five harmonics.
Spurious Free Dynamic Range, SFDR, is the amplitude
difference from the fundamental to the largest harmonically
or non-harmonically related spur within the specified
window.
Output Voltage Compliance Range, is the voltage limit
imposed on the output. The output impedance load should
be chosen such that the voltage developed does not violate
the compliance range.
Offset Error, is measured by setting the data inputs to all
zeros and measuring the output voltage through a known
resistance. Offset error is defined as the maximum deviation
of the output current from a value of 0mA.
Offset Drift, is measured by setting the data inputs to all
zeros and measuring the output voltage through a known
resistance as the temperature is varied from TMIN to TMAX .
It is defined as the maximum deviation from the value
measured at room temperature to the value measured at
either TMIN or TMAX . The units are ppm of FSR (Full Scale
Range) per degree C.
Power Supply Rejection, is measured using a single power
supply. Its nominal +5V is varied ±10% and the change in the
DAC full scale output is noted.
Reference Input Multiplying Bandwidth, is defined as the
3dB bandwidth of the voltage reference input. It is measured
by using a sinusoidal waveform as the external reference
with the digital inputs set to all 1s. The frequency is
increased until the amplitude of the output waveform is
0.707 of its original value.
Internal Reference Voltage Drift, is defined as the
maximum deviation from the value measured at room
temperature to the value measured at either TMIN or TMAX .
The units are ppm per degree C.
Detailed Description
The HI5628 is a dual, 8-bit, current out, CMOS, digital to
analog converter. Its maximum update rate is 125MSPS and
can be powered by either single or dual power supplies in
the recommended range of +3V to +5V. It consumes less
than 330mW of power when using a +5V supply with the
data switching at 100MSPS. The architecture is based on a
segmented current source arrangement that reduces glitch
by reducing the amount of current switching at any one time.
The five MSBs are represented by 31 major current sources
of equivalent current. The three LSBs are comprised of
binary weighted current sources. Consider an input pattern
to the converter which ramps through all the codes from 0 to
255. The three LSB current sources would begin to count up.
When they reached the all high state (decimal value of 7)
and needed to count to the next code, they would all turn off
and the first major current source would turn on. To continue
counting upward, the 3 LSBs would count up another 7
codes, and then the next major current source would turn on
and the three LSBs would all turn off. The process of the
single, equivalent, major current source turning on and the
three LSBs turning off each time the converter reaches
another 7 codes greatly reduces the glitch at any one
switching point. In previous architectures that contained all
binary weighted current sources or a binary weighted
resistor ladder, the converter might have a substantially
larger amount of current turning on and off at certain, worst-
case transition points such as midscale and quarter scale
transitions. By greatly reducing the amount of current
switching at certain ‘major’ transitions, the overall glitch of
the converter is dramatically reduced, improving settling
times and transient problems.
HI5628
9
Digital Inputs and Termination
The HI5628 digital inputs are guaranteed to CMOS levels.
However, TTL compatibility can be achieved by lowering the
supply voltage to 3V due to the digital threshold of the input
buffer being approximately half of the supply voltage. The
internal register is updated on the rising edge of the clock. To
minimize reflections, proper termination should be
implemented. If the lines driving the clock and the digital
inputs are 50Ω lines, then 50Ω termination resistors should be
placed as close to the converter inputs as possible, connected
to the digital ground plane (if separate grounds are used).
Ground Plane(s)
If separate digital and analog ground planes are used, then all
of the digital functions of the device and their corresponding
components should be over the digital ground plane and
terminated to the digital ground plane. The same is true for the
analog components and the analog ground plane. The
converter will function properly with a single ground plane, as
the Evaluation Board is configured in this matter.
Noise Reduction
To minimize power supply noise, 0.1µF capacitors should be
placed as close as possible to the converter’s power supply
pins, AVDD and DVDD . Also, should the layout be designed
using separate digital and analog ground planes, these
capacitors should be terminated to the digital ground for
DVDD and to the analog ground for AVDD . Additional filtering
of the power supplies on the board is recommended.
Voltage Reference
The internal voltage reference of the device has a nominal
value of +1.2V with a ± 60 ppm /
oC drift coefficient over the full
temperature range of the converter. It is recommended that a
0.1µF capacitor be placed as close as possible to the REFIO
pin, connected to the analog ground. The REFLO pin (15)
selects the reference. The internal reference can be selected if
pin 15 is tied low (ground). If an external reference is desired,
then pin 15 should be tied high (to the analog supply voltage)
and the external reference driven into REFIO, pin 23. The full
scale output current of the converter is a function of the voltage
reference used and the value of RSET
. IOUT should be within
the 2mA to 20mA range, through operation below 2mA is
possible, with performance degradation.
If the internal reference is used, VFSADJ will equal
approximately 1.16V (pin 22). If an external reference is used,
VFSADJ will equal the external reference. The calculation for
IOUT (Full Scale) is:
IOUT (Full Scale) = (VFSADJ/RSET) x 32.
If the full scale output current is set to 20mA by using the
internal voltage reference (1.16V) and a 1.86kΩ RSET
resistor, then the input coding to output current will resemble
the following:
Outputs
IOUTA and IOUTB (or QOUTA and QOUTB) are
complementary current outputs. The sum of the two currents
is always equal to the full scale output current minus one
LSB. If single ended use is desired, a load resistor can be
used to convert the output current to a voltage. It is
recommended that the unused output be either grounded or
equally terminated. The voltage developed at the output
must not violate the output voltage compliance range of
-0.3V to 1.25V. RLOAD should be chosen so that the desired
output voltage is produced in conjunction with the output full
scale current, which is described above in the ‘Reference’
section. If a known line impedance is to be driven, then the
output load resistor should be chosen to match this
impedance. The output voltage equation is:
VOUT = IOUT X RLOAD .
These outputs can be used in a differential-to-single-ended
arrangement to achieve better harmonic rejection. The
SFDR measurements in this data sheet were performed with
a 1:1 transformer on the output of the DAC (see Figure 1).
With the center tap grounded, the output swing of pins 16
and 17 will be biased at zero volts. It is important to note
here that the negative voltage output compliance range limit
is -300mV, imposing a maximum of 600mVP-P amplitude
with this configuration. The loading as shown in Figure 1 will
result in a 500mV signal at the output of the transformer if
the full scale output current of the DAC is set to 20mA.
VOUT = 2 x IOUT x REQ ,where REQ is ~12.5Ω .
Allowing the center tap to float will result in identical
transformer output, however the output pins of the DAC will
have positive DC offset. The 50Ω load on the output of the
transformer represents the spectrum analyzer’s input
impedance.
TABLE 1. INPUT CODING vs OUTPUT CURRENT
INPUT CODE (D7-D0) IOUTA (mA) IOUTB (mA)
1111 1111 20 0
1000 0000 10 10
0000 0000 020
PIN 17 (20)
PIN 16 (21)
VOUT = (2 x IOUT x REQ)V
100Ω
50Ω
50Ω
50Ω
IOUTB (QOUTB)
IOUTA (QOUTA)
FIGURE 4.
HI5628
10
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
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Pin Descriptions
PIN NO. PIN NAME PIN DESCRIPTION
39-32 QD7 (MSB) Through
QD0 (LSB)
Digital Data Bit 7, the Most Significant Bit through Digital Data Bit 0, the Least Significant Bit, of the Q
channel.
1-5, 48-46 ID7 (MSB) Through
ID0 (LSB)
Digital Data Bit 7, the Most Significant Bit through Digital Data Bit 0, the Least Significant Bit, of the I
channel.
8SLEEP Control Pin for Power-Down Mode. Sleep Mode is active high; connect to ground for Normal Mode. Sleep
pin has internal 20µA active pulldown current.
15 REFLO Connect to analog ground to enable internal 1.2V reference or connect to AVDD to disable.
23 REFIO Reference voltage input if internal reference is disabled and reference voltage output if internal reference is
enabled. Use 0.1µF cap to ground when internal reference is enabled.
22 FSADJ Full Scale Current Adjust. Use a resistor to ground to adjust full scale output current. Full Scale Output
Current Per Channel = 32 x IFSADJ .
14, 24 ICOMP1, QCOMP1 Reduces noise. Connect each to AVDD with 0.1µF capacitor. The ICOMP1 and QCOMP1 pins MUST be
tied together externally.
13, 18, 19, 25 AGND Analog Ground Connections.
17 IOUTB The complementary current output of the I channel. Bits set to all 0s gives full scale current.
16 IOUTA Current output of the I channel. Bits set to all 1s gives full scale current.
20 QOUTB The complementary current output of the Q channel. Bits set to all 0s gives full scale current.
21 QOUTA Current output of the Q channel. Bits set to all 1s gives full scale current.
11, 27 NC No Connect. Recommended: Connect to ground.
12, 26 AVDD Analog Supply (+2.7V to +5.5V).
6, 7, 10, 28, 30,
31, 41, 44
DGND Digital Ground.
9, 29, 40, 45 DVDD Supply voltage for digital circuitry (+2.7V to +5.5V).
43 ICLK Clock input for I channel. Positive edge of clock latches data.
42 QCLK Clock input for Q channel. Positive edge of clock latches data.
HI5628
