Not recommended for new designs - Please use 25AA640A or 25LC640A. 25AA640/25LC640 64K SPI Bus Serial EEPROM Device Selection Table Description: Part Number VCC Range 25AA640 1.8-5.5V 1 MHz I 25LC640 2.5-5.5V 2 MHz I 25LC640 4.5-5.5V 3/2.5 MHz I, E Max Clock Frequency Temp Ranges Features: The Microchip Technology Inc. 25AA640/25LC640 (25XX640*) is a 64 Kbit Serial Electrically Erasable PROM [EEPROM]. The memory is accessed via a simple Serial Peripheral Interface (SPI) compatible serial bus. The bus signals required are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a Chip Select (CS) input. Communication to the device can be paused via the hold pin (HOLD). While the device is paused, transitions on its inputs will be ignored, with the exception of Chip Select, allowing the host to service higher priority interrupts. * Low-Power CMOS Technology - Write current: 3 mA, typical - Read current: 500 A, typical - Standby current: 500 nA, typical * 8192 x 8 Bit Organization * 32 Byte Page * Write Cycle Time: 5 ms max. * Self-Timed Erase and Write Cycles * Block Write Protection - Protect none, 1/4, 1/2 or all of array * Built-in Write Protection - Power on/off data protection circuitry - Write enable latch - Write-protect pin * Sequential Read * High Reliability - Data retention: > 200 years - ESD protection: > 4000V * 8-pin PDIP, SOIC and TSSOP Packages * Temperature Ranges Supported: - Industrial (I): -40C to +85C - Automotive (E): -40C to +125C Block Diagram STATUS Register HV Generator EEPROM Memory Control Logic I/O Control Logic XDEC Array Page Latches SI Y Decoder SO CS SCK Sense Amp. R/W Control HOLD WP VCC VSS Package Types 1 SO 2 WP 3 VSS 4 8 VCC 7 HOLD 6 SCK 5 SI TSSOP HOLD VCC CS SO 1 2 3 4 25XX640 CS 25XX640 PDIP/SOIC 8 7 6 5 SCK SI VSS WP *25XX640 is used in this document as a generic part number for the 25AA640/25LC640 devices. (c) 2008 Microchip Technology Inc. DS21223H-page 1 25AA640/25LC640 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings() VCC .............................................................................................................................................................................7.0V All inputs and outputs w.r.t. VSS ........................................................................................................ -0.6V to VCC + 1.0V Storage temperature .................................................................................................................................-65C to 150C Ambient temperature under bias ...............................................................................................................-65C to 125C ESD protection on all pins ..........................................................................................................................................4 kV NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an extended period of time may affect device reliability. TABLE 1-1: DC CHARACTERISTICS DC CHARACTERISTICS Param. No. Sym D1 VIH1 D2 VIH2 D3 VIL1 D4 VIL2 D5 VOL Characteristics Industrial (I): TA = -40C to +85C VCC = 1.8V to 5.5V Automotive (E): TA = -40C to +125C VCC = 4.5V to 5.5V Min Max Units Conditions High-level input voltage 2.0 VCC + 1 V VCC 2.7V (Note 1) 0.7 VCC VCC + 1 V VCC < 2.7V (Note 1) Low-level input voltage -0.3 0.8 V VCC 2.7V (Note 1) -0.3 0.2 VCC V VCC < 2.7V (Note 1) Low-level output voltage -- 0.4 V IOL = 2.1 mA -- 0.2 V IOL = 1.0 mA, VCC = < 2.5V VCC - 0.5 -- V IOH = -400 A D6 VOH High-level output voltage D7 ILI Input leakage current -- 1 A CS = VCC, VIN = VSS TO VCC D8 ILO Output leakage current -- 1 A CS = VCC, VOUT = VSS TO VCC D9 CINT Internal Capacitance (all inputs and outputs) -- 7 pF TA = 25C, CLK = 1.0 MHz, VCC = 5.0V (Note 1) D10 ICC Read Operating Current -- -- 1 500 mA A VCC = 5.5V; FCLK = 3.0 MHz; SO = Open VCC = 2.5V; FCLK = 2.0 MHz; SO = Open D11 ICC Write -- -- 5 3 mA mA VCC = 5.5V VCC = 2.5V D12 ICCS -- -- 5 1 A A CS = VCC = 5.5V, Inputs tied to VCC or VSS CS = VCC = 2.5V, Inputs tied to VCC or VSS Note 1: Standby Current This parameter is periodically sampled and not 100% tested. DS21223H-page 2 (c) 2008 Microchip Technology Inc. 25AA640/25LC640 TABLE 1-2: AC CHARACTERISTICS Industrial (I): TA = -40C to +85C Automotive (E): TA = -40C to +125C AC CHARACTERISTICS Param. No. Sym Characteristic VCC = 1.8V to 5.5V VCC = 4.5V to 5.5V Min Max Units Conditions -- -- -- 3 2 1 MHz MHz MHz VCC = 4.5V to 5.5V (Note 2) VCC = 2.5V to 5.5V VCC = 1.8V to 5.5V 1 FCLK Clock Frequency 2 TCSS CS Setup Time 100 250 500 -- -- -- ns ns ns VCC = 4.5V to 5.5V VCC = 2.5V to 5.5V VCC = 1.8V to 5.5V 3 TCSH CS Hold Time 150 250 475 -- -- -- ns ns ns VCC = 4.5V to 5.5V VCC = 2.5V to 5.5V VCC = 1.8V to 5.5V 4 TCSD CS Disable Time 500 -- ns 5 TSU Data Setup Time 30 50 50 -- -- -- ns ns ns VCC = 4.5V to 5.5V VCC = 2.5V to 5.5V VCC = 1.8V to 5.5V 6 THD Data Hold Time 50 100 100 -- -- -- ns ns ns VCC = 4.5V to 5.5V VCC = 2.5V to 5.5V VCC = 1.8V to 5.5V 7 TR CLK Rise Time -- 2 s (Note 1) 8 TF CLK Fall Time -- 2 s (Note 1) 9 THI Clock High Time 150 230 475 -- -- -- ns ns ns VCC = 4.5V to 5.5V VCC = 2.5V to 5.5V VCC = 1.8V to 5.5V 10 TLO Clock Low Time 150 230 475 -- -- -- ns ns ns VCC = 4.5V to 5.5V VCC = 2.5V to 5.5V VCC = 1.8V to 5.5V 11 TCLD Clock Delay Time 50 -- ns 12 TCLE Clock Enable Time 50 -- ns 13 TV Output Valid from Clock Low -- -- -- 150 230 475 ns ns ns VCC = 4.5V to 5.5V VCC = 2.5V to 5.5V VCC = 1.8V to 5.5V 14 THO Output Hold Time 0 -- ns (Note 1) 15 TDIS Output Disable Time -- -- -- 200 250 500 ns ns ns VCC = 4.5V to 5.5V (Note 1) VCC = 2.5V to 5.5V (Note 1) VCC = 1.8V to 5.5V (Note 1) 16 THS HOLD Setup Time 100 100 200 -- -- -- ns ns ns VCC = 4.5V to 5.5V VCC = 2.5V to 5.5V VCC = 1.8V to 5.5V 17 THH HOLD Hold Time 100 100 200 -- -- -- ns ns ns VCC = 4.5V to 5.5V VCC = 2.5V to 5.5V VCC = 1.8V to 5.5V 18 THZ HOLD Low to Output High-Z 100 150 200 -- -- -- ns ns ns VCC = 4.5V to 5.5V (Note 1) VCC = 2.5V to 5.5V (Note 1) VCC = 1.8V to 5.5V (Note 1) 19 THV HOLD High to Output Valid 100 150 200 -- -- -- ns ns ns VCC = 4.5V to 5.5V VCC = 2.5V to 5.5V VCC = 1.8V to 5.5V 20 TWC Internal Write Cycle Time -- 5 ms 21 -- Endurance 1M -- E/W Cycles (Note 3) Note 1: This parameter is periodically sampled and not 100% tested. 2: FCLK max. = 2.5 MHz for TA > 85C. 3: This parameter is not tested but established by characterization. For endurance estimates in a specific application, please consult the Total EnduranceTM Model which can be obtained from Microchip's web site at: www.microchip.com. (c) 2008 Microchip Technology Inc. DS21223H-page 3 25AA640/25LC640 FIGURE 1-1: HOLD TIMING CS 16 17 16 17 SCK 18 SO n+2 n+1 n 19 High-Impedance n 5 Don't Care n+2 SI n+1 n-1 n n n-1 HOLD FIGURE 1-2: SERIAL INPUT TIMING 4 CS 12 2 7 Mode 1,1 11 8 3 SCK Mode 0,0 5 SI 6 MSB In LSB In High-Impedance SO FIGURE 1-3: SERIAL OUTPUT TIMING CS 9 3 10 Mode 1,1 SCK Mode 0,0 13 14 SO SI DS21223H-page 4 MSB Out 15 LSB Out Don't Care (c) 2008 Microchip Technology Inc. 25AA640/25LC640 TABLE 1-3: AC TEST CONDITIONS FIGURE 1-4: AC Waveform: AC TEST CIRCUIT VCC VLO = 0.2V VHI = VCC - 0.2V (Note 1) VHI = 4.0V (Note 2) Timing Measurement Reference Level Input 0.5 VCC Output 0.5 VCC 2.25 k SO 1.8 k 100 pF Note 1: For VCC 4.0V 2: For VCC > 4.0V (c) 2008 Microchip Technology Inc. DS21223H-page 5 25AA640/25LC640 2.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 2-1. TABLE 2-1: PIN FUNCTION TABLE Name PDIP SOIC TSSOP CS 1 1 3 Chip Select Input SO 2 2 4 Serial Data Output WP 3 3 5 Write-Protect Pin VSS 4 4 6 Ground SI 5 5 7 Serial Data Input SCK 6 6 8 Serial Clock Input HOLD 7 7 1 Hold Input VCC 8 8 2 Supply Voltage 2.1 Description Chip Select (CS) A low level on this pin selects the device. A high level deselects the device and forces it into Standby mode. However, a programming cycle which is already initiated or in progress will be completed, regardless of the CS input signal. If CS is brought high, or remains high during a program cycle, the device will go into Standby mode when the programming cycle is complete. When the device is deselected, SO goes to the high-impedance state, allowing multiple parts to share the same SPI bus. A low-to-high transition on CS after a valid write sequence initiates an internal write cycle. After power-up, a high-to-low transition on CS is required prior to any sequence being initiated. 2.2 Serial Output (SO) The SO pin is used to transfer data out of the 25XX640. During a read cycle, data is shifted out on this pin after the falling edge of the serial clock. 2.3 The WP pin function is blocked when the WPEN bit in the STATUS register is low. This allows the user to install the 25XX640 in a system with WP pin grounded and still be able to write to the STATUS register. The WP pin functions will be enabled when the WPEN bit is set high. 2.4 Serial Input (SI) The SI pin is used to transfer data into the device. It receives instructions, addresses, and data. Data is latched on the rising edge of the serial clock. 2.5 Serial Clock (SCK) The SCK is used to synchronize the communication between a master and the 25XX640. Instructions, addresses, or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin is updated after the falling edge of the clock input. 2.6 Hold (HOLD) The HOLD pin is used to suspend transmission to the 25XX640 while in the middle of a serial sequence without having to retransmit the entire sequence over again. It must be held high any time this function is not being used. Once the device is selected and a serial sequence is underway, the HOLD pin may be pulled low to pause further serial communication without resetting the serial sequence. The HOLD pin must be brought low while SCK is low, otherwise the HOLD function will not be invoked until the next SCK high-tolow transition. The 25XX640 must remain selected during this sequence. The SI, SCK, and SO pins are in a high-impedance state during the time the device is paused and transitions on these pins will be ignored. To resume serial communication, HOLD must be brought high while the SCK pin is low, otherwise serial communication will not resume. Lowering the HOLD line at any time will tri-state the SO line. Write-Protect (WP) This pin is used in conjunction with the WPEN bit in the STATUS register to prohibit writes to the nonvolatile bits in the STATUS register. When WP is low and WPEN is high, writing to the nonvolatile bits in the STATUS register is disabled. All other operations function normally. When WP is high, all functions, including writes to the nonvolatile bits in the STATUS register operate normally. If the WPEN bit is set, WP low during a STATUS register write sequence will disable writing to the STATUS register. If an internal write cycle has already begun, WP going low will have no effect on the write. DS21223H-page 6 (c) 2008 Microchip Technology Inc. 25AA640/25LC640 3.0 FUNCTIONAL DESCRIPTION 3.3 3.1 Principles Of Operation Prior to any attempt to write data to the 25XX640 array or STATUS register, the write enable latch must be set by issuing the WREN instruction (Figure 3-4). This is done by setting CS low and then clocking out the proper instruction into the 25XX640. After all eight bits of the instruction are transmitted, the CS must be brought high to set the write enable latch. If the write operation is initiated immediately after the WREN instruction without CS being brought high, the data will not be written to the array because the write enable latch will not have been properly set. The 25XX640 is a 8192 byte Serial EEPROM designed to interface directly with the Serial Peripheral Interface (SPI) port of many of today's popular microcontroller families, including Microchip's PIC16C6X/7X microcontrollers. It may also interface with microcontrollers that do not have a built-in SPI port by using discrete I/O lines programmed properly with the software. The 25XX640 contains an 8-bit instruction register. The device is accessed via the SI pin, with data being clocked in on the rising edge of SCK. The CS pin must be low and the HOLD pin must be high for the entire operation. Table 3-1 contains a list of the possible instruction bytes and format for device operation. All instructions, addresses, and data are transferred MSB first, LSB last. Data is sampled on the first rising edge of SCK after CS goes low. If the clock line is shared with other peripheral devices on the SPI bus, the user can assert the HOLD input and place the 25XX640 in `HOLD' mode. After releasing the HOLD pin, operation will resume from the point when the HOLD was asserted. 3.2 Read Sequence The device is selected by pulling CS low. The 8-bit READ instruction is transmitted to the 25XX640 followed by the 16-bit address with the three MSBs of the address being "don't care" bits. After the correct READ instruction and address are sent, the data stored in the memory at the selected address is shifted out on the SO pin. The data stored in the memory at the next address can be read sequentially by continuing to provide clock pulses. The internal Address Pointer is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached (1FFFh), the address counter rolls over to address 0000h allowing the read cycle to be continued indefinitely. The read operation is terminated by raising the CS pin (Figure 3-1). TABLE 3-1: Write Sequence Once the write enable latch is set, the user may proceed by setting the CS low, issuing a WRITE instruction, followed by the address, and then the data to be written. Up to 32 bytes of data can be sent to the 25XX640 before a write cycle is necessary. The only restriction is that all of the bytes must reside in the same page. A page address begins with XXX0 0000 and ends with XXX1 1111. If the internal address counter reaches XXX1 1111 and the clock continues, the counter will roll back to the first address of the page and overwrite any data in the page that may have been written. For the data to be actually written to the array, the CS must be brought high after the Least Significant bit (D0) of the nth data byte has been clocked in. If CS is brought high at any other time, the write operation will not be completed. Refer to Figure 3-2 and Figure 3-3 for more detailed illustrations on the byte write sequence and the page write sequence, respectively. While the write is in progress, the STATUS register may be read to check the status of the WPEN, WIP, WEL, BP1, and BP0 bits (Figure 3-6). A read attempt of a memory array location will not be possible during a write cycle. When the write cycle is completed, the write enable latch is reset. INSTRUCTION SET Instruction Name Instruction Format Description READ 0000 0011 Read data from memory array beginning at selected address WRITE 0000 0010 Write data to memory array beginning at selected address WREN 0000 0110 Set the write enable latch (enable write operations) WRDI 0000 0100 Reset the write enable latch (disable write operations) RDSR 0000 0101 Read STATUS register WRSR 0000 0001 Write STATUS register (c) 2008 Microchip Technology Inc. DS21223H-page 7 25AA640/25LC640 FIGURE 3-1: READ SEQUENCE CS 0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 SCK Instruction SI 0 0 0 0 16-bit Address 0 0 1 15 14 13 12 1 2 1 0 Data Out High-Impedance 7 SO FIGURE 3-2: 6 5 4 3 2 1 BYTE WRITE SEQUENCE CS Twc Instruction SI 0 0 0 0 0 0 16-bit Address 0 0 15 14 13 12 1 Data Byte 2 1 0 7 6 5 4 3 2 1 0 High-Impedance SO FIGURE 3-3: PAGE WRITE SEQUENCE CS 0 1 0 0 2 3 4 5 6 0 1 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 SCK Instruction SI 0 0 0 16-bit Address Data Byte 1 2 0 15 14 13 12 1 0 7 6 5 4 3 2 1 0 CS 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCK Data Byte 2 SI 7 DS21223H-page 8 6 5 4 3 2 Data Byte 3 1 0 7 6 5 4 3 2 Data Byte n (32 max) 1 0 7 6 5 4 3 2 1 0 (c) 2008 Microchip Technology Inc. 25AA640/25LC640 3.4 Write Enable (WREN) and Write Disable (WRDI) The following is a list of conditions under which the write enable latch will be reset: * * * * The 25XX640 contains a write enable latch. See Table 3-3 for the Write-Protect Functionality Matrix. This latch must be set before any write operation will be completed internally. The WREN instruction will set the latch, and the WRDI will reset the latch. FIGURE 3-4: Power-up WRDI instruction successfully executed WRSR instruction successfully executed WRITE instruction successfully executed WRITE ENABLE SEQUENCE CS 0 1 2 3 4 5 6 7 SCK SI 0 0 0 0 0 1 1 0 High-Impedance SO FIGURE 3-5: WRITE DISABLE SEQUENCE CS 0 1 2 3 4 5 6 7 SCK SI 0 0 0 0 0 1 10 0 High-Impedance SO (c) 2008 Microchip Technology Inc. DS21223H-page 9 25AA640/25LC640 3.5 Read Status Register Instruction (RDSR) The Write Enable Latch (WEL) bit indicates the status of the write enable latch. When set to a `1', the latch allows writes to the array and STATUS register, when set to a `0', the latch prohibits writes to the array and STATUS register. The state of this bit can always be updated via the WREN or WRDI commands regardless of the state of write protection on the STATUS register. This bit is read-only. The Read Status Register instruction (RDSR) provides access to the STATUS register. The STATUS register may be read at any time, even during a write cycle. The STATUS register is formatted as follows: 7 WPEN 6 X 5 X 4 X 3 BP1 2 BP0 1 WEL 0 WIP The Block Protection (BP0 and BP1) bits indicate which blocks are currently write-protected. These bits are set by the user issuing the WRSR instruction. These bits are nonvolatile. The Write-In-Process (WIP) bit indicates whether the 25XX640 is busy with a write operation. When set to a `1', a write is in progress, when set to a `0', no write is in progress. This bit is read-only. FIGURE 3-6: See Figure 3-6 for RDSR timing sequence. READ STATUS REGISTER TIMING SEQUENCE CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK Instruction SI 0 0 0 0 0 1 0 1 Data from STATUS Register High-Impedance SO DS21223H-page 10 7 6 5 4 3 2 1 0 (c) 2008 Microchip Technology Inc. 25AA640/25LC640 3.6 TABLE 3-2: Write Status Register Instruction (WRSR) The Write Status Register instruction (WRSR) allows the user to select one of four levels of protection for the array by writing to the appropriate bits in the STATUS register. The array is divided up into four segments. The user has the ability to write-protect none, one, two, or all four of the segments of the array. The partitioning is controlled as shown in Table 3-2. The Write-Protect Enable (WPEN) bit is a nonvolatile bit that is available as an enable bit for the WP pin. The Write-Protect (WP) pin and the Write-Protect Enable (WPEN) bit in the STATUS register control the programmable hardware write-protect feature. Hardware write protection is enabled when the WP pin is low and the WPEN bit is high. Hardware write protection is disabled when either the WP pin is high or the WPEN bit is low. When the chip is hardware write-protected, only writes to nonvolatile bits in the STATUS register are disabled. See Table 3-3 for a matrix of functionality on the WPEN bit. ARRAY PROTECTION BP1 BP0 Array Addresses Write-Protected 0 0 none 0 1 upper 1/4 (1800h-1FFFh) 1 0 upper 1/2 (1000h-1FFFh) 1 1 all (0000h-1FFFh) See Figure 3-7 for WRSR timing sequence. FIGURE 3-7: WRITE STATUS REGISTER TIMING SEQUENCE CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 0 SCK Instruction SI 0 0 0 0 0 Data to STATUS Register 0 0 1 7 6 5 4 3 2 High-Impedance SO (c) 2008 Microchip Technology Inc. DS21223H-page 11 25AA640/25LC640 3.7 Data Protection 3.8 The following protection has been implemented to prevent inadvertent writes to the array: * The write enable latch is reset on power-up * A write enable instruction must be issued to set the write enable latch * After a byte write, page write, or STATUS register write, the write enable latch is reset * CS must be set high after the proper number of clock cycles to start an internal write cycle * Access to the array during an internal write cycle is ignored and programming is continued TABLE 3-3: Power-On-State The 25XX640 powers on in the following state: * The device is in low-power Standby mode (CS = 1) * The write enable latch is reset * SO is in high-impedance state * A high-to-low transition on CS is required to enter the active state . WRITE-PROTECT FUNCTIONALITY MATRIX WPEN WP WEL Protected Blocks Unprotected Blocks STATUS Register X X 0 Protected Protected Protected 0 X 1 Protected Writable Writable 1 Low 1 Protected Writable Protected X High 1 Protected Writable Writable DS21223H-page 12 (c) 2008 Microchip Technology Inc. 25AA640/25LC640 4.0 PACKAGING INFORMATION 4.1 Package Marking Information 8-Lead PDIP (300 mil) XXXXXXXX XXXXXNNN YYWW 25LC640 /P017 0410 8-Lead SOIC (150 mil) XXXXXXXX XXXXYYWW NNN 8-Lead TSSOP XXXX YYWW NNN Legend: XX...X Y YY WW NNN e3 * Note: * Example: Example: 25LC640 I/SN0410 017 Example: 5LCX 0410 017 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. Standard marking consists of Microchip part number, year code, week code, traceability code (facility code, mask rev#, and assembly code). For marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. (c) 2008 Microchip Technology Inc. DS21223H-page 13 25AA640/25LC640 3 & ' !&" & 4# *!( !!& 4 %& &#& && 255***' '5 4 N NOTE 1 E1 1 3 2 D E A2 A L A1 c e eB b1 b 6&! '! 9'&! 7"') %! 7,8. 7 7 & ; < & & 7: 1, = = - 1!& & = = . - - ##4 "# & 4!! "# >#& ##4>#& . < : 9& -< -? 9 - < ) ? ) < 1 = = & & 9# 6 4!! 9#>#& 9 * 9#>#& : * + - !"#$%&" ' ()"&'"!&) &#*& & & # +%&, & !& - '! !#.# &"#' #%! & "! ! #%! & "! !! &$#/ !# '! #& .0 1,21!'! &$& "! **& "&& ! DS21223H-page 14 * ,<1 (c) 2008 Microchip Technology Inc. 25AA640/25LC640 ! ""#$%& !' 3 & ' !&" & 4# *!( !!& 4 %& &#& && 255***' '5 4 D e N E E1 NOTE 1 1 2 3 h b h A2 A c L A1 L1 6&! '! 9'&! 7"') %! 99. . 7 7 7: ; < & : 8 & = = = = = ##4 4!! &# %%+ 1, : >#& . ##4>#& . -1, : 9& 1, , '% @ 3 & A &9& 9 3 & & 9 3 & ?1, = = .3 I B = <B = 9#>#& ) - = # %& D B = B # %&1 && ' E B = 9# 4!! B !"#$%&" ' ()"&'"!&) &#*& & & # +%&, & !& - '! !#.# &"#' #%! & "! ! #%! & "! !! &$#'' !# '! #& .0 1,2 1!'! &$& "! **& "&& ! .32 % '! ("!"*& "&& (% % '& " !! (c) 2008 Microchip Technology Inc. * ,1 DS21223H-page 15 25AA640/25LC640 ! ""#$%& !' 3 & ' !&" & 4# *!( !!& 4 %& &#& && 255***' '5 4 DS21223H-page 16 (c) 2008 Microchip Technology Inc. 25AA640/25LC640 () )" * ! (+%+( ! 3 & ' !&" & 4# *!( !!& 4 %& &#& && 255***' '5 4 D N E E1 NOTE 1 1 2 b e c A2 A A1 L L1 6&! '! 9'&! 7"') %! 99. . 7 7 7: ; < & : 8 & = = < = ##4 4!! &# %% ?1, : >#& . ##4>#& . - ##49& - - 3 &9& 9 ? 3 & & 9 3 & 9# 4!! ?1, .3 I B = <B = 9#>#& ) = - !"#$%&" ' ()"&'"!&) &#*& & & # '! !#.# &"#' #%! & "! ! #%! & "! !! &$#'' !# - '! #& .0 1,2 1!'! &$& "! **& "&& ! .32 % '! ("!"*& "&& (% % '& " !! (c) 2008 Microchip Technology Inc. * ,<?1 DS21223H-page 17 25AA640/25LC640 APPENDIX A: REVISION HISTORY Revision F Corrections to Section 1.0, Electrical Characteristics. Revision G Product ID System, Example C: Corrected part number, added "Alternate Pinout" and corrected part number in Header. Updated Trademark and Sales List pages. Revision H (June 2008) Added "Not Recommended" note; Updated Packaging; General updates. DS21223H-page 18 (c) 2008 Microchip Technology Inc. 25AA640/25LC640 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: Users of Microchip products can receive assistance through several channels: * Product Support - Data sheets and errata, application notes and sample programs, design resources, user's guides and hardware support documents, latest software releases and archived software * General Technical Support - Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing * Business of Microchip - Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives * * * * * Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com CUSTOMER CHANGE NOTIFICATION SERVICE Microchip's customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. (c) 2008 Microchip Technology Inc. DS21223H-page 19 25AA640/25LC640 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: Technical Publications Manager RE: Reader Response Total Pages Sent ________ From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y Device: 25AA640/25LC640 N Literature Number: DS21223H Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS21223H-page 20 (c) 2008 Microchip Technology Inc. 25AA640/25LC640 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Device Temperature Range Package Pattern Examples: a) b) Device 25AA640: 25AA640T: 64K bit 1.8V SPI Serial EEPROM 64K bit 1.8V SPI Serial EEPROM (Tape and Reel) 25AA640X: 64K bit 1.8V SPI Serial EEPROM in alternate pinout (ST only) 25AA640XT: 64K bit 1.8V SPI Serial EEPROM in alternate pinout Tape and Reel (ST only) 25LC640: 64K bit 2.5V SPI Serial EEPROM 25LC640T: 64K bit 2.5V SPI Serial EEPROM (Tape and Reel) 25LC640X: 64K bit 2.5V SPI Serial EEPROM in alternate pinout (ST only) 25LC640XT: 64K bit 2.5V SPI Serial EEPROM in alternate pinout Tape and Reel (ST only) Temperature Range I E Package P SN ST = = c) d) e) f) 25AA640-I/SN: Industrial Temp., SOIC package 25AA640T-I/SN: Tape and Reel, Industrial Temp., SOIC package 25AA640X-I/ST: Alternate Pinout Industrial Temp., TSSOP package 25LC640-I/SN: Industrial Temp., SOIC package 25LC640T-I/SN: Tape and Reel, Industrial Temp., SOIC package 25LC640X-I/ST: Alternate Pinout, Industrial Temp., TSSOP package -40C to +85C -40C to +125C = = = (c) 2008 Microchip Technology Inc. Plastic DIP (300 mil Body), 8-lead Plastic SOIC (150 mil Body), 8-lead Plastic TSSOP (4.4 mm Body), 8-lead DS21223H-page 21 25AA640/25LC640 NOTES: DS21223H-page 22 (c) 2008 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2008, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. (c) 2008 Microchip Technology Inc. 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