© 2008 Microchip Technology Inc. DS21223H-page 1
25AA640/25LC640
Device Selection Table
Features:
• Low-Power CMOS Technology
- Write current: 3 mA, typical
- Read current: 500 μA, typical
- S tandb y current: 500 nA, typ ical
• 8192 x 8 Bit Organization
• 32 Byte Page
• Write Cycle Time: 5 ms max.
• Self-Timed Erase and Write Cycles
• Block Write Protection
- Protect none, 1/4, 1/2 or all of array
• Built -in W ri te Protec tio n
- Power on/off data protection circuitry
- Write enable latch
- Write-protect pin
• Seque nti al Read
• High Reliability
- Data retention: > 200 years
- ESD protection: > 4000V
• 8-pin PDIP, SOIC and TSSOP Packages
• Temperature Ranges Supported:
- Industrial (I): -40°C to +85°C
- Automotive (E): -40°C to +125°C
Description:
The Microchip Technology Inc. 25AA640/25LC640
(25XX640*) is a 64 Kbit Serial Electrically Erasable
PROM [EEPROM]. The memory is accessed via a
simple Serial Peripheral Interface (SPI) compatible
serial bus. The bus signals required are a clock input
(SCK) plus separate data in (SI) and data out (SO)
lines. Ac cess to the dev ice is contro lled th rough a C hip
Select (CS) input.
Communication to the device can be paused via the
hold pin (HOLD). While the device is paused,
transitions on its inputs will be ignored, with the
exception of Chip Select, allowing the host to service
higher priority interrupts.
Block Diagram
Package Types
Part
Number VCC
Range Max Clock
Frequency Temp
Ranges
25AA640 1.8-5.5V 1 MHz I
25LC640 2.5-5.5V 2 MHz I
25LC640 4.5-5.5V 3/2.5 MHz I, E
SI
SO
SCK
CS
HOLD
WP
I/O Control Memory
Control
Logic
HV Generator
EEPROM
Array
Page
Y Decoder
Sense Amp.
R/W Control
Logic
VCC
VSS
Latches
XDEC
STATUS
Register
25XX640
25XX640
PDIP/SOIC
TSSOP
CS
SO
WP
VSS
VCC
HOLD
SCK
SI
8
7
6
5
1
2
3
4
8
7
6
5
1
2
3
4
HOLD
VCC
CS
SO
SCK
SI
VSS
WP
64K SPI Bus Serial EEPROM
*25XX640 is used in this document as a generic part number for the 25AA640/25LC640 devices.
Not recommended for new designs –
Please use 25AA640A or 25LC640A.
25AA640/25LC640
DS21223H-page 2 © 2008 Microchip Technology Inc.
1.0 ELECTRICAL CHARAC TERISTICS
Absolute Maximum Ratings(†)
VCC.............................................................................................................................................................................7.0V
All inputs and outputs w.r.t. VSS ........................................................................................................ -0.6V to VCC + 1.0V
Storage temperature .................................................................................................................................-65°C to 150°C
Ambient temperature under bias...............................................................................................................-65°C to 125°C
ESD protection on all pins..........................................................................................................................................4 kV
TABLE 1-1: DC CHARACTERISTICS
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device . This i s a stres s ratin g only and functio nal operati on of the devic e at thos e or any other co nditio ns abov e thos e
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an
extended period of time may affect device reliability.
DC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C VCC = 1.8V to 5.5V
Automotive (E): TA = -40°C to +125°C VCC = 4.5V to 5.5V
Param.
No. Sym Characteristics Min Max Units Conditions
D1 VIH1 High-level input
voltage 2.0 VCC + 1 V VCC ≥ 2.7V (Note 1)
D2 VIH2 0.7 VCC VCC + 1 V VCC < 2.7V (Note 1)
D3 VIL1 Low-level input
voltage -0.3 0.8 V VCC ≥ 2.7V (Note 1)
D4 VIL2 -0.3 0 .2 VCC VVCC < 2.7V (Note 1)
D5 VOL Low-level output
voltage —0.4VIOL = 2.1 mA
—0.2VI
OL = 1.0 mA, VCC = < 2.5V
D6 VOH High-level output
voltage VCC - 0.5 — V IOH = -400 μA
D7 ILI Input leakage current — ±1 μACS = VCC, VIN = VSS TO VCC
D8 ILO Output lea kage
current —±1μACS = VCC, VOUT = VSS TO VCC
D9 CINT Intern al Cap acit ance
(all inputs and
outputs)
—7pFT
A = 25°C, CLK = 1.0 MHz,
VCC = 5.0V (Note 1)
D10 ICC Read Operating Current —
—1
500 mA
μAVCC = 5.5V; FCLK = 3.0 MHz;
SO = Open
VCC = 2.5V; FCLK = 2.0 MHz;
SO = Open
D11 ICC Write —
—5
3mA
mA VCC = 5.5V
VCC = 2.5V
D12 ICCS Standby Current —
—5
1μA
μACS = VCC = 5.5V, Inputs tied to VCC or
VSS
CS = VCC = 2.5V, Inputs tied to VCC or
VSS
Note 1: This parameter is periodically sampled and not 100% tested.
© 2008 Microchip Technology Inc. DS21223H-page 3
25AA640/25LC640
TABLE 1-2: AC CHARACTERISTICS
AC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C VCC = 1.8V to 5.5V
Automotive (E): TA = -40°C to +125°C VCC = 4.5V to 5.5V
Param.
No. Sym Characteristic Min Max Units Conditions
1F
CLK Clock Frequency —
—
—
3
2
1
MHz
MHz
MHz
VCC = 4.5V to 5.5V (Note 2)
VCC = 2.5V to 5.5V
VCC = 1.8V to 5.5V
2T
CSS CS Setup Time 100
250
500
—
—
—
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 5.5V
VCC = 1.8V to 5.5V
3T
CSH CS Hold Time 150
250
475
—
—
—
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 5.5V
VCC = 1.8V to 5.5V
4T
CSD CS Disable Time 500 — ns
5T
SU Data Setup Time 30
50
50
—
—
—
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 5.5V
VCC = 1.8V to 5.5V
6T
HD Data Hold T ime 50
100
100
—
—
—
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 5.5V
VCC = 1.8V to 5.5V
7T
RCLK Rise Time — 2 μs(Note 1)
8T
FCLK Fall Time — 2 μs(Note 1)
9T
HI Clock High Time 150
230
475
—
—
—
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 5.5V
VCC = 1.8V to 5.5V
10 TLO Clock Low Time 150
230
475
—
—
—
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 5.5V
VCC = 1.8V to 5.5V
11 TCLD Clock Delay Time 50 — ns
12 TCLE Clock Enable Time 50 — ns
13 TVOutput Valid from
Clock Low —
—
—
150
230
475
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 5.5V
VCC = 1.8V to 5.5V
14 THO Output Hold Time 0 — ns (Note 1)
15 TDIS Output Disable Time —
—
—
200
250
500
ns
ns
ns
VCC = 4.5V to 5.5V (Note 1)
VCC = 2.5V to 5.5V (Note 1)
VCC = 1.8V to 5.5V (Note 1)
16 THS HOLD Setup Time 100
100
200
—
—
—
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 5.5V
VCC = 1.8V to 5.5V
17 THH HOLD Hold Time 100
100
200
—
—
—
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 5.5V
VCC = 1.8V to 5.5V
18 THZ HOLD Low to Output
High-Z 100
150
200
—
—
—
ns
ns
ns
VCC = 4.5V to 5.5V (Note 1)
VCC = 2.5V to 5.5V (Note 1)
VCC = 1.8V to 5.5V (Note 1)
19 THV HOLD High to Output
Valid 100
150
200
—
—
—
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 5.5V
VCC = 1.8V to 5.5V
20 TWC Internal Write Cycle
Time —5ms
21 — Endurance 1M — E/W
Cycles (Note 3)
Note 1: This parameter is periodically sampled and not 100% tested.
2: FCLK max. = 2.5 MHz for TA > 85°C.
3: This parameter is not tested but established by characterization. For endurance estimates in a specific application,
please consult the Total Endurance™ Model which can be obtained from Microchip’s web site at: www.microchip.com.
25AA640/25LC640
DS21223H-page 4 © 2008 Microchip Technology Inc.
FIGURE 1-1: HOLD TIMING
FIGURE 1-2: SERIAL INPUT TIMING
FIGURE 1-3: SERIAL OUTPUT TIMING
CS
SCK
SO
SI
HOLD
17
16 16 17
1918
Don’t Care 5
High-Impedance
n + 2 n + 1 n n - 1
n
n + 2 n + 1 n nn - 1
CS
SCK
SI
SO
65
8
711
3
LSB In
MSB In
High-Impedance
12
Mode 1,1
Mode 0,0
4
2
CS
SCK
SO
10
9
13
MSB Out LSB Out
3
15
Don’t Care
SI
Mode 1,1
Mode 0,0
14
© 2008 Microchip Technology Inc. DS21223H-page 5
25AA640/25LC640
TABLE 1-3: AC TEST CONDITIONS FIGURE 1-4: AC TEST CIRCUIT
AC Waveform:
VLO = 0.2V
VHI = VCC – 0.2V (Note 1)
VHI = 4.0V (Note 2)
Timing Measurement Refere nce Lev el
Input 0.5 VCC
Output 0.5 VCC
Note 1: For VCC ≤ 4.0V
2: For VCC > 4.0V
VCC
SO
100 pF
1.8 kΩ
2.25 kΩ
25AA640/25LC640
DS21223H-page 6 © 2008 Microchip Technology Inc.
2.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1: PIN FUNCTION TABLE
2.1 Chip Select (CS)
A low level on this pin selects the device. A high level
deselects the device and forces it into Standby mode.
However, a programming cycle which is already
initiated or in p r ogre ss w il l be co mpl ete d, regardle ss of
the CS input signal. If CS is brought high, or remains
high during a program cycle, the device will go into
Standby mode when the programming cycle is
complete. When the device is deselected, SO goes to
the high-impedance state, allowing multiple parts to
share the s ame SPI bus. A low-to-hi gh transition on CS
after a valid write sequence initiates an internal write
cycle. After power-up, a high-to-low transition on CS is
required prior to any sequence being initiated.
2.2 Serial Output (SO)
The SO pin is used to transfer data out of the 25XX640.
During a read cy cl e, data is sh if ted out on this pin after
the falling edge of the serial clock.
2.3 Write-Protect (WP)
This pin is used in conjunction with the WPEN bit in the
STATUS register to prohibit writes to the nonvolatile
bits in the STATUS register. When WP is low and
WPEN is high, w riting to the nonvolat ile bits in the STA-
TUS register is disabled. All other operations function
normally. When WP is high, all functions, including
writes to the nonvolatile bits in the STATUS register
operate no rmally. If the WPEN bit is set, WP low during
a STATUS register write sequence will disable writing
to the STATUS register. If an internal write cycle has
already begun, WP go ing low w ill h ave no ef fect on the
write.
The WP pin function is blocked when the WPEN bit in
the STATUS register is low. This allows the user to
install the 25XX640 in a system with WP pin grounded
and still be able to write to the STATUS register. The
WP pin functi ons will be enabl ed when the WPEN bit is
set high.
2.4 Serial Input (SI)
The SI pin is used to transfer data into the device. It
receives instructions, addresses, and data. Data is
latched on the rising edge of the serial clock.
2.5 Serial Clock (SCK)
The SCK is used to synchronize the communication
between a master and the 25XX640. Instructions,
addresses, or data present on the SI pin are latched on
the risin g e dge of the c lo ck in put, while dat a on t he SO
pin is updated after the falling edge of the clock input.
2.6 Hold (HOLD)
The HOLD pin is used to suspend transmission to the
25XX640 w hile in the middle of a seri al sequ ence wit h-
out having to retransmit the entire sequence over
again. It must be held high any time this function is not
being used. Once the device is selected and a serial
sequence is underway, the HOLD pin may be pulled
low to pause further serial communication without
resetting the serial sequence. The HOLD pin must be
brought low while SCK is low, otherwise the HOLD
function will not be invoked until the next SCK high-to-
low transition. The 25XX640 must remain selected
during th is s equ enc e. The SI, SC K, an d SO pins ar e i n
a high-impedance state during the time the device is
paus ed and tran sitions on these p ins will be ignored. To
resume serial communication, HOLD must be brought
high while the SCK pin is low, otherwise serial
communication will not resume. Lowering the HOLD
line at any time will tri-state the SO line.
Name PDIP SOIC TSSOP Description
CS 1 1 3 Chip Select Input
SO 2 2 4 Serial Data Output
WP 3 3 5 Write-Protect Pin
VSS 44 6Ground
SI 5 5 7 Serial Data In put
SCK 6 6 8 Serial Clock Input
HOLD 7 7 1 Hold Input
VCC 8 8 2 Supply Voltage
© 2008 Microchip Technology Inc. DS21223H-page 7
25AA640/25LC640
3.0 FUNCTIONAL DESCRIPTION
3.1 Principles Of Operation
The 25XX640 is a 8192 by te Serial EEPROM designed
to interface directly with the Serial Peripheral Interface
(SPI) port of many of today’s popular microcontroller
families, including Microchip’s PIC16C6X/7X micro-
controllers. It may also interface with microcontrollers
that do not have a built-in SPI port by using discrete
I/O lines programmed properly with the software.
The 25XX64 0 contain s an 8-bit instr uction regist er . The
device is accessed via the SI pin, with data being
clocked in on the ris ing edg e of SCK. Th e C S pin mus t
be low and the HOLD pin must be high for the entire
operation.
Table 3-1 contains a list of the possible instruction
bytes and format for device operation. All instructions,
addresses, and data are transferred MSB first, LSB
last.
Dat a is sampled on the firs t rising edg e of SCK afte r CS
goes low. If the clock line is shared with other
periphe ral devices on the SPI bu s, the us er can assert
the HOLD input and place the 25XX640 in ‘HOLD’
mode. After releasing the HOLD pin, operation will
resume from the point when the HOLD was asserted.
3.2 Read Sequence
The device is selected by pulling CS low. The 8-bit
READ instruction is transmitted to the 25XX640 fol-
lowed by the 16-bit add ress wit h the three MSBs of the
address being “don’t care” bits. After the correct READ
instruc tio n a nd address ar e s en t, t he dat a store d i n th e
memory at the selected address is shifted out on the
SO pin. The data stored in the memory at the next
address can be read sequentially by continuing to pro-
vide cl ock puls es. The inter nal Addr ess Pointe r is auto-
matically incremented to the next higher address after
each byte of data is shifted out. When the highest
address is reached (1FFFh), the address counter rolls
over to address 0000h allowing the read cycle to be
continu ed indefi nitely. The read op eration is terminate d
by raising the CS pin (Figure 3-1).
3.3 Write Sequence
Prior to an y a ttem pt to wri te d at a to the 25XX640 arra y
or STATUS register, the write enable latch must be set
by issuing the WREN instruction (Figure 3-4). This is
done by setting CS low and then clocking out the
proper instruction into the 25XX640. After all eight bits
of the instruction are transmitted, the CS must be
brought high to set the write enable latch. If the write
operation is initiated immediately after the WREN
instruction without CS being brought high, the data will
not be written to the array because the write enable
latch will not have been properly set.
Once the write enable latch is set, the user may
proceed by setting the CS low, issuing a WRITE
instruction, followed by the address, and then the data
to be written. Up to 32 bytes of data can be sent to the
25XX640 before a write cycle is necessary. The only
restriction is that all of the bytes must reside in the
same page. A page address begins with XXX0 0000
and ends with XXX1 1111. If the internal address
counter reaches XXX1 1111 and the clock continues,
the coun ter will roll b ack to the firs t address of the page
and overw rite any da ta in t he page th at may have bee n
written.
For the data to be actually written to the array, the CS
must be brought high a fter the Leas t Significant bit (D0)
of the nth data byte has been clocked in. If CS is
brought high at any other time, the write operation will
not be completed. Refer to Figure 3-2 and Figure 3-3
for more detailed illustrations on the byte write
sequence and the page write sequence, respectively.
While the write is in pro gress, the STA TUS regi ster may
be read to check the status of the WPEN, WIP, WEL,
BP1, and BP0 bits (Figure 3-6). A read attempt of a
memory array location will not be possible during a
write cycle. When the write cycle is completed, the
write enab le latc h is res et.
TABLE 3-1: INSTRUCTION SET
Instruction Name Instruction Format Description
READ 0000 0011 Read data from memory array beginning at selected address
WRITE 0000 0010 Write data to memory array beginning at selected address
WREN 0000 0110 Set the write enable latch (enable write operations)
WRDI 0000 0100 Reset the write enable latch (disable write operations)
RDSR 0000 0101 Read STATUS register
WRSR 0000 0001 Wri te STATUS register
25AA640/25LC640
DS21223H-page 8 © 2008 Microchip Technology Inc.
FIGURE 3-1: REA D SEQUE NCE
FIGURE 3-2: BYTE WRITE SEQUENCE
FIGURE 3-3: PAGE WRITE SEQUENCE
SO
SI
SCK
CS
0 234567891011 21222324252627282930311
0100000115 14 13 12 210
76543210
Instruction 16-bit Address
Data Out
High-Impedance
SO
SI
CS
0000000115 14 13 12 21076543210
Instruction 16-bit Address Data Byte
High-Impedance
Twc
SI
CS
91011 2122232425262728293031
0000000115 14 13 12 21076543210
Instruction 16-bit Address Data Byte 1
SCK 0 23456718
SI
CS
41 42 43 46 47
76543210
Data Byte n (32 max)
SCK 32 34 35 36 37 38 3933 40
76543210
Data Byte 3
76543210
Data Byte 2
44 45
© 2008 Microchip Technology Inc. DS21223H-page 9
25AA640/25LC640
3.4 Wr it e En able (WREN) and
Wr ite Disable (WRDI)
The 25XX640 contains a write enable latch. See
Table 3-3 for the Write-Protect Functionality Matrix.
This latch must be set before any write operation will be
completed internally. The WREN instruction will set the
latch, and the WRDI will reset the latch.
The following is a list of conditions under which the
write enab le latc h wi ll be reset:
• Power-up
•WRDI instruction successfully executed
•WRSR instruction successfully executed
•WRITE instruction successfully executed
FIGURE 3-4: WRITE ENABLE SEQUENCE
FIGURE 3-5: WRITE DISABLE SEQUENCE
SCK
0 2345671
SI
High-Impedance
SO
CS
010000 01
SCK
0 2345671
SI
High-Impedance
SO
CS
010000 01
0
25AA640/25LC640
DS21223H-page 10 © 2008 Microchip Technology Inc.
3.5 Read Status Register Instruction
(RDSR)
The Read Status Register instruction (RDSR) provi des
access to the STATUS register. The STATUS register
may be rea d at any time, ev en during a write cy cle. The
STATUS register is formatted as follows:
The Write-In-Process (WIP) bit indicates whether the
25XX640 is busy with a write operation. When set to a
‘1’, a write is in progress, when set to a ‘0’, no writ e is
in progress. This bit is read-only.
The Write Enable Lat ch (WEL) bit indicat es the st atus
of the write enable latch. When set to a ‘1’, the latch
allows writes to the array and STATUS register, when
set to a ‘0’, the latch prohibits writes to the array and
STATUS register. The state of this bit can always be
updated via the WREN or WRDI comman ds regardles s
of the st a te of wr ite protec ti on on th e STATUS register.
This bit is read-only.
The Block Protection (BP0 and BP1) bits indicate
which blocks are currently write-protected. These bits
are set by th e us er i ssui ng the WRSR in structi on . These
bits are nonvolatile.
See Figure 3-6 for RDSR timing sequence.
FIGURE 3-6: READ STATUS REGISTER TIMING SEQUENCE
7 654 3 2 1 0
WPEN X X X BP1 BP0 WEL WIP
SO
SI
CS
9101112131415
11000000
7654 210
Instruction
Data from STATUS Register
High-Impedance
SCK
0 23456718
3
© 2008 Microchip Technology Inc. DS21223H-page 11
25AA640/25LC640
3.6 Wr ite Status Register Inst ruction
(WRSR)
The W rite S t atus Register inst ruction (WRSR) allows the
user to select one of four levels of protection for the
array by writing to the appropriate bits in the STATUS
register. The array is divided up into four segments.
The user ha s the abili ty to write-p rotect none , one, two,
or all fo ur of the se gment s of th e array. The partitio ning
is controlled as shown in Table 3-2.
The Write-Protect Enable (WPEN) bit is a nonvolatile
bit that is availabl e as an enab le bit for the WP pi n. The
Write-Protect (WP) pin and the Write-Protect Enable
(WPEN) bit in the STATUS register control the pro-
grammable hardware write-protect feature. Hardware
write p rotection is en abl ed w hen the WP pin is low an d
the WPEN bit is high. Hardware write protection is dis-
abled when either the WP pin i s hi gh or th e W PEN bit
is low. When t he chi p is hardware w rite -protected, only
writes to nonvolatile bit s in the STA TUS register are dis-
abled. See Table 3-3 for a ma trix o f fu nc tio nal ity o n th e
WPEN bit.
See Figure 3-7 for WRSR timing sequence.
TABLE 3-2: ARRAY PROTECTION
FIGURE 3-7: WRITE STATUS REGISTER TIMING SEQUENCE
BP1 BP0 Array Addresses
Write-Protected
00 none
01 upper 1/4
(1800h-1FFFh)
10 upper 1/2
(1000h-1FFFh)
11 all
(0000h-1FFFh)
SO
SI
CS
9101112131415
01000000
7654 210
Inst ruction Data to STATUS Reg ister
High-Impedance
SCK
0 23456718
3
25AA640/25LC640
DS21223H-page 12 © 2008 Microchip Technology Inc.
3.7 Data Protection
The following protection has been implemented to
prevent inadvert ent write s to the array:
• The write enable latch is reset on power-up
• A write enable instruction must be issued to set
the write enable latch
• After a byte write, page write, or STATUS register
write, the write enable latch is reset
•CS
must be set high after the proper number of
clock cycles to start an internal write cycle
• Access to the array during an internal write cycle
is ignored and programming is continued
3.8 Power-On-State
The 25XX640 powers on in the following state:
• The device is in low-power Standby mode
(CS =1)
• The write enable latch is reset
• SO is in high-impedance state
• A high-to-low transition on CS is required to enter
the active state
.
TABLE 3-3: WRITE-PROTECT FUNCTIONALITY MATRIX
WPEN WP WEL Protected Blocks Unprotected Blocks STATUS Register
XX 0 Protected Protected Protected
0X 1 Protected Writable Writable
1Low 1Protected Writable Protected
XHigh 1Protected Writable Writable
© 2008 Microchip Technology Inc. DS21223H-page 13
25AA640/25LC640
4.0 PACKAGING INFORMATION
4.1 Package Marking Information
*Standard marking consists of Microchip part number, year code, week code, traceability code (facility
code, mask rev#, and assembly code). For marking beyond this, certain price adders apply. Please
check with your Microchip Sales Office.
XXXXXXXX
XXXXXNNN
YYWW
8-Lead PDIP (300 mil) Example:
8-Lead SOIC (150 mil) Example:
XXXXXXXX
XXXXYYWW
NNN
25LC640
/P017
0410
25LC640
I/SN0410
017
8-Lead TSSOP Example:
XXXX
YYWW
NNN
5LCX
0410
017
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanu meric tracea bil ity code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is P b-free. The Pb- fre e JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the even t the full M icroc hip p art numb er cann ot be mark ed on one line, it w ill
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
25AA640/25LC640
DS21223H-page 14 © 2008 Microchip Technology Inc.
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3&'!&"&4#*!(!!&4%&&#&
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6&! 7,8.
'!9'&! 7 7: ;
7"')%! 7 <
& 1,
&& = =
##44!! -
1!&& = =
"#&"#>#& . - -
##4>#& . <
: 9& -< -?
&& 9 -
9#4!! <
69#>#& ) ?
9*9#>#& ) <
: *+ 1 = = -
N
E1
NOTE 1
D
12
3
A
A1
A2
L
b1
b
e
E
eB
c
* ,<1
© 2008 Microchip Technology Inc. DS21223H-page 15
25AA640/25LC640
! ""#$%& !'
!"#$%&"' ()"&'"!&)&#*&&&#
+%&,&!&
- '!!#.#&"#'#%!&"!!#%!&"!!!&$#''!#
'!#&.0
1,2 1!'!&$& "!**&"&&!
.32 %'!("!"*&"&&(%%'&"!!
3&'!&"&4#*!(!!&4%&&#&
&&255***''54
6&! 99..
'!9'&! 7 7: ;
7"')%! 7 <
& 1,
: 8& = =
##44!! = =
&#%%+ =
: >#& . ?1,
##4>#& . -1,
: 9& 1,
,'%@&A =
3&9& 9 =
3&& 9 .3
3& IB = <B
9#4!! =
9#>#& ) - =
#%& DB = B
#%&1&&' EB = B
D
N
e
E
E1
NOTE 1
12 3
b
A
A1
A2
L
L1
c
h
h
φ
β
α
* ,1
25AA640/25LC640
DS21223H-page 16 © 2008 Microchip Technology Inc.
! ""#$%& !'
3&'!&"&4#*!(!!&4%&&#&
&&255***''54
© 2008 Microchip Technology Inc. DS21223H-page 17
25AA640/25LC640
() )"* ! (+%+( !
!"#$%&"' ()"&'"!&)&#*&&&#
'!!#.#&"#'#%!&"!!#%!&"!!!&$#''!#
- '!#&.0
1,2 1!'!&$& "!**&"&&!
.32 %'!("!"*&"&&(%%'&"!!
3&'!&"&4#*!(!!&4%&&#&
&&255***''54
6&! 99..
'!9'&! 7 7: ;
7"')%! 7 <
& ?1,
: 8& = =
##44!! <
&#%% =
: >#& . ?1,
##4>#& . -
##49& - -
3&9& 9 ?
3&& 9 .3
3& IB = <B
9#4!! =
9#>#& ) = -
D
N
E
E1
NOTE 1
12
b
e
c
A
A1
A2
L1 L
φ
* ,<?1
25AA640/25LC640
DS21223H-page 18 © 2008 Microchip Technology Inc.
APPENDIX A: REVISION HISTORY
Revision F
Corrections to Section 1.0, Electrical Characteristics.
Revision G
Product ID System, Example C: Corrected part
number, added “Alternate Pinout” and corrected part
number in Header.
Updated Trademark and Sales List pages.
Revision H (June 2008)
Added “Not Reco mmended” note; Upda ted Packaging;
General updates.
© 2008 Microchip Technology Inc. DS21223H-page 19
25AA640/25LC640
THE MICROCHIP WEB SITE
Microc hip pro vides onl ine s upport v ia our W WW site at
www.microchi p.c om . Thi s web si te i s us ed as a m ean s
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
•Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
•General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online dis cu ss io n gr oups, Microchip con sultant
program member listing
•Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of sem inar s and events, listings of
Microchip sales offices, distributors and factory
representatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specif ied produ ct family or develo pment tool of interes t.
To register, access the Microchip web site at
www.microchip.com, click on Customer Change
Notification and follow the registration instructions.
CUSTOMER SUPP ORT
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local S ales Office
• Field Application Engineer (FAE)
• Technical Support
• Development Systems Information Line
Customers should contact their distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical s upport is a vailable through the web si te
at: http://support.microchip.com
25AA640/25LC640
DS21223H-page 20 © 2008 Microchip Technology Inc.
READER RESP ONSE
It is ou r intentio n to provide you w it h th e b es t do cument ation po ss ib le to ensure suc c es sfu l u se of y ou r M ic roc hip prod-
uct. If you wi sh to prov ide you r comment s on org aniza tion, clar ity, subj ect matte r , and ways i n which o ur docum entatio n
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
To: Technical Publications Manager
RE: Reader Response Total Pages Sent ________
From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
Application (optional):
Would you like a reply? Y N
Device: Literature Number:
Questions:
FAX: (______) _________ - _________
DS21223H25AA640/25LC640
1. What are the be st fe atur es of this d ocument?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
© 2008 Microchip Technology Inc. DS21223H-page 21
25AA640/25LC640
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. X/XX XXX
PatternPackageTemperature
Range
Device
Device 25AA640: 64K bit 1.8V SPI Serial EEPROM
25AA640T: 64K bit 1.8V SPI Serial EEPROM
(Tape and Reel)
25AA640X: 64K bit 1.8V SPI Serial EEPROM
in alternate pinout (ST only)
25AA640XT: 64K bit 1.8V SPI Serial EEPROM
in alternate pinout Tape and Reel (ST only)
25LC640: 64K bit 2.5V SPI Serial EEPROM
25LC640T: 64K bit 2.5V SPI Serial EEPROM
(Tape and Reel)
25LC640X: 64K bit 2.5V SPI Serial EEPROM
in alternate pinout (ST only)
25LC640XT: 64K bit 2.5V SPI Serial EEPROM
in alternate pinout Tape and Reel (ST only)
Temperature Range I = -40°C to +85°C
E= -40°C to +125°C
Package P = Plastic DIP (300 mil Body), 8-lead
SN = Plastic SOIC (150 mil Body), 8-lead
ST = Plastic TSSOP (4. 4 mm Bo dy), 8-lead
Examples:
a) 25AA640-I/SN: Indust rial Tem p.,
SOIC package
b) 25AA640T -I/ SN: Tape and Reel,
Industrial Temp., SOIC package
c) 25AA640X -I/ST: Alternate Pinout
Industrial Temp ., TSSO P package
d) 25LC640-I/SN: Industrial Temp.,
SOIC package
e) 25LC640T-I/SN: Tape and Reel,
Industrial Temp., SOIC package
f) 25LC640X-I/ST: Alternate Pinout,
Industrial Temp ., TSSO P package
25AA640/25LC640
DS21223H-page 22 © 2008 Microchip Technology Inc.
NOTES:
© 2008 Microchip Technology Inc. DS21223H-page 23
Information contained in this publication regarding device
applications a nd the lik e is pro vid ed only for your c on ve nience
and may be supers eded by u pdates. It is y our res po ns i bil it y to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICST ART, PRO MA TE, rfPIC and SmartShunt are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
FilterLab, Linear Active Thermistor, MXDEV, MXLAB,
SEEV AL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, In-Circuit Serial
Prog ra m ming , IC S P, ICE PI C , M i n di , MiWi, MPASM, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM,
PICDEM.net, PICtail , PIC32 logo, PowerCal, PowerInfo,
PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total
Endurance, UNI/O, WiperLock and ZENA are trademarks of
Microchip Technology I ncorporat ed in the U.S.A. and other
countries.
SQTP is a service mark of Microchip T echnology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2008, Microchip Technology Incorporated, Pr inted in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure famili es of its kind on t he market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is c onstantly evolving. We a t Microc hip are co m mitted to continuously improving the code prot ect ion featur es of our
products. Attempts to break Microchip’ s code protection feature may be a violation of the Digital Millennium Copyright Act. If such act s
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperiph erals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS21223H-page 24 © 2008 Microchip Technology Inc.
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