5962F0151601QYX - Aeroflex Incorporated

Standard Products

UT28F64LV Radiation-Hardened 8K x 8 PROM

Data Sheet

April 2001

FEATURES

qProgrammable, read-only, asynchronous, radiation-

hardened, 8K x 8 memory

-Supported by industry standard programmer

q55ns maximum address access time (-55 oC to

+125 oC)

qThree-state data bus

qLow operating and standby current

-Operating: 50mA maximum @18.2 MHz

•Derating: 1.5mA/MHz

-Standby: 500µA maximum (post-rad)

qRadiation-hardened process and design; total dose

irradiation testing to MIL-STD-883, Method 1019

-Total dose: 1E6 rad(Si)

- LETTH(0.25) ~ 100 MeV-cm2/mg

- SEL Immune >128 MeV-cm2/mg

- Saturated Cross Section cm2 per bit, 1.0E-11

- 1.2E-8 errors/device-day, Adams 90% geosynchronous

heavy ion

-Memory cell LET threshold: >128 MeV-cm2/mg

qQML Q & V compliant part (check factory for

availability)

-AC and DC testing at factory

qPackaging options:

-28-pin 100-mil center DIP (0.600 x 1.4)

-28-lead 50-mil center flatpack (0.490 x 0.74)

qVDD: 3.0 to 3.6volts

q Standard Microcircuit Drawing 5962-01516

PRODUCT DESCRIPTION

The UT28F64LV amorphous silicon anti-fuse PROM is a high

performance, asynchronous, radiation-hardened,

8K x 8 programmable memory device. The UT28F64LV PROM

features fully asychronous operation requiring no external clocks

or timing strobes. An advanced radiation-hardened twin-well

CMOS process technology is used to implement the

UT28F64LV. The combination of radiation- hardness, fast

access time, and low power consumption make the UT28F64LV

ideal for high speed systems designed for operation in radiation

environments.

DECODER MEMORY

ARRAY

SENSE AMPLIFIER

PROGRAMMING

CONTROL

LOGIC DQ(7:0)

A(12:0)

Figure 1. PROM Block Diagram

DEVICE OPERATION

The UT28F64LV has three control inputs: Chip Enable (CE),

Program Enable (PE), and Output Enable (OE); thirteen address

inputs, A(12:0); and eight bidirectional data lines, DQ(7:0). CE

is the device enable input that controls chip selection, active, and

standby modes. Asserting CE causes IDD to rise to its active value

and decodes the thirteen address inputs to select one of 8,192

words in the memory. PE controls program and read operations.

During a read cycle, OE must be asserted to enable the outputs.

PIN NAMES

Table 1. Device Operation Truth Table 1

Notes:

1. “X” is defined as a “don’t care” condition.

2. Device active; outputs disabled.

ABSOLUTE MAXIMUM RATINGS 1

(Referenced to VSS)

Notes:

1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the

device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

2. Test per MIL-STD-883, Method 1012, infinite heat sink.

A12

DQ0

DQ1

DQ2

VSS

VDD

A11

A10

DQ7

DQ6

DQ5

DQ4

DQ3

PIN CONFIGURATION

A(12:0) Address

CE Chip Enable

OE Output Enable

PE Program Enable

DQ(7:0) Data Input/Data Output

OE PE CE I/O MODE MODE

X1 1 Three-state Standby

010 Data Out Read

100 Data In Program

110Three-state Read 2

SYMBOL PARAMETER LIMITS UNITS

VDD DC supply voltage -0.3 to 7.0 V

VI/O Voltage on any pin -0.5 to (VDD + 0.5) V

TSTG Storage temperature -65 to +150 °C

PDMaximum power dissipation 1.5 W

TJMaximum junction temperature +175 °C

ΘJC Thermal resistance, junction-to-case 23.3 °C/W

IIDC input current ±10 mA

RECOMMENDED OPERATING CONDITIONS

DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)*

(VDD = 3.0V to 3.6V; -55°C < TC < +125°C)

Notes:

* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019 at 1.0E6 rads(Si).

1. Measured only for initial qualification, and after process or design changes that could affect input/output capacitance.

2. Supplied as a design limit but not guaranteed or tested.

3. Not more than one output may be shorted at a time for maximum duration of one second.

4. Functional test.

5. Derates at 1.5mA/MHz.

SYMBOL PARAMETER LIMITS UNITS

VDD Positive supply voltage 3.0 to 3.6 V

TCCase temperature range -55 to +125 °C

VIN DC input voltage 0 to VDD V

SYMBOL PARAMETER CONDITION MINIMUM MAXIMUM UNIT

VIH High-level input voltage .7VDD V

VIL Low-level input voltage .25VDD V

VOL1Low-level output voltage IOL = 100µA, VDD = 3.0V VSS + 0.05 V

VOL2Low-level output voltage IOL = 1.0mA, VDD = 3.0V VSS + 0.1 V

VOH1High-level output voltage IOH = -100µA, VDD = 3.0V VDD - 0.15 V

VOH2High-level output voltage IOH = -1.0mA VDD = 3.0V VDD - 0.3 V

CIN 1Input capacitance ƒ = 1MHz, VDD = 3.3V 15 pF

CIO 1, 4 Bidirectional I/O capacitance ƒ = 1MHz, VDD = 3.3V

VOUT = 0V

15 pF

IIN Input leakage current VIN = 0V to VDD -3 3µA

IOZ Three-state output leakage

current VO = 0V to VDD

VDD = 3.6V

OE = 3.6V

-8 8µA

IOS 2,3 Short-circuit output current VDD = 3.6V, VO = VDD

VDD = 3.6V, VO = 0V -90 90 mA

IDD(OP)5Supply current operating

@18.2MHz (55ns product) CMOS input levels (IOUT = 0),

VIL = 0.2V, VIH = 3.0V

VDD, PE = 3.6V

50 mA

IDD(SB)

post-rad Supply current standby CMOS input levels,

VIL = VSS +0.25V

CE = VDD -025, VIH = VDD -0.25V

500 µA

READ CYCLE

A combination of PE greater than VIH(min), and CE less than

VIL(max) defines a read cycle. Read access time is measured

from the latter of device enable, output enable, or valid address

to valid data output.

An address access read is initiated by a change in address inputs

while the chip is enabled with OE asserted and PE deasserted.

Valid data appears on data output, DQ(7:0), after the specified

tAVQV is satisfied. Outputs remain active throughout the entire

cycle. As long as device enable and output enable are active, the

address inputs may change at a rate equal to the minimum read

cycle time.

The chip enable-controlled access is initiated by CE going active

while OE remains asserted, PE remains deasserted, and the

addresses remain stable for the entire cycle. After the specified

tELQV is satisfied, the eight-bit word addressed by A(12:0)

appears at the data outputs DQ(7:0).

Output enable-controlled access is initiated by OE going active

while CE is asserted, PE is deasserted, and the addresses are

stable. Read access time is tGLQV unless tAVQV or tELQV have

not been satisfied.

AC CHARACTERISTICS READ CYCLE (Post-Radiation)*

(VDD = 3.0V to 3.6V; -55°C < TC < +125°C)

Notes:

* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019 at 1.0E6 rads(Si).

1. Functional test.

2. Three-state is defined as a 400mV change from steady-state output voltage.

SYMBOL PARAMETER 28F64-55

MIN MAX UNIT

tAVAV1Read cycle time 55 ns

tAVQV Read access time 55 ns

tAXQX2Output hold time 0ns

tGLQX2OE-controlled output enable time 0ns

tGLQV OE-controlled access time 25 ns

tGHQZ OE-controlled output three-state time 25 ns

tELQX2 CE-controlled output enable time 0ns

tELQV CE-controlled access time 55 ns

tEHQZ CE-controlled output three-state time 25 ns

RADIATION HARDNESS

The UT28F64LV PROM incorporates special design and layout

features which allow operation in high-level radiation

environments. UTMC has developed special low-temperature

processing techniques designed to enhance the total-dose

radiation hardness of both the gate oxide and the field oxide while

maintaining the circuit density and reliability. For transient

radiation hardness and latchup immunity, UTMC builds all

radiation-hardened products on epitaxial wafers using an

advanced twin-tub CMOS process. In addition, UTMC pays

special attention to power and ground distribution during the

design phase, minimizing dose-rate upset caused by rail collapse.

RADIATION HARDNESS DESIGN SPECIFICATIONS 1

Note:

1. The PROM will not latchup during radiation exposure under recommended operating conditions.

Figure 2. PROM Read Cycle

tAVAV

tAVQV

tELQV

tGLQV

tAVQV

tAXQX

tEHQZ

tGHQZ

A(12:0)

DQ(7:0) tGLQX

tELQX

Total Dose 5.0E5 rad(Si)

Latchup LET Threshold >128 MeV-cm2/mg

Memory Cell LET Threshold >128 MeV-cm2/mg

Transient Upset LET Threshold 54 MeV-cm2/mg

Transient Upset Device Cross Section @ LET=128 MeV-cm2/mg 1E-6 cm2

Notes:

1. 50pF including scope probe and test socket.

2. Measurement of data output occurs at the low to high or high to low transition mid-point

(CMOS input = VDD).

90%

Figure 3. AC Test Loads and Input Waveforms

Input

Pulses

10%

< 5ns < 5ns

VDD

200 ohms

VREF=1.04V

50pF

90%

10%

Figure 4. 28-Pin 100-mil Center DIP (0.600 x 1.4)

Notes:

1. Seal ring to be electrically isolated.

2. All exposed metalized areas to be plated per MIL-PRF-38535.

3. Ceramic to be opaque.

4. Dimension letters refer to MIL-STD-1835.

5. Total weight is approximately 5.0 grams.

1.400 ± 0.020

PIN NO. 1 ID.

0.005 MIN.

0.595 ± 0.015 E1

0.600 + 0.020

- 0.010

0.010 +0.002

- 0.001

0.175 MAX.

0.200

0.125

0.100

0.018 ±.002 Q

0.060

0.015

TOP VIEW

SIDE VIEW

END VIEW

0.065

0.045

0.015

0.008

0.015

0.008 PIN NO. 1 ID. 6

26 PLACES

0.050 BSC

0.550 MAX

-B-

(4) PLACES

0.000 MIN.

-D-

-C-

0.115

0.045

0.026 L

0.370

0.250

0.180 MIN E3

0.030 MIN

0.520

0.460

-H-

0.009

0.004

0.040

0.022

0.015 28 PLACES

-A-

HA-B D5SS

0.010 M

HA-B D

SSM

0.036

TOP VIEW

END VIEW

Figure 5. 28-Lead 50-mil Center Flatpack (0.490 x 0.74)

Notes:

1. All exposed metalized areas to be plated per MIL-PRF-38535.

2. The lid is connected to VSS.

3. Lead finishes are in accordance with MIL-PRF-38535.

4. Dimension letters refer to MIL-STD-1835.

5. Lead position and coplanarity are not measured.

6. ID mark symbol is vendor option.

7. With solder, increase maximum by 0.003.

8. Total weight is approximately 2.4 grams.

0.740 MAX

ORDERING INFORMATION

UT28F64LV PROM: SMD

Lead Finish:

(A) = Solder

(X) =Optional

Case Outline:

(X) =28-pin DIP

(Y) =28-lead Flatpack

Class Designator:

(Q) =Class Q

(V) =Class V

Device Type

(01) = 55ns Access Time, CMOS compatible inputs and CMOS compatible outputs

Drawing Number: 01516

Total Dose:

(F) =3E5 rads(Si)

(G) =5E5 rads(Si)

(H) =1E6 rads(Si)

(R) =1E5 rads(Si)

Federal Stock Class Designator: No options

5962 * 01516 * * * *

Notes:

1. Lead finish (A, C, or X) must be specified.

2. If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold).

3. Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening.

4. Lead finish: Factory programming either solder or gold. Field programming gold only.

UT28F64LV PROM

UT **** *** - * * * * * *

Total Dose:

( ) =None

Lead Finish:

(A) =Solder

(X) =Optional

Screening:

(P) =Prototype

Package Type:

(P) =28-lead DIP

(U) =28-lead Flatpack

Access Time:

(55) = 55ns access time

Device Type Modifier:

Device Type:

(28F64LV) = 3.3V, 8Kx8 One Time Programmable PROM

Notes:

1. Lead finish (A,C, or X) must be specified.

2. If an “X” is specified when ordering, then the part marking will match the lead finish and will be either “A” (solder) or “C” (gold).

3. Military Temperature Range flow per UTMC Manufacturing Flows Document. Radiation characteristics are neither tested nor guaranteed and may not

be specified.

4. Prototype flow per UTMC Manufacturing Flows Document. Devices have prototype assembly and are tested at 25°C only. Radiation characteristics

are neither tested nor guaranteed and may not be specified.

5. Lead finish: Factory programming either solder or gold. Field programming gold only.

Notes