Freescale Semiconductor
Data Sheet: Advance Information Document Number: MCF54455
Rev. 8, 02/2012
© Freescale Semiconductor, Inc., 2007-2012. All rights reserved.
This document contains information on a new product. Specifications and information herein
are subject to change without notice.
MCF54455
MAPBGA–256
17mm x 17mm TEPBGA–360
23mm x 23mm
Features
• Version 4 ColdFire Core with MMU and EMAC
• Up to 410 Dhrystone 2.1 MIPS @ 266 MHz
• 16-KBytes instruction cache and 16-KBytes data cache
• 32-KBytes internal SRAM
• Support for booting from SPI-compatible flash, EEPROM,
and FRAM devices
• Crossbar switch technology (XBS) for concurrent access to
peripherals or RAM from multiple bus masters
• 16-channel DMA controller
• 16-bit 133-MHz DDR/mobile-DDR/DDR2 controller
• USB 2.0 On-the-Go controller with ULPI su pport
• 32-bit PCI controller @ 66MHz
• ATA/ATAPI controller
• 2 10/100 Ethernet MACs
• Coprocessor for acceleration of the DES, 3DES, AES,
MD5, and SHA-1 algorithms
• Random number generator
• Synchronous serial interface (SSI)
• 4 periodic interrupt timers (PIT)
• 4 32-bit timers with DMA support
• DMA-supported serial peripheral interface (DSPI)
• 3 UARTs
•I
2C bus interface
MCF5445x ColdFire
Microprocessor Data Sheet
MCF5445x ColdFire Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor2
Table of Contents
1 MCF5445x Family Comparison . . . . . . . . . . . . . . . . . . . . . . . .4
2 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3 Hardware Design Considerations. . . . . . . . . . . . . . . . . . . . . . .5
3.1 Analog Power Filtering . . . . . . . . . . . . . . . . . . . . . . . . . .5
3.2 Oscillator Power Filtering . . . . . . . . . . . . . . . . . . . . . . . .6
3.3 Supply Voltage Sequencing . . . . . . . . . . . . . . . . . . . . . .6
3.3.1 Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . .7
3.3.2 Power-Down Sequence. . . . . . . . . . . . . . . . . . . .7
4 Pin Assignments and Reset States . . . . . . . . . . . . . . . . . . . . .7
4.1 Signal Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
4.2 Pinout—256 MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . .15
4.3 Pinout—360 TEPBGA. . . . . . . . . . . . . . . . . . . . . . . . . .16
5 Electrical Characteri stics . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
5.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . .17
5.2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .18
5.3 ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
5.4 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . .19
5.5 ClockTiming Specifications. . . . . . . . . . . . . . . . . . . . . .20
5.6 Reset Timing Specifications . . . . . . . . . . . . . . . . . . . . .22
5.7 FlexBus Timing Specifications . . . . . . . . . . . . . . . . . . .23
5.8 SDRAM AC Timing Characteristics. . . . . . . . . . . . . . . .25
5.9 PCI Bus Timing Specifications . . . . . . . . . . . . . . . . . . .27
5.9.1 Overshoot and Undershoot . . . . . . . . . . . . . . . 28
5.10 ULPI Timing Specifications . . . . . . . . . . . . . . . . . . . . . 29
5.11 SSI Timing Specifications . . . . . . . . . . . . . . . . . . . . . . 30
5.12 I2C Timing Specifications . . . . . . . . . . . . . . . . . . . . . . 32
5.13 Fast Ethernet Timing Specifications . . . . . . . . . . . . . . 33
5.13.1 Receive Signal Timing Specifications . . . . . . . 33
5.13.2 Transmit Signal Timing Specifications . . . . . . . 34
5.13.3 Asynchronous Input Signal Timing
Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.13.4 MII Serial Management Timing Specifications. 35
5.14 32-Bit Timer Module Timing Specifications . . . . . . . . . 35
5.15 ATA Interface Timing Specifications. . . . . . . . . . . . . . . 36
5.16 DSPI Timing Specifications. . . . . . . . . . . . . . . . . . . . . 36
5.17 SBF Timing Specifications. . . . . . . . . . . . . . . . . . . . . . 38
5.18 General Purpose I/O Timing Specifications. . . . . . . . . 39
5.19 JTAG and Boundary Scan Timing . . . . . . . . . . . . . . . . 40
5.20 Debug AC Timing Specifications. . . . . . . . . . . . . . . . . 42
6 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8 Product Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
MCF5445x ColdFire Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor 3
Figure 1. MCF54455 Block Diagram
Version 4 ColdFire Core
LEGEND
2 INTCs
DSPI
EPORT
3 UARTs
I2C
Watchdog
4 DMA
RTC
ATA – Advanced Technology Attachment Controller
BDM – Background debug module
CAU – Cryptography acceleration unit
DSPI – DMA serial peripheral interface
eDMA – Enhanced direct memory access
EMAC – Enchance multiply-accumulate unit
EPORT – Edge port module
FEC – Fast Ethernet controller
GPIO – General Purpose Input/Output
I2C– Inter-Intergrated Circuit
INTC – Interrupt controller
JTAG – Joint Test Action Group interface
MMU – Memory management unit
PCI – Peripheral Component Interconnect
PIT – Programmable interrupt timers
PLL – Phase locked loop module
RNG – Random Number Generator
RTC – Real time clock
SSI – Synchronous Serial Interface
USB OTG – Universal Serial Bus On-the-Go controller
MCF54455
EMAC 2 FECs
Crossbar Switch (XBS)
32K
SRAM
Peripheral Bridge
CAU
16K
Instruction
Cache
16K
Data
Cache
Timers
BDM
ATA SDRAM
Controller FlexBus
eDMA
USB OT G
4 PITs
SSI RNG GPIO
MMU
Hardware
Divide
Oscillator PLLJTAG
PCI Serial Boot
MCF5445x ColdFire Microprocessor Data Sheet, Rev. 8
MCF5445x Family Comparison
Freescale Semiconductor4
1 MCF5445x Family Comparison
The following table compares the various device derivatives avail able wit hin the MCF5445x family.
Table 1. MCF5445x Family Configurations
Module MCF54450 MCF54451 MCF54452 MCF54453 MCF54454 MCF54455
ColdFire Version 4 Core with EMAC
(Enhanced Multiply-Accumulate Unit) ••••••
Core (System) Clock up to 240 MHz up to 266 MHz
Peripheral Bus Clock
(Core clock 2) up to 120 MHz up to 133 MHz
External Bus Clock
(Core clock 4) up to 60 MHz up to 66 MHz
Performance (Dhrystone/2.1 MIPS) up to 370 up to 410
Independent Data/Instruction Cache 16 Kbytes each
Static RAM (SRAM) 32 Kbytes
PCI Controller ——••••
Cryptography Acceleration Unit (CAU) — • — • — •
ATA Controller ———— • •
DDR SDRAM Controller ••••••
FlexBus External Interface ••••••
USB 2.0 On-the-Go ••••••
UTMI+ Low Pin Interface (ULPI) ••••••
Synchronous Serial Interface (SSI) ••••••
Fast Ethernet Controller (FEC) 112222
UARTs 333333
I2C ••••••
DSPI ••••••
Real Time Clock ••••••
32-bit DMA Timers 444444
Watchdog Timer (WDT) ••••••
Periodic Interrupt Timers (PIT) 444444
Edge Po rt Module (EPORT) ••••••
Interrupt Controllers (INTC) 222222
16-channel Direct Memory Access (DMA)••••••
General Purpose I/O (GPIO) ••••••
JTAG - IEEE® 1149.1 Test Access Port ••••••
Package 256 MAPBGA 360 TEPBGA
Ordering Information
MCF5445x ColdFire Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor 5
2 Ordering Information
3 Hardware Design Considerations
3.1 Analog Power Filtering
To further enhance noise isolati on, an extern al filter is strongly recommended for the analog VDD pins (VDD_A_PLL,
VDD_RTC). The filter shown in Figure 2 should be connected between the board IVDD and the analog pins. The resistor and
capacitors should be placed as close to the dedicated analog VDD pin as possible. The 10- resistor in the given filter is required.
Do not implement the filter ci rcuit using only capacitors. The analog power pins draw very little current . Concerns regarding
voltage loss across the 10-ohm resistor are not valid.
Figure 2. System Analog VDD Power Filter
Table 2. Orderable Part Numbers
Freescale Part
Number Description Package Speed Temperature
MCF54450CVM180 MCF54450 Microprocessor
256 MAPBGA
180 MHz –40 to +85 C
MCF54450VM24 0 240 MHz 0 to +70 C
MCF54451CVM180 MCF54451 Microprocessor 180 MHz –40 to +85 C
MCF54451VM24 0 240 MHz 0 to +70 C
MCF54452CVR200
MCF54452 Microprocessor
360 TEPBGA
200 MHz –40 to +85 C
MCF54452YVR200 200 MHz –40 to +105 C
MCF54452VR266 266 MHz 0 to +70 C
MCF54453CVR200 MCF54453 Microprocesso r 200 MHz –40 to +85 C
MCF54453VR266 266 MHz 0 to +70 C
MCF54454CVR200 MCF54454 Microprocesso r 200 MHz –40 to +85 C
MCF54454VR266 266 MHz 0 to +70 C
MCF54455CVR200 MCF54455 Microprocesso r 200 MHz –40 to +85 C
MCF54455VR266 266 MHz 0 to +70 C
Board IVDD 10
0.1 µF
Analog VDD Pin
10 µF
GND
MCF5445x ColdFire Microprocessor Data Sheet, Rev. 8
Hardware Design Considerations
Freescale Semiconductor6
3.2 Oscillator Power Filtering
Figure 3 shows an example for isolating the oscillator power supply from th e I/O supply (EVD D) and ground.
Figure 3. Oscillator Power Filter
3.3 Supply Voltage Sequencing
Figure 4 shows situations in sequencing th e I/O VDD (EVDD), SDRAM VDD (SDVDD), PLL VDD (PVDD), and internal
logic/core VDD (IVDD).
Figure 4. Supply Voltage Sequencing and Separation Cautions
The relationship between SDVDD and EVDD is non-critical during power-up and power-down sequences. SDVDD (2.5 V or
1.8V) and EVDD are specified relative to IVDD.
VDD_OSC 10
0.1 µF
EVDD Pin
1 µF
GND
VSS_OSC 100 MHz
EVDD (3.3V)
IVDD, PVDD
Time
3.3V
1.5V
0
DC Power Supply Voltage
Notes:
1Input voltage must not be greater than the supply voltage (EVDD, SD VDD, IVDD, or PVDD) b y more than 0.5V
at any time, including during power-up.
2Use 50 V/millisecond or slower rise time for all supplies.
2.5V
Supplies Stable
SDVDD (2.5V — DDR)
1.8V SDVDD (1.8V — DDR2)
Pin Assignments and Res et States
MCF5445x ColdFire Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor 7
3.3.1 Power-Up Sequence
If EVDD/SDVDD are powered up with the IVDD at 0 V, the sense circuits in the I/O pads cause all pad output drivers connected
to the EVDD/SDVDD to be in a high impedance state. There is no limit on how long after EVDD/SDVDD powers up before IVDD
must power up. The rise times on the power supp lies shoul d be slower than 50 V/millisecond to avo id turnin g on the internal
ESD protection clamp diodes.
3.3.2 Power-Down Sequence
If IVDD/PVDD are powered down first, sense circuits in the I/O pads cause all output drivers to be in a high impedance state.
There is no limit on how long after IVDD and PVDD power down before EVDD or SDVDD must power down. There are no
requirements for the fall times of the power supplies.
4 Pin Assignments and Reset States
4.1 Signal Multiplexing
The following table lists all the MCF5445x pins grouped by function. The Dir column is the direction for the primary function
of the pin only. Refer to Section 4, “Pin Assignments and Reset States,” for package diagrams . For a more detailed discussion
of the MCF5445x signals, consult the MCF54455 Refer ence Manual (MCF54455RM).
NOTE
In this table and throughout this document, a single signal within a group is designat ed
without square brackets (i.e., FB_AD23), while designations for multiple signals within a
group use brackets (i.e., FB_AD[23:21]) and is meant to include all signals within the two
bracketed numbers when these numbers are separated by a colon.
NOTE
The primary functionality of a pin is not necessarily its default functionality . Most pins that
are muxed with GPIO default to their GPIO functionali ty. See Table 3 for a list of the
exceptions.
Table 3. Special-Case Default Signal Functionality
Pin 256 MAPBGA 360 TEPBGA
FB_AD[31:0] FB_AD[31:0] except when serial boot selects 0-bit
boot port size.
FB_BE/BWE[3:0] FB_BE/BWE[3:0]
FB_CS[3:1] FB_CS[3:1]
FB_OE FB_OE
FB_R/W FB_R/W
FB_TA FB_TA
FB_TS FB_TS
MCF5445x ColdFire Microprocessor Data Sheet, Rev. 8
Pin Assignments and Reset States
Freescale Semiconductor8
PCI_GNT[3:0] GPIO PCI_GNT[3:0]
PCI_REQ[3:0] GPIO PCI_REQ[3:0]
IRQ1 GPIO PCI_INTA and
configured as an agent.
ATA_RESET GPIO ATA reset
Table 4. MCF5445x Signal Information and Muxing
Signal Name GPIO Alternate 1 Alternate 2
Pull-up (U)1
Pull-down (D)
Direction2
Voltage Domain
MCF54450
MCF54451
256 MAPBGA
MCF54452
MCF54453
MCF54454
MCF54455
360 TEPBGA
Reset
RESET — — — U IEVDD L4 Y18
RSTOUT — — — — OEVDD M15 B17
Clock
EXTAL/PCI_CLK — — — — IEVDD M16 A16
XTAL — — — U3OEVDD L16 A17
Mode Selection
BOOTMOD[1:0] — — — — IEVDD M5, M7 AB17, AB21
FlexBus
FB_AD[31:24] PFBADH[7:0]4FB_D[31:24] — —I/O EVDD A14, A13, D12,
C12, B12, A12,
D11, C11
J2, K4, J1, K1–3,
L1, L4
FB_AD[23:16] PFBADMH[7:0]4FB_D[23:16] — —I/O EVDD B11, A11, D10,
C10, B10, A10, D9,
C9
L2, L3, M1 –4 ,
N1–2
FB_AD[15:8] PFBADML[7:0]4FB_D[15:8] — —I/O EVDD B9, A9, D8, C8, B8,
A8, D7, C7 P1–2, R1–3, P4,
T1–2
FB_AD[7:0] PFBADL[7:0]4FB_D[7:0] — —I/O EVDD B7, A7, D6, C6, B6,
A6, D5, C5 T3–4, U1–3, V1–2,
W1
FB_BE/BWE[3:2] PBE[3:2] FB_TSIZ[1:0] — —OEVDD B5, A5 Y1, W2
FB_BE/BWE[1:0] PBE[1:0] — — — OEVDD B4, A4 W3, Y2
FB_CLK — — — —OEVDD B13 J3
FB_CS[3:1] PCS[3:1] — — —OEVDD C2, D4, C3 W5, AA4, AB3
FB_CS0 —— ——OEVDD C4 Y4
FB_OE PFBCTL3 — — —OEVDD A2 AA1
FB_R/W PFBCTL2 — — — OEVDD B2 AA3
FB_TA PFBCTL1 — — U IEVDD B1 AB2
Table 3. Special-Case Default Signal Functionality (continued)
Pin 256 MAPBGA 360 TEPBGA
Pin Assignments and Res et States
MCF5445x ColdFire Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor 9
FB_TS PFBCTL0 FB_ALE FB_TBST —OEVDD A3 Y3
PCI Controller5
PCI_AD[31:0] — FB_A[31:0] — —I/O EVDD — C11, D11, A10,
B10, J4, G2, G3,
F1, D12, C12, B12,
A11, B11, B9, D9,
D10, A8, B8, A5,
B5, A4, A3, B3, D4,
D3, E3–E1, F3, C2,
D2, C1
— — FB_A[23:0] — —I/O EVDD K14–13, J15–13,
H13–15, G15–13,
F14–13, E15–13,
D16, B16, C15,
B15, C14, D15,
C16, D14
—
PCI_CBE[3:0] — — — —I/O EVDD — G4, E4, D1, B1
PCI_DEVSEL —— ——OEVDD — F2
PCI_FRAME —— ——I/O EVDD — B2
PCI_GNT3 PPCI7 ATA_DMACK — — OEVDD — B7
PCI_GNT[2:1] PPCI[6:5] — — —OEVDD — C8, C9
PCI_GNT0/
PCI_EXTREQ PPCI4 — — —OEVDD — A9
PCI_IDSEL — — — —IEVDD — D5
PCI_IRDY —— ——I/O EVDD — C3
PCI_PAR — — — —I/O EVDD — C4
PCI_PERR —— ——I/O EVDD — B4
PCI_REQ3 PPCI3 ATA_INTRQ — —IEVDD — C7
PCI_REQ[2:1] PPCI[2:1] — — —IEVDD — D7, C5
PCI_REQ0/
PCI_EXTGNT PPCI0 — — —IEVDD — A2
PCI_RST —— ——OEVDD — B6
PCI_SERR —— ——I/O EVDD — A6
PCI_STOP —— ——I/O EVDD — A7
PCI_TRDY —— ——I/O EVDD — C10
SDRAM Controller
SD_A[13:0] — — — —OSDVDD R1, P1, N2, P2 ,
R2, T2, M4, N3,
P3, R3, T3, T4, R4,
N4
V22, U20–22,
T19–22, R20–22,
N19, P20–21
Table 4. MCF5445x Signal Information and Muxing (continued)
Signal Name GPIO Alternate 1 Alternate 2
Pull-up (U)1
Pull-down (D)
Direction2
Voltage Domain
MCF54450
MCF54451
256 MAPBGA
MCF54452
MCF54453
MCF54454
MCF54455
360 TEPBGA
MCF5445x ColdFire Microprocessor Data Sheet, Rev. 8
Pin Assignments and Reset States
Freescale Semiconductor10
SD_BA[1:0] — — — —OSDVDD P4, T5 P22, P19
SD_CAS —— ——OSDVDD T6 L19
SD_CKE — — — —OSDVDD N5 N22
SD_CLK — — — —OSDVDD T9 L22
SD_CLK —— ——OSDVDD T8 M22
SD_CS[1:0] — — — —OSDVDD P6, R6 L20, M20
SD_D[31:16] — — — —I/O SDVDD N6, T7, N7, P7, R7,
R8, P8, N8, N9,
T10, R1 0, P10,
N10, T11, R11,
P11
L21, K22, K21,
K20, J20, J19, J21,
J22, H20, G22,
G21, G20, G19,
F22, F21, F20
SD_DM[3:2] — — — —OSDVDD P9, N12 H21, E21
SD_DQS[3:2] — — — —OSDVDD R9, N11 H22, E22
SD_RAS —— ——OSDVDD P5 N21
SD_VREF — — — —ISDVDD M8 M21
SD_WE —— ——OSDVDD R5 N20
External Interrupts Port6
IRQ7 PIRQ7 — — — IEVDD L1 ABB13
IRQ4 PIRQ4 —SSI_CLKIN —IEVDD L2 ABB13
IRQ3 PIRQ3 — — — IEVDD L3 AB14
IRQ1 PIRQ1 PCI_INTA — — IEVDD F15 C6
FEC0
FEC0_MDC PFECI2C3 — — — OEVDD F3 AB8
FEC0_MDIO PFECI2C2 — — — I/O EVDD F2 Y7
FEC0_COL PFEC0H4 —ULPI_DATA7 —IEVDD E1 AB7
FEC0_CRS PFEC0H0 —ULPI_DATA6 —IEVDD F1 AA7
FEC0_RXCLK PFEC0H3 —ULPI_DATA1 —IEVDD G1 AA8
FEC0_RXDV PFEC0H2 FEC0_RMII_
CRS_DV — — IEVDD G2 Y8
FEC0_RXD[3:2] PFEC0L[3:2] —ULPI_DATA[5:4] —IEVDD G3, G4 AB9, Y9
FEC0_RXD1 PFEC0L1 FEC0_RMII_RXD1 — — IEVDD H1 W9
FEC0_RXD0 PFEC0H1 FEC0_RMII_RXD0 — — IEVDD H2 AB10
FEC0_RXER PFEC0L0 FEC0_RMII_RXER — — IEVDD H3 AA10
Table 4. MCF5445x Signal Information and Muxing (continued)
Signal Name GPIO Alternate 1 Alternate 2
Pull-up (U)1
Pull-down (D)
Direction2
Voltage Domain
MCF54450
MCF54451
256 MAPBGA
MCF54452
MCF54453
MCF54454
MCF54455
360 TEPBGA
Pin Assignments and Res et States
MCF5445x ColdFire Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor 11
FEC0_TXCLK PFEC0H7 FEC0_RMII_
REF_CLK — — IEVDD H4 Y10
FEC0_TXD[3:2] PFEC0L[7:6] —ULPI_DATA[3:2] —OEVDD J1, J2 W10, AB11
FEC0_TXD1 PFEC0L5 FEC0_RMII_TXD1 — — OEVDD J3 AA11
FEC0_TXD0 PFEC0H5 FEC0_RMII_TXD0 — — OEVDD J4 Y11
FEC0_TXEN PFEC0H6 FEC0_RMII_TXEN — — OEVDD K1 W11
FEC0_TXER PFEC0L4 —ULPI_DATA0 —OEVDD K2 AB12
FEC1
FEC1_MDC PFECI2C5 —ATA_DIOR —OEVDD —W20
FEC1_MDIO PFECI2C4 —ATA_DIOW —I/O EVDD —Y22
FEC1_COL PFEC1H4 —ATA_DATA7 —IEVDD —AB18
FEC1_CRS PFEC1H0 —ATA_DATA6 —IEVDD —AA18
FEC1_RXCLK PFEC1H3 —ATA_DATA5 —IEVDD —W14
FEC1_RXDV PFEC1H2 FEC1_RMII_
CRS_DV ATA_DATA15 —IEVDD —AB15
FEC1_RXD[3:2] PFEC1L[3:2] —ATA_DATA[4:3] —IEVDD —AA15, Y15
FEC1_RXD1 PFEC1L1 FEC1_RMII_RXD1 ATA_DATA14 —IEVDD —AA17
FEC1_RXD0 PFEC1H1 FEC1_RMII_RXD0 ATA_DATA13 —IEVDD —Y17
FEC1_RXER PFEC1L0 FEC1_RMII_RXER ATA_DATA12 —IEVDD —W17
FEC1_TXCLK PFEC1H7 FEC1_RMII_
REF_CLK ATA_DATA11 —IEVDD —AB19
FEC1_TXD[3:2] PFEC1L[7:6] —ATA_DATA[2:1] —OEVDD —Y19, W18
FEC1_TXD1 PFEC1L5 FEC1_RMII_TXD1 ATA_DATA10 —OEVDD —AA19
FEC1_TXD0 PFEC1H5 FEC1_RMII_TXD0 ATA_DATA9 —OEVDD —Y20
FEC1_TXEN PFEC1H6 FEC1_RMII_TXEN ATA_DATA8 —OEVDD —AA21
FEC1_TXER PFEC1L4 —ATA_DATA0 —OEVDD —AA22
USB On-the-Go
USB_DM — — — — OUSB
VDD F16 A14
USB_DP — — — — OUSB
VDD E16 A15
USB_VBUS_EN PUSB1 USB_PULLUP ULPI_NXT —OUSB
VDD E5 AA2
USB_VBUS_OC PUSB0 —ULPI_STP UD7IUSB
VDD B3 V4
Table 4. MCF5445x Signal Information and Muxing (continued)
Signal Name GPIO Alternate 1 Alternate 2
Pull-up (U)1
Pull-down (D)
Direction2
Voltage Domain
MCF54450
MCF54451
256 MAPBGA
MCF54452
MCF54453
MCF54454
MCF54455
360 TEPBGA
MCF5445x ColdFire Microprocessor Data Sheet, Rev. 8
Pin Assignments and Reset States
Freescale Semiconductor12
ATA
ATA_BUFFER_EN PATAH5 — — — OEVDD —Y13
ATA_CS[1:0] PATAH[4:3] — — — OEVDD —W21, W22
ATA_DA[2:0] PATAH[2:0] — — — OEVDD —V19–21
ATA_RESET PATAL2 — — — OEVDD —W13
ATA_DMARQ PATAL1 — — — IEVDD —AA14
ATA_IORDY PATAL0 — — — IEVDD —Y14
Real Time Clock
EXTAL32K — — — — IEVDD J16 A13
XTAL32K — — — — OEVDD H16 A12
SSI
SSI_MCLK PSSI4 — — — OEVDD T13 D20
SSI_BCLK PSSI3 U1CTS — — I/O EVDD R13 E19
SSI_FS PSSI2 U1RTS — — I/O EVDD P12 E20
SSI_RXD PSSI1 U1RXD —UD IEVDD T12 D21
SSI_TXD PSSI0 U1TXD —UD OEVDD R12 D22
I2C
I2C_SCL PFECI2C1 —U2TXD UI/O EVDD K3 AA12
I2C_SDA PFECI2C0 —U2RXD UI/O EVDD K4 Y12
DMA
DACK1 PDMA3 —ULPI_DIR —OEVDD M14 C17
DREQ1 PDMA2 —USB_CLKIN UIEVDD P16 C18
DACK0 PDMA1 DSPI_PCS3 — — OEVDD N15 A18
DREQ0 PDMA0 — — U IEVDD N16 B18
DSPI
DSPI_PCS5/PCSS PDSPI6 — — — OEVDD N14 D18
DSPI_PCS2 PDSPI5 — — — OEVDD L13 A19
DSPI_PCS1 PDSPI4 SBF_CS — — OEVDD P14 B20
DSPI_PCS0/SS PDSPI3 — — U I/O EVDD R16 D17
DSPI_SCK PDSPI2 SBF_CK — — I/O EVDD R15 A20
Table 4. MCF5445x Signal Information and Muxing (continued)
Signal Name GPIO Alternate 1 Alternate 2
Pull-up (U)1
Pull-down (D)
Direction2
Voltage Domain
MCF54450
MCF54451
256 MAPBGA
MCF54452
MCF54453
MCF54454
MCF54455
360 TEPBGA
Pin Assignments and Res et States
MCF5445x ColdFire Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor 13
DSPI_SIN PDSPI1 SBF_DI —8IEVDD P15 B19
DSPI_SOUT PDSPI0 SBF_DO — — OEVDD N13 C20
UARTs
U1CTS PUART7 — — — IEVDD —V3
U1RTS PUART6 — — — OEVDD —U4
U1RXD PUART5 — — — IEVDD —P3
U1TXD PUART4 — — — OEVDD —N3
U0CTS PUART3 — — — IEVDD M3 Y16
U0RTS PUART2 — — — OEVDD M2 AA16
U0RXD PUART1 — — — IEVDD N1 AB16
U0TXD PUART0 — — — OEVDD M1 W15
Note: The UART1 and UART 2 signals are multiplexed on the DMA timers and I2C pins.
DMA Timers
DT3IN PTIMER3 DT3OUT U2RXD —IEVDD C13 H2
DT2IN PTIMER2 DT2OUT U2TXD —IEVDD D13 H1
DT1IN PTIMER1 DT1OUT U2CTS —IEVDD B14 H3
DT0IN PTIMER0 DT0OUT U2RTS —IEVDD A15 G1
BDM/JTAG9
PSTDDATA[7:0] — — — — OEVDD E2, D1, F4, E3, D2,
C1, E4, D3 AA6, AB6, AB5,
W6, Y6, AA5, AB 4,
Y5
JTAG_EN — — — D IEVDD M11 C21
PSTCLK —TCLK — — IEVDD P13 C22
DSI —TDI — U IEVDD T15 C19
DSO —TDO — — OEVDD T14 A21
BKPT —TMS — U IEVDD R14 B21
DSCLK —TRST — U IEVDD M13 B22
Test
TEST — — — D IEVDD M6 AB20
PLLTEST — — — — OEVDD K16 D15
Table 4. MCF5445x Signal Information and Muxing (continued)
Signal Name GPIO Alternate 1 Alternate 2
Pull-up (U)1
Pull-down (D)
Direction2
Voltage Domain
MCF54450
MCF54451
256 MAPBGA
MCF54452
MCF54453
MCF54454
MCF54455
360 TEPBGA
MCF5445x ColdFire Microprocessor Data Sheet, Rev. 8
Pin Assignments and Reset States
Freescale Semiconductor14
Power Supplies
IVDD — — — — — — E6–12, F5, F12 D6, D8, D14, F4,
H4, N4, R4, W4,
W7, W8, W12,
W16, W19
EVDD — — — — — — G5, G12, H5, H12,
J5, J12, K5, K1 2,
L5–6, L12
D13, D19, G8,
G11, G14, G16, J7,
J16, L7, L16, N1 6,
P7, R16, T8, T12,
T14, T16
SD_VDD — — — — — — L7–11, M9, M10 F19, H19, K19,
M19, R19, U19
VDD_OSC — — — — — — L14 B16
VDD_A_PLL — — — — — — K15 C14
VDD_RTC — — — — — — M12 C13
VSS — — — — — — A1, A16, F6–11,
G6–11, H6–11,
J6–11, K6–11, T1,
T16
A1, A22, B14, G7,
G9–10, G12–13,
G15, H7, H16,
J9–14, K7, K9–14,
K16, L9–14, M7,
M9–M14, M16, N7,
N9–14, P9–14,
P16, R7, T7,
T9–11, T13, T15,
AB1, AB22
VSS_OSC — — — — — — L15 C16
1Pull-ups are generally only enabled on pins with their primary function, except as noted.
2Refers to pin’s primary function.
3Enabled only in oscillator bypass mode (internal crystal oscillator is disabled).
4Serial bo ot must select 0-bit boot port size to enable the GPIO mode on these pins.
5When the PCI is enabled, all PCI b us pins come up configured as such. This includes the PCI_GNT and PCI_REQ lines, which hav e
GPIO. The IRQ1/PCI_INTA signal is a special case. It comes up as PCI_INTA when booting as a PCI agent and as GPIO when booting
as a PCI host.
For the 360 TEPBGA, booting with PCI disabled results in all dedicated PCI pins being safe-stated. The PCI_GNT and PCI_REQ lines
and IRQ1/PCI_INTA come up as GPIO.
6GPIO functionality is determined by the edge port module. The pin multiple xing and control module is only responsible for assigning
the alternate functions.
7Depends on programmed polarity of the USB_VBUS_OC signal.
8Pull-up when the serial boot facility (SBF) controls the pin
9If JTAG_EN is asserted, these pins default to Alternate 1 (JTAG) functionality. The pin multiplexing and control module is not
responsible for assigning these pins.
Table 4. MCF5445x Signal Information and Muxing (continued)
Signal Name GPIO Alternate 1 Alternate 2
Pull-up (U)1
Pull-down (D)
Direction2
Voltage Domain
MCF54450
MCF54451
256 MAPBGA
MCF54452
MCF54453
MCF54454
MCF54455
360 TEPBGA
Pin Assignments and Res et States
MCF5445x ColdFire Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor 15
4.2 Pinout—256 MAPBGA
The pinout for the MCF54450 and MCF54451 packages are shown below.
Figure 5. MCF54450 and MCF54451 Pinout (256 MAPBGA)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
AVSS FB_OE FB_TS FB_BE/
BWE0 FB_BE/
BWE2 FB_AD
2FB_AD
6FB_AD
10 FB_AD
14 FB_AD
18 FB_AD
22 FB_AD
26 FB_AD
30 FB_AD
31 T0IN VSS A
BFB_TA FB_R/W USB_
VBUS_
OC
FB_BE/
BWE1 FB_BE/
BWE3 FB_AD
3FB_AD
7FB_AD
11 FB_AD
15 FB_AD
19 FB_AD
23 FB_AD
27 FB_CLK T1IN FB_A
4FB_A
6B
CPST
DDATA2 FB_CS3 FB_CS1 FB_CS0 FB_AD
0FB_AD
4FB_AD
8FB_AD
12 FB_AD
16 FB_AD
20 FB_AD
24 FB_AD
28 T3IN FB_A
3FB_A
5FB_A
1C
DPST
DDATA6 PST
DDATA3 PST
DDATA0 FB_CS2 FB_AD
1FB_AD
5FB_AD
9FB_AD
13 FB_AD
17 FB_AD
21 FB_AD
25 FB_AD
29 T2IN FB_A
0FB_A
2FB_A
7D
EFEC0_
COL PST
DDATA7 PST
DDATA4 PST
DDATA1
USB_
VBUS_
EN IVDD IVDD IVDD IVDD IVDD IVDD IVDD FB_A
8FB_A
9FB_A
10 USB_
DP E
FFEC0_
CRS FEC0_
MDIO FEC0_
MDC PST
DDATA5 IVDD VSS VSS VSS VSS VSS VSS IVDD FB_A
11 FB_A
12 IRQ_1 USB_
DM F
GFEC0_
RXCLK FEC0_
RXDV FEC0_
RXD3 FEC0_
RXD2 EVDD VSS VSS VSS VSS VSS VSS EVDD FB_A
13 FB_A
14 FB_A
15 NC G
HFEC0_
RXD1 FEC0_
RXD0 FEC0_
RXER FEC0_
TXCLK EVDD VSS VSS VSS VSS VSS VSS EVDD FB_A
18 FB_A
17 FB_A
16 XTAL
32K H
JFEC0_
TXD3 FEC0_
TXD2 FEC0_
TXD1 FEC0_
TXD0 EVDD VSS VSS VSS VSS VSS VSS EVDD FB_A
19 FB_A
20 FB_A
21 EXTAL
32K J
KFEC0_
TXEN FEC0_
TXER I2C_
SCL I2C_
SDA EVDD VSS VSS VSS VSS VSS VSS EVDD FB_A
22 FB_A
23 VDD_A
_PLL PLL
TEST K
LIRQ_7 IRQ_4 IRQ_3 RESET EVDD EVDD SDVDD SDVDD SDVDD SDVDD SDVDD EVDD DSPI_
PCS2 VDD_
OSC VSS_
OSC XTAL L
MU0TXD U0RTS U0CTS SD_A7 BOOT
MOD1 TEST BOOT
MOD0 SD_
VREF SDVDD SDVDD JTAG_
EN VDD_
RTC TRST DACK1 RST
OUT EXTAL M
NU0RXD SD_A11 SD_A6 SD_A0 SD_
CKE SD_D31 SD_D29 SD_D24 SD_D23 SD_D19 SD_
DQS2 SD_DM2 DSPI_
SOUT DSPI_
PCS5 DACK0 DREQ0 N
PSD_A12 SD_A10 SD_A5 SD_BA1 SD_
RAS SD_
CS1 SD_D28 SD_D25 SD_
DM3 SD_D20 SD_D16 SSI_FS TCLK DSPI_
PCS1 DSPI_
SIN DREQ1 P
RSD_A13 SD_A9 SD_A4 SD_A1 SD_WE SD_
CS0 SD_D27 SD_D26 SD_
DQS3 SD_D21 SD_D17 SSI_TXD SSI_
BCLK TMS DSPI_
SCK DSPI_
PCS0 R
TVSS SD_A8 SD_A3 SD_A2 SD_BA0 SD_
CAS SD_D30 SD_
CLK SD_
CLK SD_D22 SD_D18 SSI_RXD SSI_
MCLK TDO TDI VSS T
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16