General Description
The MAX1515 constant-off-time, pulse-width-modulated
(PWM) source/sink step-down DC-DC converter is opti-
mized for use in low-voltage active-termination power
rails or chipset power supplies in notebook and sub-
notebook computers. This device features dual internal
n-channel MOSFET power switches for high efficiency
and reduced component count. External Schottky
diodes are not required. An integrated boost switch
eliminates the need for an external boost diode. The
internal 40mΩNMOS power switches easily source and
sink continuous load currents up to 3A. The MAX1515
produces an adjustable output from +0.5V to +2.7V
and achieves efficiencies as high as 95%.
The MAX1515 can be configured as a DDR regulator,
producing an output that is exactly half the memory
supply rail. The input of the power stage can be taken
from the memory supply rail itself, resulting in an effi-
cient power supply that returns the energy to the rail
from which it was sourced. The MAX1515 includes a
reference buffer that provides ±5mA of drive current.
The MAX1515 uses a unique current-mode, constant-
off-time, PWM control scheme. A selectable pulse-skip-
ping mode maintains high efficiency during light-load
operation, yet still sources and sinks current on
demand. The MAX1515 can also be operated in fixed-
PWM mode for low output ripple. The programmable
constant-off-time architecture sets switching frequen-
cies up to 1MHz, which allows the user to optimize per-
formance trade-offs between efficiency, output
switching noise, component size, and cost. The
MAX1515 features an adjustable soft-start to limit surge
currents during startup and a low-power shutdown
mode to disconnect the input from the output and
reduce supply current below 1µA. The MAX1515 is
available in a 24-pin thin QFN package with an
exposed backside pad.
Applications
Notebook DDR Memory Termination
Active-Termination Buses
Chipset/Graphics Processor Supplies
Features
♦Dual 40mΩ Internal n-Channel MOSFETs
♦Integrated Boost Switch
♦+1.3V to +3.6V Input Voltage Range
♦1% VOUT Accuracy Over Line and Load
♦1MHz Maximum Switching Frequency
♦DDR Termination Regulator (DDR Mode)
Tracking Output Voltage
Source/Sink Pulse Skipping
±5mA Reference Buffer
♦Output Voltage (Non-DDR Mode)
+2.5V, +1.8V, or +1.5V Pin Selectable
+0.5V to +2.7V Adjustable
♦1.1V ±0.75% Reference Output
♦Adjustable Soft-Start Inrush Current Limiting
♦< 1µA (typ) Shutdown Supply Current
♦< 800µA (max) Operating Supply Current
♦Selectable Pulse-Skipping Operation at Light Loads
♦Positive and Negative Current Limit
♦Power-Good Window Comparator
♦Output Short-Circuit Protection
MAX1515
Low-Voltage, Internal Switch,
Step-Down/DDR Regulator
________________________________________________________________ Maxim Integrated Products 1
Ordering Information
MAX1515
LX
GND
VCC
FB
COMP
PGND
IN
REFOUT
PGOOD
VBIAS
(3.0V TO 3.6V)
VIN
(1.3V TO 3.6V)
VOUT = VTT
VREFOUT = VTTR
VDDQ
(2.5V OR 1.8V)
MODE
FBSEL1
BST
VDD
SHDN
SKIP
FBSEL0
SS
REFIN
REF
TOFF
Minimal Operating Circuit
19-3507; Rev 1; 3/06
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
EVALUATION KIT
AVAILABLE
PART
TEMP RANGE
PIN-
PACKAGE
PKG CODE
MAX1515ETG
-40°C to +85°C
24 Thin QFN
4mm x 4mm
T2444-4
MAX1515ETG+
-40°C to +85°C
24 Thin QFN
4mm x 4mm
T2444-4
Pin Configuration appears at end of data sheet.
+Denotes lead-free package.
MAX1515
Low-Voltage, Internal Switch,
Step-Down/DDR Regulator
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, VIN = +3.3V, VCC = VDD = SHDN = MODE = +3.3V, VREFIN = VREF, SKIP = GND, TA= 0°C to +85°C, unless oth-
erwise noted. Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCC, VDD, LX, SHDN to GND ...................................-0.3V to +4V
MODE, IC to GND ....................................................-0.3V to +4V
COMP, FB, REF, REFIN, REFOUT, PGOOD
to GND.........................................................-0.3V to (VCC + 0.3V)
FBSEL0, FBSEL1, TOFF, SKIP, SS to GND....-0.3V to (VCC + 0.3V)
VDD to VCC ...........................................................-0.3V to + 0.3V
IN to VDD ....................................................-0.3V to (VDD + 0.3V)
PGND to GND ...................................................... -0.3V to +0.3V
LX to BST................................................................. -4V to +0.3V
BST to GND .......................................................... -0.3V to +8.0V
LX Current (Note 1).............................................................±4.7A
REF Short Circuit to GND ...........................................Continuous
REFOUT Short Circuit to GND....................................Continuous
Continuous Power Dissipation (TA= +70°C)
24-Pin Thin QFN (derate 20.8mW/°C above +70°C;
part mounted on 1in2of 1oz copper)........................1667mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
PWM CONTROLLER
VIN 1.3 3.6
Input Voltage Range
VCC, VDD
3.0 3.6 V
Output Adjust Range VOUT ≤ VIN 0.5 2.7 V
TA = +25°C
to +85°C -3 0 +3
VFB -
VREFIN
VIN = +3.3V, ILOAD = 0,
MODE = VCC TA = 0°C to
+85°C -4 0 +4
mV
TA = +25°C
to +85°C
2.463
2.5
2.537
FBSEL0 = VCC,
FBSEL1 = VCC,
REFIN = REF TA = 0°C to
+85°C
2.450
2.5
2.550
TA = +25°C
to +85°C
1.782 1.800 1.827
FBSEL0 = VCC,
FBSEL1 = GND,
REFIN = REF TA = 0°C to
+85°C
1.773 1.800 1.836
TA = +25°C
to +85°C
1.477 1.500 1.523
FBSEL0=GND
FBSEL1=VCC
REFIN=REF TA = 0°C to
+85°C
1.470 1.500 1.530
TA = +25°C
to +85°C
0.492 0.500 0.508
Feedback Voltage Accuracy
VFB
VIN = +3.3V,
ILOAD = 0,
MODE = low
FBSEL0=GND
FBSEL1=GND
REFIN=0.5V TA = 0°C to
+85°C
0.490 0.500 0.510
V
Feedback Load-Regulation Error
VIN = +1.3V to +3.6V, ILOAD = 0 to 3A,
SKIP = VCC 0.1 %
Note 1: LX has clamp diodes to PGND and IN. If continuous current is applied through these diodes, thermal limits must be observed.
MAX1515
Low-Voltage, Internal Switch,
Step-Down/DDR Regulator
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = +3.3V, VCC = VDD = SHDN = MODE = +3.3V, VREFIN = VREF, SKIP = GND, TA= 0°C to +85°C, unless oth-
erwise noted. Typical values are at TA= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Sink-Mode Detect Threshold VFB -
VREFIN MODE = VCC, VREFIN = +0.5V to +1.5V
+18 +32
mV
Source-Mode Detect Threshold VFB -
VREFIN MODE = VCC, VREFIN = +0.5V to +1.5V -32 -18 mV
MOSFET On-Resistance RNMOS VCC = VDD = VIN = +3.3V, ILOAD = 0.5A
0.04 0.10
Ω
Switching Frequency fSW (Note 2) 1
MHz
Maximum Output Current
IOUT
(
RMS
)
(Note 3) 3.3 A
ILIMIT_P
VIN = +3.3V, MODE = GND or VCC,
positive or sourcing mode
3.60
4.2
4.85
Current-Limit Threshold
ILIMIT_N
MODE = VCC, negative or sinking mode
-3.0
A
Pulse-Skipping Current Threshold
ISKIP_P VIN = +3.3V, MODE = GND or VCC, positive
or sourcing mode 0.5 0.8 1.1 A
IZX_P VIN = +3.3V, MODE = GND or VCC, positive
or sourcing mode
200
Zero Cross Current Threshold
IZX_N MODE = VCC, negative or sinking mode
-350
mA
FB Input Bias Current FB = 1.01 x VTARGET (Note 4) -50
+50
nA
RTOFF = 33.2kΩ0.270 0.34 0.405
RTOFF = 110kΩ0.85 1.00 1.15
Off-Time tOFF VFB > 0.3 x VTARGET
(Note 4)
RTOFF = 499kΩ
3.8 4.5 5.2
µs
Extended Off-Time
tOFF
(
EXT
)
VFB < 0.3 x VTARGET (Notes 2, 4) 4 x
tOFF
µs
Minimum On-Time
tON
(
MIN
)
(Note 2)
180
ns
Maximum On-Time
tON
(
MAX
)
511 µs
SS Source Current
ISS
(
SRC
)
3.50 5.25 6.75
µA
SS Sink Current
ISS
(
SNK
)
100
µA
MODE = GND,
FBSEL0 = GND,
FBSEL1 = GND,
VFB = 1.01 x
VTARGET
450
800
No-Load Supply Current
ICC + IDD
+ IIN
VIN = 3.3V
(not switching) (Note 4)
MODE = VCC,
VFB = VTARGET 700 1200
µA
ICC + IDD
+ IIN
SHDN = MODE = GND, LX = 0V or 3.3V 0.2 20
IIN SHDN = MODE = GND, LX = 0V 0.2 20
Shutdown Supply Currents
ILX SHDN = MODE = GND, LX = 3.3V 0.1 20
µA
MAX1515
Low-Voltage, Internal Switch,
Step-Down/DDR Regulator
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = +3.3V, VCC = VDD = SHDN = MODE = +3.3V, VREFIN = VREF, SKIP = GND, TA= 0°C to +85°C, unless oth-
erwise noted. Typical values are at TA= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
REFERENCE
TA = +25°C to
+85°C
1.0923 1.100 1.1077
Reference Voltage VREF VCC = +3.0V to +3.6V
TA = 0°C to
+85°C
1.0907 1.100 1.1094
V
Reference Load Regulation IREF = -1µA to +50µA 10 mV
REFIN Input Voltage Range VREFIN VCC = +3.0V to +3.6V 0.5 1.5 V
VREFIN = +0.5V to +1.5V
IREFOUT = -1mA
to +1mA -10
+10
REFOUT Output Accuracy VREFIN -
VREFOUT VREFIN = +0.5V to +1.5V
IREFOUT = -5mA
to +5mA
-20 +20
mV
REFIN Input Bias Current IREFIN VREFIN = 1.1V -50
+50
nA
FAULT DETECTION
Thermal Shutdown TSHDN Rising, hysteresis = 15°C
+165
°C
Undervoltage-Lockout Threshold
VCC
(
UVLO
)
VCC rising, 2% falling-edge hysteresis 2.5 2.7 2.9 V
PGOOD Trip Threshold (Lower) No load, falling edge, hysteresis = 1% -13 -10 -7 %
PGOOD Trip Threshold (Upper) No load, rising edge, hysteresis = 1% +7
+10 +13
%
PGOOD Propagation Delay
tPGOOD
FB forced 2% beyond PGOOD trip
threshold 10 µs
PGOOD Output Low Voltage ISINK = 1mA 0.1 V
PGOOD Leakage Current
Condition
H i g h state, for ced to 3.6V ; V
C C
= V
D D
= 3.6V
1µA
INPUTS AND OUTPUTS
Logic Input High Voltage SKIP, SHDN, MODE, FBSEL0, FBSEL1 2.0 V
Logic Input Low Voltage SKIP, SHDN, MODE, FBSEL0, FBSEL1 0.8 V
Logic Input Current SKIP, SHDN, MODE, FBSEL0, FBSEL1
-0.5 +0.5
µA
MAX1515
Low-Voltage, Internal Switch,
Step-Down/DDR Regulator
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, VIN = +3.3V, VCC = VDD = SHDN = MODE = +3.3V, VREFIN = VREF, SKIP = GND, TA= -40°C to +85°C, unless
otherwise noted. Note 5)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
PWM CONTROLLER
VIN 1.3 3.6
Input Voltage Range
VCC, VDD
3.0 3.6 V
Output Adjust Range VOUT ≤ VIN 0.5
VCC
V
VFB -
VREFIN VIN = +3.3V, ILOAD = 0, MODE = VCC -5 +5 mV
FBSEL0 = VCC,
FBSEL1 = VCC,
REFIN = REF
2.438 2.562
FBSEL0 = VCC,
FBSEL1 = GND,
REFIN = REF
1.755 1.845
FBSEL0 = GND,
FBSEL1 = VCC,
REFIN = REF
1.463 1.538
Feedback Voltage Accuracy
VFB VIN = +3.3V, ILOAD = 0,
MODE = low
FBSEL0 = GND,
FBSEL1 = GND,
REFIN = 0.5V
0.487 0.513
V
Sink-Mode Detect Threshold VFB -
VREFIN MODE = VCC, VREFIN = +0.5V to +1.5V
+15 +35
mV
Source-Mode Detect Threshold VFB -
VREFIN MODE = VCC, VREFIN = +0.5V to +1.5V -35 -15 mV
nFET On-Resistance RNMOS VCC = VDD = VIN = +3.3V, ILOAD = 0.5A
0.10
Ω
Switching Frequency fSW (Note 2) 1
MHz
Current-Limit Threshold
ILIMIT_P
VIN = +3.3V, MODE = GND or VCC,
positive or sourcing mode
3.35 5.05
A
Pulse-Skipping Current Threshold
ISKIP_P VIN = +3.3V, MODE = GND or VCC,
positive or sourcing mode 0.4 1.2 A
RTOFF = 33.2kΩ0.250 0.425
RTOFF = 110kΩ
0.8 1.2
Off-Time tOFF VFB > 0.3 x VTARGET
(Note 4)
RTOFF = 499kΩ
3.8 5.2
µs
Maximum On-Time
tON
(
MAX
)
5µs
SS Source Current
ISS
(
SRC
)
37µA
SS Sink Current
ISS
(
SNK
)
100 µA
MAX1515
Low-Voltage, Internal Switch,
Step-Down/DDR Regulator
6 _______________________________________________________________________________________
Note 2: Guaranteed by design. Not production tested.
Note 3: Not tested; guaranteed by layout. Maximum output current may be limited by thermal capability to a lower value.
Note 4: VTARGET is the set output voltage determined by VREFIN, FBSEL0, and FBSEL1.
Note 5: Specifications to -40°C are guaranteed by design, not production tested.
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = +3.3V, VCC = VDD = SHDN = MODE = +3.3V, VREFIN = VREF, SKIP = GND, TA= -40°C to +85°C, unless
otherwise noted. Note 5)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
MODE = GND,
FBSEL0 =
FBSEL1 = GND,
VFB = 1.01 x
VTARGET
900
No-Load Supply Current ICC + IDD
+ IIN
VIN = 3.3V
(Note 4)
MODE = VCC
VFB = VTARGET 1300
µA
ICC + IDD
+ IIN
SHDN = MODE = GND, LX = 0V or 3.3V 20
IIN SHDN = MODE = GND, LX = 0V 20
Shutdown Supply Currents
ILX SHDN = MODE = GND, LX = 3.3V 20
µA
REFERENCE
Reference Voltage VREF VCC = +3.0V to +3.6V 1.086
1.114
V
Reference Load Regulation IREF = -1µA to +50µA 12 mV
REFIN Input Voltage Range VREFIN V
C C = + 3.0V to + 3.6V , V
C C
> V
RE F IN
+ 1.35V 0.5 1.5 V
VREFIN = +0.5V to +1.5V
IREFOUT = -1mA
to +1mA -15
+15
REFOUT Output Accuracy VREFIN -
VREFOUT VREFIN = +0.5V to +1.5V
IREFOUT = -5mA
to +5mA -25
+25
mV
FAULT DETECTION
Undervoltage-Lockout Threshold
VCC
(
UVLO
)
VCC rising, 2% falling-edge hysteresis
2.40 2.95
V
PGOOD Trip Threshold (Lower) No load, falling edge, hysteresis = 1% -13 -7 %
PGOOD Trip Threshold (Upper) No load, rising edge, hysteresis = 1% +7
+13
%
INPUTS AND OUTPUTS
Logic Input High Voltage SKIP, SHDN, MODE, FBSEL0, FBSEL1 2.0 V
Logic Input Low Voltage SKIP, SHDN, MODE, FBSEL0, FBSEL1 0.8 V
MAX1515
Low-Voltage, Internal Switch,
Step-Down/DDR Regulator
_______________________________________________________________________________________ 7
1.25V OUTPUT EFFICIENCY
vs. LOAD CURRENT
MAX1515 toc01
LOAD CURRENT (A)
EFFICIENCY (%)
10.10.01
10
20
30
40
50
60
70
80
90
100
0
0.001 10
SINK, SKIP
SOURCE,
PWM SINK, PWM
SOURCE, SKIP
VIN = 2.5V
VOUT = 1.25V
RTOFF = 110kΩ
1.25V OUTPUT EFFICIENCY
vs. LOAD CURRENT
MAX1515 toc02
LOAD CURRENT (A)
EFFICIENCY (%)
10.10.01
10
20
30
40
50
60
70
80
90
100
0
0.001 10
SINK, SKIP
SOURCE,
PWM SINK, PWM
SOURCE, SKIP
VIN = 2.5V
VOUT = 1.25V
RTOFF = 220kΩ
1.25V OUTPUT VOLTAGE
vs. LOAD CURRENT
MAX1515 toc03
LOAD CURRENT (A)
OUTPUT VOLTAGE (V)
32-2 -1 0 1
1.246
1.250
1.254
1.258
1.242
-3 4
SINK, SKIP
SOURCE, PWM
SINK, PWM
SOURCE, SKIP
VIN = 2.5V
VOUT = 1.25V
RTOFF = 110kΩ
0.9V OUTPUT EFFICIENCY
vs. LOAD CURRENT
MAX1515 toc04
LOAD CURRENT (A)
EFFICIENCY (%)
10.10.01
10
20
30
40
50
60
70
80
90
100
0
0.001 10
SINK, SKIP
SOURCE,
PWM
SINK, PWM
SOURCE, SKIP
VIN = 1.8V
VOUT = 0.9V
RTOFF = 110kΩ
0.9V OUTPUT EFFICIENCY
vs. LOAD CURRENT
MAX1515 toc05
LOAD CURRENT (A)
EFFICIENCY (%)
10.10.01
10
20
30
40
50
60
70
80
90
100
0
0.001 10
SINK, SKIP
SOURCE,
PWM
SINK, PWM
SOURCE, SKIP
VIN = 1.8V
VOUT = 0.9V
RTOFF = 220kΩ
0.9V OUTPUT VOLTAGE
vs. LOAD CURRENT
MAX1515 toc06
LOAD CURRENT (A)
OUTPUT VOLTAGE (V)
32-2 -1 0 1
0.896
0.900
0.904
0.908
0.892
-3 4
SINK, SKIP
SOURCE, PWM
SINK, PWM
SOURCE, SKIP
VIN = 1.8V
VOUT = 0.9V
RTOFF = 110kΩ
SWITCHING FREQUENCY
vs. LOAD CURRENT
MAX1515 toc07
LOAD CURRENT (A)
SWITCHING FREQUENCY (kHz)
3210-1-2
100
200
300
400
500
600
0
-3 4
PWM MODE
SKIP MODE
VIN = 2.5V
VOUT = 1.25V
Typical Operating Characteristics
(MAX1515 Circuit of Figure 1, VIN = 2.5V, VDD = VCC = SHDN = MODE = 3.3V, TA = +25°C, unless otherwise noted.)
MAX1515
Low-Voltage, Internal Switch,
Step-Down/DDR Regulator
8 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(MAX1515 Circuit of Figure 1, VIN = 2.5V, VDD = VCC = SHDN = MODE = 3.3V, TA = +25°C, unless otherwise noted.)
REF VOLTAGE
vs. REF LOAD CURRENT
MAX1515 toc08
REF LOAD CURRENT (μA)
REF VOLTAGE ERROR (V)
806020 40
1.098
1.100
1.102
1.104
1.096
0100
REFOUT VOLTAGE REGULATION
vs. LOAD CURRENT
MAX1515 toc09
REFOUT LOAD CURRENT (mA)
REFOUT VOLTAGE (V)
1050-5-10
1.240
1.245
1.250
1.255
1.260
1.265
1.235
-15 15
TOFF TIME
vs. TOFF RESISTOR
MAX1515 toc10
TOFF RESISTOR (kΩ)
TOFF (μs)
400300200100
1
2
3
4
5
0
0500
PEAK CURRENT LIMIT
vs. SS VOLTAGE
MAX1515 toc11
SS VOLTAGE (V)
PEAK CURRENT LIMIT (A)
1.61.41.2
1
2
3
4
5
0
1.0 1.8
VIN = 2.5V
VOUT = 1.25V
RTOFF = 110kΩ
STARTUP AND SHUTDOWN WAVEFORM
(HEAVY LOAD)
MAX1515 toc12
500μs/div
3.3V
A
B
C
D
E
0
0
0
1A
0
1.25V
0
A: PGOOD, 5V/div
B: SS, 2V/div
C: SHDN, 5V/div
D: INDUCTOR CURRENT, 1A/div
E: OUTPUT VOLTAGE, 1V/div
SKIP = GND, RLOAD = 10Ω
MAX1515
Low-Voltage, Internal Switch,
Step-Down/DDR Regulator
_______________________________________________________________________________________ 9
Typical Operating Characteristics (continued)
(MAX1515 Circuit of Figure 1, VIN = 2.5V, VDD = VCC = SHDN = MODE = 3.3V, TA = +25°C, unless otherwise noted.)
STARTUP AND SHUTDOWN WAVEFORM
(LIGHT LOAD)
MAX1515 toc13
1ms/div
3.3V
A
B
C
D
E
0
0
0
1A
0
1.25V
0
A: PGOOD, 5V/div
B: SS, 2V/div
C: SHDN, 5V/div
D: INDUCTOR CURRENT, 1A/div
E: OUTPUT VOLTAGE, 1V/div
SKIP = GND, RLOAD = 100Ω
DDR-MODE LOAD TRANSIENT
MAX1515 toc14
20μs/div
2.5V
A
B
C
D
0
0
2A
0
2A
1.25V
A: LX, 2V/div
B: LOAD CONTROL,
5V/div
C: INDUCTOR CURRENT, 2A/div
D: OUTPUT VOLTAGE, 50mV/div
SKIP = GND
DDR-MODE LOAD TRANSIENT
MAX1515 toc15
20μs/div
2.5V
A
B
C
D
0
0
2A
0
-2A
1.25V
A: LX, 2V/div
B: LOAD CONTROL,
5V/div
C: INDUCTOR CURRENT, 2A/div
D: OUTPUT VOLTAGE, 50mV/div
SKIP = GND
DDR-MODE LOAD TRANSIENT
MAX1515 toc16
20μs/div
2.5V
A
B
C
D
0
0
2A
0
-2A
1.25V
A: LX, 2V/div
B: LOAD CONTROL,
5V/div
C: INDUCTOR CURRENT, 2A/div
D: OUTPUT VOLTAGE, 50mV/div
SKIP = GND
MAX1515
Low-Voltage, Internal Switch,
Step-Down/DDR Regulator
10 ______________________________________________________________________________________
Typical Operating Characteristics (continued)
(MAX1515 Circuit of Figure 1, VIN = 2.5V, VDD = VCC = SHDN = MODE = 3.3V, TA = +25°C, unless otherwise noted.)
DDR-MODE LOAD TRANSIENT
MAX1515 toc17
20μs/div
2.5V
A
B
C
D
0
0
2A
0
-2A
1.25V
A: LX, 2V/div
B: LOAD CONTROL,
5V/div
C: INDUCTOR CURRENT, 2A/div
D: OUTPUT VOLTAGE, 50mV/div
SKIP = GND
DDR-MODE LOAD TRANSIENT
MAX1515 toc18
20μs/div
2.5V
A
B
C
D
0
0
2A
0
-2A
1.25V
A: LX, 2V/div
B: LOAD CONTROL,
5V/div
C: INDUCTOR CURRENT, 2A/div
D: OUTPUT VOLTAGE, 50mV/div
SKIP = GND
REFIN TRANSITION
MAX1515 toc19
50μs/div
3.3V
A
B
C
D
0
1.5V
1.0V
1.5V
1.0V
2A
0A
-2A
A: PGOOD, 5V/div
B: REFIN, 0.5V/div
C: OUTPUT VOLTAGE, 0.5V/div
D: INDUCTOR CURRENT, 2A/div
SKIP = GND
REFOUT LOAD TRANSIENT
MAX1515 toc20
10μs/div
A
B
+10mA
-10mA
1.25V
1.26V
1.24V
A: REFOUT LOAD, 20mA/div B: REFOUT VOLTAGE, 10mV/div
MAX1515
Low-Voltage, Internal Switch,
Step-Down/DDR Regulator
______________________________________________________________________________________ 11
Pin Description
PIN NAME FUNCTION
1, 2 PGND Power Ground. Internal connection to the source of the internal synchronous-rectifier switch. Connect
both PGND pins together.
3 IC Internally Connected Pin. Connect to PGND.
4V
DD
Supply Input for the Low-Side Gate Drive and REFOUT Buffer. Connect to the system supply voltage,
+3.0V to +3.6V. Bypass to PGND with a 1µF (min) ceramic capacitor. VDD supplies power to the
drivers and the REFOUT buffer.
5 REFOUT REFIN Buffered Output. REFOUT provides a buffered output voltage of REFIN when MODE = VCC.
Bypass to GND with a 0.47µF ceramic capacitor. REFOUT is disabled when MODE = GND.
6 SS Soft-Start. Connect a capacitor from SS to GND to limit the inrush current during startup.
7 PGOOD
Power-Good Open-Drain Output. PGOOD is low when the output voltage is more than 10% above or
below the normal regulation point. PGOOD is high impedance when the output is in regulation.
PGOOD is low in shutdown.
8 TOFF Off-Time Select Input. Connect a resistor from TOFF to GND to adjust the off-time.
9FB
Feedback Input.
In DDR mode (MODE = VCC), FB regulates to the voltage at REFIN.
In non-DDR mode (MODE = GND), connect directly to the output for preset voltage operation or to a
resistive voltage-divider for adjustable-mode operation.
10 COMP Integrator Compensation. Connect a 470pF capacitor from COMP to VCC for integrator
compensation.
11 VCC Analog Supply Input. Connect to the system supply voltage, +3.0V to +3.6V, with a series 10Ω
resistor. Bypass to GND with a 1µF (min) ceramic capacitor.
12 GND Analog Ground. Connect exposed backside pad to GND.
13 REF +1.1V Reference Voltage Output. Bypass to GND with a 1.0µF bypass capacitor. Can supply 50µA
for external loads. Reference turns off in shutdown.
14 REFIN External Reference Input. In DDR mode (MODE = VCC), REFIN sets the voltage that FB regulates to.
In non-DDR mode (MODE = GND), connect REFIN to REF.
15 SHDN
Shutdown Control. Low disables the switching regulator. SHDN and MODE select the operational
mode of the MAX1515.
SHDN
MODE
Description
Low Low Step-down regulator and REFOUT OFF
Low High Step-down regulator OFF, REFOUT active
High Low Step-down regulator ON, non-DDR mode, REFOUT OFF
High High Step-down regulator ON, DDR mode, REFOUT active
16 MODE
Mode-Select Pin. Mode sets the regulator into DDR mode or non-DDR operation mode, and controls
the REFOUT buffer. When MODE = VCC, MAX1515 is set in DDR mode and REFOUT is active. When
MODE = GND, MAX1515 is set in non-DDR mode and REFOUT is disabled. See the Modes of
Operation (MODE) section.
17 FBSEL0 Used with FBSEL1 to set the output voltage of the step-down regulator when MODE = GND.
Connect to GND if MODE = VCC.
MAX1515
Low-Voltage, Internal Switch,
Step-Down/DDR Regulator
12 ______________________________________________________________________________________
Standard Application Circuit
The MAX1515 standard application circuit (Figure 1)
generates a tracking output voltage and a reference
buffer output required for DDR termination regulators.
See Table 1 for component selections. Table 2 lists the
component manufacturers.
Detailed Description
The MAX1515 synchronous, current-mode, constant
off-time, PWM DC-DC converter steps down an input
voltage (VIN) from +1.3V to +3.6V to an output voltage
from +0.5V to +2.7V. The MAX1515 output delivers up
to 3A of continuous current. Internal 40mΩNMOS
power switches improve efficiency, reduce component
count, and eliminate the need for a boost diode or any
external Schottky diodes (Figure 2).
Pin Description (continued)
PIN NAME FUNCTION
18 FBSEL1 Used with FBSEL0 to set the output voltage of the step-down regulator when MODE = GND.
Connect to GND if MODE = VCC.
19 SKIP Pulse-Skipping Control Input. Connect to VCC for low-noise, forced-PWM mode. Connect to GND to
enable automatic pulse-skipping operation.
20 BST Boost Flying-Capacitor Connection. Connect an external 0.01µF capacitor as shown in the standard
application circuit (Figure 1).
21, 22 LX Inductor Switched Node. LX is the connection for the source of the high-side NMOS power switch
and drain of the low-side NMOS synchronous-rectifier switch. Connect both LX pins together.
23, 24 IN Power Input. Supply voltage input for the switching regulator. Connect to a +1.3V to +3.6V supply
voltage. Connect both IN pins together.
Table 1. Component Selection for Standard Applications
COMPONENT ±2A AT 1.25VOUT
DDR MODE (MODE = VCC)
±2A AT 0.9VOUT
DDR MODE (MODE = VCC)
Input Voltage (VIN) 2.3V to 2.7V 1.6V to 2.0V
Output Voltage (VOUT) 1.25V 0.9V
CIN, Input Capacitor 33µF, 6.3V, ceramic
TDK C3225XR0J336V
33µF, 6.3V, ceramic
TDK C3225XR0J336V
Switching Frequency (fSW)
250kHz 500kHz 250kHz 500kHz
L, Inductor 2.5µH, 4.5A, Sumida
CDRH8D28-2R5
1.2µH, 6.8A, Sumida
CDR7D28MN-1R2
2.5µH, 4.5A, Sumida
CDRH8D28-2R5
1.2µH, 6.8A, Sumida
CDR7D28MN-1R2
COUT, Output Capacitor
330µF, 18mΩ
Sanyo 2R5TPE330MI
POSCAP
220µF, 18mΩ
Sanyo 2R5TPE220MI
POSCAP
330µF, 18mΩ
Sanyo 2R5TPE330MI
POSCAP
220µF, 18mΩ
Sanyo 2R5TPE220MI
POSCAP
RTOFF 221kΩ, 1% 110kΩ, 1% 221kΩ, 1% 110kΩ, 1%
Table 2. Component Suppliers
SUPPLIER WEBSITE
Coilcraft www.coilcraft.com
Coiltronics www.coiltronics.com
Kemet www.kemet.com
Panasonic www.panasonic.com
Sanyo www.sanyo.com
Sumida www.sumida.com
Taiyo Yuden www.t-yuden.com
TDK www.component.tdk.com
TOKO www.tokoam.com
MAX1515
Low-Voltage, Internal Switch,
Step-Down/DDR Regulator
______________________________________________________________________________________ 13
MAX1515
LX
GND
VCC
FB
COMP
PGND
IN
REFOUT
PGOOD
VBIAS
(3.0V TO 3.6V)
VCC
(DDR MODE)
VIN
(1.3V TO 3.6V)
VOUT = VTT = VDDC / 2
VREFOUT = VTTR
VDDQ
(2.5V OR 1.8V)
MODE
FBSEL1
BST
VDD
SHDN
SKIP
FBSEL0
SS
REFIN
REF
TOFF
R1
10Ω
R2
100kΩ
RTOFF
110kΩ
RSS (OPTIONAL)
CSS
0.01μF
CBST
0.01μF
PWM MODE
SKIP MODE
ON
OFF
R3
10kΩ
1%
R4
10kΩ
1%
SEE TABLE 1 FOR COMPONENT SPECIFICATIONS
CVDD
1μF
CIN
33μF
COUT
220μF
CREFOUT
0.47μF
L
1.2μH
CVCC
1μF
CREFIN
0.01μF
CCOMP
470pF
CREF
1μF
ERR
MAX1515
LX
SNK/SRC
THRESHOLD SRC
SNK
IN
PGND
FB
FB GAIN
SINK/
SOURCE
LOGIC
SS
SOFT-
START
PWM
LOGIC
COMP
TOFF
TIMER
CURRENT
SENSE
ZX(+)
CURRENT
SENSE (+/-)
ZX(-)
GND
BST
SHDN
MODE
FBSEL0FBSEL1
FBSEL
DECODE
SKIP
VDD
L-SIDE
DRIVER
H-SIDE
DRIVER
PGOOD
PGOOD
LOGIC
VDD
REF BUF
REFIN
REFOUT
REF
REF
1.1V
VCC
MODE
Gm
Figure 1. Standard Application Circuit
Figure 2. Functional Diagram
MAX1515
Low-Voltage, Internal Switch,
Step-Down/DDR Regulator
14 ______________________________________________________________________________________
+3.3V Bias Supply (VCC and VDD)
The MAX1515 requires a 3.3V bias supply for its inter-
nal circuitry. Typically, this 3.3V bias supply is the note-
book’s 95%-efficient, 3.3V system supply. The 3.3V
bias supply must provide VCC (PWM controller) and
VDD (gate-drive and reference buffer power), so the
maximum current drawn is:
IBIAS = ICC + IREFOUT + fSW (QG(LOW) + QG(HIGH))
where ICC is 450µA (typ), fSW is the switching frequen-
cy, and QG(LOW) and QG(HIGH) are the internal MOS-
FET total gate charge of approximately 1nC.
The input supply (VIN) and 3.3V bias inputs (VCC and
VDD) can be connected together if the input source is a
fixed 3.0V to 3.6V supply. If the 3.3V bias supply pow-
ers up prior to the input supply, the enable signal
(SHDN going from low to high) must be delayed until
the input voltage is present to ensure startup.
Current Limit
The MAX1515 provides peak current limiting to protect
the MOSFETs during source/sink overload and short
circuit. During source mode the controller switches the
high-side MOSFET off when the inductor current
exceeds 4.2A. Use the following equation to calculate
the maximum source current:
where ISOURCE_MAX is the maximum source current,
ILIMIT_P is the source inductor current limit (4.2A typ),
and tOFF is the fixed off-time. For typical operating con-
ditions and component selection, this results in a maxi-
mum source current of 3.7A.
In sink mode, the MAX1515 does not issue an off-time
until the inductor current is above -3.2A. Use the follow-
ing equation to calculate the maximum sink current:
where ISINK_MAX is the maximum sink current, ILIMIT_N
is the sink inductor current limit (-3.0A typ), tDLY is the
current-limit propagation delay of approximately 500ns,
and tOFF is the fixed off-time. For typical operating con-
ditions and component selection, this results in a maxi-
mum sink current of -2.5A.
Soft-Start Current Limit
Soft-start allows a gradual increase of the internal cur-
rent limit to reduce input surge currents at startup and at
exit from shutdown. A timing capacitor, CSS, placed
from SS to GND sets the rate at which the internal cur-
rent limit is changed. Upon power-up, when the device
comes out of undervoltage lockout (2.6V typ) or after the
SHDN pin is pulled high, a 5µA (typ) constant-current
source charges the soft-start capacitor and the voltage
on SS increases. When the voltage on SS is less than
approximately 0.7V, the current limit is set to zero. As
the voltage increases from 0.7V to approximately 1.8V,
the current limit is adjusted from 0 to the current-limit
threshold (see the Electrical Characteristics). The volt-
age across the soft-start capacitor changes with time
according to the equation:
where ISS(SRC) is the soft-start source current from the
Electrical Characteristics.
The time when full current limit is available is given by:
The soft-start current limit varies with the voltage on the
soft-start pin, SS, according to the equation:
where ILIMIT_P is the positive current threshold from the
Electrical Characteristics. The constant-current source
stops charging once the voltage across the soft-start
capacitor reaches 1.8V (Figure 3).
Adjustable Positive Current Limit
The MAX1515 has internal current-limit circuitry that
limits the maximum current through the NMOS to 4.2A.
For applications that require a lower current limit, the
maximum current limit can be reduced by placing a
resistor (RSS) from SS to GND. The time constant for
the soft-start current limit is RSS x CSS.
where ILIMIT is the desired reduced current limit, and
ILIMIT_P and ISS(SRC) are taken from the Electrical
Characteristics.
RVI
IVI
SS REF LIMIT
LIMIT P SS SRC
=×+
⎛
⎝
⎜⎞
⎠
⎟
. /
_()
07
SSI VV
VI
LIMIT SS
REF LIMIT P
=×
−07. _
tCV
I
SS
SS SRC
=×18.
()
VIt
C
SS SS SRC
SS
=×
()
II
Vt V V t
L
SINK MAX LIMIT N
OUT OFF IN OUT DLY
__
=+
()
−−2
2
II
Vt
L
SOURCE MAX LIMIT P OUT OFF
__
=×
×
−2
MAX1515
Low-Voltage, Internal Switch,
Step-Down/DDR Regulator
______________________________________________________________________________________ 15
Short-Circuit/Overload Protection
The MAX1515 can sustain a constant short circuit or
overload. Under a source-mode short-circuit or over-
load condition, when VFB < 0.3 x VTARGET, the
MAX1515 uses an extended off-time to control the cur-
rent. Operation during a short circuit or overload is sim-
ilar to forced-PWM mode except the off-time is 4 x tOFF.
At the end of each off-time, the high-side NMOS switch
turns on and remains on until the output is in regulation
or the current through the switch increases to the maxi-
mum current limit. When the high-side NMOS switch
turns off, it remains off for four times the programmed
off-time (tOFF), and the low-side NMOS synchronous
switch turns on. Since either NMOS switch is always on,
the inductor current is continuous. The RMS inductor
current during a short circuit remains below the maxi-
mum current-limit threshold. The MAX1515 operates
using the extended off-time until the short circuit or
overload is removed and VFB > 0.3 x VTARGET.
Prolonged short circuit or overload can result in thermal
shutdown.
Summing Comparator
Three signals are added together at the input of the
summing comparator (Figure 2): an output-voltage
error signal relative to the reference voltage, an inte-
grated output-voltage error-correction signal, and the
sensed high-side NMOS switch current. The integrated
error signal is provided by a transconductance amplifi-
er with an external capacitor at COMP. This integrator
provides high DC accuracy without the need for a high-
gain amplifier. Connecting a capacitor at COMP modi-
fies the overall loop response (see the Integrator
Amplifier section).
Integrator Amplifier
The MAX1515 includes an internal transconductance
amplifier that improves the output DC accuracy.
A capacitor, CCOMP, from COMP to VCC compensates
the transconductance amplifier. For stability, choose
CCOMP = 470pF.
Modes of Operation (MODE)
Use MODE to configure the MAX1515 for DDR mode
(MODE = VCC) or non-DDR mode (MODE = GND). In
DDR mode, the MAX1515 can sink current even while
SKIP is low (see the Pulse Skipping (Source Mode) and
Pulse Skipping (Sink Mode) sections). Also, DDR mode
enables the REFOUT buffer, providing a buffered out-
put of the REFIN voltage. In non-DDR mode, the
MAX1515 can only source current when SKIP is low.
The REFOUT buffer is also disabled in non-DDR mode.
Light-Load Operation (
SKIP
)
The MAX1515 includes a pulse-skipping mode that
reduces current consumption during light loads. To con-
figure the MAX1515 for pulse-skipping mode, connect
SKIP to GND. Forced-PWM mode keeps the switching
frequency relatively constant and is desirable in appli-
cations that must always keep the frequency of con-
ducted and radiated emissions in a narrow band. Visit
Maxim’s website (www.maxim-ic.com) for more informa-
tion on how to control electromagnetic interference
(EMI). Pulse-skipping mode has a dynamic switching
frequency under light loads and is desirable in applica-
tions that require high efficiency at light loads.
Forced-PWM Mode
Connect SKIP to VCC to force the MAX1515 to operate
in low-noise, constant-off-time PWM mode. Constant
off-time PWM architecture provides a relatively constant
switching frequency (see the Frequency Variation with
Output Current section). A single resistor (RTOFF) sets
the high-side NMOS power-switch off-time that results
in a switching frequency up to 1MHz, allowing perfor-
mance trade-offs in efficiency, switching noise, compo-
nent size, and cost.
Forced-PWM mode regulates the output voltage by
increasing the high-side NMOS switch on-time to
increase the amount of energy transferred to the load
per cycle. At the end of each off-time, the high-side
NMOS switch turns on and remains on until the output is
in regulation or the current through the switch reaches
the 4.2A current limit. When the high-side NMOS switch
turns off, it remains off for the programmed off-time
(tOFF), and the low-side NMOS synchronous switch
turns on. The low-side NMOS switch remains on until the
end of tOFF. Since either NMOS switch is always on in
PWM mode, the inductor current is continuous.
1.8V
0.7V
ILIMIT_P
VSS (V)
ILIMIT (A)
SHDN
Figure 3. Soft-Start Current Limit
MAX1515
Low-Voltage, Internal Switch,
Step-Down/DDR Regulator
16 ______________________________________________________________________________________
Pulse Skipping (Source Mode)
Connect SKIP to GND to allow the MAX1515 to auto-
matically switch between high-efficiency pulse-skipping
mode under light loads and PWM mode under heavy
loads. The transition from PWM mode to pulse-skipping
mode occurs when the load current is half the pulse-
skipping mode current threshold (800mA typ).
In pulse-skipping mode, the switching frequency is
reduced to increase efficiency. The inductor current is
discontinuous in this mode, and the MAX1515 only initi-
ates an LX switching cycle when VFB < VREFIN. When
VFB falls below VREFIN, the high-side NMOS switch
turns on and remains on until output is in regulation and
the current through the switch increases to the positive
pulse-skipping-mode current threshold (ISKIP_P) of
800mA. When the high-side NMOS switch turns off, the
low-side NMOS synchronous switch turns on and
remains on until the current through the switch decreas-
es to the zero-cross-current threshold of 200mA.
Pulse Skipping (Sink Mode)
When pulse-skipping operation is selected (SKIP =
GND) while in DDR mode (MODE = VCC), the
MAX1515’s source/sink controller switches operating
modes when the output voltage crosses either hys-
teretic sink/source thresholds (VREFIN ±25mV). In
pulse-skipping source mode, the MAX1515 regulates
the valley of the output ripple voltage (see the Pulse
Skipping (Source Mode) section). When the output volt-
age rises above the sink-mode threshold, the MAX1515
enters sink mode. The MAX1515 begins each sink-
mode cycle by turning on the low-side NMOS. The low-
side NMOS remains on until the off-time (tOFF). After the
low-side NMOS turns off, the high-side NMOS turns on
and remains on until the current through the switch
reaches the zero-cross-current threshold of -350mA. As
long as the output voltage remains below the feedback
threshold, the controller remains in the high-impedance
state. Under light-load conditions, this allows the sink-
mode controller to automatically skip pulses. Under
heavy-load conditions, the output voltage remains
above the feedback threshold, forcing the sink-mode
controller to emulate typical forced-PWM operation.
The pulse-skipping current threshold allows the sink-
mode control scheme to automatically switch between
pulse-skipping PFM and nonskipping PWM operation.
This mechanism forces the boundary between continu-
ous and discontinuous inductor-current operation to be
half the negative pulse-skipping current threshold.
Output Voltage in Non-DDR Mode
In non-DDR mode (MODE = GND and VREFIN = VREF),
the output of the MAX1515 is selectable between one
of three preset output voltages: 2.5V, 1.8V, and 1.5V.
For a preset output voltage, connect FB to the output
voltage and connect FBSEL0 and FBSEL1 as indicated
in Table 4. For an adjustable output voltage, connect
FBSEL0 and FBSEL1 to GND and connect REFIN to a
Table 3. Modes of Operation
SHDN MODE
PIN SKIP REFOUT
BUFFER
STEP-DOWN
REGULATOR MODE
STEP-DOWN
REGULATOR CURRENT
Low Low X
Off, High-Z
Off Off
Low High X On Off Off
High Low Low
Off, High-Z
On, non-DDR mode.
FB regulates to preset voltage or 0.5V.
Source only.
Pulse-skipping mode.
High Low High
Off, High-Z
On, non-DDR mode.
FB regulates to preset voltage or 0.5V.
Source/sink.
Forced-PWM mode.
High High Low On On, DDR mode.
FB regulates to REFIN.
Source/sink.
Pulse-skipping mode.
High High High On On, DDR mode.
FB regulates to REFIN.
Source/sink.
Forced-PWM mode.
Table 4. Output-Voltage Programming
FBSEL0 FBSEL1 OUTPUT
VOLTAGE
GND GND Adjustable
VFB = VREFIN
GND VCC 1.5V
VCC GND 1.8V
VCC VCC 2.5V
X = Don’t care.
MAX1515
Low-Voltage, Internal Switch,
Step-Down/DDR Regulator
______________________________________________________________________________________ 17
resistive divider between REF and ground (Figure 5).
Regulation is maintained for adjustable output voltages
when VFB = VREFIN. Use 100kΩfor RB. RAis given by
the equation:
where VREF = 1.1V.
The preset output voltages use an internally trimmed
resistor-divider network that sets the output voltage to
the correct level when REFIN is connected to REF.
Connecting REFIN to other voltage levels while using
the preset voltage modes results in a ratiometrically
scaled output voltage.
Output Voltage in DDR Mode
In DDR mode (MODE = VCC), the MAX1515 regulates
FB to the voltage set at REFIN. For DDR applications,
the termination supply must track to exactly half the
memory supply voltage. Figure 1 shows the MAX1515
configured for DDR applications.
Reference Buffer (REFOUT)
A unity-gain amplifier provides a buffered output for the
reference input (VREFIN) when MODE = VCC. This
transconductance amplifier must be compensated with
a 0.47µF or greater ceramic capacitor. Larger capaci-
tor values decrease the amplifier’s bandwidth, thereby
increasing the response time to dynamic input-voltage
changes. The buffer allows this dynamic reference to
remain within ±20mV of the input voltage (VREFIN) even
when loaded with ±5mA. The input voltage range of the
amplifier is 0.5V to 1.5V. The reference buffer shuts
down when MODE = GND.
Power-Good Output (PGOOD)
PGOOD is the open-drain output for a window compara-
tor that continuously monitors the output. PGOOD is
actively held low in shutdown and during soft-start. After
soft-start terminates, PGOOD becomes high impedance
as long as the respective output voltage is within ±10%
of the nominal regulation voltage. When the output volt-
age drops 10% below or rises 10% above the nominal
regulation voltage, the MAX1515 pulls the power-good
output (PGOOD) low by turning on the MOSFET (Figure
2). For logic-level output voltages, connect an external
pullup resistor between PGOOD and VCC. A 100kΩ
resistor works well in most applications.
Thermal Shutdown
The MAX1515 features a thermal fault-protection circuit.
When the junction temperature rises above +165°C, a
thermal sensor shuts down the MAX1515 regardless of
VSHDN. The MAX1515 is reactivated after the junction
temperature cools to +150°C.
Thermal Resistance
Junction-to-ambient thermal resistance, θJA, is highly
dependent on the amount of copper area connected to
the exposed backside pad. Airflow over the board sig-
nificantly reduces θJA. For heatsinking purposes, evenly
distribute the copper area connected at the IC among
the high-current pins. Refer to the Maxim website
(www.maxim-ic.com) for QFN thermal considerations.
Power Dissipation
Power dissipation in the MAX1515 is dominated by
conduction losses in the two internal power switches.
Power dissipation due to supply current in the control
section and average current used to charge and dis-
charge the gate capacitance of the internal switches
(i.e., switching losses—PSL) is approximately:
PSL = C x VIN2x fSW
VV R
RR
FB REF B
AB
=+
⎛
⎝
⎜⎞
⎠
⎟
LOAD
CURRENT
INDUCTOR
CURRENT
OUTPUT
VOLTAGE
LX
VOLTAGE
VREFIN
VIN
VOUT
GND
0
-2A
0
-2A
tOFF
MAX1515
LX
GND
FB
PGND
VOUT
FBSEL1
FBSEL0
MODE
REFIN
REF
RB
RA
COUT
L
Figure 4. Sink-Mode Waveforms
Figure 5. Setting VOUT with a Resistive Voltage-Divider at REFIN
MAX1515
Low-Voltage, Internal Switch,
Step-Down/DDR Regulator
18 ______________________________________________________________________________________
where:
C = 5nF
fSW = switching frequency
The combined conduction losses (PCL) in the two
power switches are approximated by:
PCL = IOUT2x RNMOS
where:
IOUT = load current
RNMOS = NMOS switch on-resistance
Design Procedure
For typical DDR applications, use the recommended
component values in Table 1. For other applications,
use the recommended component values in Table 5, or
take the following steps:
1) Select the desired PWM-mode switching frequency.
See Figure 6 for maximum operating frequency.
2) Select the constant off-time as a function of input
voltage, output voltage, and switching frequency.
3) Select RTOFF as a function of off-time.
4) Select the inductor as a function of output voltage,
off-time, and peak-to-peak inductor current.
Programming the No-Load Switching
Frequency and Off-Time
The MAX1515 features a programmable PWM mode
switching frequency, which is set by the input and out-
put voltage and the value of RTOFF. RTOFF sets the
high-side NMOS power switch off-time in PWM mode.
Use the following equation to select the off-time
according to the desired no-load switching frequency
in PWM mode:
where:
tOFF = the programmed off-time
VIN = the input voltage
VOUT = the output voltage
fPWM = no-load switching frequency, PWM mode
Select RTOFF according to the formula:
VRTOFF is typically 1.1V and the recommended values
for RTOFF range from 33.2kΩto 499kΩfor off-times of
0.35µs to 4.5µs.
Frequency Variation with Output Current
The operating frequency of the MAX1515 in PWM mode
is determined primarily by tOFF (set by RTOFF), VIN, and
VOUT as shown in the following formula:
where:
VCHG = the voltage drop in the inductor charge path
due to high-side FET RNMOS and inductor DCR
VDISCHG = the voltage drop in the inductor discharge
path due to low-side FET RNMOS and inductor DCR
fVV V
tV V V
PWM IN OUT CHG
OFF IN CHG DISCHG
=+
()
−−
−
Rt s
k
s
TOFF OFF
=
()
− .
.
0 035 110
100
μμ
Ω
tVV
fV
OFF
IN OUT
PWM IN
=×
−
0
200
600
400
800
1000
FREQUENCY (kHz)
MAXIMUM RECOMMENDED OPERATING
FREQUENCY vs. INPUT VOLTAGE
VIN (V)
1.5 2.52.0 3.0 3.5
NO LOAD
VOUT = 1.25V VOUT = 0.9V
VOUT = 2.5V
VOUT = 1.8V
VOUT = 1.5V
Figure 6. Maximum Operating Frequency vs. Input Voltage
Table 5. Recommended Component
Values (IOUT = 3A)
VIN
(V)
VOUT
(V)
fPWM
(kHz)
L
(µH)
COUT
(µF)
RTOFF
(kΩ)
3.3 2.5 400 1.5 100 49.9
3.3 1.8 400 2.2 150 110
3.3 1.5 480 2.2 180 110
3.3 1.2 420 2.2 220 150
2.5 1.8 430 1.2 100 49.9
2.5 1.5 320 1.8 150 110
2.5 1.2 440 1.5 180 110
MAX1515
Low-Voltage, Internal Switch,
Step-Down/DDR Regulator
______________________________________________________________________________________ 19
While sourcing current, VCHG and VDISCHG increase
with source load current and the voltage across the
inductor decreases. This causes the frequency to drop.
Conversely, while sinking current, VCHG and VDISCHG
decrease with sink load current and the voltage across
the inductor increases. Approximate the change in fre-
quency with the following formula:
where RDROP is the resistance of the internal MOSFETs
(40mΩtyp) and the inductor.
Inductor Selection
The key inductor parameters must be specified: induc-
tor value (L) and peak current (IPEAK). The following
equation includes a constant, denoted as LIR, which is
the ratio of peak-to-peak inductor AC ripple current to
maximum DC load current. A higher value of LIR allows
smaller inductance but results in higher losses and rip-
ple. A good compromise between size and losses is
found at approximately a 25% ripple-current to load-
current ratio (LIR = 0.25), which corresponds to a peak
inductor current 1.125 times the DC load current:
Additionally, the minimum inductance chosen must be
high enough to limit the inductor current during the
high-side switch on-time to less than 1A/µs.
The peak-inductor current at full load is 1.125 x
IOUT(MAX) if the above equation is used; otherwise, the
peak current is calculated by:
Choose an inductor with a saturation current at least as
high as the peak-inductor current. The inductor select-
ed should exhibit low losses at the chosen operating
frequency.
Input Capacitor Selection
The input-filter capacitors reduce peak currents and
noise at the voltage source. Place a low-ESR and low-
ESL 0.1µF capacitor for noise filtering no further than
5mm from IN. Select the bulk input capacitor according
to the RMS input ripple-current requirements and volt-
age rating:
Output Capacitor Selection
The output filter capacitor affects the output-voltage
ripple, output load-transient response, and feedback-
loop stability. For stable operation, the MAX1515
requires a minimum output ripple voltage of VRIPPLE ≥
1% x VOUT. The minimum ESR of the output capacitor
is calculated by:
Stable operation for source-only applications requires
the correct output filter capacitor. When choosing the
output capacitor, ensure that:
For DDR applications, the output capacitance require-
ment needs to be two times the above requirement.
The output filter capacitor must have low enough equiv-
alent series resistance (ESR) to meet output ripple and
load-transient requirements, yet have high enough ESR
to satisfy stability requirements.
For applications where the output is subject to violent
load transients, the output capacitor’s size depends on
how much ESR is needed to prevent the output from
dipping too low under a load transient. Ignoring the sag
due to finite capacitance:
In applications without large and fast load transients,
the output capacitor’s size often depends on how much
ESR is needed to maintain an acceptable level of out-
put voltage ripple. The output ripple voltage of a step-
down controller equals the total inductor ripple current
multiplied by the output capacitor’s ESR. Therefore, the
maximum ESR required to meet ripple specifications is:
RV
I LIR
ESR RIPPLE
OUT MAX
≤
()
RV
I
ESR STEP
OUT MAX
≤
()
Δ
CVt
VFs
OUT REFIN OFF
OUT
≥×× /105μμ
ESR L
tOFF
% ≥×1
II VVV
V
RMS OUT MAX OUT IN OUT
IN
=⎛
⎝
⎜
⎜
⎞
⎠
⎟
⎟
−
()
()
II Vt
L
PEAK OUT MAX OUT OFF
=+
×
×
() 2
LV V s
A
MIN IN MAX OUT
()
≥
()
×−1
1
μ
LVt
I LIR
OUT OFF
OUT MAX
=×
×
()
ΔfIR
Vt
PWM
OUT DROP
IN OFF
=×
×
−
MAX1515
Low-Voltage, Internal Switch,
Step-Down/DDR Regulator
20 ______________________________________________________________________________________
The actual capacitance value required relates to the
physical size needed to achieve low ESR, as well as to
the chemistry of the capacitor technology. Thus, the
capacitor is usually selected by ESR and voltage rating
rather than by capacitance value (this is true of tanta-
lums, OS-CONs, polymers, and other electrolytics).
Transient Response
The inductor ripple current also impacts transient-
response performance, especially at low VIN - VOUT dif-
ferentials. Low inductor values allow the inductor
current to slew faster, replenishing charge removed
from the output filter capacitors by a sudden load step.
The worst-case output sag can be calculated from:
where ΔIOUT is the maximum load transient.
Typically, the maximum load transient is equal to the
maximum load current (ΔIOUT = ILOAD(MAX)). For DDR-
termination applications, the output must source and
sink current. In these applications, the actual peak-to-
peak transient current (ΔIOUT) is defined as the sum of
both the maximum source and sink load currents:
The amount of overshoot during a full-load to no-load
transient due to stored inductor energy can be calculat-
ed as:
When using the pulse-skipping source/sink feature
(MODE = VCC and SKIP = GND), the output transient
voltage should not exceed or drop below the sink and
source (respectively) detection thresholds (VREFIN
±20mV).
Applications Information
Dropout Operation
The MAX1515 improves dropout performance by hav-
ing a maximum on-time of 10µs. When working with low
input voltages, the duty-factor limit must be calculated
using worst-case values for on- and off-times. Keep in
mind that transient-response performance of step-down
regulators operated too close to dropout is poor, and
bulk output capacitance must often be added (see the
VSAG equation in the Design Procedure section).
The absolute point of dropout is when the inductor cur-
rent ramps down during the off-time (ΔIDOWN) as much
as it ramps up during the on-time (ΔIUP). The ratio h =
ΔIUP/ΔIDOWN indicates the controller’s ability to slew
the inductor current higher in response to increased
load, and must always be greater than 1. As h
approaches 1, the absolute minimum dropout point, the
inductor current cannot increase as much during each
switching cycle and VSAG greatly increases unless
additional output capacitance is used.
A reasonable minimum value for h is 1.5, but adjusting
this up or down allows trade-offs between VSAG, output
capacitance, and minimum operating voltage. For a
given value of h, the minimum operating voltage can be
calculated as:
where VCHG and VDISCHG are the parasitic voltage
drops in the charge and discharge paths (see the
Frequency Variation with Output Current section),
tON(MAX) is from the Electrical Characteristics, and tOFF
is the programmed off-time. The absolute minimum
input voltage is calculated with h = 1.
If the calculated VIN(MIN) is greater than the required
minimum input voltage, then tOFF must be reduced or
output capacitance added to obtain an acceptable
VSAG. If operation near dropout is anticipated, calcu-
late VSAG to be sure of adequate transient response.
Dropout Design Example:
VOUT = 2.5V
tOFF = 1µs
VCHG = VDISCHG = 100mV
h = 1.5
= 2.99V
Dynamic Output-Voltage Transitions
By changing the voltage at REFIN, the MAX1515 can
be used in applications that require dynamic output-
voltage changes between two set points. An n-channel
MOSFET can be used to dynamically adjust the second
controller’s output voltage by changing the resistive
VVV
sVV
s
IN MIN() ...(..)
=++
×× +
25 01 15 1 25 01
10
μ
μ
VVV
ht V V
t
IN MIN OUT CHG OFF OUT DISCHG
ON MAX
() ()
()
=++
×× +
VIL
CV
SOAR OUT
OUT OUT
≈ ()
Δ2
2
ΔII I
OUT SOURCE MAX SINK MAX
=+
() ()
VILVt
LC V V
Vt
LC
It
C
SAG OUT OUT OFF
OUT IN OUT
OUT OFF
OUT
OUT OFF
OUT
≈+
×−
()
+×
+
()
Δ
Δ
22
22
MAX1515
Low-Voltage, Internal Switch,
Step-Down/DDR Regulator
______________________________________________________________________________________ 21
voltage-divider network at REFIN. The resulting output
voltages are determined by the following equations:
Forced-PWM operation is required to ensure fast, accu-
rate negative voltage transitions when REFIN is low-
ered. Since forced-PWM operation disables the
zero-crossing comparator, the inductor current can
reverse under light loads, quickly discharging the out-
put capacitors.
For a step voltage change at REFIN, the rate-of-change
of the output voltage is limited by the inductor current
ramp, the total output capacitance, the current limit,
and the load during the transition. The inductor current
ramp is limited by the voltage across the inductor and
the inductance. The total output capacitance deter-
mines how much current is needed to change the out-
put voltage. Additional load current slows down the
output-voltage change during a positive REFIN voltage
change, and speeds up the output-voltage change dur-
ing a negative REFIN voltage change. Increasing the
current-limit setting speeds up a positive output-voltage
change.
To avoid tripping the power-good comparators, the ref-
erence-voltage slew rate must be slow enough that the
output voltage (VOUT) can accurately track the refer-
ence voltage (VREFIN). Add a capacitor across REFIN
and GND to control the rate-of-change of the REFIN
voltage during dynamic transitions and filter noise.
With the additional capacitance, the REFIN voltage
slews between the two set points with a time constant
given by REQ x CREFIN, where REQ is the equivalent
parallel resistance seen by the slew capacitor.
Referring to Figure 7, the time constant for a positive
REFIN voltage transition is:
and the time constant for a negative REFIN voltage
transition is:
PC Board Layout Guidelines
Good layout is necessary to achieve the intended out-
put power level, high efficiency, and low noise. Good
layout includes the use of a ground plane, careful com-
ponent placement, and correct routing of traces using
appropriate trace widths. Refer to the MAX1515 EV kit
for a reference of a good layout.
The following points are in order of decreasing impor-
tance:
1) Minimize switched-current and high-current ground
loops. Connect the input capacitor’s ground, the
output capacitor’s ground, and PGND at a single
point. Connect the resulting island to GND at only
one point.
2) Connect the input filter capacitor less than 5mm
away from IN. The connecting copper trace carries
large currents and must be at least 1mm wide,
preferably 2.5mm.
3) Place the LX node components as close together
and as near to the device as possible. This reduces
noise, resistive losses, and switching losses.
4) A ground plane is essential for optimal perfor-
mance. In most applications, the circuit is located
on a multilayer board, and full use of the four or
more layers is recommended. Use the top and bot-
tom layers for interconnections and the inner layers
for an uninterrupted ground plane. Avoid large AC
currents through the ground plane.
Chip Information
TRANSISTOR COUNT: 8258
PROCESS: BiCMOS
τPOS REFIN
RR
RR
C=×
+
⎡
⎣
⎢⎤
⎦
⎥
12
12
τPOS REFIN
RRR
RR RC=×+
++
⎡
⎣
⎢⎤
⎦
⎥
123
12 3
()
VV
R
RR
VV
RR
RR R
OUT LOW REF
OUT HIGH REF
()
()
=+
⎛
⎝
⎜⎞
⎠
⎟
=+
++
⎛
⎝
⎜⎞
⎠
⎟
2
12
23
12 3
MAX1515
LX
GND
FB
PGND
VOUT
FBSEL1
SKIP
FBSEL0
MODE
REFIN
REF
R3
R2
R1
VOUT(LOW)
VOUT(HIGH)
COUT
VCC L
CREFIN
Figure 7. Dynamic Output Voltages
MAX1515
Low-Voltage, Internal Switch,
Step-Down/DDR Regulator
22 ______________________________________________________________________________________
18 17 16 15 14 13
123456
7
8
9
10
11
12
24
23
22
21
20
19
MAX1515
THIN QFN
(4mm x 4mm)
TOP VIEW
SKIP
BST
LX
LX
IN
IN
+
GND
VCC
COMP
FB
TOFF
PGOOD
SS
REFOUT
VDD
IC
PGND
PGND
FBSEL1
FBSEL0
MODE
SHDN
REFIN
REF
Pin Configuration
MAX1515
Low-Voltage, Internal Switch,
Step-Down/DDR Regulator
______________________________________________________________________________________ 23
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
24L QFN THIN.EPS
PACKAGE OUTLINE,
21-0139 2
1
E
12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm
MAX1515
Low-Voltage, Internal Switch,
Step-Down/DDR Regulator
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
24 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2006 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.
PACKAGE OUTLINE,
21-0139
2
2
E
12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
