MMA6270Q - Freescale Semiconductor

Document Number: MMA6270QT

Rev 4, 04/2008

Freescale Semiconductor

Technical Data

±1.5 g - 6 g Dual Axis Low-g

Micromachined Accelerometer

The MMA6270QT low cost capacitive micromachined accelerometer

features signal conditioning, a 1-pole low pass filter , temperature compensation

and g-Select which allows for the selection among four sensiti vi ti es. Zero-g

offset full scale span and filter cut-off are factory set and require no external

devices. Includes a Sleep Mode that makes it ideal for handhel d battery

powered electronics.

Features

• Selectable Sensitivity (1.5 g / 2 g / 4 g / 6 g)

• Low Current Consumption: 500 μA

• Sleep Mod e: 3 μA

• Low Voltage Operation: 2.2 V – 3.6 V

• 6 mm x 6 mm x 1.45 mm QFN

• High Sensitivity (800 mV/g @1.5 g)

• Fast Turn On Time

• Integral Signal Conditioning with Low Pass Filter

• Robust Design, High Shocks Survivability

• Pb-Free Terminations

• Environmentally Preferred Package

• Low Cost

Typical Applications

• Laptop PC: Freefall Detection , Anti-Theft

• Cell Phone: Image Stability, Text Scroll, Motion Dialing, E-Compass

• PDA: Text Scroll

• Navigation and Dead Reckonin g: E-Compass Tilt Compensation

• Gaming: Tilt and Motion Sensing, Event Recorder

• Robotics: Motion Sensing

• Appliances: Vibration Sensing

ORDERING INFORMATION

Device Name Temperature

Range Package

Drawing Package

MMA6270QT – 40 to +105°C 1622-02 QFN-16, Tray

MMA6270QR2 – 40 to +105°C 1622-02 QFN-16,Tape & Reel

MMA6270QT

MMA6270QT: XY AXIS

ACCELEROMETER

±1.5 g / 2 g / 4 g / 6 g

16-LEAD

QFN

CASE 1622-02

Bottom View

Figure 1. Pin Connections

Top View

1516 14 13

5678

g-Select1

N/C

N/Cg-Select2

N/C

N/CN/C

N/C

OUT

Sleep

Mode

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Figure 2. Simplified Accelerometer Functional Block Diagram

ELECTRO STATIC DISCHARGE (ESD)

WARNING: This device is sensitive to electrostatic

discharge.

Although the Freescale accelerometer contains internal

2000 V ESD protection circuitry, extra precaution must be

taken by the user to protect the chip from ESD. A charge of

over 2000 volts can accumulate on the human body or

associated test equipment. A charge of this magnitude can

alter the performance or cause failure of the chip. When

handling the accelerometer, proper ESD precautions should

be followed to avoid exposing the device to discharges which

may be detrimental to its performance.

Table 1. Maximum Ratings

(Maximum ratings are the limits to which the devi ce can be exposed without causing permanent damage.)

Rating Symbol Value Unit

Maximum Acceleration (all axis) gmax ±2000 g

Supply Voltage VDD –0.3 to +3.6 V

Drop Test(1)

1. Dropped onto concrete surface from any axis.

Ddrop 1.8 m

Storage Temperature Range Tstg –40 to +125 °C

VSS

YOUT

XOUT

g-Select1

g-Select2

Sleep Mode

VDD

G-Cell

Sensor

Oscillator Clock

Generator X-Temp

Comp

Y-Temp

Comp

C to V

Converter

Gain

Filter

Control Logic

EEPROM Trim Circuits

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Table 2. Operating Characteristics

Unless otherwise noted: –40°C < TA < 105°C, 2.2 V < VDD < 3.6 V, Acceleration = 0 g, Loaded output(1)

Characteristic Symbol Min Typ Max Unit

Operating Range(2)

Supply Voltage(3)

Supply Current

Supply Current at Sleep Mode(4)

Operating Temperature Range

Acceleration Range, X-Axis, Y-Axis,

g-Select1 & 2: 00

g-Select1 & 2: 10

g-Select1 & 2: 01

g-Select1 & 2: 11

VDD

IDD

gFS

2.2

—

–40

—

3.3

500

—

±1.5

±2.0

±4.0

±6.0

3.6

800

+105

—

μA

°C

Output Signal

Zero-g (TA = 25°C, VDD = 3.3 V)(5)

Zero-g(4)

X-axis

Y-axis

Sensitivity (TA = 25°C, VDD = 3.3 V)

1.5 g

2 g

4 g

6 g

Sensitivity(4)

X-axis

Y-axis

Bandwidth Response

VOFF

VOFF, TA

S1.5g

S2g

S4g

S6g

S, TA

f-3dB

1.485

±2.6(6)

±5.8(6)

740

555

277.5

185

±0.02(6)

±0.01(6)

—

1.65

±0.6

±5.8

800

600

300

200

±0.02

±0.01

350

1.815

±3.8(7)

±5.9(7)

860

645

322.5

215

±0.02(7)

±0.01(7)

—

mg/°C

mV/g

%/°C

Noise

RMS (0.1 Hz – 1 kHz)(4)

Power Spectral Density RMS (0.1 Hz – 1 kHz)(4) nRMS

nPSD

—

—4.7

350 —

—mVrms

μg/

Control Timing

Power-Up Response Time(8)

Enable Response Time(9)

Sensing Element Resonant Frequency

Internal Sampling Frequency

tRESPONSE

tENABLE

fGCELL

fCLK

—

1.0

0.5

6.0

2.0

—

kHz

Output Stage Performance

Full-Scale Output Range (IOUT = 30 µA) VFSO VSS+0.25 — VDD–0.25 V

Nonlinearity, XOUT, YOUT NLOUT –1.0 — +1.0 %FSO

Cross-Axis Sensitivity(10) VXY, XZ, YZ ——5.0 %

Ratiometric Error(11) error — — — %

1. For a loaded output, the measurements are observed after an RC filter consisting of a 1.0 kΩ resistor and a 0.1 µF capacitor on VDD-GND.

2. These limits define the range of operation for which the part will meet specification.

3. Within the supply range of 2.2 and 3.6 V, the device operates as a fully calibrated linear accelerometer. Beyond these supply limits the device

may operate as a linear device but is not guaranteed to be in calibration.

4. This value is measured with g-Select in 1.5 g mode.

5. The device can measure both + and – acceleration. With no input acceleration the output is at midsupply. For positive acceleration the output

will increase above VDD/2. For negative acceleration, the output will decrease below VDD/2.

6. These values represent the 10th percentile, not the minimum.

7. These values represent the 90th percentile, not the maximum.

8. The response time between 10% of full scale VDD input voltage and 90% of the final operating output voltage.

9. The response time between 10% of full scale Sleep Mode input voltage and 90% of the final operating output voltage.

10. A measure of the device’s ability to reject an acceleration applied 90° from the true axis of sensitivity.

11.Zero-g offset ratiometric error can be typically >20% at VDD = 2.2 V. Sensitivity ratiometric error can be typically >3% at VDD = 2.2. Consult

factory for additional information

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PRINCIPLE OF OPERATION

The Freescal e accelerometer is a surf ace-micromachined

integrated-circuit accelerometer.

The device consists of two surface micromachined

capacitive sensing cells (g- cell) and a signal conditioning

ASIC contained in a single integrated circuit package. The

sensing elements are sealed hermetically at the wafer level

using a bulk micromachined cap wafer.

The g-cell is a mechanical structure formed from

semiconductor materials (polysilicon) using semiconductor

processes (masking and etching). It can be modeled as a set

of beams attached to a movable central mass that move

between fixed beams. The movable beams can be deflected

from their rest position by subjecting the system to an

acceleration (Figure 3).

As the beams attached to the central mass move, the

distance from them to the fixed beams on one side will

increase by the same amount that the distance to the fixed

beams on the other side decreases. The change in distance

is a measure of acceleration.

The g-cell beams form two back-to-back capacitors

(Figure 3). As the center beam moves with acceleration, the

distance between the beams changes and each capacitor's

value will change, (C = Aε/D). Where A is the area of the

beam, ε is the dielectric constant, and D is the distance

between the beams.

The ASIC uses switched capacitor techniques to measure

the g-cell capacitors and extract the acceleration data from

the difference between the two capacitors. The ASIC also

signal conditions and filters (switched capacitor) the signal,

providing a high level output voltage that is ratiometric and

proportional to acceleration.

Figure 3. Simplified Transducer Physical Model

SPECIAL FEATURES

g-Select

The g-Select feature allows for the selection among 4

sensitivities present in the device. Depending on the logic

input placed on pins 1 and 2, the device internal gain will be

changed allowing it to function with a 1.5 g, 2 g, 4 g, or 6 g

sensitiv ity (Table 3). This feature is ideal when a product has

applications requi ring different sensitivities for optimum

performance. The sensitivity can be changed at anytime

during the operation of the product. The g-Select1 and g-

Select2 pins can be left unconnecte d for applications

requiring only a 1.5 g sensitivity as the device has an internal

pull-down to keep it at that sensitiv ity (800 mV/g).

Sleep Mode

The dual axis accelerometer provides a Sleep Mode that

is ideal for battery operated products. When Sleep Mode is

active, the device outputs are turned off, providing significant

reduction of operating current. A low input signal on pin 12

(Sleep Mode) will place the device in thi s mode and redu ce

the current to 3 μA typ. For lower power consumption, it is

recommended to set g-Select1 and g-Select2 to 1.5 g mode.

By placing a high input signal on pin 12, the device will

resume to normal mode of operation.

Filtering

The dual axis accelerometer contains onboard single-pole

switched capacitor filters. Because the filter is realized using

switched capacitor techniques, there is no requirement for

external passive components (resistors and capacitors) to set

the cut-off frequency.

Ratiometricity

Ratiometricity simply means the output offset voltage and

sensitivity will scale linearly with applied supply voltage. That

is, as supply voltage is increased, the sensitivity and offset

increase linearly; as supply voltage decreases, offset and

sensitivity decrease linearly. This is a key feature when

interfacing to a microcontroller or an A/D converter because

it provides system level cancellation of supply induced errors

in the analog to digital conversion process.

Acceleration

Table 3. g-Select Pin Descriptions

g-Select2 g-Select1 g-Range Sensitivity

0 0 1.5 g 800 mV/g

0 1 2 g 600 mV/g

1 0 4 g 300 mV/g

1 1 6 g 200 mV/g

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BASIC CONNECTIONS

Pin Descriptions

Figure 4. Pinout Description

Figure 5. Accelerometer with Recommended

Connection Diagram

PCB Layout

Figure 6. Reco mme n de d PCB La y out for Interfacing

Accelerometer to Microcontroller

NOTES:

1. Verify VDD line has the ability to reach 2.2 V in <

0.1 ms as measured on the device at the VDD pin.

Rise times greater than this most likely will prevent

start up operation.

2. Physical coupling distance of the accelerometer to

the microcontroller should be minimal.

3. The flag underneath the package is internally

connected to ground. It is not recommended for the

flag to be soldered down.

4. Place a ground plane ben eath the accelerometer to

reduce noise, the ground plane should be attached to

all of the open ended terminals shown in Figure 6.

5. Use an RC filter with 1.0 kW and 0.1 µF on the

outputs of the accelerometer to minimize clock noise

(from the switched capacitor filter circuit).

6. PCB layout of power and ground should not couple

power supply noise.

7. Accelerometer and microcontroller should not be a

high current path.

8. A/D sampling rate and any external power supply

switching frequency should be selected such that

they do not interfere with th e in t ern a l acce le ro meter

sampling frequency (11 kHz for the sampling

frequency). This will prevent aliasing errors.

9. PCB layout should not run traces or vias under the

QFN part . Th is co ul d le ad to gr ou nd shorting to the

accelerometer flag.

Table 4. Pin Descriptions

Pin No. Pin Name Description

1 g-Select1 Logic input pin to select g level.

2 g-Select2 Logic input pin to select g level.

DD Power Supply Input

SS Power Supply Ground

5 - 7 N/C No internal connection.

Leave unconnected.

8 - 11 N/C Unused for factory trim.

Leave unconnected.

12 Sleep Mode Logic input pin to enable product or

Sleep Mode.

13 N/C No internal connection.

Leave unconnected

14 YOUT Y direction output voltage.

15 XOUT X direction output voltage.

16 N/C No internal connection.

Leave unconnected.

Top View

1516 14 13

5678

g-Select1

N/C

N/Cg-Select2

VDD

VSS

N/C

N/CN/C

N/C

XOUT

YOUT

Sleep Mode

VDD

VSS

0.1 μF

VDD

0.1 μF

12 XOUT

YOUT

1 kΩ

Logic

Input

Logic

Inputs

g-Select2

g-Select1

MMA6270QT

POWER SUPPLY

VDD

VSS

Sleep Mode

g-Select1

g-Select2

OUT

Accelerometer

VDD

VSS

VRH

A/DIN

CCC

Microcontroller

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1516 14 13

5678

DYNAMIC ACCELERATION

-Y

-X

Top View

16-Pin QFN Package

STATIC ACCELERATION

Direction of Earth’s gravity field.*

OUT

@ 0g = 1.65V

OUT

@ -1g = 0.85V

XOUT @ -1g = 0.85 V

YOUT @ 0g = 1.65 V

XOUT @ 0g = 1.65 V

YOUT @ +1g = 2.45 V

XOUT @ +1g = 2.45 V

YOUT @ 0g = 1.65 V

* When positioned as shown, the Earth’s gravity will result in a positive 1g output.

Side View

Top

Bottom

: Arrow indicates direction of mass movement.

Top View

Side View

XOUT @ 0g = 1.65 V

YOUT @ 0g = 1.65 V

XOUT @ 0g = 1.65 V

YOUT @ 0g = 1.65 V

(For reference only)

Z direction

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MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS

Surface mount board layout is a critical portion of the total

design. The footprint for the surface mount packages must be

the correct size to ensure proper solder connection interface

between the board and the package.

With the correct footprint, the packages will self-align when

subjected to a solder reflow process. It is always

recommended to design boards with a solder mask layer to

avoid bridging and shorting between solder pads.

The flag underneath the package is internally connected to

ground. It is not recommended for the flag to be soldered

down.

Figure 7. PCB Footprint for 16-Lead QFN, 6x6 mm for

Consumer Grade Products and Applications

Pin 1 ID

(non-metallic)

Note: The die pad (flag) is not generally recommended to be

soldered down for consumer product application. All dimensions

are in mm.

Do not solder down

flag and 4 corner

ground pads on the

package for

consumer application

Do not place any top

metal patterns or via

structures beneath

the package

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PCB DESIGN GUIDELINES

The following are the recommended guidelines to follow

for mounting QFN sensors for either automotive or consumer

applications.

1. NSMD (Non Solder Mask Defined) is shown in

Figure 8.

2. Solder mask opening = PCB land pad +0.1 mm.

3. Stencil aperture size = PCB land pad – 0.025mm, as

shown in Figure 9 with a 6 mil stencil.

4. Do not place insertion components or vias at a

distance less than 2mm from the package land area.

5. Signal trace connected to pads should be as

symmetric as possible. Put dummy traces if there is

NC pads, in order to have same length of exposed

trace for all pads. Signal traces with 0.1mm width and

min. 0.5mm length for all PCB land pad near package

are recommended as shown in Figure 8 and

Figure 9. Wider trace can be continued after the

0.5mm zone.

6. Use a standard pick and place process and

equipment (no hand soldering process).

7. It is recommended to use a cleanable solder paste

with an additional cleaning step after SMT mount

8. It is recommended to avoid screwing down the PCB

to fix it into an enclosure since this may cause the

PCB to bend.

9. PC boards should be rated for multiple reflow of lead-

free conditions with 260°C maximum temperature.

Figure 8. NSMD Solder Mask Design Guidelines

Figure 9. Stencil Design Guidelines

0.55 mm

0.50 m

Packag e Pad PCB l and pattern - NSMD

Cu: 0. 55 x 0.50 mm sq .

So lder ma sk open ing =

PCB land pad +0.1mm

=0.65x0. 60 mm sq.

Signal trace 0. 1mm wid t h

and 0.5mm (min) length near

pac kage. Wi der trace can be

continued after these traces.

Stencil opening (black) for land pad (yellow)

= PCB landing pad -0.025mm

= 0. 5 25mmx 0,475mm

Package foot pirnt

Signal tr ace near package : 0.1mm w idth and

0.5mm (m in) length are recom m ended near

package. Wider trace can be continued after

these.

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MMA6270QT

PACKAGE DIMENSIONS

CASE 1622-02

ISSUE B

16-LEAD QFN

PAGE 1 OF 3

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MMA6270QT

PACKAGE DIMENSIONS

CASE 1622-02

ISSUE B

16-LEAD QFN

PAGE 2 OF 3

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MMA6270QT

PACKAGE DIMENSIONS

CASE 1622-02

ISSUE B

16-LEAD QFN

PAGE 3 OF 3

MMA6270QT

Rev 4

04/2008

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