CY7C1339
Document #: 38-05084 Rev. ** Page 4 of 16
Introduction
Functional Overview
All syn chrono us in puts p ass through input regist ers co ntrolle d
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. Max-
imum access delay from the clock rise (tCO) is 3.5 ns (166-MHz
device).
The CY7C1339 supports secondary cache in systems utilizing
either a linear or interleaved burst sequence. The interleaved
burst o rder supp orts Pentium an d i 48 6 p roc es so rs. The linear
burst sequence is suited for processors that utilize a linear
burst s equ enc e. The bu rst order is user se lec tab le, and is d e-
termined by sampling the MODE input. Accesses can be initi-
ated with either the Processor Address Strobe (ADSP) or the
Controller Address Strobe (ADSC). Address advancement
through the burst sequence is controlled by the ADV input. A
two-bit on-chip wraparound burst counter captu res the first ad-
dress in a burst sequence and automatically increments the
address for the rest of the burst access.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byt e Write S elect (BW[3:0]) inputs. A Global Write
Enable (G W) overri des all byte write inp uts and wri tes data to
all four bytes. All writes are simplified with on-chip synchro-
nous self- t imed w rite ci rcu itry.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynch ro nous Ou tp ut En able ( O E) provide for easy bank se-
lection and output three-state control. ADSP is ignored if CE1
is HIGH.
Single Read Accesses
This access is initiated when the following conditions are sat-
isfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
CE1, CE2, CE3 are all asse rted active, and (3) the writ e signals
(GW, BWE) are all deserted HIGH. ADSP is ignored if CE1 is
HIGH. T he address prese nted to the ad dress inputs (A [16:0]) is
stored into the address advancement logic and the Address
Register while being presented to the memory core. The cor-
responding data is allowed to propagate to the input of the
Output Registers. At the ris ing edge of th e nex t clo ck t he da ta
is allowed to propagate through the output register and onto
the data bus within 3.5 ns (166-MHz device) if OE is active
LOW . The only exception occurs when the SRAM is emerging
from a deselected state to a selected state, its outputs are
always three-stated during the first cycle of the access. After
the f irs t cy cl e of t h e a cc ess, t h e ou t pu ts a r e co nt ro ll e d by the
OE signal. Consecutive single read cycles are supported.
Once the SRAM is deselected at clock rise by the chip select
and either ADSP or ADSC signals, its output will three-state
immediately.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and (2)
CE1, CE2, CE3 are all asserted active. The addres s presented
to A[16:0] is loaded into the address register and the address
advancement logic while being delivered to the RAM core. The
write signals (GW, BW E , and BW[3:0]) and ADV inputs are ig-
nored during this first cycle.
ADSP-triggered write accesses require two clock cycles to
complete. If GW is as serted LOW on the second clock rise, the
data presented to the DQ[31:0] inputs is written into the corre-
sponding address location in the RAM core. If GW is HIGH,
then the wr ite opera tion is c ontroll ed by BWE and BW[3:0] sig-
nals. The CY7C1339 provides byte write capability that is de-
scribed in the Write Cycle Descriptions table. Asserting the
Byte Write Enable input (BWE) with the selected Byte Write
(BW[3:0]) input will selectively write to only the desired bytes.
Bytes not selected during a byte write operation will remain
unaltered. A synchronous self-timed write mechanism has
been provided to simplify the write operations.
Because the CY7C1339 is a common I/O device, the Output
Enable (OE) must be deserted HIGH bef ore pres enting d ata
to the DQ[31:0] inputs. Doing so will three -state th e output driv-
ers. As a safety precaution, DQ[31:0] are automatically
three- stated whe never a wr ite cycle is detecte d, regardl ess of
the state of OE.
Single Write Accesses Initiated by ADSC
ADSC write accesses are initiated when the following condi-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deserted HIGH, (3) CE 1, CE2, CE3 are all asserted active, and
(4) the ap propriate c ombination of the wri te inputs (GW , BWE ,
and BW[3:0]) are asserted active to conduct a write to the de-
sired byte(s ). ADSC- triggered write acces ses requ ire a singl e
clock cycle to complete. The address presented to A[16:0] is
loaded into the address register and the address advance-
ment logic while being delivered to the RAM core. The ADV
input is ignored during this cycle. If a globa l write is conducted,
the data presented to the DQ[31:0] is written into the corre-
sponding address location in the RAM core. If a byte write is
conducted, only the selected bytes are written. Bytes not se-
lected during a byte write operation will remain unaltered. A
synchronous self-timed write mechanism has been provided
to simplify the write operations.
Because the CY7C1339 is a common I/O device, the Output
Enable (OE) must be deserted HIGH bef ore pres enting d ata
to the DQ[31:0] inputs. Doing so will three -state th e output driv-
ers. As a safety precaution, DQ[31:0] are automatically
three- stated whe never a wr ite cycle is detecte d, regardl ess of
the state of OE.
Burst Sequences
The CY7C13 39 provides a two-bi t wraparound cou nter , fed by
A[1:0], that implements either an interlea ved or li near bu rst se-
quence. The interleaved burst sequence is designed specifi-
cally to support Intel Pentium applications. The linear burst
sequence is designed to support processors that follow a lin-
ear burst sequence. The burst sequence is user selectable
through the MODE input.
Asserting ADV LOW at clock ri se will automatic al ly in crement
the burst counter to the next address in the burst sequence.
Both read and write burst operations are supported.
Interleaved Burst Sequence
First
Address Second
Address Third
Address Fourth
Address
A[1:0] A[1:0] A[1:0] A[1:0]
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00