● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
VP2106
P-Channel Enhancement-Mode
Vertical DMOS FET
Absolute Maximum Ratings
Parameter Value
Drain-to-source voltage BVDSS
Drain-to-gate voltage BVDGS
Gate-to-source voltage ±20V
Operating and storage temperature -55OC to +150OC
Soldering temperature* 300OC
Absolute Maximum Ratings are those values beyond which damage to the device
may occur. Functional operation under these conditions is not implied. Continuous
operation of the device at the absolute rating level may affect device reliability. All
voltages are referenced to device ground.
* Distance of 1.6mm from case for 10 seconds.
Ordering Information
Device Package Option BVDSS/BVDGS
(V)
RDS(ON)
(max)
(Ω)
ID(ON)
(min)
(mA)
TO-92
VP2106 VP2106N3-G -60 12 -500
-G indicates package is RoHS compliant (‘Green’)
TO-92 (N3)
Product Marking
TO-92 (N3)
YY = Year Sealed
WW = Week Sealed
= “Green” Packaging
SiVP
2106
Y Y W W
Features
Free from secondary breakdown
Low power drive requirement
Ease of paralleling
Low CISS and fast switching speeds
High input impedance and high gain
Excellent thermal stability
Integral source-to-drain diode
Applications
Motor controls
Converters
Amplifiers
Switches
Power supply circuits
Drivers (relays, hammers, solenoids, lamps,
memories, displays, bipolar transistors, etc.)
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General Description
The Supertex VP2106 is an enhancement-mode (normally-
off) transistor that utilizes a vertical DMOS structure
and Supertex’s well-proven silicon-gate manufacturing
process. This combination produces a device with the
power handling capabilities of bipolar transistors, and the
high input impedance and positive temperature coefficient
inherent in MOS devices. Characteristic of all MOS
structures, this device is free from thermal runaway and
thermally-induced secondary breakdown.
Supertex’s vertical DMOS FETs are ideally suited to a
wide range of switching and amplifying applications where
very low threshold voltage, high breakdown voltage, high
input impedance, low input capacitance, and fast switching
speeds are desired.
GATE
SOURCE
DRAIN
Pin Configuration
Package may or may not include the following marks: Si or
2
VP2106
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
Electrical Characteristics (TA = 25OC unless otherwise specified)
Sym Parameter Min Typ Max Units Conditions
BVDSS Drain-to-source breakdown voltage -60 - - V VGS = 0V, ID = -1.0mA
VGS(th) Gate threshold voltage -1.5 - -3.5 V VGS = VDS, ID= -1.0mA
ΔVGS(th) Change in VGS(th) with temperature - 5.8 6.5 mV/OC VGS = VDS, ID= -1.0mA
IGSS Gate body leakage - -1.0 -100 nA VGS = ± 20V, VDS = 0V
IDSS Zero gate voltage drain current
- - -10 µA VGS = 0V, VDS = Max Rating
- - -1.0 mA VDS = 0.8 Max Rating,
VGS = 0V, TA = 125°C
ID(ON) On-state drain current -0.5 -1.0 - A VGS = -10V, VDS = -25V
RDS(ON) Static drain-to-source on-state resistance - 11 15 ΩVGS = -5.0V, ID = -100mA
- 9.0 12 VGS = -10V, ID = -500mA
ΔRDS(ON) Change in RDS(ON) with temperature - 0.55 1.0 %/OC VGS = -10V, ID = -500mA
GFS Forward transductance 150 200 - mmho VDS = -25V, ID = -500mA
CISS Input capacitance - 45 60
pF
VGS = 0V,
VDS = -25V,
f = 1.0MHz
COSS Common source output capacitance - 22 30
CRSS Reverse transfer capacitance - 3.0 8.0
td(ON) Turn-on delay time - 4.0 5.0
ns
VDD = -25V,
ID = -500mA,
RGEN = 25Ω
trRise time - 5.0 8.0
td(OFF) Turn-off delay time - 5.0 9.0
tfFall time - 4.0 8.0
VSD Diode forward voltage drop - -1.2 -2.0 V VGS = 0V, ISD = -500mA
trr Reverse recovery time - 400 - ns VGS = 0V, ISD = -500mA
Notes:
All D.C. parameters 100% tested at 25OC unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)
All A.C. parameters sample tested.
1.
2.
Notes:
† ID (continuous) is limited by max rated Tj .
Thermal Characteristics
Package
ID
(continuous)†
(mA)
ID
(pulsed)
(mA)
Power Dissipation
@TA = 25OC
(W)
θjc
(OC/W)
θja
(OC/W)
IDR
†
(mA)
IDRM
(mA)
TO-92 -250 -800 0.74 125 170 -250 -800
Switching Waveforms and Test Circuit
90%
10%
90% 90%
10%
10%
PULSE
GENERATOR
V
DD
R
L
Output
D.U.T.
t(ON)
td(ON)
t(OFF)
td(OFF) tF
tr
INPUT
INPUT
OUTPUT
0V
V
DD
R
GEN
0V
-10V
3
VP2106
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
Typical Performance Curves
Output Characteristics
-2.0
-1.6
-1.2
-0.8
-0.4
0
Saturation Characteristics
-1.0
-0.8
-0.6
-0.4
-0.2
-0
Maximum Rated Safe Operating Area
-0.1 -100-10-1.0
-0.01
-0.1
-1.0
-0.001
Thermal Response Characteristics
)d
e
zilamro
n(
ecn
a
tsise
R
lamr
e
hT
1.0
0.8
0.6
0.4
0.2
0
0.001 100.01 0.1 1.0
Transconductance vs. Drain Current Power Dissipation vs. Ambient Temperature
0 15010050
1.0
0.5
0
1257525
VDS = 25V
TO-92 (DC)
0 -10 -20 -30 -50-40 0 -2 -4 -6 -10-8
TO-92 (pulsed)
250
200
150
100
50
0
0 -0.2 -0.4 -0.6 -1.0-0.8
-7V
-6V
-5V
-4V
-3V
-9V
-7V
-6V
-5V
-4V
-8V
-9V
T
A
= 25°C
TO-92
P
D
= 1.0W
T
A
= 25°C
TO-92
VGS = -10V
VDS (volts)
ID)sere
p
m
a(
ID)serepma(
VDS (volts)
VGS = -10V
GSF )sne
m
ei
si
llim(
ID (amperes) TA (°C)
PD)sttaw(
T
A
= 125°C
T
A
= 25°C
T
A
= -55°C
VDS (volts)
ID)ser
e
pma(
tp (seconds)
-8V
4
VP2106
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
Typical Performance Curves (cont.)
Gate Drive Dynamic Characteristics
On-Resistance vs. Drain Current
Transfer Characteristics
Capacitance vs. Drain-to-Source Voltage
100
75
50
25
0
)sdarafocip
(
C
0 -10 -20 -30 -40
0 -2 -4 -6 -8 -10
-1.0
-0.8
-0.6
-0.4
-0.2
0
-50 0 50 100 150
-1.1
-1.0
20
16
12
8
4
0
1.4
1.2
1.0
0.8
0.6
-10
-8
-6
-4
-2
0
-50 0 50 100 150
35 pF
VGS = -10V
125°C
0 -0.2 -0.4 -0.6 -1.0-0.8
f = 1MHz
C
ISS
C
OSS
C
RSS
-0.9
101 pF
2.0
1.6
1.2
0.8
0.4
0
V(th)@ 1mA
RDS(ON) @ -10V, 0.5A
25°C
0
1.0 2.0
R)NO(SD )smho(
V
BSSD )d
e
zi
lam
ro
n(
Tj (°C) ID (amperes)
BVDSS Variation with Temperature
VGS = -5V
Tj (°C)
V)
h
t(SG )dezilamron(
V(th) and RDS Variation with Temperature
VGS (volts)
ID)ser
e
p
m
a(
R)NO(SD )dezilamron(
VDS = -25V
T
A
= -55
°C
QG (nanocoulombs)
VSG )stlov(
VDS (volts)
VDS = -40V
VDS = -10V
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an
adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the
replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications
are subject to change without notice. For the latest product specifications refer to the Supertex inc. website: http//www.supertex.com.
©2009 All rights reserved. Unauthorized use or reproduction is prohibited.
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
www.supertex.com
5
VP2106
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline
information go to http://www.supertex.com/packaging.html.)
Doc.# DSFP-VP2106
A012409
3-Lead TO-92 Package Outline (N3)
Symbol A b c D E E1 e e1 L
Dimensions
(inches)
MIN .170 .014†.014†.175 .125 .080 .095 .045 .500
NOM - - - - - - - - -
MAX .210 .022†.022†.205 .165 .105 .105 .055 .610*
JEDEC Registration TO-92.
* This dimension is not specified in the original JEDEC drawing. The value listed is for reference only.
† This dimension is a non-JEDEC dimension.
Drawings not to scale.
Supertex Doc.#: DSPD-3TO92N3, Version D080408.
Seating Plane
1
2
3
Front View Side View
Bottom View
E1 E
D
e1
L
e
c
1 2 3
b
A
