1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
M38277M8MXXXFP
SEG9
P31/SEG19
P30/SEG18
P32/SEG20
P33/SEG21
P34/SEG22
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
P35/SEG23
P36/SEG24
P37/SEG25
P00/SEG26
P01/SEG27
P02/SEG28
P03/SEG29
P04/SEG30
P05/SEG31
P06/SEG32
P07/SEG33
P10/SEG34
P11/SEG35
P12/SEG36
P13/SEG37
P14/SEG38
P15/SEG39
C1
VL1
P67/AN7
P66/AN6
P65/AN5
P64/AN4
P62/SCLK21/AN2
P61/SOUT2/AN1
P60/SIN2/AN0
P57/DA2
P56/DA1
P55/CNTR1
P54/CNTR0
P53/RTP1
P52/RTP0
P51/PWM1
P50/PWM0
P46/SCLK1
P45/TXD
P44/RXD
P43/φ/TOUT
P42/INT2
P41/INT1
P40/ADT
P77
P76
P75
P74
C2
VL2
VL3
COM0
COM1
COM2
VREF
AVSS
VCC
SEG8
SEG0
SEG1
SEG2
SEG4
SEG5
SEG6
SEG7
SEG3
P72
P73
P71
P70/INT0
XCIN
XCOUT
XIN
XOUT
VSS
P27
P26
P25
P24
P23
P21
P16
P22
P20
P17
RESET
SEG16
SEG17
COM3
P47/SRDY1
P63/SCLK22/AN3
DESCRIPTION
The 3827 group is the 8-bit microcomputer based on the 740 fam-
ily core technology.
The 3827 group has the LCD drive control circuit, the A-D/D-A
converter, the UART, and the PWM as additional functions.
The various microcomputers in the 3827 group include variations
of inter nal memory size and packaging. For details, refer to the
section on part numbering.
For details on availability of microcomputers in the 3827 group, re-
fer to the section on group expansion.
FEATURES
●Basic machine-language instr uctions ...................................... 71
●The minimum instruction execution time ...........................0.5 µs
(at 8MHz oscillation frequency)
●Memory siz e
RO M ................................................................. 4 K to 60 K bytes
RAM................................................................. 192 to 2048 bytes
●Prog rammable input/output ports ............................................ 55
●Output port ................................................................................. 8
●Input port .................................................................................... 1
●Interrupts ................................................. 17 sources, 16 vectors
(includes key input interrupt)
●Timers...........................................................8-bit ✕ 3, 16-bit ✕ 2
●Serial I/O1 ....................8-bit ✕ 1 (UART or Clock-synchronized)
●Serial I/O2 ...................................8-bit ✕ 1 (Clock-synchronized)
●PWM output.................................................................... 8-bit ✕ 1
●A-D converter ............................................... 10-bit ✕ 8 channels
●D-A converter ................................................. 8-bit ✕ 2 channels
●LCD drive control circuit
Bias...................................................................................1/2, 1/3
Duty ...........................................................................1/2, 1/3, 1/4
Common output.......................................................................... 4
Segment output ........................................................................ 40
●2 Clock generating circuits
(connect to external ceramic resonator or quartz-cr ystal oscillator)
●Watchdog timer ............................................................ 14-bit ✕ 1
●Power source voltage ................................................ 2.2 to 5.5 V
●Power dissipation
In high-speed mode ..........................................................40 mW
(at 8 MHz oscillation frequency, at 5 V power source voltage)
In low-speed mode............................................................ 60 µW
(at 32 kHz oscillation frequency, at 3 V power source voltage)
●Operating temperature range................................... – 20 to 85°C
APPLICATIONS
Camera, wireless phone, etc.
3827 Group
MITSUBISHI MICROCOMPUTERS
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Fig. 1 M38277M8MXXXFP pin configuration
PIN CONFIGURATION (TOP VIEW)
Package type : 100P6S-A (100-pin plastic-molded QFP)
2
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
3827 Group
MITSUBISHI MICROCOMPUTERS
M38277M8MXXXGP
M38277M8MXXXHP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
P50/PWM0
P47/SRDY1
P57/DA2
P46/SCLK1
P44/RXD
P43/φ/TOUT
P42/INT2
P54/CNTR0
P52/RTP0
P53/RTP1
P51/PWM1
P55/CNTR1
P67/AN7
P66/AN6
P65/AN5
P64/AN4
P63/SCLK22/AN3
P62/SCLK21/AN2
P61/SOUT2/AN1
P60/SIN2/AN0
P45/TXD
P41/INT1
P40/ADT
P77
31
32
33
34
35
36
37
38
39
40
41
42
49
50
43
44
45
46
47
48
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
59
58
57
60
56
54
53
52
55
51
SEG13
SEG14
SEG15
SEG16
SEG17
P30/SEG18
P31/SEG19
P32/SEG20
P33/SEG21
P34/SEG22
P35/SEG23
P36/SEG24
P37/SEG25
P01/SEG27
P02/SEG28
P03/SEG29
P04/SEG30
P05/SEG31
P06/SEG32
P07/SEG33
P12/SEG36
P13/SEG37
P00/SEG26
P10/SEG34
P11/SEG35
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
100 26
27
28
29
30
P70/INT0
XIN
XOUT
VSS
P27
P26
P25
P24
P23
P22
P21
P20
RESET
XCOUT
XCIN
P17
P16
P71
P72
P73
P74
P75
P76
P15/SEG39
P14/SEG38
76
77
78
79
80
VCC
SEG6
SEG7
SEG5
SEG3
SEG4
SEG2
SEG1
SEG0
VREF
AVSS
COM2
COM3
COM1
COM0
VL3
SEG8
SEG9
VL2
C2
C1
VL1
SEG10
SEG11
SEG12
P56/DA1
Package type : GP........ 100P6Q-A (100-pin plastic-molded LQFP)
Package type : HP........ 100PFB-A (100-pin plastic-molded TQFP)
PIN CONFIGURATION (TOP VIEW)
Fig. 2 M38277M8MXXXGP/M38277M8MXXXHP pin configuration
3
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3827 Group
FUNCTIONAL BLOCK DIAGRAM
Fig. 3 Functional block diagram
Key input/key-on wake-up interrupt
INT1,INT2
CNTR0,CNTR1
DA1
DA2TOUT
INT0
ADT
Data bus
C P U
A
X
Y
S
PCHPCL
PS
RESET VCC VSS
Reset input ( 5 V ) ( 0 V )
R O M R A M
LCD display
RAM
(20 bytes)
I/O port P5
P4(8)
I/O port P4 I/O port P2
P2(8)
I/O port P0
P0(8)
I/O port P1
P1(8)
P6(8)
I/O port P7
P7(8)
Output port P3
P3(8)
I/O port P6
P5(8)
Sub-clock input
Sub-clock output
XCIN XCOUT
Clock generating circuit
XIN OUT
X
Main clock input Main clock output
COUT
X
XCIN
Sub-clock output
Sub-clock input
SI/O1 (8)
VREF
AVSS
A-D converter
(10)
Timer X(16)
Timer Y(16)
Timer 1(8) Timer 2(8)
Timer 3(8)
LCD drive
control circuit
VL1
C1
C2
VL2
VL3
COM0
COM1
COM2
COM3
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
φ
XCIN COUT
X
SI/O2(8)
Watchdog timer Reset
PWM(8)
φ
Real time port function
D-A2 D-A1
4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
3827 Group
MITSUBISHI MICROCOMPUTERS
PIN DESCRIPTION
Table 1 Pin description (1)
VCC, VSS
FunctionPin Name Function except a port function
•LCD segment output pins
Power source •Apply voltage of 2.2 V to 5.5 V to VCC, and 0 V to VSS.
VREF
AVSS
RESET
XIN
XOUT
VL1–VL3
C1, C2
COM
0
–COM
3
SEG
0
–SEG
17
P00/SEG26–
P07/SEG33
P10/SEG34–
P15/SEG39
P16, P17
P20 – P27
P3
0
/SEG
18
–
P3
7
/SEG
25
Analog refer-
ence voltage
Analog power
source
Reset input
Clock input
Clock output
LCD power
source
Charge-pump
capacitor pin
Common output
Segment output
I/O port P0
I/O port P1
I/O port P2
Output port P3
•Reference voltage input pin for A-D converter and D-A converter.
•GND input pin for A-D converter and D-A converter.
•Connect to VSS.
•Reset input pin for active “L”.
•Input and output pins for the main clock generating circuit.
•Connect a cer amic resonator or a quartz-crystal oscillator between the XIN and XOUT pins to set
the oscillation frequency.
•If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.
•Input 0 ≤ VL1 ≤ VL2 ≤ VL3 ≤ VCC voltage.
•Input 0 – VL3 voltage to LCD.
•External capacitor pins for a voltage multiplier (3 times) of LCD contorl.
•LCD common output pins.
•COM2 and COM3 are not used at 1/2 duty ratio.
•COM3 is not used at 1/3 duty ratio.
•LCD segment output pins.
•8-bit output port.
•CMOS compatible input level.
•CMOS 3-state output structure.
•Pull-up control is enabled.
•I/O direction register allows each por t to be individually
programmed as either input or output.
•6-bit output port with same function as port P0.
•CMOS compatible input level.
•CMOS 3-state output structure.
•Pull-up control is enabled.
•I/O direction register allows each 6-bit pin to be pro-
grammed as either input or output.
•2-bit I/O port.
•CMOS compatible input level.
•CMOS 3-state output structure.
•I/O direction register allows each pin to be individually programmed as either input or output.
•Pull-up control is enabled.
•8-bit I/O por t with same function as port P0.
•CMOS compatible input level.
•CMOS 3-state output structure.
•Pull-up control is enabled.
•8-bit output port with same function as port P0.
•CMOS 3-state output structure.
•Port output control is enab led.
•Key input (key-on wake-up) interrupt
input pins
•LCD segment output pins
5
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3827 Group
Table 2 Pin description (2)
FunctionPin Name Function except a port function
•A-D trigger input pin
•Interrupt input pin
P40/ADT
P41/INT1,
P42/INT2
P43/φ/TOUT
P44/RXD,
P45/TXD,
P46/SCLK1,
P47/SRDY1
P50/PWM0,
P51/PWM1
P52/RTP0,
P53/RTP1
P54/CNTR0,
P55/CNTR1
P56/DA1,
P57/DA2
P6
0
/AN
0
/S
IN2,
P6
1
/AN
1
/S
OUT2,
P6
2
/AN
2
/S
CLK21,
P6
3
/AN
3
/S
CLK22
P64/AN4–
P67/AN7
P70/INT0
P71–P77
XCOUT
XCIN
I/O port P4
I/O port P5
I/O port P6
Input port P7
I/O port P7
Sub-clock output
Sub-clock input
•1-bit I/O port with same function as P16 and P17.
•CMOS compatible input level.
•CMOS 3-state output structure.
•7-bit I/O port with same function as P16 and P17.
•CMOS compatible input level.
•CMOS 3-state output structure.
•Pull-up control is enabled.
•8-bit I/O port with same function as P16 and P17.
•CMOS compatible input level.
•CMOS 3-state output str ucture.
•Pull-up control is enabled.
•8-bit I/O port with same function as P16 and P17.
•CMOS compatible input level.
•CMOS 3-state output str ucture.
•Pull-up control is enabled.
•1-bit I/O port.
•CMOS compatible input level.
•7-bit I/O port with same function as P16 and P17.
•CMOS compatible input level.
•N-channel open-dr ain output str ucture.
•Sub-clock generating circuit I/O pins.
(Connect a resonator. External clock cannot be used.)
•Interrupt input pins
•φ clock output pin
•Timer 2 output pin
•Serial I/O1 I/O pins
•PWM function pins
•Real time port function pins
•Timer X, Y function pins
•D-A conversion output pins
•A-D conversion input pins
•Serial I/O2 I/O pins
•A-D conversion input pins
•Interrupt input pin
6
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
3827 Group
MITSUBISHI MICROCOMPUTERS
M3827 7 M 8 M XXX HP
Product
ROM/PROM size
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
: 4096 bytes
: 8192 bytes
: 12288 bytes
: 16384 bytes
: 20480 bytes
: 24576 bytes
: 28672 bytes
: 32768 bytes
: 36864 bytes
: 40960 bytes
: 45056 bytes
: 49152 bytes
: 53248 bytes
: 57344 bytes
: 61440 bytes
The first 128 bytes and the last 2 bytes of ROM
are reserved areas ; they cannot be used.
Memory type
M
E : Mask ROM version
: EPROM or One Time PROM version
RAM size
0
1
2
3
4
5
6
7
8
9
: 192 bytes
: 256 bytes
: 384 bytes
: 512 bytes
: 640 bytes
: 768 bytes
: 896 bytes
: 1024 bytes
: 1536 bytes
: 2048 bytes
ROM number
Omitted in some types.
Normally, using hyphen
When electrical characteristic, or division of quality
identification code using alphanumeric character.
– : Standard
M : Low power source version
Package type
FP
HP
GP
FS
: 100P6S-A package
: 100PFB-A package
: 100P6Q-A package
: 100D0 package
PART NUMBERING
Fig. 4 Part numbering
7
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3827 Group
GROUP EXPANSION
Mitsubishi plans to expand the 3827 group as follows:
Memory Type
Support f or Mask ROM, One Time PROM, and EPROM versions
Memor y Size
ROM/PROM size ................................................. 4 K to 60 K bytes
RAM size ............................................................192 to 2048 bytes
Package
100PFB-A ................................0.4 mm-pitch plastic molded TQFP
100P6Q-A ................................0.5 mm-pitch plastic molded LQFP
100P6S-A ................................0.65 mm-pitch plastic molded QFP
100D0 ..................... Window type ceramic LCC (EPROM version)
Currently supported products are listed below.
Memor y Expansion Plan
Remarks
Package
Product
As of May 1998
RAM size (bytes)
32768
(32638)
(P) ROM size (bytes)
ROM size for User in ( )
61440
(61310)
Fig. 5 Memory expansion plan
Table 3 List of supported products
M38277M8MXXXFP
M38277M8MXXXHP
M38277M8MXXXGP
M38279EF-XXXFP
M38279EFFP
M38279EF-XXXHP
M38279EFHP
M38279EF-XXXGP
M38279EFGP
M38279EFFS
1024
2048
100P6S-A
100PFB-A
100P6Q-A
100P6S-A
100P6S-A
100PFB-A
100PFB-A
100P6Q-A
100P6Q-A
100D0
Mask ROM version
Mask ROM version
Mask ROM version
One Time PROM version
One Time PROM version (blank)
One Time PROM version
One Time PROM version (blank)
One Time PROM version
One Time PROM version (blank)
EPROM version
Note: Products under development or planning: the development schedule and specifications
may be revised without notice.
ROM size (bytes)
32K
28K
24K
20K
16K
12K
8K
4K
256 384 512 640 768 896 1024
192 RAM size (bytes) 204819201152 1280 1408 1536 1664 1792
36K
40K
44K
48K
52K
56K
60K
Under development
M38277M8M
M38278MCM
Planning
M38279EF
Under development
8
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
3827 Group
MITSUBISHI MICROCOMPUTERS
Not available
Processor mode bits
b1 b0
0 0 : Single-chip mode
0 1 :
1 0 :
1 1 :
Stack page selection bit
0 : 0 page
1 : 1 page
Not used (returns “1” when read)
(Do not write “0” to this bit.)
Port X
C
switch bit
0 : Stop oscillating
1 : X
CIN
, X
COUT
Main clock ( X
IN
-X
OUT
) stop bit
0 : Oscillating
1 : Stopped
Main clock division ratio selection bit
0 : X
IN
/2 (high-speed mode)
1 : X
IN
/8 (middle-speed mode)
Internal system clock selection bit
0 : X
IN
-X
OUT
selected (middle-/high-speed mode)
1 : X
CIN
-X
COUT
selected (low-speed mode)
CPU mode register
(CPUM (CM) : address 003B
16
)
b7 b0
FUNCTIONAL DESCRIPTION
Central Processing Unit (CPU)
The 3827 group uses the standard 740 family instr uction set. Re-
fer to the table of 740 family addressing modes and machine
instructions or the 740 Family Software Manual for details on the
instruction set.
Machine-resident 740 family instructions are as follows:
The FST and SLW instruction cannot be used.
The STP, WIT, MUL, and DIV instr uction can be used.
[CPU Mode Register (CPUM)] 003B16
The CPU mode register contains the stack page selection bit and
the internal system clock selection bit.
The CPU mode register is allocated at address 003B16.
Fig. 6 Structure of CPU mode register
9
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3827 Group
MEMORY
Special Function Register (SFR) Area
The Special Function Register area in the zero page contains con-
trol registers such as I/O ports and timers.
RAM
RAM is used for data storage and for stack area of subroutine
calls and interrupts .
ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the rest is user area for storing progr ams.
Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
Zero Page
Access to this area with only 2 bytes is possible in the zero page
addressing mode.
Special Page
Access to this area with only 2 bytes is possible in the special
page addressing mode.
Fig. 7 Memory map diagram
192
256
384
512
640
768
896
1024
1536
2048
00FF16
013F16
01BF16
023F16
02BF16
033F16
03BF16
043F16
063F16
083F16
RAM area
RAM size
(bytes) Address
XXXX16
4096
8192
12288
16384
20480
24576
28672
32768
36864
40960
45056
49152
53248
57344
61440
F00016
E00016
D00016
C00016
B00016
A00016
900016
800016
700016
600016
500016
400016
300016
200016
100016
F08016
E08016
D08016
C08016
B08016
A08016
908016
808016
708016
608016
508016
408016
308016
208016
108016
ROM area
ROM size
(bytes) Address
YYYY16 Address
ZZZZ16
010016
000016
004016
084016
FF0016
FFDC16
FFFE16
FFFF16
XXXX16
YYYY16
ZZZZ16
RAM
ROM
005416
Reserved area
SFR area
Not used
Interrupt vector area
Reserved ROM area
(128 bytes)
Zero page
Special page
LCD display RAM area
Reserved ROM area
10
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
3827 Group
MITSUBISHI MICROCOMPUTERS
Fig. 8 Memory map of special function register (SFR)
000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
Port P0 (P0)
Port P1 (P1)
Port P1 output control register (P1D)
Port P2 (P2)
Port P2 direction register (P2D)
Port P3 (P3)
Port P4 (P4)
Port P4 direction register (P4D)
Port P5 (P5)
Port P5 direction register (P5D)
Port P6 (P6)
Port P6 direction register (P6D)
Port P7 (P7)
Port P7 direction register (P7D)
Serial I/O1 status register (SIO1STS)
Serial I/O1 control register (SIO1CON)
UART control register (UARTCON)
Baud rate generator (BRG)
PULL register A (PULLA)
PULL register B (PULLB)
Transmit/Receive buffer register(TB/RB)
Port P0 direction register (P0D)
Port P3 output control register (P3C)
Key input control register (KIC)
Serial I/O2 control register (SIO2CON)
Reserved area
Serial I/O2 register (SIO2)
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
003016
003116
003216
003316
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16 Interrupt control register 2(ICON2)
Timer 3 (T3)
Timer X mode register (TXM)
Interrupt edge selection register (INTEDGE)
CPU mode register (CPUM)
Interrupt request register 1(IREQ1)
Interrupt request register 2(IREQ2)
Interrupt control register 1(ICON1)
Timer X (low) (TXL)
Timer Y (low) (TYL)
Timer 1 (T1)
Timer 2 (T2)
Timer X (high) (TXH)
Timer Y (high) (TYH)
Timer Y mode register (TYM)
Timer 123 mode register (T123M)
TOUT/φ output control register (CKCON)
Segment output enable register (SEG)
LCD mode register (LM)
A-D control register (ADCON)
A-D control register (low-order) (ADL)
PWM control register (PWMCON)
PWM prescaler (PREPWM)
PWM register (PWM)
A-D control register (high-order) (ADH)
D-A1 conversion register (DA1)
D-A2 conversion register (DA2)
D-A control register (DACON)
Watchdog timer control register (WDTCON)
11
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3827 Group
I/O PORTS
Direction Registers
The I/O ports ha ve direction registers which determine the input/
output direction of each individual pin. (P00–P07 and P10–P15 use
bit 0 of port P0, P1 direction registers respectively.)
When “1” is written to that bit, that pin becomes an output pin.
When “0” is written to the bit corresponding to a pin, that pin be-
comes an input pin.
If data is read from a pin set to output, the value of the port output
latch is read, not the value of the pin itself. Pins set to input are
floating and the value of that pin can be read. If a pin set to input
is written to, only the port output latch is wr itten to and the pin re-
mains floating.
Port P3 Output Control Register
Bit 0 of the por t P3 output control register (address 000716) en-
ables control of the output of ports P30 to P37.
When the bit is set to “1”, the port output function is valid.
When resetting, bit 0 of the port P3 output control register is set to
“0” (the port output function is invalid.) and por ts P30 to P37 are
pulled up.
Pull-up Control
By setting the PULL register A (address 001616) or the PULL reg-
ister B (address 001716), ports P0 to P6 can control pull-up with a
program.
However, the contents of PULL register A and PULL register B do
not affect ports programmed as the output ports.
The PULL register A setting is invalid for pins set to segment out-
put on the segment output enable register.
Fig. 9 Structure of PULL register A and PULL register B
P00, P01 pull-up
P02, P03 pull-up
P04–P07 pull-up
P10–P13 pull-up
P14, P15 pull-up
P16, P17 pull-up
P20–P23 pull-up
P24–P27 pull-up
PULL register A
(PULLA : address 001616)
b7 b0
P41–P43 pull-up
P44–P47 pull-up
P50–P53 pull-up
P54–P57 pull-up
P60–P63 pull-up
P64–P67 pull-up
Not used (return “0” when read)
0 : No pull-up
1 : Pull-up
PULL register B
(PULLB : address 001716)
b7 b0
Note : The contents of PULL register A and PULL register B
do not affect ports programmed as the output port.
12
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
3827 Group
MITSUBISHI MICROCOMPUTERS
PWM output
DA2 output
DA1 output
A-D VREF input
Diagr am No.
Related SFRs
Input/OutputName
Pin Non-Port Function
I/O Format
Table 4 List of I/O port function (1)
P00/SEG26–
P07/SEG33
P10/SEG34–
P15/SEG39
P16 , P17
P20–P27
P30/SEG18–
P37/SEG25
P40/ADT
P41/INT1,
P42/INT2
P43/φ/TOUT
P44/RXD,
P45/TXD,
P46/SCLK1,
P47/SRDY1
P50/PWM0,
P51/PWM1
P52/RTP0,
P53/RTP1
P54/CNTR0
P55/CNTR1
P56/DA1
P57/DA2
Port P0
Port P1
Port P2
Port P3
Port P4
Port P5
Input/output,
byte unit
Input/output,
6-bit unit
Input/output,
individual bits
Input/output,
individual bits
Output
Input/output,
individual bits
Input/output,
individual bits
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
CMOS 3-state output
CMOS compatible
input level
N-channel open-drain
output
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
LCD segment output
LCD segment output
Key input (key-on
wake-up) interrupt
input
LCD segment output
A-D trigger input
External interrupt input
External interrupt input
Timer output φ output
Ser ial I/O1 function I/O
Real time port
function output
Timer X function I/O
Timer Y function input
PULL register A
Segment output enable
register
PULL register A
Segment output enable
register
PULL register A
PULL register A
Interrupt control register2
Key input control register
PULL register A
Segment output enable
register
P3 output enable register
A-D control register
Interrupt edge selection
register
PULL register B
Interrupt edge selection
register
PULL register B
Timer 123 mode register
TOUT/φ output control
register
PULL register B
Serial I/O1 control register
Serial I/O1 status register
UART control register
PULL register B
PWM control register
PULL register B
Timer X mode register
PULL register B
Timer X mode register
PULL register B
Timer Y mode register
PULL register B
D-A control register
A-D control register
PULL register B
D-A control register
(1)
(2)
(1)
(2)
(4)
(4)
(3)
(13)
(4)
(12)
(5)
(6)
(7)
(8)
(10)
(9)
(11)
(14)
(15)
(15)
13
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3827 Group
Pin Name I/O Format Non-Port Function Related SFRS
Diagr am No.
Input/Output
Notes1: How to use double-function ports as function I/O ports, refer to the applicable sections.
2: Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction. When an input level is at an intermediate po-
tential, a current will flow VCC to VSS through the input-stage gate.
Table 5 List of I/O port function (2)
P60/SIN2/AN0
P61/SOUT2/
AN1
P62/SCLK21/
AN2
P63/SCLK22 /
AN3
P64/AN4–
P67/AN7
P70/INT0
P71–P77
COM0–COM3
SEG0–SEG17
Port P6
Port P7
Common
Segment
Input/
output,
individnal
bits
Input
Input/
output,
individnal
bits
Output
Output
CMOS compatible input
level
CMOS 3-state output
CMOS compatible input
level
CMOS compatible input
level
N-channel open-drain
output
LCD common output
LCD segment output
A-D conversion input
Serial I/O2 function I/O
A-D conversion input
External interrupt input
A-D control register
Ser ial I/O2 control
register
A-D control register
Interrupt edge
selection register
LCD mode register
(17)
(18)
(19)
(20)
(16)
(23)
(13)
(21)
(22)
14
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
3827 Group
MITSUBISHI MICROCOMPUTERS
Fig. 10 Port block diagram (1)
(5) Port P44
(4) Ports P16, P17, P2, P41, P42
Except P16, P17
Data bus
Direction register
Port latch
Pull-up control
Key input interrupt input
INT1, INT2 interrupt input
Serial I/O1 enable bit
Reception enable bit
Serial I/O1 input
Port latch
Pull-up control
(1) Ports P01–P07, P11–P15
Port direction register
Data bus Port latch
Segment data
LCD drive timing
Port/Segment
Segment/Port
Segment
Port
Pull-up
VL1/VSS
VL2/VL3/VCC
Interface logic level
shift circuit
Port direction register
(2) Ports P00, P10
Port direction register
Data bus Port latch
Segment data
LCD drive timing
Port/Segment
Segment/Port
Segment
Port
Pull-up
VL1/VSS
VL2/VL3/VCC
Interface logic level
shift circuit
Direction register
(3) Port P3
Output control
Data bus Port latch
Segment data
LCD drive timing
Port/Segment
Segment/Port
Segment
Port
Pull-up
VL1/VSS
VL2/VL3/VCC
Interface logic level
shift circuit
Data bus
Direction register
15
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3827 Group
Fig. 11 Port block diagram (2)
(6) Port P45(7) Port P46
(8) Port P47
Data bus
Serial I/O1 enable bit
Transmission enable bit
Serial I/O1 output
P45/TxD P-channel output disable bit
Port latch
Direction register
Pull-up control
Serial I/O1 ready output
Data bus Port latch
Serial I/O1 mode selection bit
Serial I/O1 enable bit
SRDY1 output enable bit
Direction register
Pull-up control (9) Ports P52, P53
Data bus Port latch
Real time control bit
Real time port data
Direction register
Pull-up control
Serial I/O1 clock
selection bit
Data bus
Serial I/O1 clock outupt Serial I/O1 clock input
Serial I/O1 mode selection bit
Serial I/O1 enable bit
Port latch
Direction register
Serial I/O1 enable bit Pull-up control
(10) Ports P50,P51
Data bus Port latch
PWM function enable bit
PWM output
Direction register
Pull-up control
(11) Port P54
Port latch
Data bus
Pulse output mode
Timer output
CNTR0 interrupt input
Direction register
Pull-up control
16
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
3827 Group
MITSUBISHI MICROCOMPUTERS
Fig. 12 Port block diagram (3)
(12) Port P43
Port latchData bus
TOUT/φ output control
Timer output
Direction register
Pull-up control
φ output
TOUT/φ selection bit
(13) Ports P40, P71–P77
Port latch
Data bus
Direction register
(14) Port P55
Data bus
Direction register
Port latch
Pull-up control
CNTR1 interrupt input
(15) Ports P56, P57
Data bus
Direction register
Port latch
Pull-up control
D-A conversion output
A-D trigger input
Except P71 to P77
(16) Ports P64–P67
Analog input pin selection bit
A-D conversion input
Data bus Port latch
Direction register
Pull-up control
(17) Port P60
Data bus Port latch
Direction register
Pull-up control
Serial I/O2 input
D-A1, D-A2 output enable bit
VREF input switch
VREF input selection bit
Except P57
A-D conversion input
Analog input pin selection bit
17
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3827 Group
Fig. 13 Port block diagram (4)
(18) Port P61(19) Port P62
(20) Port P63
Data bus
Serial I/O2 output
Port latch
Serial I/O2 transmit completion signal
Synchronous clock selection bit
Serial I/O2 port selection bit
Direction register
Pull-up control
Analog input pin selection bit
A-D conversion input
P61/SOUT2 P-channel output disable bit
(21) COM0–COM3
(22) SEG0–SEG17
VL3
VL2
VL1
VSS
VL2/VL3
VL1/VSS
The gate input signal of each
transistor is controlled by the
LCD duty ratio and the bias
value.
The voltage applied to the sources of
P-channel and N-channel transistors
is the controlled voltage by the bias
value.
(23) Port P70
Data bus Port latch
Direction register
INT0 input
Synchronous clock selection bit
Data bus
Serial I/O2 clock output Serial I/O2 clock input
Port latch
Direction register
Data bus Port latch
Direction register
Synchronous clock selection bit
Serial I/O2 port selection bit
Synchronous clock output pin selection bit
Pull-up control
Synchronous clock output pin
selection bit
Serial I/O2 port selection bit
Pull-up control
Analog input pin selection bit
A-D conversion input
Serial I/O2 clock output
Analog input pin selection bit
A-D conversion input
18
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
3827 Group
MITSUBISHI MICROCOMPUTERS
INTERRUPTS
Interrupts occur by seventeen sources: seven external, nine inter-
nal, and one software.
Interrupt Control
Each interr upt except the BRK instruction interrupt have both an
interrupt request bit and an interrupt enable bit, and is controlled
by the interrupt disable flag. An interrupt occurs if the correspond-
ing interrupt request and enable bits are “1” and the interrupt
disable flag is “0.” Interrupt enable bits can be set or cleared by
software. Interrupt request bits can be cleared by software, but
cannot be set by software. The BRK instruction interr upt and reset
cannot be disabled with any flag or bit. The I flag disables all inter-
rupts except the BRK instruction interrupt and reset. If several
interrupts requests occurs at the same time the interrupt with high-
est priority is accepted first.
Interrupt Operation
Upon acceptance of an interrupt the following operations are auto-
matically performed:
1. The contents of the program counter and processor status
register are automatically pushed onto the stack.
2. The interrupt disable flag is set and the corresponding
interr upt request bit is cleared.
3. The interrupt jump destination address is read from the vec-
tor table into the program counter.
■Notes
When the active edge of an external interrupt (INT0–INT2, CNTR0,
CNTR1) is set or when switching interrupt sources of ADT/A-D
conversion interrupt, the corresponding interrupt request bit may
also be set. Therefore, take following sequence:
(1) Disable the external interrupt which is selected.
(2) Change the active edge in interrupt edge selection register
(timer XY mode register when using CNTR0, CNTR1)
(3) Clear the set interrupt request bit to “0.”
(4) Enable the external interrupt which is selected.
Notes1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
Table 6 Interrupt vector addresses and priority
Remarks
Interrupt Request
Generating Conditions
At reset
At detection of either rising or
falling edge of INT0 input
At detection of either rising or
falling edge of INT1 input
At completion of serial I/O1 data
reception
At completion of serial I/O1
transmit shift or when transmis-
sion buffer is empty
Interr upt Source LowHigh
Priority Vector Addresses (Note 1)
Reset (Note 2)
INT0
INT1
Ser ial I/O1
reception
Ser ial I/O1
transmission
Timer X
Timer Y
Timer 2
Timer 3
CNTR0
CNTR1
Timer 1
INT2
Ser ial I/O2
Key input
(Key-on wake-up)
ADT
A-D conversion
BRK instruction
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
FFFD16
FFFB16
FFF916
FFF716
FFF516
FFF316
FFF116
FFEF16
FFED16
FFEB16
FFE916
FFE716
FFE516
FFE316
FFE116
FFDF16
FFDD16
FFFC16
FFFA16
FFF816
FFF616
FFF416
FFF216
FFF016
FFEE16
FFEC16
FFEA16
FFE816
FFE616
FFE416
FFE216
FFE016
FFDE16
FFDC16
At timer X underflow
At timer Y underflow
At timer 2 underflow
At timer 3 underflow
At detection of either rising or
falling edge of CNTR0 input
At detection of either rising or
falling edge of CNTR1 input
At timer 1 underflow
At detection of either rising or
falling edge of INT2 input
At completion of serial I/O2 data
transmission or reception
At falling of conjunction of input
level for port P2 (at input mode)
At falling of ADT input
At completion of A-D conversion
At BRK instruction execution
Non-maskable
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Valid when serial I/O1 is selected
Valid when serial I/O1 is selected
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Valid when serial I/O2 is selected
External interrupt
(valid when an “L” level is applied)
Valid when ADT interrupt is se-
lected External interrupt
(Valid at falling)
Valid when A-D interrupt is se-
lected
Non-maskable software interrupt
19
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3827 Group
Fig. 14 Interrupt control
Fig. 15 Structure of interrupt-related registers
b7 b0 Interrupt edge selection register
INT
0
interrupt edge selection bit
INT
1
interrupt edge selection bit
INT
2
interrupt edge selection bit
INT
3
interrupt edge selection bit
Not used (return “0” when read)
(INTEDGE : address 003A
16
)
Interrupt request register 1
INT
0
interrupt request bit
INT
1
interrupt request bit
Serial I/O1 receive interrupt request bit
Serial I/O1 transmit interrupt request bit
Timer X interrupt request bit
Timer Y interrupt request bit
Timer 2 interrupt request bit
Timer 3 interrupt request bit
Interrupt control register 1
INT
0
interrupt enable bit
INT
1
interrupt enable bit
Serial I/O receive interrupt enable bit
Serial I/O transmit interrupt enable bit
Timer X interrupt enable bit
Timer Y interrupt enable bit
Timer 2 interrupt enable bit
Timer 3 interrupt enable bit
0 : No interrupt request issued
1 : Interrupt request issued
(IREQ1 : address 003C
16
)
(ICON1 : address 003E
16
)
Interrupt request register 2
CNTR
0
interrupt request bit
CNTR
1
interrupt request bit
Timer 1 interrupt request bit
INT
2
interrupt request bit
Serial I/O2 interrupt request bit
Key input interrupt request bit
ADT/AD conversion interrupt request bit
Not used (returns “0” when read)
(IREQ2 : address 003D
16
)
Interrupt control register 2
CNTR
0
interrupt enable bit
CNTR
1
interrupt enable bit
Timer 1 interrupt enable bit
INT
2
interrupt enable bit
Serial I/O2 interrupt enable bit
Key input interrupt enable bit
ADT/AD conversion interrupt enable bit
Not used (returns “0” when read)
(Do not write “1” to this bit.)
0 : Interrupts disabled
1 : Interrupts enabled
(ICON2 : address 003F
16
)
0 : Falling edge active
1 : Rising edge active
b7 b0
b7 b0
b7 b0
b7 b0
Interrupt request bit
Interrupt enable bit
Interrupt disable flag (I)
BRK instruction
Reset Interrupt request
20
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
3827 Group
MITSUBISHI MICROCOMPUTERS
Key Input Interrupt (Key-on wake-up)
A Key-on wake up interr upt request is generated by applying “L”
level to any pin of port P2 that have been set to input mode. In
other words, it is generated when AND of input level goes from “1”
to “0”. An example of using a key input interrupt is shown in Figure
16, where an interrupt request is generated by pressing one of the
keys consisted as an active-low key matrix which inputs to ports
P20–P23.
Fig. 16 Connection example when using key input interrupt and port P2 block diagram
✽✽✽
✽✽✽
✽✽✽
✽✽✽
✽✽✽
✽✽✽
✽✽✽
✽✽✽
Port P20
latch
Port P20
direction register = “0”
Port P21
latch
Port P21
direction register = “0”
Port P22
latch
Port P22
direction register = “0”
Port P23
latch
Port P23
direction register = “0”
Port P24
latch
Port P24
direction register = “1”
Port P25
latch
Port P25
direction register = “1”
Port P26
latch
Port P27
latch
Port P27
direction register = “1”
Port P20
input
Port P21
input
Port P22
input
Port P23
input
Port P24 output
Port P25 output
Port P26 output
Port P27 output
PULLA register
Bit 2 = “1”
Port P2 input
reading circuit
Key input interrupt request
Port PXx
“L” level output
✽ P-channel transistor for pull-up
✽✽ CMOS output buffer
Key input control register = “1”
Key input control register = “1”
Key input control register = “1”
Key input control register = “1”
Key input control register = “1”
Key input control register = “1”
Key input control register = “1”
Port P26
direction register = “1”
Key input control register = “1”
21
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3827 Group
CNTR0 active
edge switch bit
Timer 1 count source
selection bit
Real time port
control bit “0”
“1”
P55/CNTR1“0”
f(XIN)/16
(f(XCIN)✕16 in φ = XCIN divided by 2)
CNTR1 active
edge switch bit
“10”
Timer Y stop
control bit
Falling edge detection Period
measurement mode
Timer Y
interrupt
request
Pulse width HL continuously measurement mode
Rising edge detection
“00”,“01”,“11”
Timer Y operating
mode bit
Timer X
interrupt
request
Timer X mode register
write signal
P54/CNTR0
Q
QT
S
P54 direction register
Pulse output mode
P54 latch
Timer X stop
control bit
“0”
“1”
Timer X write
control bit
Q D
Latch
Q D
Latch
“1”
“0”
“1” “10”
Timer X operat-
ing mode bits
“00”,“01”,“11”
f(XIN)/16
(f(XIN)/16 in low-speed mode✽)
Pulse width
measurement
mode
CNTR0 active
edge switch bit
Pulse output mode
Q
QT
S
“0”
P43 direction register P43 latch
“1”
TOUT output
active edge
switch bit
Timer 2 write
control bit
“0”
“1”
TOUT output
control bit
“1”
P43/φ/TOUT
XCIN
Timer 3 count
source selection bit
“0”
“1”
Timer 2
interrupt
request
Timer 3
interrupt
request
Timer 2 count source
selection bit
Timer 1
interrupt
request
Data bus
f(XIN)/16
(f(XCIN)/16 in φ = XCIN divided by 2)
f(XIN)/16
(f(XCIN)✕16 in φ=XCIN divided by 2)
f(XIN)/16(f(XCIN)/16 in low-speed mode✽)
CNTR0
interrupt
request
CNTR1
interrupt
request
Timer Y operating mode bit
“00”,“01”,“10”
“11”
Real time port
control bit “1”
P52 latch
Real time port
control bit “1”
P53 latch
Timer Y (low) (8) Timer Y (high) (8)
Timer 3 latch (8)
Timer 3 (8)
Timer 1 latch (8)
Timer 1 (8) Timer 2 latch (8)
Timer 2 (8)
Timer X (low) (8) Timer X (high) (8)
Timer X (low) latch (8) Timer X (high) latch (8)
Timer Y (low) latch (8) Timer Y (high) latch (8)
TOUT output
control bit
“0”
“0”
“0”
P52
P53
P52 direction register
P53 direction register
P52 data for real time port
P53 data for real time port
TIMERS
The 3827 group has five timers: timer X, timer Y, timer 1, timer 2,
and timer 3. Timer X and timer Y are 16-bit timers, and timer 1,
timer 2, and timer 3 are 8-bit timers.
All timers are down count timers. When the timer reaches “0016”,
an underflow occurs at the next count pulse and the correspond-
ing timer latch is reloaded into the timer and the count is
continued. When a timer underflows, the interrupt request bit cor-
responding to that timer is set to “1”.
Read and write operation on 16-bit timer must be performed for
both high and low-order bytes. When reading a 16-bit timer, read
the high-order byte first. When writing to a 16-bit timer, write the
low-order byte first. The 16-bit timer cannot perform the correct op-
eration when reading dur ing the wr ite operation, or when writing
during the read operation.
Fig. 17 Timer block diagram
22
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
3827 Group
MITSUBISHI MICROCOMPUTERS
Timer X mode register
(TXM : address 0027
16
)
Timer X write control bit
0 : Write value in latch and counter
1 : Write value in latch only
Real time port control bit
0 : Real time port function invalid
1 : Real time port function valid
P5
2
data for real time port
P5
3
data for real time port
Timer X operating mode bits
b5 b4
0 0 : Timer mode
0 1 : Pulse output mode
1 0 : Event counter mode
1 1 : Pulse width measurement mode
CNTR
0
active edge switch bit
0 : Count at rising edge in event counter mode
Start from “H” output in pulse output mode
Measure “H” pulse width in pulse width
measurement mode
Falling edge active for CNTR
0
interrupt
1 : Count at falling edge in event counter mode
Start from “L” output in pulse output mode
Measure “L” pulse width in pulse width
measurement mode
Rising edge active for CNTR
0
interrupt
Timer X stop control bit
0 : Count start
1 : Count stop
b7 b0
Timer X
Timer X is a 16-bit timer that can be selected in one of four modes
and can be controlled the timer X wr ite and the real time port by
setting the timer X mode register.
(1) Timer Mode
The timer counts f(XIN)/16 (or f(XCIN)/16 in low-speed mode).
(2) Pulse Output Mode
Each time the timer underflows, a signal output from the CNTR0
pin is inverted. Except for this, the operation in pulse output mode
is the same as in timer mode. When using a timer in this mode, set
the port shared with the CNTR0 pin to input.
(3) Event Counter Mode
The timer counts signals input through the CNTR0 pin.
Except for this, the operation in event counter mode is the same
as in timer mode. When using a timer in this mode, set the port
shared with the CNTR0 pin to input.
(4) Pulse Width Measurement Mode
The count source is f(XIN)/16 (or f(XCIN)/16 in low-speed mode). If
CNTR0 active edge switch bit is “0”, the timer counts while the in-
put signal of CNTR0 pin is at “H”. If it is “1”, the timer counts while
the input signal of CNTR0 pin is at “L”. When using a timer in this
mode, set the port shared with tha CNTR0 pin to input.
●Timer X write control
If the timer X write control bit is “0”, when the value is written in the
address of timer X, the value is loaded in the timer X and the latch
at the same time.
If the timer X write control bit is “1”, when the value is written in the
address of timer X, the value is loaded only in the latch. The value
in the latch is loaded in timer X after timer X underflows.
If the value is written in latch only, unexpected value may be set in
the high-order counter when the writing in high-order latch and the
underflow of timer X are performed at the same timing.
■Note on CNTR0 interrupt active edge
selection
CNTR0 interrupt active edge depends on the CNTR0 active edge
switch bit.
●Real time port control
While the real time port function is valid, data for the real time port
are output from ports P52 and P53 each time the timer X
underflows. (However, if the real time por t control bit is changed
from “0” to “1”, data are output without the timer X.) When the data
for the real time port is changed while the real time port function is
valid, the changed data are output at the next underflow of timer X.
Before using this function, set the corresponding port direction
registers to output mode.
Fig. 18 Structure of timer X mode register
23
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3827 Group
Timer Y
Timer Y is a 16-bit timer that can be selected in one of four modes.
(1) Timer Mode
The timer counts f(XIN)/16 (or f(XCIN)/16 in low-speed mode).
(2) Period Measurement Mode
CNTR1 interrupt request is generated at rising/falling edge of
CNTR1 pin input signal. Simultaneously, the value in timer Y latch
is reloaded in timer Y and timer Y continues counting down. Except
for the abo ve-mentioned, the operation in period measurement
mode is the same as in timer mode.
The timer value just before the reloading at rising/falling of CNTR1
pin input signal is retained until the timer Y is read once after the
reload.
The rising/falling timing of CNTR1 pin input signal is found by
CNTR1 interrupt. When using a timer in this mode, set the por t
shared with the CNTR1 pin to input.
(3) Event Counter Mode
The timer counts signals input through the CNTR1 pin.
Except for this, the operation in event counter mode is the same
as in timer mode. When using a timer in this mode, set the port
shared with the CNTR1 pin to input.
(4) Pulse Width HL Continuously Measurement
Mode
CNTR1 interrupt request is generated at both rising and falling
edges of CNTR1 pin input signal. Except for this, the operation in
pulse width HL continuously measurement mode is the same as in
period measurement mode. When using a timer in this mode, set
the port shared with the CNTR1 pin to input.
■Note on CNTR1 interrupt active edge selection
CNTR1 interrupt active edge depends on the CNTR1 active edge
switch bit. However, in pulse width HL continuously measurement
mode, CNTR1 interrupt request is generated at both rising and
falling edges of CNTR1 pin input signal regardless of the setting of
CNTR1 active edge switch bit.
Fig. 19 Structure of timer Y mode register
Timer Y mode register
(TYM : address 002816)
b7 b0
Not used (return “0” when read)
Timer Y operating mode bits
b5 b4
0 0 : Timer mode
0 1 : Period measurement mode
1 0 : Event counter mode
1 1 : Pulse width HL continuously
measurement mode
CNTR1 active edge switch bit
0 : Count at rising edge in event counter mode
Measure the falling edge to falling edge
period in period measurement mode
Falling edge active for CNTR1 interrupt
1 : Count at falling edge in event counter mode
Measure the rising edge period in period
measurement mode
Rising edge active for CNTR1 interrupt
Timer Y stop control bit
0 : Count start
1 : Count stop
24
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
3827 Group
MITSUBISHI MICROCOMPUTERS
Timer 1, Timer 2, Timer 3
Timer 1, timer 2, and timer 3 are 8-bit timers. The count source for
each timer can be selected by timer 123 mode register. The timer
latch value is not affected b y a change of the count source. How-
ever, because changing the count source may cause an
inadvertent count down of the timer. Therefore, rewrite the value of
timer whenever the count source is changed.
●Timer 2 write control
If the timer 2 write control bit is “0”, when the value is written in the
address of timer 2, the value is loaded in the timer 2 and the latch
at the same time.
If the timer 2 write control bit is “1”, when the value is written in the
address of timer 2, the value is loaded only in the latch. The value
in the latch is loaded in timer 2 after timer 2 underflows.
●Timer 2 output control
When the timer 2 (TOUT) is output enabled, an inversion signal
from the TOUT pin is output each time timer 2 underflows.
In this case, set the port shared with the TOUT pin to the output.
■Notes on timer 1 to timer 3
When the count source of timer 1 to 3 is changed, the timer count-
ing value may be changed large because a thin pulse is generated
in count input of timer . If timer 1 output is selected as the count
source of timer 2 or timer 3, when timer 1 is written, the counting
value of timer 2 or timer 3 may be changed large because a thin
pulse is generated in timer 1 output.
Therefore, set the value of timer in the order of timer 1, timer 2 and
timer 3 after the count source selection of timer 1 to 3.
Fig. 20 Structure of timer 123 mode register
TOUT output active edge switch bit
0 : Start at “H” output
1 : Start at “L” output
TOUT/φ output control bit
0 : TOUT/φ output disabled
1 : TOUT/φ output enabled
Timer 2 write control bit
0 : Write data in latch and counter
1 : Write data in latch only
Timer 2 count source selection bit
0 : Timer 1 output
1 : f(XIN)/16
(or f(XCIN)/16 in low-speed mode)
Timer 3 count source selection bit
0 : Timer 1 output
1 : f(XIN)/16
(or f(XCIN)/16 in low-speed mode)
Timer 1 count source selection bit
0 : f(XIN)/16
(or f(XCIN)/16 in low-speed mode)
1 : f(XCIN)
Not used (return “0” when read)
Timer 123 mode register
(T123M :address 002916)
Note : Internal clock φ is XCIN/2 in the low-speed mode.
b7 b0
25
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3827 Group
SERIAL I/O
Serial I/O1
Serial I/O1 can be used as either clock synchronous or asynchro-
nous (UART) ser ial I/O. A dedicated timer (baud rate generator) is
also provided for baud rate generation.
(1) Clock Synchronous Serial I/O Mode
Clock synchronous serial I/O1 can be selected by setting the
mode selection bit of the serial I/O1 control register to “1”.
For clock synchronous serial I/O1, the tr ansmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the transmit/receive buffer registers.
Fig. 21 Block diagram of clock synchronous serial I/O1
Fig. 22 Operation of clock synchronous serial I/O1 function
P4
6
/S
CLK
P4
7
/S
RDY1
P4
4
/R
X
D
P4
5
/T
X
D
f(X
IN
)1/4
1/4
F/F
Serial I/O1 status register
Serial I/O1 control register
Receive buffer register
Address 0018
16
Receive shift register
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Clock control circuit
Shift clock
Serial I/O1
clock selection bit
Frequency division ratio 1/(n+1)
Baud rate generator
Address 001C
16
BRG count source selection bit
Clock control circuit
Falling-edge detector
Data busAddress 0018
16
Shift clock Transmit shift register shift completion flag (TSC)
Transmit buffer empty flag (TBE)
Transmit interrupt request (TI)
Transmit interrupt source selection bit
Address 0019
16
Data bus
Address 001A
16
Transmit buffer register
Transmit shift register
(f(X
CIN
) in low-speed mode)
Receive enable signal SRDY1
D7D0D1D2D3D4D5D6
RBF = 1
TSC = 1
TBE = 0 TBE = 1
TSC = 0
Transfer shift clock
(1/2 to 1/2048 of the internal
clock, or an external clock)
Serial output TXD
Serial input RXD
Write signal to receive/transmit
buffer register (address 001816)
Overrun error (OE)
detection
Notes 1 : The transmit interrupt (TI) can be selected to occur either when the transmit buffer register has emptied (TBE=1)
or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the
serial I/O1 control register.
2 : If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is
output continuously from the TXD pin.
3 : The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .
D7D0D1D2D3D4D5D6
26
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
3827 Group
MITSUBISHI MICROCOMPUTERS
f(X
IN
)
1/4
OE
PE FE
1/16
1/16
Data bus
Receive buffer register
Address 0018
16
Receive shift register
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Baud rate generator
Frequency division ratio 1/(n+1)
Address 001C
16
ST/SP/PA generator
Transmit buffer register
Data bus
Transmit shift register
Address 0018
16
Transmit shift register shift completion flag (TSC)
Transmit buffer empty flag (TBE)
Transmit interrupt request (TI)
Address 0019
16
STdetector
SP detector UART control register
Address 001B
16
Character length selection bit
Address 001A
16
BRG count source selection bit
Transmit interrupt source selection bit
Serial I/O synchronous clock selection bit
Clock control circuit
Character length selection bit
7 bits
8 bits
Serial I/O1 control register
P4
6
/S
CLK
Serial I/O status register
P4
4
/R
X
D
P4
5
/T
X
D
(f(X
CIN
) in low-speed mode)
(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by
clearing the ser ial I/O mode selection bit of the ser ial I/O1 control
register to “0”.
Eight serial data transfer for mats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer regis-
ter, but the two buffers have the same address in memory. Since
the shift register cannot be written to or read from directly, transmit
data is written to the transmit buffer, and receive data is read from
the receive b uffer.
The transmit buffer can also hold the next data to be tr ansmitted,
and the receive buffer register can hold a character while the next
character is being received.
Fig. 23 Block diagram of UART serial I/O1
Fig. 24 Operation of UART serial I/O1 function
TSC=0
TBE=1
RBF=0
TBE=0 TBE=0
RBF=1 RBF=1
STD
0
D
1
SP D
0
D
1
ST SP
TBE=1 TSC=1
✽
STD
0
D
1
SP D
0
D
1
ST SP
Transmit buffer write signal
✽
Generated at 2nd bit in 2-stop-bit mode
1 start bit
7 or 8 data bits
1 or 0 parity bit
1 or 2 stop bit (s)
1 : Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
2 : The transmit interrupt (TI) can be selected to occur when either the TBE or TSC flag becomes “1” by the setting of the transmit interrupt source
selection bit (TIC) of the serial I/O1 control register.
3 : The receive interrupt (RI) is set when the RBF flag becomes “1”.
4 : After data is written to the transmit buffer register when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.
Notes
Serial output T
X
D
Serial input R
X
D
Receive buffer read signal
Transmit or receive clock
27
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3827 Group
[Transmit Buffer/Receive Buffer Register
(TB/RB)] 001816
The transmit buffer register and the receive buffer register are lo-
cated at the same address. The transmit buffer register is
wr ite-only and the receive buffer register is read-only. If a charac-
ter bit length is 7 bits, the MSB of data stored in the receive buffer
register is “0”.
[Serial I/O1 Status Register (SIO1STS)]
001916
The read-only ser ial I/O1 status register consists of seven flags
(bits 0 to 6) which indicate the operating status of the ser ial I/O
function and various errors.
Three of the flags (bits 4 to 6) are valid only in UART mode.
The receive buffer full flag (bit 1) is cleared to “0” when the receive
buffer is read.
If there is an error, it is detected at the same time that data is
transferred from the receive shift register to the receive buffer reg-
ister, and the receive buffer full flag is set. A write to the serial I/O1
status register clears all the error flags OE, PE, FE, and SE. Writ-
ing “0” to the serial I/O1 enable bit (SIOE) also clears all the status
flags, including the error flags.
All bits of the ser ial I/O1 status register are initialized to “0” at re-
set, but if the transmit enable bit (bit 4) of the serial I/O1 control
register has been set to “1”, the transmit shift register shift comple-
tion flag (bit 2) and the transmit buffer empty flag (bit 0) become
“1”.
[Serial I/O1 Control Register (SIO1CON)]
001A16
The serial I/O1 control register contains eight control bits for the
serial I/O1 function.
[UART Control Register (UARTCON) ]001B16
This is a 5 bit register containing four control bits, which are valid
when UART is selected and set the data format of an data re-
ceiver/transfer, and one control bit, which is always valid and sets
the output structure of the P45/TXD pin.
[Baud Rate Generator(BRG)] 001616
The baud rate generator determines the baud rate for serial trans-
fer.
The baud rate generator divides the frequency of the count source
by 1/(n + 1), where n is the value written to the baud rate genera-
tor.
28
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
3827 Group
MITSUBISHI MICROCOMPUTERS
Fig. 25 Structure of serial I/O1 control registers
BRG count source selection bit (CSS)
0: f(X
IN
) (f(X
CIN
) in low-speed mode)
1: f(X
IN
)/4 (f(X
CIN
)/4 in low-speed mode)
Serial I/O1 synchronous clock selection bit (SCS)
0: BRG output divided by 4 when clock synchronous serial
I/O is selected.
BRG output divided by 16 when UART is selected.
1: External clock input when clock synchronous serial I/O is
selected.
External clock input divided by 16 when UART is selected.
S
RDY1
output enable bit (SRDY)
0: P4
7
pin operates as ordinary I/O pin.
1: P4
7
pin operates as S
RDY1
output pin.
Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
Transmit enable bit (TE)
0: Transmit disabled
1: Transmit enabled
Receive enable bit (RE)
0: Receive disabled
1: Receive enabled
Serial I/O1 mode selection bit (SIOM)
0: Asynchronous serial I/O (UART)
1: Clock synchronous serial I/O
Serial I/O1 enable bit (SIOE)
0: Serial I/O1 disabled
(pins P4
4
–P4
7
operate as ordinary I/O pins)
1: Serial I/O1 enabled
(pins P4
4
–P4
7
operate as serial I/O pins)
Serial I/O1 control register
(SIO1CON : address 001A
16
)
b7 b0
Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty
Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full
Transmit shift register shift completion flag (TSC)
0: Transmit shift in progress
1: Transmit shift completed
Overrun error flag (OE)
0: No error
1: Overrun error
Parity error flag (PE)
0: No error
1: Parity error
Framing error flag (FE)
0: No error
1: Framing error
Summing error flag (SE)
0: OE U PE U FE =0
1: OE U PE U FE =1
Not used (returns “1” when read)
Serial I/O1 status register
(SIO1STS : address 0019
16
)
b7 b0
UART control register
(UARTCON : address 001B
16
)
Character length selection bit (CHAS)
0: 8 bits
1: 7 bits
Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enabled
Parity selection bit (PARS)
0: Even parity
1: Odd parity
Stop bit length selection bit (STPS)
0: 1 stop bit
1: 2 stop bits
P4
5
/T
X
D P-channel output disable bit (POFF)
0: CMOS output (in output mode)
1: N-channel open-drain output (in output mode)
Not used (return “1” when read)
b7 b0
29
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3827 Group
Serial I/O2
The serial I/O2 function can be used only for clock synchronous
serial I/O.
For clock synchronous serial I/O2 the transmitter and the receiver
must use the same clock. When the internal clock is used, transfer
is started by a write signal to the serial I/O2 register.
When an internal clock is selected as the synchronous clock of the
serial I/O2, either P62 or P63 can be selected as an output pin of
the synchronous clock. In this case, the pin that is not selected as
an output pin of the synchronous clock functions as a port.
[Serial I/O2 Control Register (SIO2CON)]
001D16
The serial I/O2 control register contains 8 bits which control vari-
ous serial I/O2 functions.
Fig. 26 Structure of serial I/O2 control register
Serial I/O2 control register
(SIO2CON : address 001D16)
b7
Internal synchronous clock select bits
0 0 0: f(XIN)/8 (f(XCIN)/8 in low-speed mode)
0 0 1: f(XIN)/16 (f(XCIN)/16 in low-speed mode)
0 1 0: f(XIN)/32 (f(XCIN)/32 in low-speed mode)
0 1 1: f(XIN)/64 (f(XCIN)/64 in low-speed mode)
1 0 0:
1 0 1:
1 1 0: f(XIN)/128 (f(XCIN)/128 in low-speed mode)
1 1 1: f(XIN)/256 (f(XCIN)/256 in low-speed mode)
Serial I/O2 port selection bit
0: I/O port
1: SOUT2,SCLK21/SCLK22 signal output
P61/SOUT2 P-channel output disable bit
0: CMOS output (in output mode)
1: N-channel open-drain output
(in output mode)
Transfer direction selection bit
0: LSB first
1: MSB first
Synchronous clock selection bit
0: External clock
1: Internal clock
Synchronous clock output pin selection bit
0: SCLK21
1: SCLK22
b0
b2 b1 b0
Do not set
Fig. 27 Block diagram of serial I/O2 function
f(X
IN
)
“1”
“0”
“0”
“1”
“0”
“1”
S
CLK2
(Note)
1/8
1/16
1/32
1/64
1/128
1/256
Data bus
Serial I/O2
interrupt request
Serial I/O2 port selection bit
Serial I/O counter 2 (3)
Serial I/O shift register 2 (8)
Synchronous circuit
Synchronous clock
selection bit
External clock
Internal synchronous
clock select bits
Divider
P6
3
latch
P6
3
/S
CLK22
P6
2
/S
CLK21
P6
1
/S
OUT2
P6
0
/S
IN2
P6
2
latch
P6
1
latch
(Note)
Note: It is selected by the synchronous clock selection bit, the synchronous
clock output pin selection bit, and the serial I/O port selection bit.
(f(X
CIN
) in low-speed mode)
30
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
3827 Group
MITSUBISHI MICROCOMPUTERS
Fig. 28 Timing of serial I/O2 function
D7D0D1D2D3D4D5D6
Transfer clock (Note 1)
Serial I/O2 output SOUT2
Serial I/O2 input SIN2
Serial I/O2 register
write signal
(Note 2)
Serial I/O2 interrupt request bit set
1: When the internal clock is selected as the transfer clock, the divide ratio can be selected by setting bits 0 to 2 of the serial
I/O2 control register.
2: When the internal clock is selected as the transfer clock, the SOUT2 pin goes to high impedance after transfer completion.
When the external clock is selected as the transfer clock, a content of the serial I/O shift register is continued to shift
during inputting a transfer clock. The SOUT2 pin does not go to high impedance after transfer completion.
Notes
31
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3827 Group
PULSE WIDTH MODULATION (PWM)
The 3827 group has a PWM function with an 8-bit resolution,
based on a signal that is the clock input XIN or that clock input di-
vided by 2.
Data Setting
The PWM output pin also functions as ports P50 and P51. Set the
PWM period by the PWM prescaler, and set the period during
which the output pulse is an “H” by the PWM register.
If PWM count source is f(XIN) and the value in the PWM prescaler
is n and the value in the PWM register is m (where n = 0 to 255
and m = 0 to 255) :
PWM period = 255 ✕ (n+1)/f(XIN)
= 51 ✕ (n+1) µs (when XIN = 5 MHz)
Output pulse “H” period = PWM period ✕ m/255
= 0.2 ✕ (n+1) ✕ m µs
(when XIN = 5 MHz)
PWM Operation
When at least either bit 1 (PWM0 output enable bit) or bit 2 (PWM1
output enable bit) of the PWM control register is set to “1”, oper a-
tion starts by initializing the PWM output circuit, and pulses are
output starting at an “H”. When one PWM output is enab led and
that the other PWM output is enabled, PWM output which is en-
abled to output later starts pulse output from halfway.
When the PWM register or PWM prescaler is updated during
PWM output, the pulses will change in the cycle after the one in
which the change was made.
Fig. 29 Timing of PWM c ycle
Fig. 30 Block diagram of PWM function
51 ✕ m ✕ (n+1)
255 µs
T = [51 ✕ (n+1)] µs
PWM output
m: Contents of PWM register
n : Contents of PWM prescaler
T : PWM cycle (when f(X
IN
) = 5 MHz)
Data bus
Count source
selection bit
“0”
“1”
PWM
prescaler pre-latch PWM
register pre-latch
PWM
prescaler latch PWM
register latch
Transfer control circuit
PWM circuit
1/2
X
IN
PWM
0
enable bit
Port P5
6
PWM prescaler
PWM
1
enable bit
32
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
3827 Group
MITSUBISHI MICROCOMPUTERS
Fig. 32 PWM output timing when PWM register or PWM prescaler is changed
Fig. 31 Structure of PWM control register
b7 b0 PWM control register
(PWMCON : address 002B
16
)
Count source selection bit
0:f(X
IN
)
1:f(X
IN
)/2
PWM
0
function enable bit
0:PWM
0
disabled
1:PWM
0
enabled
PWM
1
function enable bit
0:PWM
1
disabled
1:PWM
1
enabled
Not used (return “0” when read)
TT2
C
B
T
PWM register
write signal
PWM prescaler
write signal
(Changes from “A” to “B” during “H” period)
(Changes from “T” to “T2” during PWM period)
PWM
(internal)
AB
TC
T2
=
stop
PWM
0
function
enable bit
PWM
1
function
enable bit
PWM
0
output Port
Port
PWM
1
output
Port
stop
Port
When the contents of the PWM register or PWM prescaler have changed, the PWM
output will change from the next period after the change.
33
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3827 Group
A-D CONVERTER
[A-D Conversion Register (AD)] 003516
The A-D conversion register is a read-only register that contains
the result of an A-D conversion. During A-D conversion, do not
read this register.
[A-D Control Register (ADCON)] 003416
The A-D control register controls the A-D conversion process. Bits
0 to 2 are analog input pin selection bits. Bit 3 is an A-D conver-
sion completion bit and “0” during A-D conversion, then changes
to “1” when the A-D conversion is completed. Writing “0” to this bit
starts the A-D conversion. Bit 4 controls the transistor which
breaks the through current of the resistor ladder. When bit 5, which
is the AD external tr igger valid bit, is set to “1”, A-D conversion is
started even by a rising edge or falling edge of an ADT input. Set
ports which share with ADT pins to input when using an A-D exter-
nal trigger.
[Comparison V oltage Generator]
The comparison voltage generator divides the voltage betw een
AVSS and VREF, and outputs the divided voltages.
[Channel Selector]
The channel selector selects one of the input ports P67/AN7–P60/
AN0, and inputs it to the comparator.
[Comparator and Control Circuit]
The comparator and control circuit compares an analog input volt-
age with the comparison voltage and stores the result in the A-D
conversion register. When an A-D conversion is completed, the
control circuit sets the AD conversion completion bit and the AD
interr upt request bit to “1”.
Note that the comparator is constructed linked to a capacitor, so
set f(XIN) to at least 500 kHz during A-D conversion.
Use a clock divided the main clock XIN as the inter nal clock φ.
Fig. 34 A-D converter block diagram
Fig. 33 Structure of A-D contr ol register
A-D control register
(ADCON : address 003116)
Analog input pin selection bits
0 0 0 : P60/SIN2/AN0
0 0 1 : P61/SOUT2/AN1
0 1 0 : P62/SCLK21/AN2
0 1 1 : P63/SCLK22/AN3
1 0 0 : P64/AN4
1 0 1 : P65/AN5
1 1 0 : P66/AN6
1 1 1 : P67/AN7
AD conversion completion bit
0 : Conversion in progress
1 : Conversion completed
VREF input switch bit
0 : OFF
1 : ON
AD external trigger valid bit
0 : A-D external trigger invalid
1 : A-D external trigger valid
Interrupt source selection bit
0 : Interrupt request at A-D
conversion completed
1 : Interrupt request at ADT
input rising or falling
Reference voltage input selection bit
0 : VREF
1 : P56/DA1
b7 b0
b7 b0
b9 b8 b7 b6 b5 b4 b3 b2
b7 b0
b9 b8
b7 b0
b7 b6 b5 b4 b3 b2
8-bit read (Read only address 003216.)
(Address 003216)
10-bit read (Read address 003316 first.)
(Address 003316)
(Address 003216)
Note: High-order 6 bits of address 003316 becomes “0” at reading.
b1 b0
Data bus
A-D control register
A-D conversion register
Resistor ladder
AVSS
Comparater
ADT/A-D interrupt request
b7 b0
A-D control register
3
P60/SIN2/AN0
P61/SOUT2/AN1
P62/SCLK21/AN2
P63/SCLK22/AN3
P64/AN4
P65/AN5
P66/AN6
P67/AN7
10
P40/ADT
VREF
A-D conversion register
(H) (L)
P56/DA1
Channel selector
34
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
3827 Group
MITSUBISHI MICROCOMPUTERS
D-A CONVERTER
The 3827 group has an on-chip D-A converter with 8-bit resolution
and 2 channels (DAi (i=1, 2)). The D-A converter is performed by
setting the value in the D-A conversion register. The result of D-A
converter is output from DAi pin. When using the D-A conver ter,
the corresponding port direction register bit (P5 6/DA1, P57/DA2)
should be set to “0” (input status).
The output analog voltage V is deter mined by the value n (base
10) in the D-A conversion register as f ollows:
V=VREF ✕ n/256 (n=0 to 255)
Where VREF is the reference voltage.
At reset, the D-A conversion registers are cleared to “0016”, the
DAi output enable bits are cleared to “0”, and DAi pin goes to
high impedance state. The DA output is not buffered, so connect
an external buffer when driving a low-impedance load. Fig. 35 Structure of D-A control register
Fig. 36 Block diagram of D-A converter
Fig. 37 A-D converter, D-A conver ter block diagram
DA1 output enable bit/DA1 VREF
ON/OFF switch
DA2 output enable bit/DA2 VREF
ON/OFF switch
Not used (return “0” when read)
0 : Output disabled/OFF
1 : Output enabled/ON
b7 b0 D-A control register
(DACON : address 003616)
D-A1 conversion register (0034
16
)
D-A2 conversion register (0035
16
)
P5
6
/DA
1
P5
7
/DA
2
Data bus
D-A i conversion register (8)
R-2R resistor ladder
DA i output enable bit
V
REF
Resistor ladder A-D conversion register
(10 bits)
D-A1 conversion register (8 bits)
D-A2 conversion register (8 bits)
R-2R resistor ladder
R-2R resistor ladder
D-A2 output
D-A1 output
(P5
6
)
(P5
7
)
D-A2 output enable switch
D-A1 output enable switch
V
REF
input
ON/OFF switch
Internal: D-A output
External: V
REF
Reference voltage input select switch
D-A1 V
REF
ON/OFF switch
D-A2 V
REF
ON/OFF switch
35
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3827 Group
LCD DRIVE CONTROL CIRCUIT
The 3827 group has the built-in Liquid Crystal Display (LCD) drive
control circuit consisting of the following.
●LCD display RAM
●Segment output enable register
●LCD mode register
●Voltage multiplier
●Selector
●Timing controller
●Common driver
●Segment driver
●Bias control circuit
A maximum of 40 segment output pins and 4 common output pins
can be used.
Fig. 38 Structure of LCD mode register
Up to 160 pixels can be controlled for LCD display. When the LCD
enable bit is set to “1” after data is set in the LCD mode register,
the segment output enable register and the LCD display RAM, the
LCD drive control circuit starts reading the display data automati-
cally, performs the bias control and the duty ratio control, and
displays the data on the LCD panel.
Table 7 Maximum number of display pixels at each duty ratio
Duty ratio Maximum number of display pix el
80 dots
or 8 segment LCD 10 digits
120 dots
or 8 segment LCD 15 digits
160 dots
or 8 segment LCD 20 digits
2
3
4
Segment output enable bit 0
0 : Output ports P30–P35
1 : Segment output SEG18–SEG23
Segment output enable bit 1
0 : Output ports P36, P37
1 : Segment output SEG24,SEG25
Segment output enable bit 2
0 : I/O ports P00–P05
1 : Segment output SEG26–SEG31
Segment output enable bit 3
0 : I/O ports P06,P07
1 : Segment output SEG32,SEG33
Segment output enable bit 4
0 : I/O port P10
1 : Segment output SEG34
Segment output enable bit 5
0 : I/O ports P11–P15
1 : Segment output SEG35–SEG39
LCD output enable bit
0 : Disable
1 : Enable
Not used (return “0” when read)
(Do not write “1” to this bit)
Segment output enable register
(SEG : address 003816)
b7 b0 LCD mode register
(LM : address 003916)
Duty ratio selection bits
0 0 : Not used
0 1 : 2 duty (use COM0, COM1)
1 0 : 3 duty (use COM0–COM2)
1 1 : 4 duty (use COM0–COM3)
Bias control bit
0 : 1/3 bias
1 : 1/2 bias
LCD enable bit
0 : LCD OFF
1 : LCD ON
Voltage multiplier control bit
0 : Voltage multiplier disabled
1 : Voltage multiplier enabled
LCD circuit divider division ratio selection bits
0 0 : 1 division of clock input
0 1 : 2 division of clock input
1 0 : 4 division of clock input
1 1 : 8 division of clock input
LCDCK count source selection bit (Note)
0 : f(XCIN)/32
1 : f(XIN)/8192 (f(XCIN)/8192 in low-speed mode)
Note : LCDCK is a clock for a LCD timing controller.
b7 b0
36
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
3827 Group
MITSUBISHI MICROCOMPUTERS
Fig. 39 Block diagram of LCD controller/driver
37
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3827 Group
VOLTAGE MULTIPLIER (3 TIMES)
The voltage multiplier performs threefold boosting. This circuit in-
puts a reference voltage for boosting from LCD power input pin
VL1. (However, when using a 1/2 bias, connect VL1 and V L2 and
apply voltage by external resistor division.)
Set each bit of the segment output enable register and the LCD
mode register in the following order for operating the voltage mul-
tiplier.
1. Set the segment output enable bits (bits 0 to 5) of the seg-
ment output enable register to “0” or “1.”
2. Set the duty ratio selection bits (bits 0 and 1), the bias con-
trol bit (bit 2), the LCD circuit divider division ratio selection
bits (bits 5 and 6), and the LCDCK count source selection
bit (bit 7) of the LCD mode register to “0” or “1.”
3. Set the LCD output enable bit (bit 6) of the segment output
enable register to “1.”
4. Set the voltage multiplier control bit (bit 4) of the LCD mode
register to “1.”
When voltage is input to the V L1 pin dur ing operating the voltage
multiplier, voltage that is twice as large as V L1 occurs at the VL2
pin, and voltage that is three times as large as VL1 occurs at the
VL3 pin.
When using the voltage multiplier, apply 1.3 V ≤ V oltage ≤ 2.3 V to
the VL1 pin.
When not using the voltage multiplier,apply proper voltage to the
LCD power input pins (VL1–VL3). Then set the LCD output enable
bit to “1.”
When the LCD output enable bit is set to “0,” the VCC voltage is
applied to the V L3 pin inside of this microcomputer.
The voltage multiplier control bit (bit 4 of the LCD mode register)
controls the voltage multiplier.
Fig. 40 Example of circuit at each bias
Table 8 Bias control and applied voltage to VL1–VL3
Bias value
1/3 bias
Voltage value
VL3=VLCD
VL2=2/3 VLCD
VL1=1/3 VLCD
Note 1: VLCD is the maximum value of supplied voltage for the
LCD panel.
Bias Control and Applied Voltage to LCD
Power Input Pins
To the LCD power input pins (VL1–VL3), apply the voltage shown in
Table 8 according to the bias value .
Select a bias value b y the bias control bit (bit 2 of the LCD mode
register).
1/2 bias VL3=VLCD
VL2=VL1=1/2 VLCD
V
L3
V
L2
C
2
C
1
V
L1
1/3 bias
when using the voltage multiplier
V
L3
V
L2
C
2
C
1
V
L1
1/3 bias
when not using the voltage multiplier
Open
Open R2
R1
R3
R1=R2=R3
Contrast control
V
L3
V
L2
C
2
C
1
V
L1
1/2 bias
Open
Open
R4
R5
R4=R5
Contrast control
V
CC
V
CC
PX
X
38
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
3827 Group
MITSUBISHI MICROCOMPUTERS
Common Pin and Duty Ratio Control
The common pins (COM0–COM3) to be used are deter mined by
duty ratio.
Select duty ratio by the duty ratio selection bits (bits 0 and 1 of the
LCD mode register).
When releasing from reset, the VCC (VL3) voltage is output from
the common pins.
Table 9 Duty ratio control and common pins used
Duty
ratio
Common pins used
Notes1: COM2 and COM3 are open.
2: COM3 is open.
Bit 1 Bit 0 COM0, COM1 (Note 1)
Duty ratio selection bit
2
3
4
0
1
1
1
0
1COM0–COM2 (Note 2)
COM0–COM3
Segment Signal Output Pin
Segment signal output pins are classified into the segment-only
pins (SEG0–SEG17), the segment/output port pins (SEG18–
SEG25), and the segment/I/O port pins (SEG26–SEG39).
Segment signals are output according to the bit data of the LCD
RAM corresponding to the duty ratio. After reset release, a VCC
(=VL3) voltage is output to the segment-only pins and the seg-
ment/output por t pins are pulled up to the VCC (=V L3) voltage in
the high impedance condition. The segment/I/O port pins are set
to input por ts, and VCC (=VL3) is applied to them by pull-up resis-
tor.
LCD Display RAM
Address 004016 to 005316 is the designated RAM for the LCD dis-
play. When “1” are written to these addresses, the corresponding
segments of the LCD display panel are turned on.
LCD Drive Timing
The LCDCK timing frequency (LCD drive timing) is generated in-
ternally and the frame frequency can be determined with the
following equation;
f(LCDCK) =
Frame frequency =
Fig. 41 LCD display RAM map
(frequency of count source for LCDCK)
(divider division ratio for LCD)
f(LCDCK)
(duty ratio)
Bit
address 76 5432 10
0040
16
0041
16
0042
16
0043
16
0044
16
0045
16
0046
16
SEG
1
SEG
3
SEG
5
SEG
7
SEG
9
SEG
0
SEG
2
SEG
4
SEG
6
SEG
8
SEG
10
COM
3
COM
2
COM
1
COM
0
SEG
12
SEG
14
SEG
16
SEG
18
SEG
20
SEG
22
SEG
24
SEG
26
SEG
28
SEG
30
SEG
32
SEG
34
SEG
36
SEG
38
SEG
21
SEG
23
SEG
25
SEG
27
SEG
11
SEG
13
SEG
15
SEG
17
SEG
19
SEG
29
SEG
31
SEG
33
SEG
35
SEG
37
SEG
39
0047
16
0048
16
0049
16
004A
16
004B
16
004C
16
004D
16
004E
16
004F
16
0050
16
0051
16
0052
16
0053
16
COM
3
COM
2
COM
1
COM
0
39
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3827 Group
Fig. 42 LCD drive waveform (1/2 bias)
Internal signal
LCDCK timing
1/4 duty Voltage level
V
L3
V
L2
=V
L1
V
SS
V
L3
V
SS
COM
0
COM
1
COM
2
COM
3
SEG
0
OFF ON OFF ON
COM
3
COM
2
COM
1
COM
0
COM
3
COM
2
COM
1
COM
0
1/3 duty
V
L3
V
L2
=V
L1
V
SS
V
L3
V
SS
OFFON ON OFF ON OFF
1/2 duty
COM
0
COM
1
COM
2
SEG
0
COM
0
COM
1
SEG
0
V
L3
V
L2
=V
L1
V
SS
V
L3
V
SS
OFFON OFFON OFFON OFFON
COM
0
COM
2
COM
1
COM
0
COM
2
COM
1
COM
0
COM
2
COM
1
COM
0
COM
1
COM
0
COM
1
COM
0
COM
1
COM
0
40
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
3827 Group
MITSUBISHI MICROCOMPUTERS
Fig. 43 LCD drive waveform (1/3 bias)
Internal signal
LCDCK timing
1/4 duty Voltage level
V
L3
V
SS
COM
0
COM
1
COM
2
COM
3
SEG
0
OFF ON OFF ON
COM
3
COM
2
COM
1
COM
0
COM
3
COM
2
COM
1
COM
0
1/3 duty
OFFON ON OFF ON OFF
1/2 duty
COM
0
COM
1
COM
2
SEG
0
COM
0
COM
1
SEG
0
OFFON OFFON OFFON OFFON
V
L3
V
L2
V
SS
V
L1
V
L3
V
L2
V
SS
V
L1
V
L3
V
SS
V
L3
V
L2
V
SS
V
L1
V
L3
V
SS
COM
0
COM
2
COM
1
COM
0
COM
2
COM
1
COM
0
COM
2
COM
1
COM
0
COM
1
COM
0
COM
1
COM
0
COM
1
COM
0
41
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3827 Group
WATCHDOG TIMER
The watchdog timer gives a mean of retur ning to the reset status
when a program cannot run on a normal loop (for example, be-
cause of a software runaway).
The watchdog timer consists of an 8-bit watchdog timer L and a 6-
bit watchdog timer H. At reset or writing to the watchdog timer
control register (address 003716), the watchdog timer is set to
“3FFF16.” When any data is not written to the watchdog timer con-
trol register (address 003716) after reset, the watchdog timer is in
stop state. The watchdog timer starts to count down from “3FFF16”
by writing an optional value into the watchdog timer control regis-
ter (address 0037 16) and an internal reset occurs at an underflow.
Accordingly, programming is usually performed so that writing to
the watchdog timer control register (address 003716) may be
started before an underflow. The watchdog timer does not function
when an optional value have not written to the watchdog timer
control register (address 003716). When address 003716 is read,
the following values are read:
●value of high-order 6-bit counter
●value of STP instruction disable bit
●value of count source selection bit.
When bit 6 of the watchdog timer control register (address 003716)
is set to “0,” the STP instruction is valid. The STP instruction is dis-
abled by re writing this bit to “1.” At this time, if the STP instruction
is executed, it is processed as an undefined instruction, so that a
reset occurs inside.
This bit cannot be rewritten to “0” by programming. This bit is “0”
immediately after reset.
The count source of the watchdog timer becomes the system
clock φ divided by 8. The detection time in this case is set to 8.19 s
at XCIN = 32 kHz and 65.536 ms at XIN = 4 MHz.
However, count source of high-order 6-bit timer can be connected
to a signal divided system clock by 8 directly by writing the bit 7 of
the watchdog timer control register (address 003716) to “1.” The
detection time in this case is set to 32 ms at XCIN = 32 kHz and
256 µs at XIN = 4 MHz. There is no difference in the detection time
between the middle-speed mode and the high-speed mode.
Fig. 44 Block diagram of watchdog timer
Fig. 45 Structure of watchdog timer control register
Fig. 46 Timing of reset output
XIN
Data bus
XCIN
“1”
“0”
Internal
system clock
selection bit
“0”
“1”
1/16 Watchdog timer
H (6)
Watchdog timer count
source selection bit
Reset circuit
Undefined instruction
Reset
“3F16” is set when
watchdog timer is
written to.
Internal reset
RESETIN Reset release time wait
Watchdog timer
L (8)
“FF16” is set when
watchdog timer is
written to.
STP instruction
STP instruction disable bit
Watchdog timer H (for read-out of high-order 6 bit)
“3FFF
16
” is set to the watchdog timer by writing values to this address.
Watchdog timer H count source selection bit
0 : Internal system clock/2048 (f(X
IN
)/4096)
1 : Internal system clock/8 (f(X
IN
)/16)
STP instruction disable bit
0 STP instruction enabled
1 : STP instruction disabled
b7
Watchdog timer register (address 0037
16
)
WDTCON
b0
Internal
reset signal
Watchdog timer detection
2ms (f(XIN) = 4MHZ)
f(XIN)
42
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
3827 Group
MITSUBISHI MICROCOMPUTERS
TOUT/φ CLOCK OUTPUT FUNCTION
The internal system clock φ or timer 2 divided by 2 (TOUT output)
can be output from por t P43 by setting the TOUT/φ output control
bit (bit 1) of the timer 123 mode register and the TOUT/φ output
control register. Set bit 3 of the por t P4 direction register to “1”
when outputting the clock.
Fig. 47 Structure of TOUT/φ output-related register
TOUT/φ output control bit
0 : φ clock output
1 : TOUT output
Not used (return “0” when read)
TOUT/φ output control register
(CKOUT : address 002A16)
b7 b0 Timer 123 mode register
(T123M : address 002916)
TOUT output active edge switch bit
0 : Start on “H” output
1 : Start on “L” output
TOUT/φ output control bit
0 : TOUT/φ output disable
1 : TOUT/φ output enable
Timer 2 write control bit
0 : Write data in latch and timer
1 : Write data in latch only
Timer 2 count source selection bit
0 : Timer 1 output
1 : f(XIN)/16
(or f(XCIN)/16 in low-speed mode✽)
Timer 3 count source selection bit
0 : Timer 1 output
1 : f(XIN)/16
(or f(XCIN)/16 in low-speed mode✽)
Timer 1 count source selection bit
0 : f(XIN)/16
(or f(XCIN)/16 in low-speed mode✽)
1 : f(XCIN)
Not used (return “0” when read)
✽ : Internal clock φ is f(XCIN)/2 in low-speed mode.
b7 b0
43
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3827 Group
RESET CIRCUIT
To reset the microcomputer, RESET pin should be held at an “L”
level for 2 µs or more. Then the RESET pin is retur ned to an “H”
level (the power source voltage should be between VCC(min.) and
5.5 V, and the oscillation should be stable), reset is released. After
the reset is completed, the program star ts from the address con-
tained in address FFFD 16 (high-order byte) and address FFFC 16
(low-order byte). Make sure that the reset input voltage is less
than 0.2 VCC for VCC of VCC (min.).
Fig. 48 Reset Circuit Example
Fig. 49 Reset Sequence
(Note)
0.2VCC
0V
0V
Poweron
VCCRESET
VCC
RESET
Power source
voltage detection
circuit
Power source
voltage
Reset input
voltage
Note : Reset release voltage ; VCC=VCC(min.)
RESET
Internal
reset
Address
Data
SYNC
φ
XIN
FFFC FFFD ADH, ADL
ADLADH
????
XIN : about 8200 cycles
Notes 1: The frequency relation of f(XIN) and f(φ) is f(XIN) = 8 • f(φ).
2: The question marks (?) indicate an undefined state that
depends on the previous state.
Reset address from
vector table
44
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
3827 Group
MITSUBISHI MICROCOMPUTERS
Fig. 50 Initial status at reset
Address
(28)
(29)
(30)
(31)
(32)
(33)
(34)
(35)
(36)
(37)
(38)
(39)
(40)
(41)
(42)
(43)
(44)
(45)
(46)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
(20)
(21)
(22)
(23)
(24)
(25)
(26)
(27)
Port P0 direction register
Port P1 direction register
Port P2 direction register
Port P3 output control register
Port P4 direction register
Port P5 direction register
Port P6 direction register
Port P7 direction register
Key input control register
PULL register A
PULL register B
Serial I/O1 status register
Serial I/O1 control register
UART control register
Serial I/O2 control register
Timer X (low-order)
Timer X (high-order)
Timer Y (low-order)
Timer Y (high-order)
Timer 1
Timer 2
Timer 3
Timer X mode register
Timer Y mode register
Timer 123 mode register
TOUT/
φ
output control register
PWM control register
000116
000316
000516
000716
000916
000B16
000D16
000F16
001516
001616
001716
001916
001A16
001B16
001D16
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
Register contentsAddress
Note: The contents of all other register and RAM are undefined after reset, so they must be initialized by software.
✕ : Undefined
Register contents
0016
0016
0016
0016
0016
0016
0016
0016
0016
3F16
0016
0016
0016
FF16
FF16
FF16
FF16
FF16
0116
FF16
0016
0016
0016
0016
0016
003116
003216
003316
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
(PS)
(PCH)
(PCL)
A-D control register
A-D conversion register
(low-order)
A-D conversion register
(high-order)
D-A1 conversion register
D-A2 conversion register
D-A control register
Watchdog timer control register
Segment output enable register
LCD mode register
Interrupt edge selection register
CPU mode register
Interrupt request register 1
Interrupt request register 2
Interrupt control register 1
Interrupt control register 2
Processor status register
Program counter
Watchdog timer (high-order)
Watchdog timer (low-order)
Contents of address FFFD16
Contents of address FFFC16
0816
XX16
XX16
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
3F16
FF16
✕✕✕✕✕✕✕ 1
10000000
11100000
00111111
01001000
45
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3827 Group
CLOCK GENERATING CIRCUIT
The 3827 group has two built-in oscillation circuits. An oscillation
circuit can be formed by connecting a resonator between XIN and
XOUT (XCIN and XCOUT). Use the circuit constants in accordance
with the resonator manufacturer's recommended values. No exter-
nal resistor is needed between XIN and XOUT since a feed-back
resistor exists on-chip. How ever, an external feed-back resistor is
needed between XCIN and XCOUT.
To supply a clock signal externally, input it to the XIN pin and make
the XOUT pin open. The sub-clock XCIN-XCOUT oscillation circuit
cannot directly input clocks that are externally generated. Accord-
ingly, be sure to cause an external resonator to oscillate.
Immediately after poweron, only the XIN oscillation circuit starts
oscillating, and XCIN and X COUT pins go to high impedance state.
Frequency Control
(1) Middle-speed Mode
The internal clock φ is the frequency of XIN divided by 8.
After reset, this mode is selected.
(2) High-speed Mode
The internal clock φ is half the frequency of XIN.
(3) Low-speed Mode
●The internal clock φ is half the frequency of XCIN.
●A low-power consumption operation can be realized by stopping
the main clock XIN in this mode. To stop the main clock, set bit 5
of the CPU mode register to “1”.
When the main clock XIN is restar ted, set enough time for oscil-
lation to stabilize by programming.
Note: If you switch the mode between middle/high-speed and low-
speed, stabilize both XIN and XCIN oscillations. The
sufficient time is required for the sub-clock to stabilize, es-
pecially immediately after poweron and at returning from
stop mode. When switching the mode between middle/high-
speed and low-speed, set the frequency on condition that
f(XIN)>3f(XCIN).
Fig. 51 Ceramic resonator circuit
Fig. 52 External clock input circuit
Oscillation Control
(1) Stop Mode
If the STP instruction is executed, the internal clock φ stops at an
“H” level, and X IN and X CIN oscillators stop. The value set to the
timer latch 1 and the timer latch 2 is loaded automatically to the
timer 1 and the timer 2. Thus, a value generated time for stabiliz-
ing oscillation should be set to the timer 1 latch and the timer 2
latch (low-order 8 bits for the timer 1, high-order 8 bits for the timer
2) before executing the STP instruction.
Either XIN or XCIN divided by 16 is input to timer 1 as count
source, and the output of timer 1 is connected to timer 2. The bits
of the timer 123 mode register except bit 4 are cleared to “0,” Set
the timer 1 and timer 2 interrupt enable bits to disabled (“0”) before
executing the STP instruction. Oscillator restarts at reset or when
an external interrupt is received, but the internal clock φ is not sup-
plied to the CPU until timer 2 underflows..This allows timer for the
clock circuit oscillation to stabilize.
(2) Wait Mode
If the WIT instruction is executed, the internal cloc k φ stops at an
“H” level. The states of XIN and XCIN are the same as the state be-
fore the executing the WIT instruction. The internal cloc k restarts
at reset or when an interrupt is received. Since the oscillator does
not stop, normal operation can be star ted immediately after the
clock is restarted.
X
CIN
X
COUT
X
IN
X
OUT
C
IN
C
OUT
C
CIN
C
COUT
Rf Rd
X
IN
X
OUT
External oscillation
circuit
Open
V
CC
V
SS
C
CIN
C
COUT
Rf Rd
X
CIN
X
COUT
46
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
3827 Group
MITSUBISHI MICROCOMPUTERS
Fig. 53 Clock generating circuit block diagram
WIT
instruction STP instruction
Timing φ
(Internal clock)
S
R
Q
STP instruction
S
R
Q
Main clock stop bit
S
R
Q
Timer 2
Timer 1
1/2 1/4
XIN XOUT
XCOUT
XCIN
Interrupt request
Reset
Timer 1 count
source selection
bit
Timer 2 count
source selection
bit
Low-speed mode
Middle-/High-speed mode
Internal system clock selection bit
(Note)
Middle-speed mode
High-speed mode
or Low-speed mode
Note: When selecting the XC oscillation, set the port XC switch bit to “1” .
Main clock division ratio selection bit
“0”
“1”
“1”
“0” “1”
“0”
Interrupt disable flag I
1/2
“1”
“0”
47
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3827 Group
Fig. 54 State transitions of system clock
Low-power dissipation
mode (f(φ) =16 kHz)
Notes 1 : Switch the mode by the allows shown between the mode blocks. (Do not switch between the mode directly without an allow.)
2 : The all modes can be switched to the stop mode or the wait mode and returned to the source mode when the stop mode or the wait mode is ended.
3 : Timer and LCD operate in the wait mode.
4 : When the stop mode is ended, wait time can be set by connecting timer 1 and timer 2 in middle-/high-speed mode.
5 : When the stop mode is ended, wait time can be set by connecting timer 1 and timer 2 in low-speed mode.
6 : Wait until oscillation stabilizes after oscillating the main clock X
IN
before the switching from the low-speed mode to middle-/high-speed mode.
7 : The example assumes that 8 MHz is being applied to the X
IN
pin and 32 kHz to the X
CIN
pin. φ indicates the internal clock.
CM
4
: Port Xc switch bit
0: I/O port function
1: X
CIN
–X
COUT
oscillating function
CM
5
: Main clock (X
IN
–X
OUT
) stop bit
0: Oscillating
1: Stopped
CM
6
: Main clock division ratio selection bit
0: f(X
IN
)/2 (high-speed mode)
1: f(X
IN
)/8 (middle-speed mode)
CM
7
: Internal system clock selection bit
0: X
IN
–X
OUT
selected
(middle-/high-speed mode)
1: X
CIN
–X
COUT
selected
(low-speed mode)
CPU mode register
(CPUM : address 003B
16
)
b7 b4
Reset
CM
6
“0”“1”
CM
4
“0”
“1”
CM
7
=0(8 MHz selected)
CM
6
=1(Middle-speed)
CM
5
=0(8 MHz oscillating)
CM
4
=0(32 kHz stopped)
Middle-speed mode (f(φ) =1 MHz)
CM
7
=0(8 MHz selected)
CM
6
=1(Middle-speed)
CM
5
=0(8 MHz oscillating)
CM
4
=1(32 kHz oscillating)
Middle-speed mode (f(φ) =1 MHz)
CM
7
=0(8 MHz selected)
CM
6
=0(High-speed)
CM
5
=0(8 MHz oscillating)
CM
4
=0(32 kHz stopped)
High-speed mode (f(φ) =4 MHz)
CM
7
=0(8 MHz selected)
CM
6
=0(High-speed)
CM
5
=0(8 MHz oscillating)
CM
4
=1(32 kHz oscillating)
High-speed mode (f(φ) =4 MHz)
CM
7
=1(32 kHz selected)
CM
6
=1(Middle-speed)
CM
5
=0(8 MHz oscillating)
CM
4
=1(32 kHz oscillating)
Low-speed mode (f(φ) =16 kHz)
CM
7
=1(32 kHz selected)
CM
6
=0(High-speed)
CM
5
=0(8 MHz oscillating)
CM
4
=1(32 kHz oscillating)
Low-speed mode (f(φ) =16 kHz)
Low-power dissipation
mode (f(φ) =16 kHz)
CM
7
=1(32 kHz selected)
CM
6
=1(Middle-speed)
CM
5
=1(8 MHz stopped)
CM
4
=1(32 kHz oscillating)
CM
7
=1(32 kHz selected)
CM
6
=0(High-speed)
CM
5
=1(8 MHz stopped)
CM
4
=1(32 kHz oscillating)
CM
6
“0”“1”
CM
6
“0”“1”
CM
6
“0”“1”
CM
4
“0”
“1”
CM
7
“0”
“1”
CM
7
“0”
“1”
CM
5
“0”
“1”
CM
5
“0”
“1”
CM
4
CM
6
“0”
“1”
“0”
“1”
CM
4
CM
6
“0”
“1”
“1”
“0”
CM
5
CM
6
“0”
“1”
“0”
“1”
CM
5
CM
6
“0”
“1”
“1”
“0”
48
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
3827 Group
MITSUBISHI MICROCOMPUTERS
NOTES ON PROGRAMMING
Processor Status Register
The contents of the processor status register (PS) after a reset are
undefined, except for the interrupt disable flag (I) which is “1”. Af-
ter a reset, initialize flags which affect program execution.
In par ticular, it is essential to initialize the index X mode (T) and
the decimal mode (D) flags because of their effect on calculations.
Interrupt
The contents of the interrupt request bits do not change immedi-
ately after they have been written. After writing to an interrupt
request register, execute at least one instruction before performing
a BBC or BBS instruction.
Decimal Calculations
• To calculate in decimal notation, set the decimal mode flag (D)
to “1”, then execute an ADC or SBC instruction. After executing
an ADC or SBC instruction, execute at least one instr uction be-
fore executing a SEC, CLC, or CLD instruction.
• In decimal mode, the values of the negative (N), overflow (V),
and zero (Z) flags are invalid.
Timers
If a value n (between 0 and 255) is written to a timer latch, the fre-
quency division ratio is 1/(n + 1).
Multiplication and Division Instructions
The index mode (T) and the decimal mode (D) flags do not affect
the MUL and DIV instruction.
The execution of these instructions does not change the contents
of the processor status register.
Ports
The contents of the port direction registers cannot be read.
The following cannot be used:
• The data transfer instruction (LDA, etc.)
• The operation instruction when the index X mode flag (T) is “1”
• The addressing mode which uses the value of a direction regis-
ter as an index
• The bit-test instr uction (BBC or BBS, etc.) to a direction register
• The read-modify-wr ite instruction (ROR, CLB, or SEB, etc.) to a
direction register
Use instructions such as LDM and STA, etc., to set the port direc-
tion registers.
Serial I/O
In clock synchronous serial I/O, if the receive side is using an ex-
ternal clock and it is to output the SRDY signal, set the transmit
enable bit, the receive enable bit, and the SRDY output enable bit
to “1”.
Serial I/O1 continues to output the final bit from the TXD pin after
transmission is completed.
In serial I/O2, the SOUT2 pin goes to high impedance state after
transmission is completed.
A-D Converter
The comparator uses inter nal capacitors whose charge will be lost
if the clock frequency is too low.
Make sure that f(XIN) is at least 500 kHz dur ing an A-D conver-
sion.
Do not execute the STP or WIT instruction dur ing an A-D conver-
sion.
Instruction Execution Time
The instruction execution time is obtained by multiplying the fre-
quency of the internal clock φ by the number of cycles needed to
execute an instruction.
The number of cycles required to execute an instruction is shown
in the list of machine instructions.
The frequency of the internal clock φ is half of the XIN frequency.
49
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3827 Group
DATA REQUIRED FOR MASK ORDERS
The follo wing are necessar y when order ing a mask ROM produc-
tion:
(1) Mask ROM Order Confirmation Form
(2) Mark Specification For m
(3) Data to be written to ROM, in EPROM for m (three identical
copies)
DATA REQUIRED FOR ROM WRITING OR-
DERS
The following are necessary when ordering a ROM writing:
(1) ROM Wr iting Confirmation Form
(2) Mark Specification For m
(3) Data to be written to ROM, in EPROM for m (three identical
copies)
ROM PROGRAMMING METHOD
The built-in PROM of the blank One Time PROM version and built-
in EPROM version can be read or programmed with a
general-purpose PROM programmer using a special programming
adapter. Set the address of PROM programmer in the user ROM
area.
Fig. 55 Programming and testing of One Time PROM version
Package
100PFB-A
100P6Q-A
100P6S-A
100D0
Name of Programming Adapter
Under development (PCA4738H-100A)
PCA4738G-100A
PCA4738F-100A
PCA4738L-100A
Table 10 Special programming adapter
The PROM of the blank One Time PROM version is not tested or
screened in the assembly process and following processes. To en-
sure proper operation after programming, the procedure shown in
Figure 55 is recommended to verify programming.
Programming with PROM
programmer
Screening (Caution)
(150°C for 40 hours)
Verification with
PROM programmer
Functional check in
target device
The screening temperature is far higher
than the storage temperature. Never
expose to 150 °C exceeding 100 hours.
Caution :
50
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
3827 Group
MITSUBISHI MICROCOMPUTERS
V
V
“H” input voltage P00–P07, P10–P17, P40, P43, P45, P47, P50–P53,
P56, P61, P64–P67, P71–P77
“H” input voltage P20–P27, P41, P42, P44, P46, P54, P55, P57, P60,
P62, P63, P70
RESET
XIN
“L” input voltage P00–P07, P10–P17, P40, P43, P45, P47, P50–P53,
P56, P61, P64–P67, P71–P77
“L” input voltage P20–P27, P41, P42, P4 4, P46, P54, P55, P57, P60,
P62, P63, P70
RESET
XIN
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Table 11 Absolute maximum ratings
RECOMMENDED OPERATING CONDITIONS
Table 12 Recommended operating conditions (VCC = 2.5 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Power source voltage
A-D, D-A conversion reference voltage
Analog power source voltage
Analog input voltage AN0–AN7
5.5
5.5
5.5
VCC+0.3
VCC
VCC
VSS
VREF
AVSS
VIA
Symbol Parameter Limits
Min.
V
V
V
V
V
Unit
4.0
2.2
2.2
2.7
AVSS
5.0
5.0
5.0
0
0
Typ. Max.
Power source voltage
VO
VO
VO
VO
Pd
Topr
Tstg
–0.3 to 7.0 VPower source voltage
Input voltage P0 0–P07, P10–P17, P20–P27,
P41–P47, P50–P57, P60–P67
Input voltage P4 0, P71–P77
Input voltage P7 0
Input voltage V L1
Input voltage V L2
Input voltage V L3
Input voltage C1, C2
Input voltage RESET, XIN
Output voltage C1, C2
VCC
VI
Symbol Parameter Conditions Ratings Unit
All voltages are based on VSS.
Output transistors are cut off.
VI
VI
VI
VI
VI
VI
VI
VO
VO
VO
Output voltage P0 0–P07, P10–P15, P30–P37
Output voltage P16, P17, P20–P27, P41–P47,
P50–P57, P60–P67, P80, P8 1
Output voltage P40, P71–P77
Output voltage V L3
Output voltage V L2, SEG0–SEG17
Output voltage XOUT
Power dissipation
Operating temperature
Storage temperature
At output port
At segment output
Ta = 25°C
–0.3 to VCC +0.3
–0.3 to 7.0
–0.3 to VCC +0.3
–0.3 to VL2
VL1 to VL3
VL2 to 7.0
–0.3 to 7.0
–0.3 to VCC +0.3
–0.3 to 7.0
–0.3 to VCC
–0.3 to VL3
–0.3 to VCC +0.3
–0.3 to 7.0
–0.3 to 7.0
–0.3 to VL3
–0.3 to VCC +0.3
300
–20 to 85
–40 to 125
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
mW
°C
°C
High-speed mode f(XIN) = 8 MHz
Middle-speed mode f(XIN) = 8 MHz
Low-speed mode
“H” input voltage
“H” input voltage
VIH
VIH
VIH
VIH
VIL
VIL
VIL
VIL “L” input voltage
“L” input voltage
0.7 VCC
0.8 VCC
0.8 VCC
0.8 VCC
0
0
0
0
VCC
VCC
VCC
VCC
0.3 VCC
0.2 VCC
0.2 VCC
0.2 VCC
V
V
V
V
V
V
51
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3827 Group
P00–P07, P1 0–P17, P20–P27, P30–P37 (Note 1)
P41–P47, P5 0–P57, P60–P67 (Note 1)
P00–P07, P1 0–P17, P20–P27, P30–P37 (Note 1)
P41–P47, P5 0–P57, P60–P67 (Note 1)
P40, P71–P77 (Note 1)
P00–P07, P1 0–P17, P20–P27, P30–P37 (Note 1)
P41–P47, P5 0–P57, P60–P67 (Note 1)
P00–P07, P1 0–P17, P20–P27, P30–P37 (Note 1)
P41–P47, P5 0–P57, P60–P67 (Note 1)
P40, P71–P77 (Note 1)
P00–P07, P1 0–P15, P30–P37 (Note 2)
“H” peak output current P16, P17, P20–P27, P41–P47, P50–P57, P60–P67
(Note 2)
P00–P07, P1 0–P15, P30–P37 (Note 2)
“L” peak output current P16, P17, P20–P27, P41–P47, P50–P57, P60–P67
(Note 2)
P40, P71–P77 (Note 2)
P00–P07, P1 0–P15, P30–P37 (Note 3)
P16, P17, P20–P27, P41–P47, P50–P57, P60–P67
P00–P07, P1 0–P15, P30–P37 (Note 3)
“L” average output current P16, P17, P20–P27, P41–P47, P50–P57, P60–P67
(Note 3)
P40, P71–P77 (Note 3)
–20
–20
20
20
80
–10
–10
10
10
40
–1.0
Table 13 Recommended operating conditions (VCC = 2.2 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Notes1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured
over 100 ms. The total peak current is the peak value of all the currents.
2: The peak output current is the peak current flowing in each port.
3: The average output current is an average value measured over 100 ms.
“H” total peak output current
“H” total peak output current
“L” total peak output current
“L” total peak output current
“L” total peak output current
“H” total average output current
“H” total average output current
“L” total average output current
“L” total average output current
“L” total average output current
“H” peak output current
ΣIOH(peak)
ΣIOH(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOH(avg)
ΣIOH(avg)
ΣIOL(avg)
ΣIOL(avg)
ΣIOL(avg)
IOH(peak)
Symbol Parameter Limits
Min. mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Unit
Typ. Max.
“L” peak output current
“L” peak output current
“H” average output current
“H” average output current
“L” average output current
“L” average output current
IOH(peak)
IOL(peak)
IOL(peak)
IOL(peak)
IOH(avg)
IOH(avg)
IOL(avg)
IOL(avg)
IOL(avg)
–5.0
5.0
10
20
–0.5
–2.5
2.5
5.0
10
mA
mA
mA
mA
mA
mA
mA
mA
mA
52
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
3827 Group
MITSUBISHI MICROCOMPUTERS
Table 14 Recommended operating conditions (Mask ROM version) (VCC = 2.2 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Notes1: When the oscillation frequency has a duty cycle of 50%.
2: When using the microcomputer in low-speed mode, make sure that the sub-clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3.
Input frequency for timers X and Y
(duty cycle 50%)
f(CNTR0)
f(CNTR1)
Symbol Parameter Limits
Min. MHz
Unit
Typ. Max.
(4.0 V ≤ VCC ≤ 5.5 V)
32.768
4.0
Main clock input oscillation frequency
(Note 1)
Sub-clock input oscillation frequency (Notes 1, 2)
f(XIN)
f(XCIN)
(2.2 V ≤ VCC ≤ 4.0 V)
High-speed mode
(4.0 V ≤ VCC ≤ 5.5 V)
High-speed mode
(2.2 V ≤ VCC ≤ 4.0 V)
Middle-speed mode
(10✕VCC
–4)/9
8.0
(20✕VCC
–8)/9
8.0
50
MHz
MHz
MHz
MHz
kHz
Table 15 Recommended operating conditions (PROM version) (VCC = 2.5 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Notes1: When the oscillation frequency has a duty cycle of 50%.
2: When using the microcomputer in low-speed mode, make sure that the sub-clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3.
Input frequency for timers X and Y
(duty cycle 50%)
f(CNTR0)
f(CNTR1)
Symbol Parameter Limits
Min. MHz
Unit
Typ. Max.
(4.0 V ≤ VCC ≤ 5.5 V)
32.768
4.0
Main clock input oscillation frequency
(Note 1)
Sub-clock input oscillation frequency (Notes 1, 2)
f(XIN)
f(XCIN)
(2.5 V ≤ VCC ≤ 4.0 V)
High-speed mode
(4.0 V ≤ VCC ≤ 5.5 V)
High-speed mode
(2.5 V ≤ VCC ≤ 4.0 V)
Middle-speed mode
(2✕VCC)
–4
8.0
(4✕VCC)
–8
8.0
50
MHz
MHz
MHz
MHz
kHz
Test conditions
Test conditions
53
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3827 Group
VCC = 5.0 V , VO = V CC, Pull-ups “on”
Output transistors “off”
VCC = 2.2 V , VO = V CC, Pull-ups “on”
Output transistors “off”
VO = VCC, Pull-ups “off”
Output transistors “off”
VO = VSS, Pull-ups “off”
Output transistors “off”
IOL = 10 mA
IOL = 3.0 mA
IOL = 2.5 mA
VCC = 2.2 V
IOL = 5 mA
IOL = 1.5 mA
IOL = 1.25 mA
VCC = 2.2 V
VOL
IOH = –1 mA
IOH = –0.25 mA
VCC = 2.2 V
IOH = –5 mA
IOH = –1.5 mA
IOH = –1.25 mA
VCC = 2.2 V
VVCC–2.0
“H” output voltage
P00–P07, P10–P15, P30–P37
Symbol Parameter Limits
Min. Unit
0.5
Typ. Max.
Test conditions
VOH
2.0
0.5
Table 16 Electrical characteristics (VCC =4.0 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
IOL = 10 mA
IOL = 5 mA
VCC = 2.2 V
VI = VCC
VI = V CC
VI = V CC
VI = V SS
Pull-ups “off”
VCC = 5 V, VI = V SS
Pull-ups “on”
VCC = 2.2 V, V I = VSS
Pull-ups “on”
VI = VSS
VI = VSS
“H” output voltage
P16, P17, P20–P27, P41–P47, P50–P57,
P60–P67 (Note 1)
“L” output voltage
P00–P07, P10–P15, P30–P37
“L” output voltage
P16, P17, P20–P27, P41–P47, P50–P57,
P60–P67
“L” output voltage
P40, P71–P77
Hysteresis
INT0–INT2, ADT, CNTR0, CNTR1, P20–P27
Hysteresis SCLK, RXD
Hysteresis RESET
“H” input current
P00–P07, P10–P17, P20–P27, P40–P47,
P50–P57, P60–P67, P70–P77
“H” input current RESET
“H” input current XIN
“L” input current
P00–P07, P10–P17, P20–P27,P40–P47,
P50–P57, P60–P67, P70–P77
“L” input current P70
“L” input current RESET
“L” input current XIN
Output load current
P30–P37
Output leak current
P30–P37
VOH
VOL
VOL
VT+ – VT–
VT+ – VT–
VT+ – VT–
IIH
IIH
IIH
IIL
IIL
IIL
ILEAK
VCC–2.0
VCC–0.5
–60.0
–5.0
–60.0
–5.0
0.5
0.5
4.0
–120.0
–20.0
–4.0
–20.0
2.0
0.5
0.5
5.0
5.0
–5.0
–240.0
–40.0
–5.0
–5.0
–240.0
–40.0
5.0
–5.0
V
V
V
V
V
V
V
V
V
V
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
IIL
ILOAD
VCC–0.8
VCC–0.8
V
V
V0.8
V
0.8
0.3 V
µA
µA
µA–120.0
54
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
3827 Group
MITSUBISHI MICROCOMPUTERS
Table 17 Electrical characteristics (VCC =2.2 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
V
5.5
• High-speed mode, VCC = 5 V
f(XIN) = 8 MHz
f(XCIN) = 32.768 kHz
Output transistors “off”
A-D converter in operating
• High-speed mode, VCC = 5 V
f(XIN) = 8 MHz (in WIT state)
f(XCIN) = 32.768 kHz
Output transistors “off”
A-D converter in operating
• Low-speed mode, V CC = 5 V, Ta ≤ 55°C
f(XIN) = stopped
f(XCIN) = 32.768 kHz
Output transistors “off”
• Low-speed mode, VCC = 5 V, Ta = 25°C
f(XIN) = stopped
f(XCIN) = 32.768 kHz (in WIT state)
Output transistors “off”
• Low-speed mode, V CC = 3 V, Ta ≤ 55°C
f(XIN) = stopped
f(XCIN) = 32.768 kHz
Output transistors “off”
• Low-speed mode, V CC = 3 V, Ta ≤ 25°C
f(XIN) = stopped
f(XCIN) = 32.768 kHz (in WIT state)
Output transistors “off”
All oscillation stopped
(in STP state)
Output transistors “off”
Symbol Parameter Limits
Min. Unit
Typ. Max.
Ta = 25 °C
Ta = 85 °C
Test conditions
ICC Power source current
6.4
VRAM RAM retention voltage At clock stop mode 2.0
When using voltage multiplier
VL1 = 1.8 V
VL1 < 1.3 V
VL1
IL1
Power source voltage
Power source current (VL1)
(Note)
Note: When the voltage multiplier control bit of the LCD mode register (bit 4 at address 003916) is “1”.
1.3
1.6
35
20
15.0
4.5
0.1
1.8
3.0
10.0
3.2
70
40
22.0
9.0
1.0
10.0
2.3
6.0
50.0
mA
µA
µA
µA
µA
µA
V
mA13
µA
55
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3827 Group
Table 18 A-D converter characteristics
(VCC = 2.2 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, 4 MHz ≤ f(XIN) ≤ 8 MHz, in middle/high-speed mode unless otherwise noted)
Symbol Parameter Limits
Min. Unit
Typ. Max.
Test conditions
– Resolution
Absolute accuracy
(excluding quantization error) VCC ≥ VREF = 4 V
VCC ≥ VREF = 2.7 V
30.5
Bits
LSB
LSB
35
10
±2.5
±4.0
31
(Note)
Note: When an internal trigger is used in middle-speed mode, it is 34 µs.
µsf(XIN) = 4 MHz
VREF = 5 V
Conversion time
Ladder resistor
Reference power source input current
–
tCONV
RLADDER
IVREF
kΩ
µA
Table 19 D-A converter characteristics
(VCC = 2.2 to 5.5 V, VCC = VREF, VSS = AVSS = 0 V, Ta = –20 to 85°C, in middle/high-speed mode unless otherwise noted)
Symbol Parameter Limits
Min. Unit
Typ. Max.
Test conditions
–Resolution VCC = VREF = 5 V
VCC = VREF = 2.7 V
1
Bits
%
%
µs
kΩ
mA
3
2.5
8
1.0
2.0
Note: Using one D-A converter, with the value in the D-A conversion register of the other D-A converter being “0016”, and excluding currents flowing through
the A-D resistance ladder.
(Note)
Setting time
Output resistor
–
tsu
RO4
6.0
50
Absolute accuracy
Analog port input currentIIA
IVREF Reference power source input current
µA
200
5.0
150
0.5
56
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
3827 Group
MITSUBISHI MICROCOMPUTERS
Table 20 Timing requirements 1 (VCC = 4.0 to 5.5 V, V SS = 0 V, Ta = –20 to 85°C, unless otherwise noted)
2
125
45
40
250
105
105
80
80
800
370
370
220
100
1000
400
400
200
200
Note: When bit 6 of address 001A 16 is “1”.
Divide this value by four when bit 6 of address 001A16 is “0”.
Reset input “L” pulse width
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT2 input “H” pulse width
INT0 to INT2 input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O1 input set up time
Serial I/O1 input hold time
Serial I/O2 clock input cycle time (Note)
Serial I/O2 clock input “H” pulse width (Note)
Serial I/O2 clock input “L” pulse width (Note)
Serial I/O2 input set up time
Serial I/O2 input hold time
tw(RESET)
tc(XIN)
twH(XIN)
twL(XIN)
tc(CNTR)
twH(CNTR)
twL(CNTR)
twH(INT)
twL(INT)
tc(SCLK1)
twH(SCLK1)
twL(SCLK1)
t
su(R
X
D–S
CLK1
)
th(SCLK1–RXD)
tc(SCLK2)
twH(SCLK2)
twL(SCLK2)
t
su(S
IN2
–S
CLK2
)
th(SCLK2–SIN2)
Symbol Parameter Limits
Min. µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
Typ. Max.
Table 21 Timing requirements 2 (VCC = 2.2 to 4.0 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted)
2
125
45
40
900/(VCC–0.4)
tc(CNTR)/2–20
tc(CNTR)/2–20
230
230
2000
950
Reset input “L” pulse width
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT2 input “H” pulse width
INT0 to INT2 input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O1 clock input “H” pulse width (Note)
tw(RESET)
tc(XIN)
twH(XIN)
twL(XIN)
tc(CNTR)
twH(CNTR)
twL(CNTR)
twH(INT)
twL(INT)
tc(SCLK1)
twH(SCLK1)
Symbol Parameter Limits
Min. µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
Typ. Max.
Note: When bit 6 of address 001A 16 is “1”.
Divide this value by four when bit 6 of address 001A16 is “0”.
t
su(S
IN2
–S
CLK2
)
th(SCLK2–SIN2)
twL(SCLK1)
t
su(R
X
D–S
CLK1
)
th(SCLK1–RXD)
tc(SCLK2)
twH(SCLK2)
twL(SCLK2)
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O1 input set up time
Serial I/O1 input hold time
Serial I/O2 clock input cycle time (Note)
Serial I/O2 clock input “H” pulse width (Note)
Serial I/O2 clock input “L” pulse width (Note)
Serial I/O2 input set up time
Serial I/O2 input hold time
950
400
200
2000
950
950
400
300
ns
ns
ns
ns
ns
ns
ns
ns
57
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3827 Group
Table 22 Switching characteristics 1 (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Notes1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: XOUT and XCOUT pins are excluded.
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O1 output valid time (Note 1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
Serial I/O2 output valid time
Serial I/O2 clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
140
30
30
0.2 ✕ tC (SCLK2)
40
30
30
Symbol Parameter Limits
Min. ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
tC (SCLK1)/2–30
tC (SCLK1)/2–30
–30
10
10
Typ. Max.
twH(SCLK1)
twL(SCLK1)
td(SCLK1–TXD)
tv(SCLK1–TXD)
tr(SCLK1)
tf(SCLK1)
twH(SCLK2)
twL(SCLK2)
t
d(S
CLK2
–S
OUT2
)
t
v(S
CLK2
–S
OUT2
)
tf(SCLK2)
tr(CMOS)
tf(CMOS)
Table 23 Switching characteristics 2 (VCC = 2.2 to 4.0 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
Notes1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: XOUT and XCOUT pins are excluded.
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O1 output valid time (Note 1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
Serial I/O2 output valid time
Serial I/O2 clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
350
50
50
0.2 ✕ tC (SCLK2)
50
50
50
Symbol Parameter Limits
Min.
tC (SCLK1)/2–50
tC (SCLK1)/2–50
–30
20
20
Max.
twH(SCLK1)
twL(SCLK1)
td(SCLK1–TXD)
tv(SCLK1–TXD)
tr(SCLK1)
tf(SCLK1)
twH(SCLK2)
twL(SCLK2)
t
d(S
CLK2
–S
OUT2
)
t
v(S
CLK2
–S
OUT2
)
tf(SCLK2)
tr(CMOS)
tf(CMOS)
Typ.
tC (SCLK2)/2–160
tC (SCLK2)/2–160
0
t
C
(S
CLK2
)/2–240
t
C
(S
CLK2
)/2–240
0
58
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
3827 Group
MITSUBISHI MICROCOMPUTERS
Fig. 56 Circuit for measuring output switching characteristics
Measurement output pin
100 pF
CMOS output
Note : When bit 4 of the UART
control register (address 001B16) is “1”.
(N-channel open-drain output mode)
N-channel open-drain output (Note)
1 kΩ
100 pF
Measurement output pin
59
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3827 Group
Fig. 57 Timing diagram
0.2V
CC
t
d
(S
CLK
-T
X
D)
t
f
0.2V
CC
0.8V
CC
0.8V
CC
t
r
t
su
(R
X
D-S
CLK
)t
h
(S
CLK
-R
X
D)
t
v
(S
CLK
-T
X
D)
t
C
(S
CLK
)
t
WL
(S
CLK
) t
WH
(S
CLK
)
T
X
D
R
X
D
S
CLK
0.2V
CC
t
WL
(X
IN
)
0.8V
CC
t
WH
(X
IN
)t
C
(X
IN
)
X
IN
0.2V
CC
0.8V
CC
t
W
(RESET)
RESET
0.2V
CC
t
WL
(CNTR)
0.8V
CC
t
WH
(CNTR)
t
C
(CNTR)
0.2V
CC
t
WL
(INT)
0.8V
CC
t
WH
(INT)
CNTR
0
,
CNTR
1
INT
0
–INT
3
60
3827 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
GZZ-SH52-92B<85A0>
Receipt
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38277M8MXXXFP/GP/HP
MITSUBISHI ELECTRIC
Mask ROM number
Date:
Section head
signature Supervisor
signature
Company
name
Note : Please fill in all items marked ❈.
Customer
❈
Issuance
signature
Date
issued
Submitted by
TEL
()
Date:
Supervisor
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We
shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Checksum code for entire EPROM (hexadecimal notation)
(1) Set the data in the unused area (the shaded area of the
diagram) to “FF16”.
(2) The ASCII codes of the product name “M38277M8M” must
be entered in addresses 000016 to 000816. And set data
“FF16” in addresses 000916 to 000F16. The ASCII codes
and addresses are listed to the right in hesadecimal
notation.
(1/2)
Address
000016
000116
000216
000316
000416
000516
000616
000716
‘M’ = 4D 16
‘3’ = 3316
‘8’ = 3816
‘2’ = 3216
‘7’ = 3716
‘7’ = 3716
‘M’ = 4D 16
‘8’ = 3816
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘ M ’ =4D16
FF16
FF16
FF16
FF16
FF16
FF16
FF16
Product name: M38277M8MXXXFP M38277M8MXXXGP M38277M8MXXXHP
MASK ROM ORDER CONFIRMATION FORM
In the address space of the microcomputer,
the internal ROM area is from address 8080 16
to FFFD16. The reset vector is stored in
addresses FFFC16 and FFFD16.
EPROM type (indicate the type used)
27512
000016
000F16
001016
807F16
808016
FFFD16
FFFE16
FFFF16
EPROM address
Product name
ASCII code :
‘M38277M8M’
Data
ROM 32K-130 bytes
61
3827 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38277M8MXXXFP/GP/HP
MITSUBISHI ELECTRIC
GZZ-SH52-92B<85A0> Mask ROM number
We recommend the use of the following pseudo-command to set the start address of the assembier source program because
ASCII codes of the product name are written to addresses 000016 to 000816 of EPROM.
27512EPROM type
The pseudo-command *=∆$0000
.BYTE∆ ‘M38277M8M’
Note: If the name of the product written to the EPROMs does not match the name of the mask ROM confirmation form, the ROM
will not be processed.
(2/2)
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark
specification form (100P6S for M38277M8MXXXFP, 100P6Q for M38277M8MXXXGP, 100PFB for M38277M8MXXXHP)
and attach it to the mask ROM confirmation form.
❈ 3. Usage conditions
Please answer the following questions about usage for use in our product inspection :
(1) How will you use the XIN-XOUT oscillator?
At what frequency? f(XIN) =
Ceramic resonator
External clock input
Quartz crystal
Other ( )
MHz
(2) How will you use the XCIN-XCOUT oscillator?
Ceramic resonator Quartz crystal
❈ 4. Comments
At what frequency? f(XCIN) =
Other ( )
MHz
62
3827 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
ROM PROGRAMMING CONFIRMATION FORM
GZZ-SH51-93B<85A0>
Receipt
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38279EF-XXXFP/GP/HP
MITSUBISHI ELECTRIC
ROM number
Date:
Section head
signature Supervisor
signature
Company
name
Note : Please fill in all items marked ❈.
Customer
❈
Issuance
signature
Date
issued
Submitted by
TEL
()
Date:
Supervisor
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce ROM programming based on
this data. We shall assume the responsibility for errors only if the programming data on the products we produce differs
from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Checksum code for entire EPROM (hexadecimal notation)
In the address space of the microcomputer,
the internal ROM area is from address 108016
to FFFD16. The reset vector is stored in
addresses FFFC16 and FFFD16.
(1) Set the data in the unused area (the shaded area of the
diagram) to “FF16”.
(2) The ASCII codes of the product name “M38279EF-” must
be entered in addresses 000016 to 000816. And set data
“FF16” in addresses 000916 to 000F16. The ASCII codes
and addresses are listed to the right in hesadecimal
notation.
EPROM type (indicate the type used)
27512
000016
000F16
001016
107F16
108016
FFFD16
FFFE16
FFFF16
EPROM address
Product name
ASCII code :
‘M38279EF-’
Data
ROM 60K-130 bytes
(1/2)
Address
000016
000116
000216
000316
000416
000516
000616
000716
‘M’ = 4D 16
‘3’ = 3316
‘8’ = 3816
‘2’ = 3216
‘7’ = 3716
‘9’ = 3916
‘E’ = 4516
‘F’ = 4616
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘ – ’ =2D16
FF16
FF16
FF16
FF16
FF16
FF16
FF16
Product name: M38279EF-XXXFP M38279EF-XXXGP M38279EF-XXXHP
63
3827 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38279EF-XXXFP/GP/HP
MITSUBISHI ELECTRIC
GZZ-SH51-93B<85A0> ROM number
We recommend the use of the following pseudo-command to set the start address of the assembier source program because
ASCII codes of the product name are written to addresses 000016 to 000816 of EPROM.
27512EPROM type
The pseudo-command *=∆$0000
.BYTE∆ ‘M38279EF-’
Note: If the name of the product written to the EPROMs does not match the name of the ROM programming confirmation form,
the ROM will not be processed.
(2/2)
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark
specification form (100P6S for M38279EF-XXXFP, 100P6Q for M38279EF-XXXGP, 100PFB for M38279EF-XXXHP) and
attach it to the ROM programming confirmation form.
❈ 3. Usage conditions
Please answer the following questions about usage for use in our product inspection :
(1) How will you use the XIN-XOUT oscillator?
At what frequency? f(XIN) =
Ceramic resonator
External clock input
Quartz crystal
Other ( )
MHz
(2) How will you use the XCIN-XCOUT oscillator?
Ceramic resonator Quartz crystal
❈ 4. Comments
At what frequency? f(XCIN) =
Other ( )
MHz
64
3827 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
QFP100-P-1420-0.65 1.58
Weight(g)
–
JEDEC Code
EIAJ Package Code Lead Material
Alloy 42
100P6S-A
Plastic 100pin 14✕20mm body QFP
–
0.1
–
––
0.2
–
–
––
–
–
––
–
Symbol Min Nom Max
A
A
2
b
c
D
E
H
E
L
L
1
y
b
2
Dimension in Millimeters
H
D
A
1
0.35 ––
I
2
1.3 ––
M
D
14.6 ––
M
E
20.6
10°0°0.1
1.4 0.80.60.4 23.122.822.5 17.116.816.5 0.65 20.220.019.8 14.214.013.8 0.20.150.13 0.40.30.25 2.8
03.05
e
e
e
E
c
H
E
1
30
31
81
50
80
51
H
D
D
M
D
M
E
A
F
b
A
1
A
2
L
1
L
y
b
2
I
2
Recommended Mount Pad
Detail F
100
LQFP100-P-1414-0.50 Weight(g)
–
JEDEC Code
EIAJ Package Code Lead Material
Cu Alloy
100P6Q-A
Plastic 100pin 14✕14mm body LQFP
–
0.1
–
––
0.2
–
–
––
–
–
––
–
Symbol Min Nom Max
A
A
2
b
c
D
E
H
E
L
L
1
y
b
2
Dimension in Millimeters
H
D
A
1
0.225 ––
I
2
1.0 ––
M
D
14.4 ––
M
E
14.4
10°0°0.1
1.0 0.70.50.3 16.216.015.8 16.216.015.8 0.5 14.114.013.9 14.114.013.9 0.1750.1250.105 0.280.180.13 1.4
01.7
e
e
e
E
c
H
E
1
76
75
51
50
26
25
H
D
D
M
D
M
E
A
F
b
A
1
A
2
L
1
L
y
b
2
I
2
Recommended Mount Pad
Detail F
100
65
3827 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
TQFP100-P-1212-0.40 Weight(g)
–
JEDEC Code
EIAJ Package Code Lead Material
Cu Alloy
100PFB-A
Plastic 100pin 12✕12mm body TQFP
––
––
–
–
––
–
–
––
–
Symbol Min Nom Max
A
A
2
b
c
D
E
H
E
L
L
1
y
b
2
Dimension in Millimeters
H
D
A
1
0.150.1
0.225 ––
I
2
1.0 ––
M
D
12.4 ––
M
E
12.4
8°0° 0.08
1.0 0.6 0.50.4 14.214.013.8 14.214.013.8 0.4 12.112.011.9 12.112.011.9 0.1750.1250.105 0.230.180.13 1.0
0.05 1.2
e
H
E
E
D
H
D
1
25
75
76
100
26 50
51
F
b
e
c
L
L
1
A
1
A
2
A
M
E
b
2
l
2
M
D
e
Recommended Mount Pad
Detail F
y
Under Development
Weight(g)
JEDEC Code
EIAJ Package Code
100D0
Glass seal 100pin QFN
––
31
50 81
51 80
30
1
1.075TYP
0.45TYP0.65TYP
INDEX
3.5TYP
5.0MAX
0.65TYP
1.075TYP
0.35TYP 0.65TYP
12.35±0.15
15.6±0.13
21.0±0.13
18.85±0.15
100
66
3827 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Customer’s Par ts Number
Note : The fonts and size of characters are standard Mitsubishi type.
Mitsubishi IC catalog name
Note1 : The mark field should be written right aligned.
2 : The fonts and size of characters are standard Mitsubishi type.
3 : Customer’s Parts Number can be up to 14 characters : Only 0 ~
9, A ~ Z, +, –, /, (, ), &, ,. (periods),, (commas) are usable.
4 : If the Mitsubishi logo is not required, check the box below.
Mitsubishi logo is not required
100P6S (100-PIN QFP) MARK SPECIFICATION FORM
Mitsubishi IC catalog name
Please choose one of the marking types below (A, B, C), and enter the Mitsubishi catalog name and the special mark (if needed).
A. Standard Mitsubishi Mark
C. Special Mark Required
B. Customer’s Parts Number + Mitsubishi catalog name
Mitsubishi IC catalog name
Note1 : If the Special Mark is to be Printed, indicate the desired
layout of the mark in the left figure. The layout will be
duplicated as close as possible.
Mitsubishi lot number (6-digit or 7-digit) and Mask ROM
number (3-digit) are always marked.
2 : If the customer’s tr ade mark logo must be used in the
Special Mark, check the box belo w.
Please submit a clean original of the logo.
For the new special character fonts a clean font original
(ideally logo drawing) must be submitted.
Special logo required
1
30
31
81 50
80 51
100
Mitsubishi lot number
(6-digit or 7-digit)
1
30
31
81 50
80 51
100
1
30
31
81 50
80 51
100
67
3827 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
1
76
75 51
50
26
25
100
Mitsubishi lot number
(6-digit or 7-digit)
Customer’s Parts Number
Note : The fonts and size of characters are standard Mitsubishi type.
Mitsubishi IC catalog name
Note1 : The mark field should be written right aligned.
2 : The fonts and size of characters are standard Mitsubishi type.
3 : Customer’s Parts Number can be up to 12 characters : Only 0 ~
9, A ~ Z, +, –, /, (, ), &, ,. (periods),, (commas) are usable.
4 : If the Mitsubishi logo is not required, check the box below.
Mitsubishi logo is not required
100P6Q (100-PIN LQFP) MARK SPECIFICATION FORM
Mitsubishi IC catalog name
Please choose one of the marking types below (A, B, C), and enter the Mitsubishi catalog name and the special mark (if needed).
A. Standard Mitsubishi Mark
C. Special Mark Required
B. Customer’s Parts Number + Mitsubishi catalog name
Mitsubishi IC catalog name
Mitsubishi IC catalog name
Note1 : If the Special Mark is to be Printed, indicate the desired
layout of the mark in the left figure. The layout will be
duplicated as close as possible.
Mitsubishi lot number (6-digit or 7-digit) and Mask ROM
number (3-digit) are always marked.
2 : If the customer’s tr ade mark logo must be used in the
Special Mark, check the box belo w.
Please submit a clean original of the logo.
For the new special character fonts a clean font original
(ideally logo drawing) must be submitted.
Special logo required
Mitsubishi lot number
(6-digit or 7-digit)
1
76
75 51
50
26
25
100
1
76
75 51
50
26
25
100
68
3827 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Customer’s Par ts Number
Note : The fonts and size of characters are standard Mitsubishi type.
Mitsubishi IC catalog name
Note1 : The mark field should be written right aligned.
2 : The fonts and size of characters are standard Mitsubishi type.
3 : Customer’s Parts Number can be up to 10 characters : Only 0 ~
9, A ~ Z, +, –, /, (, ), &, ,. (periods),, (commas) are usable.
4 : If the Mitsubishi logo is not required, check the box below.
Mitsubishi logo is not required
100PFB (100-PIN TQFP) MARK SPECIFICATION FORM
Mitsubishi IC catalog name
Please choose one of the marking types below (A, B, C), and enter the Mitsubishi catalog name and the special mark (if needed).
A. Standard Mitsubishi Mark
C. Special Mark Required
B. Customer’s Parts Number + Mitsubishi catalog name
Mitsubishi IC catalog name
Mitsubishi IC catalog name
Note1 : If the Special Mark is to be Printed, indicate the desired
layout of the mark in the left figure. The layout will be
duplicated as close as possible.
Mitsubishi lot number (6-digit or 7-digit) and Mask ROM
number (3-digit) are always marked.
2 : If the customer’s tr ade mark logo must be used in the
Special Mark, check the box belo w.
Please submit a clean original of the logo.
For the new special character fonts a clean font original
(ideally logo drawing) must be submitted.
Special logo required
1
25
75
76
100
26
50
51
Mitsubishi lot number
(6-digit or 7-digit)
Mitsubishi lot number
(6-digit or 7-digit)
1
25
75
76
100
26
50
51
1
25
75
76
100
26
50
51
5 : The allocation of Mitsubishi IC catalog name and Mitsubishi
Product number depend on the Mitsubishi IC catalog name’s
characters, and requiring Mitsubishi logo or not.
© 1998 MITSUBISHI ELECTRIC CORP.
New publication, effective Jun. 1998.
Specifications subject to change without notice.
Notes regarding these materials
• These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any
intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
• Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts or circuit application examples
contained in these materials.
• All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi
Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor
product distributor for the latest product information before purchasing a product listed herein.
• Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact
Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for
transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
• The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials.
• If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the
approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
• Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
Keep safety first in your circuit designs!
• Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of
substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
Rev. Rev.
No. date
1.0 First Edition 980602
REVISION DESCRIPTION LIST 3827 GROUP DATA SHEET
(1/1)
Revision Description