DS5001FP DS5001FP 128K Soft Microprocessor Chip FEATURES PIN ASSIGNMENT - - - - - - BA11 P0.5/AD5 PE1 P0.6/AD6 BA10 P0.7/AD7 CE1 NC CE1N BD7 ALE BD6 PSEN BD5 P2.7/A15 BD4 * 8051 compatible microprocessor adapts to its task Accesses up to 128K bytes of nonvolatile SRAM In-system programming via on-chip serial port Can modify its own program or data memory Accesses memory on a separate Byte-wide bus Performs CRC-16 check of NV RAM memory Decodes memory and peripheral chip enables P0.4/AD4 CE2 PE2 BA9 P0.3/AD3 BA8 P0.2/AD2 BA13 P0.1/AD1 R/W P0.0/AD0 VCC0 VCC MSEL P1.0 BA14 P1.1 BA12 P1.2 BA7 P1.3 PE3 PE4 BA6 * Crashproof Operation - Maintains all nonvolatile resources for over 10 years - Power-fail Reset - Early Warning Power-fail Interrupt - Watchdog Timer - Lithium backs user SRAM for program/data storage - Precision band-gap reference for power monitor * Fully 8051 Compatible 128K bytes scratchpad RAM Two timer/counters On-chip serial port 32 parallel I/O port pins DS5001FP 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 P2.6/A14 CE3 CE4 BD3 P2.5/A13 BD2 P2.4/A12 BD1 P2.3/A11 BD0 VLI BA15 GND P2.2/A10 P2.1/A9 P2.0/A8 XTAL1 XTAL2 P3.7/RD P3.6/WR P3.5/T1 PF VRST P3.4/T0 P1.4 BA5 P1.5 BA4 P1.6 BA3 P1.7 PROG BA2 RST BA1 P3.0/RXD BA0 P3.1/TXD P3.2/INT0 P3.3/INT1 - - - - 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 * Software Security Available with DS5002FP Secure Microprocessor DESCRIPTION The DS5001FP is an 8051 compatible microprocessor based on nonvolatile RAM technology. It is designed for systems that need large quantities of nonvolatile memory. Like its predecessor the DS5000(T), the DS5001FP is substantially more flexible than a standard 8051. It provides full compatibility with the 8051 instruction set, timers, serial port, and parallel I/O ports. By using NV RAM instead of ROM, the user can pro- gram, then reprogram the microprocessor while in-system. The application software can even change its own operation. This allows frequent software upgrades, adaptive programs, customized systems, etc. In addition, by using NV SRAM, the DS5001FP is ideal for data logging applications. It also connects easily to a Dallas Real Time Clock for time stamp and date. 111996 1/25 23 Copyright 1995 by Dallas Semiconductor Corporation. All Rights Reserved. For important information regarding patents and other intellectual property rights, please refer to Dallas Semiconductor data books. DS5001FP The DS5001FP provides the benefits of NV RAM without using I/O resources. It uses a non-multiplexed Byte-wide address and data bus for memory access. This bus can perform all memory access and provides decoded chip enables for SRAM. This leaves the 32 I/O port pins free for application use. The DS5001FP uses ordinary SRAM and battery backs the memory contents with an external lithium cell. Data is maintained for over 10 years at room temperature with a very small lithium cell. A DS5001FP also provides crashproof operation in portable systems or systems with unreliable power. These features include the ability to save the operating state, Power-fail Reset, Power-fail Interrupt, and Watchdog Timer. cond 64K byte data space with four accompanying chip enables. This area can be used for memory mapped peripherals or more data storage. The DS5001FP can also use its Expanded bus on Ports 0 and 2 (like an 8051) to access an additional 64K bytes of data space. Lastly, the DS5001FP provides one additional bank switch that changes up to 60K bytes of the NV RAM program space into data memory. Thus with a small amount of logic, the DS5001 accesses up to 252K bytes of data memory. For a user that wants a pre-constructed module using the DS5001FP, RAM, lithium cell, and a real time clock; the DS2251T is available and described in separate data sheet. More details are also contained in the User's Guide section of the Secure Microcontroller Data Book. For users that desire software security, the DS5002FP is functionally identical to the DS5001FP but provides the best firmware security available. A user loads programs into the DS5001FP via its on- chip Serial Bootstrap Loader. This function supervises the loading of software into NV RAM, validates it, then becomes transparent to the user. Software can be stored in multiple 32K or one 128K byte CMOS SRAM(s). Using its internal Partitioning, the DS5001FP can divide a common RAM into user selectable program and data segments. This Partition can be selected at program loading time, but can be modified anytime later. The microprocessor will decode memory access to the SRAM, access memory via its Byte-wide bus and write-protect the memory portion designated as ROM. Combining program and data storage in one device saves board space and cost. ORDERING INFORMATION The following devices are available as standard products from Dallas Semiconductor: PART # DS5001FP-16 DESCRIPTION 80-pin QFP Max. clock speed 16 MHz, 0C to +75C operation Operating information is contained in the User's Guide section of the Secure Microcontroller Data Book. This data sheet provides ordering information, pinout, and electrical specifications. The DS5001FP offers several bank switches for access to even more memory. In addition to the primary data area of 64K bytes, a peripheral selector creates a se- 111996 2/25 24 DS5001FP DS5001FP BLOCK DIAGRAM Figure 1 XTAL 1 OSC WATCHDOG TIMER R/W EEEEEE EEEEEE II I EEEEEE IIIII II I II I ALE PSEN EA TIMING AND BUS CONTROL RST BYTE-WIDE BUS INTERFACE XTAL2 CE1-4 4 ADDRESS BA15-0 16 DATA BD7-0 8 PE1-4 4 SPECIAL FUNCTION REGISTERS VCCO PORT 0 P0.7 VCC DATA REGISTERS (128 BYTES) P0.0 LITHIUM CONTROL PF VRST P1.7 PORT 1 VLI P1.0 CPU PORT 2 P2.7 BOOTSTRAP LOADER ROM P2.0 P3.7 PORT 3 TXD P3.0 RXD TIMER 0 TIMER 1 INT0 INT1 111996 3/25 25 DS5001FP PIN DESCRIPTION PIN 11, 9, 7, 5, 1, 79, 77, 75 DESCRIPTION P0.0 - P0.7. General purpose I/O Port 0. This port is open-drain and can not drive a logic 1. It requires external pull-ups. Port 0 is also the multiplexed Expanded Address/Data bus. When used in this mode, it does not require pull-ups. 15, 17, 19, 21, 25, 27, 29, 31 P1.0 - P1.7. General purpose I/O Port 1. 49, 50, 51, 56, 58, 60, 64, 66 P2.0 - P2.7. General purpose I/O Port 2. Also serves as the MSB of the address in expanded memory accesses, and as pins of the RPC mode when used. 36 P3.0 RXD. General purpose I/O port pin 3.0. Also serves as the receive signal for the on board UART. This pin should NOT be connected directly to a PC COM port. 38 P3.1 TXD. General purpose I/O port pin 3.1. Also serves as the transmit signal for the on board UART. This pin should NOT be connected directly to a PC COM port. 39 P3.2 INT0. Interrupt 0. General purpose I/O port pin 3.2. Also serves as the active low External 40 P3.3 INT1. Interrupt 1. General purpose I/O port pin 3.3. Also serves as the active low External 41 P3.4 T0. General purpose I/O port pin 3.4. Also serves as the Timer 0 input. 44 P3.5 T1. General purpose I/O port pin 3.5. Also serves as the Timer 1 input. 45 P3.6 WR. General purpose I/O port pin. Also serves as the write strobe for Expanded bus operation. 46 P3.7 RD. General purpose I/O port pin. Also serves as the read strobe for Expanded bus operation. 34 RST - Active high reset input. A logic 1 applied to this pin will activate a reset state. This pin is pulled down internally so this pin can be left unconnected if not used. An RC power-on reset circuit is not needed and is NOT recommended. 68 PSEN - Program Store Enable. This active low signal is used to enable an external program memory when using the Expanded bus. It is normally an output and should be unconnected if not used. PSEN also is used to invoke the Bootstrap Loader. At this time, PSEN will be pulled down externally. This should only be done once the DS5001FP is already in a reset state. The device that pulls down should be open drain since it must not interfere with PSEN under normal operation. 70 ALE - Address Latch Enable. Used to de-multiplex the multiplexed Expanded Address/Data bus on Port 0. This pin is normally connected to the clock input on a '373 type transparent latch. 47, 48 XTAL2, XTAL1. Used to connect an external crystal to the internal oscillator. XTAL1 is the input to an inverting amplifier and XTAL2 is the output. 52 GND - Logic ground. 13 VCC - +5V. 12 VCCO - VCC Output. This is switched between VCC and VLI by internal circuits based on the level of VCC. When power is above the lithium input, power will be drawn from VCC. The lithium cell remains isolated from a load. When VCC is below VLI, the VCCO switches to the VLI source. VCCO should be connected to the VCC pin of an SRAM. 54 VLI - Lithium Voltage Input. Connect to a lithium cell greater than VLImin and no greater than VLImax as shown in the electrical specifications. Nominal value is +3V. 111996 4/25 26 DS5001FP PIN DESCRIPTION 53, 16, 8, 18, 80, 76, 4, 6, 20, 24, 26, 28, 30, 33, 35, 37 BA15 - 0. Byte-wide Address bus bits 15-0. This bus is combined with the non-multiplexed data bus (BD7-0) to access NV SRAM. Decoding is performed using CE1 through CE4. Therefore, BA15 is not actually needed except for monitoring and debugging. Read/write access is controlled by R/W. BA14-0 connect directly to an 8K, 32K, or 128K SRAM. If an 8K RAM is used, BA13 and BA14 will be unconnected. If a 128K SRAM is used, the micro converts CE2 and CE3 to serve as A16 and A15 respectively. 71, 69, 67, 65, 61, 59, 57, 55 BD7 - 0. Byte-wide Data bus bits 7-0. This 8 bit bi-directional bus is combined with the non-multiplexed address bus (BA14-0) to access NV SRAM. BD7-0 connect directly to an SRAM, and optionally to a Real Time Clock or other peripheral. 10 R/W - Read/Write. This signal provides the write enable to the SRAMs on the Byte-wide bus. It is controlled by the memory map and Partition. The blocks selected as Program (ROM) will be write protected. 74 CE1 - Chip Enable 1. This is the primary decoded chip enable for memory access on the Byte- wide bus. It connects to the chip enable input of one SRAM. CE1 is lithium backed. It will remain in a logic high inactive state when VCC falls below VLI. 72 CE1N - Non battery backed version of chip enable 1. This can be used with a 32K byte EPROM. It should not be used with a battery backed chip. 2 CE2 - Chip Enable 2. This chip enable is provided to access a second 32K block of memory. It connects to the chip enable input of one SRAM. When MSEL=0, the micro converts CE2 into A16 for a 128K x 8 SRAM. CE2 is lithium backed and will remain at a logic high when VCC falls below VLI. 63 CE3 - Chip Enable 3. This chip enable is provided to access a third 32K block of memory. It connects to the chip enable input of one SRAM. When MSEL=0, the micro converts CE3 into A15 for a 128K x 8 SRAM. CE3 is lithium backed and will remain at a logic high when VCC falls below VLI. 62 CE4 - Chip Enable 4. This chip enable is provided to access a fourth 32K block of memory. It connects to the chip enable input of one SRAM. When MSEL=0, this signal is unused. CE4 is lithium backed and will remain at a logic high when VCC falls below VLI. 78 PE1 - Peripheral Enable 1. Accesses data memory between addresses 0000h and 3FFFh when the PES bit is set to a logic 1. Commonly used to chip enable a Byte-wide Real Time Clock such as the DS1283. PE1 is lithium backed and will remain at a logic high when VCC falls below VLI. Connect PE1 to battery backed functions only. 3 PE2 - Peripheral Enable 2. Accesses data memory between addresses 4000h and 7FFFh when the PES bit is set to a logic 1. PE2 is lithium backed and will remain at a logic high when VCC falls below VLI. Connect PE2 to battery backed functions only. 22 PE3 - Peripheral Enable 3. Accesses data memory between addresses 8000h and BFFFh when the PES bit is set to a logic 1. PE3 is not lithium backed and can be connected to any type of peripheral function. If connected to a battery backed chip, it will need additional circuitry to maintain the chip enable in an inactive state when VCC < VLI. 23 PE4 - Peripheral Enable 4. Accesses data memory between addresses C000h and FFFFh when the PES bit is set to a logic 1. PE4 is not lithium backed and can be connected to any type of peripheral function. If connected to a battery backed chip, it will need additional circuitry to maintain the chip enable in an inactive state when VCC < VLI. 32 PROG - Invokes the Bootstrap Loader on a falling edge. This signal should be debounced so that only one edge is detected. If connected to ground, the micro will enter Bootstrap loading on power up. This signal is pulled up internally. 42 VRST - This I/O pin (open drain with internal pull-up) indicates that the power supply (VCC) has fallen below the VCCmin level and the micro is in a reset state. When this occurs, the DS5001FP will drive this pin to a logic 0. Because the micro is lithium backed, this signal is guaranteed even when VCC=0V. Because it is an I/O pin, it will also force a reset if pulled low externally. This allows multiple parts to synchronize their power-down resets. 111996 5/25 27 DS5001FP PIN DESCRIPTION 43 PF - This output goes to a logic 0 to indicate that the micro has switched to lithium backup. This corresponds to VCC < VLI. Because the micro is lithium backed, this signal is guaranteed even when VCC=0V. The normal application of this signal is to control lithium powered current to isolate battery backed functions from non-battery backed functions. 14 MSEL - Memory select. This signal controls the memory size selection. When MSEL= +5V, the DS5001FP expects to use 32K x 8 SRAMs. When MSEL = 0V, the DS5001FP expects to use a 128K x 8 SRAM. MSEL must be connected regardless of Partition, Mode, etc. 73 NC - Do not connect. INSTRUCTION SET MEMORY ORGANIZATION The DS5001FP executes an instruction set that is object code compatible with the industry standard 8051 microcontroller. As a result, software development packages such as assemblers and compilers that have been written for the 8051 are compatible with the DS5001FP. A complete description of the instruction set and operation are provided in the User's Guide section of the Secure Microcontroller Data Book. Figure 2 illustrates the memory map accessed by the DS5001FP. The entire 64K of program and 64K of data are potentially available to the Byte-wide bus. This preserves the I/O ports for application use. The user controls the portion of memory that is actually mapped to the Byte-wide bus by selecting the Program Range and Data Range. Any area not mapped into the NV RAM is reached via the Expanded bus on Ports 0 and 2. An alternate configuration allows dynamic Partitioning of a 64K space as shown in Figure 3. Selecting PES=1 provides another 64K of potential data storage or memory mapped peripheral space as shown in Figure 4. These selections are made using Special Function Registers. The memory map and its controls are covered in detail in the User's Guide section of the Secure Microcontroller Data Book. Also note that the DS5001FP is embodied in the DS2251T module. The DS2251T combines the DS5001FP with between 32K and 128K of SRAM, a lithium cell, and a real time clock. This is packaged in a 72-pin SIMM module. 111996 6/25 28 DS5001FP DS5001FP MEMORY MAP IN NON-PARTITIONABLE MODE (PM=1) Figure 2 64K PROGRAM RANGE DATA RANGE NONVOLATILE PROGRAM RAM NONVOLATILE DATA RAM 255 127 128 0 0 DATA REGISTERS SPECIAL FUNCTION REGISTERS PROGRAM MEMORY DATA MEMORY PROGRAM RANGE EITHER 32K OR 64K DATA RANGE EITHER 32K OR 64K LEGEND: = ON-CHIP REGISTERS = ACCESSED VIA BYTEWIDE BUS = ACCESSED VIA EXPANDED BUS (PORTS 0 AND 2) 111996 7/25 29 DS5001FP DS5001FP MEMORY MAP IN PARTITIONABLE MODE (PM=0) Figure 3 64K RANGE NONVOLATILE DATA RAM PARTITION NONVOLATILE PROGRAM RAM 255 127 128 0 0 SPECIAL FUNCTION REGISTERS DATA REGISTERS PROGRAM MEMORY DATA MEMORY LEGEND: = ON-CHIP REGISTERS = ACCESSED VIA BYTEWIDE BUS = ACCESSED VIA EXPANDED BUS (PORTS 0 AND 2) NOTE: Partitionable mode is not supported when MSEL pin = 0 (128KB mode). DS5001FP MEMORY MAP WITH PES=1 Figure 4 IIIII IIIII IIIII IIIII IIIII IIIII IIIII IIIII IIIII IIIII IIIII IIIII IIIII II II PROGRAM MEMORY DATA MEMORY (MOVX) FFFh 64K PE4 C000h 48K PARTITION OR PROGRAM RANGE PE3 8000h 32K PE2 NV RAM PROGRAM 4000h 16K PE1 0000h NOT ACCESSIBLE 111996 8/25 30 DS5001FP Figure 5 illustrates a typical memory connection for a system using a 128K byte SRAM. Note that in this configuration, both program and data are stored in a common RAM chip Figure 6 shows a similar system with us- ing two 32K byte SRAMs. The Byte-wide Address bus connects to the SRAM address lines. The bi-directional Byte-wide data bus connects the data I/O lines of the SRAM. DS5001FP CONNECTION TO 128K X 8 SRAM Figure 5 DS5001FP +5V 13 VCC 54 VLI CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC +3V LITHIUM PORT0 PORT1 PORT2 PORT3 14 MSEL 128K x 8 SRAM VCCO 12 32 R/W 10 29 CE1 74 22 OOOOOOOOOO O OOOOOOOOOO O OO OOOOOOOOO O OO OOOOOOOOO O 2 2 CE2 BA14-BA0 CE3 63 31 BD7-BD0 16 GND 52 111996 9/25 31 VCC WE 30 CS1 CS2 A16 OE A14-A0 A15 D7-D0 GND 24 DS5001FP DS5001FP CONNECTION TO 64K X 8 SRAM Figure 6 32K x 8 SRAM DS5001FP +5V 13 V CC VCCO 54 VLI R/W +3V LITHIUM C C CCC CCCC C CCCC C CCCC C C C CCC CCCC C C C C C +5V CE1 CE2 PORT0 BA14-BA0 28 VCC 10 27 WE 74 20 CS IIIIIIIIII IIIIIIIIII OOOOOOOOOO IIIIIIIIII OOOOOOOOOO IIIIIIIIII OOOOOOOOOO IIIIIIIIII OOOOOOOOOO IIIIIIIIII OOOOOOOOOO IIIIIIIIII OOOOOOOOOO IIIIIIIIII OOOOOOOOOO IIIIIIIIII OOOOOOOOOO IIIIIIIIII OOOOOOOOOO IIIIIIIIII OOOOOOOOOO IIIIIIIIII OOOOOOOOOO IIIIIIIIII OOOOOOOOOO IIIIIIIIII OOOOOOOOOO OOOOOOOOOO 2 OE A14-A0 22 D7-D0 PORT1 14 GND PORT2 BD7-BD0 PORT3 14 MSEL 12 GND 52 28 VCC VCC 27 WE WE 20 CS CS 32K x 8 SRAM 32K x 8 SRAM 22 OE A14-A0 A14-A0 D7-D0 D7-D0 14 GND GND POWER MANAGEMENT cuitry will switch to the lithium cell for power. The majority of internal circuits will be disabled and the remaining nonvolatile states will be retained. Any devices connected to VCCO will be powered by the lithium cell at this time. VCCO will be at the lithium battery voltage less a diode drop. This drop will vary depending on the load. Low power SRAMs should be used for this reason. When using the DS5001FP, the user must select the appropriate battery to match the RAM data retention current and the desired backup lifetime. Note that the lithium cell is only loaded when VCC < VLI. The User's Guide has more information on this topic. The trip points VCCMIN and VPFW are listed in the electrical specifications. The DS5001FP monitors VCC to provide Power-fail Reset, early warning Power-fail Interrupt, and switch over to lithium backup. It uses an internal band-gap reference in determining the switch points. These are called VPFW, VCCMIN, and VLI respectively. When VCC drops below VPFW, the DS5001FP will perform an interrupt vector to location 2Bh if the power fail warning was enabled. Full processor operation continues regardless. When power falls further to VCCMIN, the DS5001FP invokes a reset state. No further code execution will be performed unless power rises back above VCCMIN. All decoded chip enables and the R/W signal go to an inactive (logic 1) state. VCC is still the power source at this time. When VCC drops further to below VLI, internal cir- 111996 10/25 32 DS5001FP ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature -0.3V to +7.0V 0C to 70C -40C to +70C 260C for 10 seconds * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. (tA=0C to 70C; VCC=5V 10%) DC CHARACTERISTICS PARAMETER SYMBOL MIN Input Low Voltage VIL Input High Voltage TYP MAX UNITS NOTES -0.3 +0.8 V 1 VIH1 2.0 VCC+0.3 V 1 Input High Voltage (RST, XTAL1, PROG) VIH2 3.5 VCC+0.3 V 1 Output Low Voltage @ IOL=1.6 mA (Ports 1, 2, 3) VOL1 0.15 0.45 V Output Low Voltage @ IOL=3.2 mA (Port 0, ALE, PSEN, PF, BA15-0, BD7-0, R/W, CE1N, CE1-4, PE1-4, VRST) VOL2 0.15 0.45 V 1 Output High Voltage @ IOH=-80 A (Ports 1, 2, 3) VOH1 2.4 4.8 V 1 Output High Voltage @ IOH=-400 A (Ports 0, ALE, PSEN, PF, BA15-0, BD7-0, R/W, CE1N, CE1-4, PE1-4) VOH2 2.4 4.8 V 1 Input Low Current VIN=0.45V (Ports 1, 2, 3) IIL -50 A Transition Current; 1 to 0 VIN=2.0V (Ports 1, 2, 3) (0C to 70C) ITL -500 A Transition Current; 1 to 0 VIN=2.0V (Ports 1, 2, 3) (-40C to +85C) ITL -600 A 111996 11/25 33 10 DS5001FP (tA=0C to 70C; VCC=5V 10%) DC CHARACTERISTICS (cont'd) PARAMETER Input Leakage Current 0.45 < VIN < VCC (Port 0, MSEL) SYMBOL MIN TYP IIL MAX UNITS 10 A RST Pull-down Resistor (0C to 70C) RRE 40 150 K RST Pull-down Resistor (-40C to +85C) RRE 40 180 K VRST Pull-up Resistor RVR 4.7 K PROG Pull-up Resistor RPR 40 K NOTES 10 Power-Fail Warning Voltage (0C to 70C) VPFW 4.25 4.37 4.50 V 1 Power-Fail Warning Voltage (-40C to +85C) VPFW 4.1 4.37 4.5 V 1, 10 Minimum Operating Voltage (0C to 70C) VCCMIN 4.00 4.12 4.25 V 1 Minimum Operating Voltage (-40C to +85C) VCCMIN 3.85 4.09 4.25 V 1, 10 Lithium Supply Voltage VLI 2.5 4.0 V 1 Operating Current @ 16 MHz ICC 36 mA 2 Idle Mode Current @ 12 MHz (0C to 70C) IIDLE 7.0 mA 3 Idle Mode Current @ 12 MHz (-40C to +85C) IIDLE 8.0 mA 3, 10 Stop Mode Current ISTOP 80 A 4 CIN 10 pF 5 Pin Capacitance Output Supply Voltage (VCCO) VCCO1 VCC-0.35 V 1, 2 Output Supply Battery-backed Mode (VCCO, CE1-4, PE1-2) (0C to 70C) VCCO2 VLI-0.65 V 1, 8 Output Supply Battery-backed Mode (VCCO, CE1-4, PE1-2) (-40C to +85C) VCCO2 VLI-0.9 V 1, 8, 10 Output Supply Current @ VCCO=VCC - 0.3V ICCO1 75 mA 6 75 nA 7 Lithium-backed Quiescent Current Reset Trip Point in Stop Mode w/BAT=3.0V (0C to 70C) w/BAT=3.0V (-40C to +85C) w/BAT=3.3V (0C to 70C) ILI 5 4.0 3.85 4.4 4.25 4.25 4.65 1 1, 10 1 111996 12/25 34 DS5001FP AC CHARACTERISTICS EXPANDED BUS MODE TIMING SPECIFICATIONS # PARAMETER 1 Oscillator Frequency 2 ALE Pulse Width 3 4 SYMBOL (tA=0C to70C; VCC=5V + 10%) MIN MAX UNITS 1/tCLK 1.0 16 MHz tALPW 2tCLK-40 ns Address Valid to ALE Low tAVALL tCLK-40 ns Address Hold After ALE Low tAVAAV tCLK-35 ns 5 ALE Low to Valid Instr. In @12 MHz @16 MHz tALLVI 6 ALE Low to PSEN Low tALLPSL tCLK-25 7 PSEN Pulse Width tPSPW 3tCLK-35 8 PSEN Low to Valid Instr. In @12 MHz @16 MHz tPSLVI 9 Input Instr. Hold after PSEN Going High tPSIV 10 Input Instr. Float after PSEN Going High tPSIX 11 Address Hold after PSEN Going High tPSAV 12 Address Valid to Valid Instr. In @12 MHz @16 MHz tAVVI 13 PSEN Low to Address Float tPSLAZ 0 ns 14 RD Pulse Width tRDPW 6tCLK-100 ns 15 WR Pulse Width tWRPW 6tCLK-100 16 RD Low to Valid Data In @12 MHz @16 MHz tRDLDV 17 Data Hold after RD High tRDHDV 18 Data Float after RD High tRDHDZ 2tCLK-70 ns 19 ALE Low to Valid Data In @12 MHz @16 MHz tALLVD 8tCLK-150 8tCLK-90 ns ns 20 Valid Addr. to Valid Data In @12 MHz @16 MHz tAVDV 9tCLK-165 9tCLK-105 ns ns 21 ALE Low to RD or WR Low 3tCLK+50 ns 22 23 4tCLK-150 4tCLK-90 ns ns ns 3tCLK-150 3tCLK-90 0 ns ns ns tCLK-20 tCLK-8 ns ns 5tCLK-150 5tCLK-90 ns ns ns 5tCLK-165 5tCLK-105 0 ns ns ns tALLRDL 3tCLK-50 Address Valid to RD or WR Low tAVRDL 4tCLK-130 ns Data Valid to WR Going Low tDVWRL tCLK-60 ns 24 Data Valid to WR High @12 MHz @16 MHz tDVWRH 7tCLK-150 7tCLK-90 ns ns 25 Data Valid after WR High tWRHDV tCLK-50 26 RD Low to Address Float tRDLAZ 27 RD or WR High to ALE High tRDHALH 111996 13/25 35 tCLK-40 ns 0 ns tCLK+50 ns DS5001FP EXPANDED PROGRAM MEMORY READ CYCLE 2 ALE 6 7 5 8 11 PSEN 13 PORT 0 10 9 3 4 A7-A0 INSTR IN A7-A0 12 PORT 2 A15-A8 A15-A8 EXPANDED DATA MEMORY READ CYCLE 27 ALE PSEN 19 21 14 RD 16 18 3 PORT 0 26 4 17 A7-A0 (Rn OR DPL) DATA IN A7-A0 (PCL) INSTR IN 22 20 PORT 2 P2.7-P2.0 OR A15-A8 FROM DPH A15-A8 FROM PCH 111996 14/25 36 DS5001FP EXPANDED DATA MEMORY WRITE CYCLE 27 ALE PSEN 21 15 WR 23 4 3 PORT 0 A7-A0 (Rn OR DPL) 25 24 DATA OUT A7-A0 (PCL) 22 PORT 2 P2.7-P2.0 OR A15-A8 FROM PDH A15-A8 FROM PCH 111996 15/25 37 INSTR IN DS5001FP AC CHARACTERISTICS (cont'd) EXTERNAL CLOCK DRIVE # PARAMETER 28 External Clock High Time 29 (tA = 0C to70C; VCC = 5V + 10%) SYMBOL MIN MAX UNITS @12 MHz @16 MHz tCLKHPW 20 15 ns ns External Clock Low Time @12 MHz @16 MHz tCLKLPW 20 15 ns ns 30 External Clock Rise Time @12 MHz @16 MHz tCLKR 20 15 ns ns 31 External Clock Fall Time @12 MHz @16 MHz tCLKF 20 15 ns ns EXTERNAL CLOCK TIMING 28 29 30 31 1 111996 16/25 38 DS5001FP AC CHARACTERISTICS (cont'd) POWER CYCLING TIMING (tA = 0C to70C; VCC = 5V + 10%) # PARAMETER SYMBOL MIN tF 130 MAX 32 Slew Rate from VCCmin to VLI 33 Crystal Start-up Time tCSU (note 9) 34 Power-On Reset Delay tPOR 21504 UNITS s tCLK POWER CYCLE TIMING VCC VPFW VCCMIN VLI 32 INTERRUPT SERVICE ROUTINE 33 CLOCK OSC 34 INTERNAL RESET LITHIUM CURRENT 111996 17/25 39 DS5001FP AC CHARACTERISTICS (cont'd) SERIAL PORT TIMING - MODE 0 # PARAMETER 35 (tA = 0C to70C; VCC = 5V + 10%) SYMBOL MIN MAX UNITS Serial Port Clock Cycle Time tSPCLK 12tCLK s 36 Output Data Setup to Rising Clock Edge tDOCH 10tCLK-133 ns 37 Output Data Hold after Rising Clock Edge tCHDO 2tCLK-117 ns 38 Clock Rising Edge to Input Data Valid tCHDV 39 Input Data Hold after Rising Clock Edge tCHDIV 10tCLK-133 ns 0 ns SERIAL PORT TIMING - MODE 0 0 1 2 3 4 5 6 7 8 ALE 35 CLOCK 36 37 DATA OUT 0 1 2 WRITE TO SBUF REGISTER 3 4 5 6 7 SET TI 39 38 SET RI INPUT DATA VALID VALID VALID VALID VALID VALID VALID CLEAR RI 111996 18/25 40 DS5001FP AC CHARACTERISTICS BYTEWIDE ADDRESS/DATA BUS TIMING (tA = 0C to70C; VCC = 5V + 10%) # PARAMETER SYMBOL 40 Delay to Byte-wide Address Valid from CE1, CE2 or CE1N Low During Opcode Fetch tCE1LPA 41 Pulse Width of CE1-4, PE1-4 or CE1N tCEPW 4tCLK-35 ns 42 Byte-wide Address Hold After CE1, CE2 or CE1N High During Opcode Fetch tCE1HPA 2tCLK-20 ns 43 Byte-wide Data Setup to CE1, CE2 or CE1N High During Opcode Fetch tOVCE1H 1tCLK+40 ns 44 Byte-wide Data Hold After CE1, CE2 or CE1N High During Opcode Fetch tCE1HOV 10 ns 45 Byte-wide Address Hold After CE1-4, PE1-4, or CE1N High During MOVX tCEHDA 4tCLK-30 ns 46 Delay from Bytewide Address Valid CE1-4, PE1-4, or CE1N Low During MOVX tCELDA 4tCLK-35 ns 47 Bytewide Data Setup to CE1-4, PE1-4, or CE1N High During MOVX (read) tDACEH 1tCLK+40 ns 48 Bytewide Data Hold After CE1-4, PE1-4, or CE1N High During MOVX (read) tCEHDV 10 ns 49 Bytewide Address Valid to R/W Active During MOVX (write) tAVRWL 3tCLK-35 ns 50 Delay from R/W Low to Valid Data Out During MOVX (write) tRWLDV 20 ns 51 Valid Data Out Hold Time from CE1-4, PE1-4, or CE1N High tCEHDV 1tCLK-15 ns 52 Valid Data Out Hold Time from R/W High tRWHDV 0 ns 53 Write Pulse Width (R/W Low Time) tRWLPW 6tCLK-20 ns 111996 19/25 41 MIN MAX UNITS 30 ns DS5001FP BYTEWIDE BUS TIMING RPC AC CHARACTERISTICS - DBB READ (tA = 0C to70C; VCC = 5V + 10%) # PARAMETER SYMBOL MIN 54 CS, A0 Setup to RD tAR 0 ns 55 CS, A0 Hold After RD tRA 0 ns 56 RD Pulse Width tRR 160 ns 57 CS, A0 to Data Out Delay tAD 58 RD to Data Out Delay tRD 59 RD to Data Float Delay tRDZ 0 MAX UNITS 130 ns 130 ns 85 ns 111996 20/25 42 DS5001FP RPC AC CHARACTERISTICS - DBB WRITE # PARAMETER 60 CS, A0 Setup to WR (tA = 0C to70C; VCC = 5V + 10%) SYMBOL MIN MAX UNITS tAW 0 ns 61A CS, Hold After WR tWA 0 ns 61B A0, Hold After WR tWA 20 ns 62 WR Pulse Width tWW 160 ns 63 Data Setup to WR tDW 130 ns 64 Data Hold After WR tWD 20 ns SYMBOL MIN AC CHARACTERISTICS - DMA (tA = 0C to70C; VCC = 5V + 10%) # PARAMETER 65 DACK to WR or RD tACC 0 ns 66 RD or WR to DACK tCAC 0 ns 67 DACK to Data Valid tACD 0 68 RD or WR to DRQ Cleared tCRQ AC CHARACTERISTICS - PROG # PARAMETER 69 70 MAX UNITS 130 ns 110 ns (tA = 0C to70C; VCC = 5V + 10%) SYMBOL MIN PROG Low to Active tPRA 48 CLKS PROG High to Inactive tPRI 48 CLKS 111996 21/25 43 MAX UNITS DS5001FP RPC TIMING MODE READ OPERATION CS OR A0 54 55 RD 56 58 59 57 DATA DATA VALID WRITE OPERATION CS OR A0 60 61 62 WR 63 DATA 64 DATA VALID DMA DACK RD 65 66 WR 65 66 VALID DATA VALID 67 DRQ 68 68 NOTES: All parameters apply to both commercial and industrial temperature operation unless otherwise noted. 1. All voltages are referenced to ground. 2. Maximum operating ICC is measured with all output pins disconnected; XTAL1 driven with tCLKR, tCLKF=10 ns, VIL = 0.5V; XTAL2 disconnected; RST = PORT0 = VCC, MSEL = VSS. 3. Idle mode IIDLE is measured with all output pins disconnected; XTAL1 driven with tCLKR, tCLKF = 10 ns, VIL = 0.5V; XTAL2 disconnected; PORT0 = VCC, RST = MSEL = VSS. 4. Stop mode ISTOP is measured with all output pins disconnected; PORT0 = VCC; XTAL2 not connected; RST = MSEL = XTAL1 = VSS. 111996 22/25 44 DS5001FP 5. Pin Capacitance is measured with a test frequency - 1 MHz, tA = 25C. 6. ICCO1 is the maximum average operating current that can be drawn from VCCO in normal operation. 7. ILI is the current drawn from VLI input when VCC = 0V and VCCO is disconnected. 8. VCCO2 is measured with VCC < VLI, and a maximum load of 10 A on VCCO. 9. Crystal start-up time is the time required to get the mass of the crystal into vibrational motion from the time that power is first applied to the circuit until the first clock pulse is produced by the on-chip oscillator. The user should check with the crystal vendor for a worst case specification on this time. 10. This parameter applies to industrial temperature operation. 111996 23/25 45 DS5001FP DS50001FP CMOS MICROPROCESSOR MILLIMETERS DIM MIN MAX A - 3.15 A1 0.25 - A2 2.55 2.87 B 0.30 0.50 C 0.13 0.23 D 23.70 24.10 D1 19.90 20.10 E 17.40 18.10 E1 13.90 14.10 e L 0.80 BSC 0.65 0.95 56-G4005-001 111996 24/25 46 DS5001FP DATA SHEET REVISION SUMMARY The following represent the key differences between 11/27/95 and 07/24/96 version of the DS50001FP data sheet. Please review this summary carefully. 1. Change VCC02 specification from VLI - 0.5 to VLI - 0.65 (PCN F62501). 2. Update mechanical specifications. The following represent the key differences between 07/24/96 and 11/19/96 version of the DS50001FP data sheet. Please review this summary carefully. 1. Change VCC01 from VCC-0.3 to VCC-0.35. 111996 25/25 47