EL5170IYZT13 - Intersil Corporation

FN7309.5

EL5170, EL5370

100MHz Differential Twisted-Pair Drivers

The EL5170 and EL5370 are single and triple high

bandwidth amplifiers with a fixed gain of 2. They are

primarily targeted for applications such as driving twisted-

pair lines in component video applications. The inputs signal

can be in either single-ended or differential form but the

outputs are always in differential form.

The output common mode level for each channel is set by

the associated VREF pin, which have a -3dB bandwidth of

over 70MHz. Generally, these pins are grounded but can be

tied to any voltage reference.

All outputs are short circuit protected to withstand temporary

overload condition.

The EL5170 and EL5370 are specified for operation over the

full -40°C to +85°C temperature range.

Features

• Fully differential inputs and outputs

• Differential input range ±2.3V typ.

• 100MHz 3dB bandwidth at fixed gain of 2

• 1200V/µs slew rate

• Single 5V or dual ±5V supplies

• 50mA maximum output current

• Low power - 7.4mA per channel

• Pb-Free Available (RoHS Compliant)

Applications

• Twisted-pair drivers

• Differential line drivers

• VGA over twisted-pairs

• ADSL/HDSL drivers

• Single ended to differential amplification

• Transmission of analog signals in a noisy environment

Ordering Information

PART

NUMBER PACKAGE TAPE & REEL PKG. DWG. #

EL5170IS 8-Pin SO - MDP0027

EL5170IS-T7 8-Pin SO 7” MDP0027

EL5170IS-T13 8-Pin SO 13” MDP0027

EL5170ISZ

(See Note)

8-Pin SO

(Pb-free)

- MDP0027

EL5170ISZ-T7

(See Note)

8-Pin SO

(Pb-free)

7” MDP0027

EL5170ISZ-

T13 (See Note)

8-Pin SO

(Pb-free)

13” MDP0027

EL5170IY 8-Pin MSOP - MDP0043

EL5170IY-T7 8-Pin MSOP 7” MDP0043

EL5170IY-T13 8-Pin MSOP 13” MDP0043

EL5170IYZ

(See Note)

8-Pin MSOP

(Pb-free)

- MDP0043

EL5170IYZ-T7

(See Note)

8-Pin MSOP

(Pb-free)

7” MDP0043

EL5170IYZ-

T13 (See Note)

8-Pin MSOP

(Pb-free)

13” MDP0043

EL5370IU 24-Pin QSOP - MDP0040

EL5370IU-T7 24-Pin QSOP 7” MDP0040

EL5370IU-T13 24-Pin QSOP 13” MDP0040

NOTE: Intersil Pb-free products employ special Pb-free material sets;

molding compounds/die attach materials and 100% matte tin plate

termination finish, which are RoHS compliant and compatible with

both SnPb and Pb-free soldering operations. Intersil Pb-free products

are MSL classified at Pb-free peak reflow temperatures that meet or

exceed the Pb-free requirements of IPC/JEDEC J STD-020C.

Pinouts

EL5170

(8-PIN SO, MSOP)

TOP VIEW

EL5370

(24-PIN QSOP)

TOP VIEW

IN+

IN-

REF

OUT+

VS-

VS+

OUT-

INP1

INN1

REF1

INP2

INN2

REF2

INP3

INN3

REF3

OUT1

OUT1B

VSP

VSN

OUT2

OUT2B

OUT3

OUT3B

Data Sheet October 29, 2004

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143 |Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

2FN7309.5

IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are

at the specified temperature and are pulsed tests, therefore: TJ = TC = TA

Absolute Maximum Ratings (TA = 25°C)

Supply Voltage (VS+ to VS-) . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6V

Maximum Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . ±60mA

Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C

Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +135°C

Recommended Operating Temperature . . . . . . . . . . -40°C to +85°C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Electrical Specifications VS+ = +5V, VS- = -5V, TA = 25°C, VIN = 0V, AV = 2, RLD = 200Ω, CLD = 1pF, unless otherwise specified.

PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT

AC PERFORMANCE

BW -3dB Bandwidth 100 MHz

BW ± 0.1dB Bandwidth 12 MHz

SR Slew Rate VOUT = 2VP-P

, 20% to 80% 800 1100 V/µs

TSTL Settling Time to 0.1% VOUT = 2VP-P 20 ns

TOVR Output Overdrive Recovery time 40 ns

VREFBW (-3dB) VREF -3dB Bandwidth AV =1, CLD = 2.7pF 70 MHz

VREFSR+ VREF Slew Rate - Rise VOUT = 2VP-P

, 20% to 80% 125 V/µs

VREFSR- VREF Slew Rate - Fall VOUT = 2VP-P

, 20% to 80% 65 V/µs

VNInput Voltage Noise f = 10kHz 28 nV/√Hz

HD2 Second Harmonic Distortion VOUT = 2VP-P

, 1MHz -79 dBc

HD2 Second Harmonic Distortion VOUT = 2VP-P

, 10MHz -65 dBc

HD3 Third Harmonic Distortion VOUT = 2VP-P

, 1MHz -62 dBc

HD3 Third Harmonic Distortion VOUT = 2VP-P

, 10MHz -43 dBc

dG Differential Gain at 3.58MHz RLD = 300Ω, AV = 2 0.14 %

dθDifferential Phase at 3.58MHz RLD = 300Ω, AV = 2 0.38 °

eSChannel Separation - For EL5370 only at f = 1MHz 85 dB

INPUT CHARACTERISTICS

VOS Input Referred Offset Voltage ±6 ±25 mV

IIN Input Bias Current (VIN, VINB) -10 -6 -2 µA

IREF Input Bias Current at REF Pin VREF = +3.2V 0.5 1.25 3 µA

VREF = -3.2V -1 0 +1 µA

Gain Gain Accuracy VIN = ±1V 1.98 2 2.02 V

RIN Differential Input Resistance 300 kΩ

CIN Differential Input Capacitance 1pF

DMIR Differential Mode Input Range ±2.1 ±2.3 V

CMIR+ Common Mode Positive Input Range at

VIN+, VIN-

3.2 3.4 V

CMIR- Common Mode Negative Input Range at

VIN+, VIN-

-4.5 -4.2 V

VREFIN Reference Input Voltage Range - Positive VIN+ = VIN- = 0V 3.4 3.8 V

Reference Input Voltage Range -

Negative

-3.3 -3 V

EL5170, EL5370

3FN7309.5

VREFOS Output Offset Relative to VREF -140 60 +140 mV

CMRR Input Common Mode Rejection Ratio VIN = ±2.5V 65 84 dB

OUTPUT CHARACTERISTICS

VOUT Positive Output Voltage Swing RLD = 200Ω3.3 3.6 V

Negative Output Voltage Swing -3.3 -3 V

IOUT(Max) Maximum Output Current RL = 10Ω (EL5170) ±50 ±80 mA

RL = 10Ω (EL5370) ±70 ±85 mA

ROUT Output Impedance 60 mΩ

SUPPLY

VSUPPLY Supply Operating Range VS+ to VS-4.7511V

IS(ON) Power Supply Current - Per channel 6 7.4 8.4 mA

IS(OFF)+ Positive Power Supply Current - Disabled EN pin tied to 4.8V (EL5170) 60 80 100 µA

IS(OFF)- Negative Power Supply Current -

Disabled

-150 -120 -90 µA

IS(OFF)+ Positive Power Supply Current - Disabled EN pin tied to 4.8V (EL5370) 0.5 2 5 µA

IS(OFF)- Negative Power Supply Current -

Disabled

-150 -120 -90 µA

PSRR Power Supply Rejection Ratio VS from ±4.5V to ±5.5V (EL5170) 70 83 dB

VS from ±4.5V to ±5.5V (EL5370) 65 83 dB

ENABLE

tEN Enable Time 200 ns

tDS Disable Time 1µs

VIH EN Pin Voltage for Power-up VS+ -

1.5

VIL EN Pin Voltage for Shut-down VS+ -

0.5

IIH-EN EN Pin Input Current High - per channel At VEN = 5V 40 50 µA

IIL-EN EN Pin Input Current Low - per channel At VEN = 0V -6 -3 µA

Electrical Specifications VS+ = +5V, VS- = -5V, TA = 25°C, VIN = 0V, AV = 2, RLD = 200Ω, CLD = 1pF, unless otherwise specified.

PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT

Pin Descriptions

EL5170 EL5370 PIN NAME PIN FUNCTION

1 2, 6, 10 IN+, INP1, 2, 3 Non-inverting inputs

21EN

Enable

3 3, 7, 11 IN-, INN1, 2, 3 Inverting inputs

4 4, 8, 12 REF1, 2, 3 Reference input, sets common-mode output voltage

5 14, 17, 23 OUT-, OUT1B, 2B, 3B Inverting outputs

6 21 VS+, VSP Positive supply

7 20 VS-, VSN Negative supply

8 15, 18, 24 OUT+, OUT1, 2, 3 Non-inverting outputs

5, 9, 13, 16, 19, 22 NC No connects, grounded for best crosstalk performance

EL5170, EL5370

4FN7309.5

Connection Diagrams

INP

INN

REF

OUT

VSN

VSP

OUTB

INP

INN

REF

RS1

50Ω

RS2

50Ω

RS3

50Ω

LOADN

RRT2

LOADP

-5V

+5V

EL5170

RRT2

50Ω

EL5370

INP1

INN1

REF1

INP2

INN2

REF2

INP3

INN3

REF3

OUT1

OUT1B

VSP

VSN

OUT2

OUT2B

OUT3

OUT3B

RSR3

50Ω

RSN3

50Ω

RSP3

50Ω

RSR2

50Ω

RSN2

50Ω

RSP2

50Ω

RSR1

50Ω

RSN1

50Ω

RSP1

50Ω

INP1

INN1

REF1

INP2

INN2

REF2

INP3

INN3

REF3

ENABLE

-5V

+5V

50Ω

RRT3B LD3B

50Ω

RRT3 LD3

50Ω

RRT2B

LD2B

50Ω

RRT2

LD2

50Ω

RRT1B

LD1B

50Ω

RRT1

LD1

EL5170, EL5370

5FN7309.5

Typical Performance Curves

FIGURE 1. FREQUENCY RESPONSE FIGURE 2. SMALL SIGNAL FREQUENCY RESPONSE vs RLD

FIGURE 3. SMALL SIGNAL FREQUENCY RESPONSE vs CLD FIGURE 4. FREQUENCY RESPONSE vs VREF

FIGURE 5. POWER SUPPLY REJECTION RATIO vs

FREQUENCY

FIGURE 6. COMMON MODE REJECTION vs FREQUENCY

100K

FREQUENCY (Hz)

10M 100M 1G

GAIN (dB)

VS = ±5V, AV = 2, RLD = 200Ω, CLD = 1pF

VOP-P = 2V

VOP-P = 1V

VOP-P = 200mV

1M 1M 100M 1G

FREQUENCY (Hz)

100K

GAIN (dB)

CLD = 1pF, VODP-P = 200mV

10M

RLD = 1kΩ

RLD = 100Ω

RLD = 500Ω

RLD = 200Ω

100K

FREQUENCY (Hz)

10M 100M 1G

GAIN (dB)

VS = ±5V, RLD = 200Ω, VODP-P = 200mV

CLD = 0pF

CLD = 20pF

CLD = 40pF

CLD = 75pF

1M 100M

FREQUENCY (Hz)

GAIN (dB)

-1

-2

-3

-4

-5

-6

10M

VREF = 200mVP-P

VREF = 1VP-P

-10

-30

-50

-60

-80

-90 1M 10M 100M

PSRR (dB)

FREQUENCY (Hz)

-70

-40

-20

100K

PSRR-

PSRR+

100K 1M 10M 100M

FREQUENCY (Hz)

COMMON MODE REJECTION (dB)

-10

-30

-50

-60

-80

-90

-70

-40

-20

+VOCM

VODM

100Ω

VOCM/VINCM

VODM/VINCM

VINCM

EL5170, EL5370

6FN7309.5

FIGURE 7. DIFFERENTIAL MODE OUTPUT BALANCE

ERROR vs FREQUENCY

FIGURE 8. INPUT VOLTAGE NOISE vs FREQUENCY

FIGURE 9. CHANNEL ISOLATION vs FREQUENCY FIGURE 10. BANDWIDTH vs SUPPLY VOLTAGE

FIGURE 11. SUPPLY CURRENT vs SUPPLY VOLTAGE FIGURE 12. HARMONIC DISTORTION vs FREQUENCY

Typical Performance Curves (Continued)

100K 1M 10M 100M

FREQUENCY (Hz)

BALANCE ERROR (dB)

-10

-20

-30

-40

-50

-60

VIN

VCM

VODM

100Ω

RTR

VOCM/VODM

100

1000

10 100 1K 10K 100K 1M 10M

FREQENCY (Hz)

VOLTAGE NOISE (nV/√Hz)

-110

-70

100K 1M 10M 100M

FREQENCY (Hz)

CHANNEL ISOLATION (dB)

-100

-90

-80

-60

-50

-40

CH1<=>CH3

CH3<=>CH1

CH1<=>CH2

CH2<=>CH3

CH2<=>CH1

CH3<=>CH2

105

110

4689 12

VS (V)

BW (MHz)

100

57 10

RLD = 200Ω

7.58

7.62

7.68

7.76

7.78

468911

VS (V)

IS (mA)

7.72

7.64

57 10

7.74

7.7

7.66

7.6

-50

-30

02 6 1012 1820

FREQUENCY (MHz)

DISTORTION (dB)

414

-40

-70

-60

-90

-80

VS = ±5V, RLD = 200Ω, VOP-P = 2V

816

HD3

HD2

EL5170, EL5370

7FN7309.5

FIGURE 13. VCOM TRANSIENT RESPONSE FIGURE 14. LARGE SIGNAL TRANSIENT RESPONSE

FIGURE 15. SMALL SIGNAL TRANSIENT RESPONSE FIGURE 16. DISABLED RESPONSE

FIGURE 17. ENABLED RESPONSE FIGURE 18. PACKAGE POWER DISSIPATION vs AMBIENT

TEMPERATURE

Typical Performance Curves (Continued)

40ns/DIV

0.5V/DIV

20ns/DIV

500mV/DIV

20ns/DIV

100mV/DIV

486mW

θJA=206°C/W

MSOP8

870mW

θJA=115°C/W

QSOP24

1.2

0.8

0.6

0.4

0 255075100 150

AMBIENT TEMPERATURE (°C)

POWER DISSIPATION (W)

12585

JEDEC JESD51-3 LOW EFFECTIVE THERMAL

CONDUCTIVITY TEST BOARD

0.2

625mW

θJA=160°C/W

SO8

EL5170, EL5370

8FN7309.5

Simplified Schematic

Description of Operation and Application

Information

Product Description

The EL5170 and EL5370 are wide bandwidth, low power

and single/differential ended to differential output amplifiers.

They have a fixed gain of 2. The EL5170 is a single channel

differential amplifier. The EL5370 is a triple channel

differential amplifier. The EL5170 and EL5370 have a –3dB

bandwidth of 100MHz while driving a 200Ω differential load.

The EL5170 and EL5370 are available with a power down

feature to reduce the power while the amplifiers are

disabled.

Input, Output and Supply Voltage Range

The EL5170 and EL5370 have been designed to operate

with a single supply voltage of 5V to 10V or a split supplies

with its total voltage from 5V to 10V. The amplifiers have an

input common mode voltage range from -4.5V to 3.4V for

±5V supply. The differential mode input range (DMIR)

between the two inputs is from –2.3V to +2.3V. The input

voltage range at the REF pin is from –3.3V to 3.8V. If the

input common mode or differential mode signal is outside the

above-specified ranges, it will cause the output signal

distorted.

The output of the EL5170 and EL5370 can swing from –3.3V

to 3.6V at 200Ω differential load at ±5V supply. As the load

resistance becomes lower, the output swing is reduced.

FIGURE 19. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE

Typical Performance Curves (Continued)

1.136W

θJA=88°C/W

QSOP24

1.4

1.2

0.8

0.6

0.2

0 255075100 150

AMBIENT TEMPERATURE (°C)

POWER DISSIPATION (W)

12585

JEDEC JESD51-7 HIGH EFFECTIVE THERMAL

CONDUCTIVITY TEST BOARD

0.4

909mW

θJA=110°C/W

SO8

870mW

θJA=115°C/W

MSOP8/10

REF

R10

RCD

OUT+

OUT-

R7R8

VB1

FBNFBPIN-IN+

VB2

VS+

VS-

200Ω

400Ω

EL5170, EL5370

9FN7309.5

Differential and Common Mode Gain Settings

As shown at the simplified schematic, since the feedback

resistors RF and the gain resistor are integrated with 200Ω

and 400Ω, the EL5170 and EL5370 have a fixed gain of 2.

The common mode gain is always one.

Driving Capacitive Loads and Cables

The EL5170 and EL5370 can drive 75pF differential

capacitor in parallel with 200Ω differential load with less than

3.5dB of peaking. If less peaking is desired in applications, a

small series resistor (usually between 5Ω to 50Ω) can be

placed in series with each output to eliminate most peaking.

However, this will reduce the gain slightly.

When used as a cable driver, double termination is always

recommended for reflection-free performance. For those

applications, a back-termination series resistor at the

amplifier’s output will isolate the amplifier from the cable and

allow extensive capacitive drive. However, other applications

may have high capacitive loads without a back-termination

resistor. Again, a small series resistor at the output can help

to reduce peaking.

Disable/Power-Down

The EL5170 and EL5370 can be disabled and placed their

outputs in a high impedance state. The turn off time is about

1µs and the turn on time is about 200ns. When disabled, the

amplifier’s supply current is reduced to 2µA for IS+ and

120µA for IS- typically, thereby effectively eliminating the

power consumption. The amplifier’s power down can be

controlled by standard CMOS signal levels at the ENABLE

pin. The applied logic signal is relative to VS+ pin. Letting the

EN pin float or applying a signal that is less than 1.5V below

VS+ will enable the amplifier. The amplifier will be disabled

when the signal at EN pin is above VS+ -0.5V.

Output Drive Capability

The EL5170 and EL5370 have internal short circuit

protection. Its typical short circuit current is ±80mA. If the

output is shorted indefinitely, the power dissipation could

easily increase such that the part will be destroyed.

Maximum reliability is maintained if the output current never

exceeds ±60mA. This limit is set by the design of the internal

metal interconnect.

Power Dissipation

With the high output drive capability of the EL5170 and

EL5370 it is possible to exceed the 125°C absolute

maximum junction temperature under certain load current

conditions. Therefore, it is important to calculate the

maximum junction temperature for the application to

determine if the load conditions or package types need to be

modified for the amplifier to remain in the safe operating

area.

The maximum power dissipation allowed in a package is

determined according to:

Where:

•T

JMAX = Maximum junction temperature

•T

AMAX = Maximum ambient temperature

•θJA = Thermal resistance of the package

The maximum power dissipation actually produced by an IC

is the total quiescent supply current times the total power

supply voltage, plus the power in the IC due to the load, or:

Where:

•V

S = Total supply voltage

•I

SMAX = Maximum quiescent supply current per channel

•∆VO = Maximum differential output voltage of the

application

•R

LD = Differential load resistance

•I

LOAD = Load current

• i = Number of channels

By setting the two PDMAX equations equal to each other, we

can solve the output current and RLOAD to avoid the device

overheat.

Power Supply Bypassing and Printed Circuit

Board Layout

As with any high frequency device, a good printed circuit

board layout is necessary for optimum performance. Lead

lengths should be as sort as possible. The power supply pin

must be well bypassed to reduce the risk of oscillation. For

normal single supply operation, where the VS- pin is

connected to the ground plane, a single 4.7µF tantalum

capacitor in parallel with a 0.1µF ceramic capacitor from VS+

to GND will suffice. This same capacitor combination should

be placed at each supply pin to ground if split supplies are to

be used. In this case, the VS- pin becomes the negative

supply rail.

For good AC performance, parasitic capacitance should be

kept to minimum. Use of wire wound resistors should be

avoided because of their additional series inductance. Use

of sockets should also be avoided if possible. Sockets add

parasitic inductance and capacitance that can result in

compromised performance. Minimizing parasitic capacitance

at the amplifier’s inverting input pin is very important. The

feedback resistor should be placed very close to the

inverting input pin. Strip line design techniques are

recommended for the signal traces.

PDMAX TJMAX TAMAX

–

ΘJA

---------------------------------------------=

PD i VSISMAX VS

∆VO

RLD

------------

×+×







×=

EL5170, EL5370

10 FN7309.5

Typical Applications

0Ω

VFB

VINB

VREF

EL5172/

EL5372

EL5170/

EL5370 VOUT

ZO = 100Ω

VIN

50Ω

FIGURE 20. TWISTED PAIR DRIVER

IN+

IN-

FIGURE 21. DUAL COAXIAL CABLE DRIVER

IN+

IN-

0Ω

VFB

VINB

VREF

VOUT

VIN EL5172/

EL5372

EL5170/

EL5370

EL5170/

EL5370

IN+

IN-

VIN

10V

FIGURE 22. SINGLE SUPPLY TWISTED PAIR DRIVER

EL5170, EL5370

11 FN7309.5

SO Package Outline Drawing

FIGURE 23. DUAL SIGNAL TRANSMISSION CIRCUIT

EL5170/

EL5370

IN+

IN-

EL5172

EL5172/

EL5372

EL5170, EL5370

12 FN7309.5

MSOP Package Outline Drawing

EL5170, EL5370

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN7309.5

QSOP Package Outline Drawing

NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at

http://www.intersil.com/design/packages/index.asp

EL5170, EL5370