SLVS354A − FEBRUAR Y 2001 − REVISED SEPTEMBER 2001
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
features
DRegulated 3.3-V Output Voltage With up to
100-mA Output Current From a 1.8-V to
3.6-V Input Voltage
DLess Than 5-mV(PP) Output Voltage Ripple
Achieved With Push-Pull Topology
DIntegrated Low-Battery and Power-Good
Detector
DSwitching Frequency Can Be Synchronized
to External Clock Signal
DExtends Battery Usage With up to 90%
Efficiency and 35-µA Quiescent Supply
Current
DEasy-to-Design, Low Cost, Low EMI Power
Supply Since No Inductors Are Used
D0.05-µA Shutdown Current, Battery is
Isolated From Load in Shutdown Mode
DCompact Converter Solution in UltraSmall
10-pin MSOP With Only Four External
Capacitors Required
DEvaluation Module Available
(TPS60200EVM-145)
applications
DReplaces DC/DC Converters With Inductors
in Battery Powered Applications Like:
− Two Battery Cells to 3.3-V Conversion
− MP3 Portable Audio Players
− Battery-Powered Microprocessor
Systems
− Backup-Battery Boost Converters
− PDA’s, Organizers, and Cordless Phones
− Handheld Instrumentation
− Glucose Meters and Other Medical
Instruments
·
description
The TPS6020x step-up, regulated charge pumps generate a 3.3-V ±4% output voltage from a 1.8-V to 3.6-V
input voltage. The devices are typically powered by two Alkaline, NiCd, or NiMH battery cells and operate down
to a minimum supply voltage of 1.6 V. Continuous output current is a minimum of 100 mA from a 2-V input. Only
four external capacitors are needed to build a complete low-ripple dc/dc converter. The push-pull operating
mode of two single-ended charge pumps assures the low output voltage ripple, as current is continuously
transferred to the output.
Figure 1. Typical Application Circuit
With Low-Battery Warning
OUTPUT
3.3 V, 100 mA
INPUT
1.6 V to 3.6 V
OFF/ON
C1 C2
Co
CiR1
R2
1
2
3
4
5
6
7
8
9
10
R3
Low Battery
Warning
IN
EN
C1−
C1+
LBI
TPS60204
OUT
C2−
C2+
LBO
GND
TPS60204
PEAK OUTPUT CURRENT
vs
INPUT VOLTAGE
150
100
50
01.6 2.0 2.4 2.8
200
250
350
3.2 3.6
300
VI − Input Voltage − V
− Peak Output Current − mA
O
I
2.2 µF
2.2 µF
1 µF
1 µF
Copyright 2001, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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SLVS354A − FEBRUAR Y 2001 − REVISED SEPTEMBER 2001
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
The devices operate in the newly developed LinSkip mode. In this operating mode, the device switches
seamlessly from the power saving pulse-skip mode at light loads to the low-noise constant-frequency,
linear-regulation mode once the output current exceeds the LinSkip threshold of about 7 mA. Even in pulse-skip
mode, the output ripple is maintained at a very low level because the output resistance of the charge pump is
still regulated.
Three operating modes can be programmed using the EN pin. EN = low disables the device, shuts down all
internal circuits, and disconnects the output from the input. EN = high enables the device and programs it to run
from the internal oscillator. The devices operate synchronized to an external clock signal if EN is clocked; thus,
switching harmonics can be controlled and minimized. The devices include a low-battery detector that issues a
warning if the battery voltage drops below a user-defined threshold voltage, or a power-good detector that goes
active when the output voltage reaches about 90% of its nominal value.
Device options with either a low-battery or power good detector are available. This dc/dc converter requires no
inductors, therefore, EMI of the system is reduced to a minimum. It is available in the small 10-pin MSOP
package (DGS).
ACTUAL SIZE
3,05 mm x 4,98 mm
1
2
3
4
5
10
9
8
7
6
LBI
GND
C1−
C1+
OUT
LBO
EN
C2−
IN
C2+
TPS60204
1
2
3
4
5
10
9
8
7
6
GND
GND
C1−
C1+
OUT
PG
EN
C2−
IN
C2+
TPS60205
DGS PACKAGES
AVAILABLE OPTIONS
TAPART NUMBER†MARKING
DGS
PACKAGE
OUTPUT
CURRENT
(mA)
OUTPUT
VOLTAGE
(V) DEVICE FEATURES
−40°C to 85°C
TPS60204DGS AFB 100 3.3 Low-battery detector
−40
°
C to 85
°
C
TPS60205DGS AFC 100 3.3 Power-good detector
†The DGS package is available taped and reeled. Add R suffix to device type (e.g., TPS60204DGSR) to order
quantities of 2500 devices per reel.
SLVS354A − FEBRUAR Y 2001 − REVISED SEPTEMBER 2001
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagrams
TPS60204 with low-battery detector
_
+
Oscillator
Control
Circuit
_
+
+
−
VREF
_
+
+
−
Shutdown/
Start-Up
Control
0.8 x VI+
−
VREF
LBI
GND LBO
EN
Charge Pump 1
C1+
C1−
C1
C2+
C2−
OUT
C2
IN
Charge Pump 2
0°
180°
TPS60205 with power-good detector
_
+
Oscillator
Control
Circuit
_
+
+
−
VREF
_
+
+
−
Shutdown/
Start-Up
Control
0.8 x VI+
−
VREF
GND PG
EN
Charge Pump 1
C1+
C1−
C1
C2+
C2−
OUT
C2
IN
Charge Pump 2
0°
180°
SLVS354A − FEBRUAR Y 2001 − REVISED SEPTEMBER 2001
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME NO.
I/O
DESCRIPTION
C1+ 4 Positive terminal of the flying capacitor C1
C1− 3 Negative terminal of the flying capacitor C1
C2+ 6 Positive terminal of the flying capacitor C2
C2− 8 Negative terminal of the flying capacitor C2
EN 9 I
Device-enable input. Three operating modes can be programmed with the EN pin.
− EN = Low disables the device. Output and input are isolated in the shutdown.
− EN = High lets the device run from the internal oscillator.
− If an external clock signal is applied to the EN pin, the device is in syncmode and runs synchronized at the
frequency of the external clock signal.
GND 2 Ground
IN 7 I Supply input. Bypass IN to GND with a capacitor of the same size as Co.
LBI/GND 1 I Low-battery detector input for the TPS60204. A low-battery warning is generated at the LBO pin when the voltage
on LBI drops below the threshold of 1.18 V. Connect LBI to GND if the low-battery detector function is not used. For
the TPS60205, this pin has to be connected to ground (GND pin).
LBO/PG 10 O
Open-drain low-battery detector output for the TPS60204. This pin is pulled low if the voltage on LBI drops below
the threshold of 1.18 V. A pullup resistor should be connected between LBO and OUT or any other logic supply rail
that is lower than 3.6 V.
Open-drain power-good detector output for the TPS60205. As soon as the voltage on OUT reaches about 90% of
it is nominal value this pin goes active high. A pullup resistor should be connected between PG and OUT or any
other logic supply rail that is lower than 3.6 V.
OUT 5 O Regulated 3.3-V power output. Bypass OUT to GND with the output filter capacitor Co.
detailed description
operating principle
The TPS6020x charge pumps provide a regulated 3.3-V output from a 1.8-V to 3.6-V input. They deliver up to
100-mA load current while maintaining the output at 3.3 V ±4%. Designed specifically for space critical battery
powered applications, the complete converter requires only four external capacitors. The device is using the
push-pull topology to achieve lowest output voltage ripple. The converter is also optimized for smallest board
space. It makes use of small sized capacitors, with the highest output current rating per output capacitance and
package size.
The TPS6020x circuits consist of an oscillator, a 1.18-V voltage reference, an internal resistive feedback circuit,
an error amplifier, two charge pump power stages with high current MOSFET switches, a shutdown/start-up
circuit, and a control circuit (see functional block diagrams).
push-pull operating mode
The two single-ended charge pump power stages operate in the so-called push-pull operating mode, i.e., they
operate with a 180°C phase shift. Each single-ended charge pump transfers charge into its transfer capacitor
(C1 or C2) in one half of the period. During the other half of the period (transfer phase), the transfer capacitor
is placed in series with the input to transfer its charge to Co. While one single-ended charge pump is in the charge
phase, the other one is in the transfer phase. This operation assures an almost constant output current which
ensures a low output ripple.
If the clock were to run continuously, this process would eventually generate an output voltage equal to two times
the input voltage (hence the name voltage doubler). In order to provide a regulated fixed output voltage of 3.3 V,
the TPS6020x devices use either pulse-skip or constant-frequency linear-regulation control mode. The mode
is automatically selected based on the output current. If the load current is below the LinSkip current threshold,
it switches into the power-saving pulse-skip mode to boost efficiency at low output power.
SLVS354A − FEBRUAR Y 2001 − REVISED SEPTEMBER 2001
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detailed description (continued)
constant-frequency mode
When the output current is higher then the LinSkip current threshold, the charge pump runs continuously at the
switching frequency f(OSC). The control circuit, fed from the error amplifier, controls the charge on C1 and C2
by controlling the gates and hence the rDS(ON) of the integrated MOSFETs. When the output voltage decreases,
the gate drive increases, resulting in a larger voltage across C1 and C2. This regulation scheme minimizes
output ripple. Since the device switches continuously, the output signal contains well-defined frequency
components, and the circuit requires smaller external capacitors for a given output ripple. However,
constant-frequency mode, due to higher operating current, is less efficient at light loads. For this reason, the
device switches seamlessly into the pulse-skip mode when the output current drops below the LinSkip current
threshold.
pulse-skip mode
The regulator enters the pulse-skip mode when the output current is lower than the LinSkip current threshold
of 7 mA. In the pulse-skip mode, the error amplifier disables switching of the power stages when it detects an
output voltage higher than 3.3 V. The controller skips switching cycles until the output voltage drops below 3.3 V.
Then the error amplifier reactivates the oscillator and switching of the power stages starts again. A 30-mV output
voltage offset is introduced in this mode.
The pulse-skip regulation mode minimizes operating current because it does not switch continuously and
deactivates all functions except the voltage reference and error amplifier when the output is higher than 3.3 V.
Even i n pulse-skip mode the rDS(ON) of the MOSFETs is controlled. This way the energy per switching cycle that
is transferred by the charge pump from the input to the output is limited to the minimum that is necessary to
sustain a regulated output voltage, with the benefit that the output ripple is kept to a minimum. When switching
is disabled from the error amplifier, the load is also isolated from the input.
start up and shutdown
During start-up, i.e. when EN is set from logic low to logic high, the output capacitor is directly connected to IN
and charged up with a limited current until the output voltage VO reaches 0.8 × VI. When the start-up comparator
detects this limit, the converter begins switching. This precharging of the output capacitor guarantees a short
start-up time. In addition, the inrush current into an empty output capacitor is limited. The converter can start
into a full load, which is defined by a 33-Ω or 66-Ω resistor, respectively.
Driving EN low disables the converter. This disables all internal circuits and reduces the supply current to only
0.05 µA. The device exits shutdown once EN is set high. When the device is disabled, the load is isolated from
the input. This is an important feature in battery operated products because it extends the products shelf life.
synchronization to an external clock signal
The operating frequency of the charge pump is limited to 400 kHz in order to avoid interference in the sensitive
455-kHz IF band. The device can either run from the integrated oscillator, or an external clock signal can be used
to drive the charge pump. The maximum frequency of the external clock signal is 800 kHz. The switching
frequency used internally to drive the charge pump power stages is half of the external clock frequency. The
external clock signal is applied to the EN pin. The device will switch off if the signal on EN is hold low for more
than 10 µs.
When the load current drops below the LinSkip current threshold, the devices will enter the pulse-skip mode
but stay synchronized to the external clock signal.
SLVS354A − FEBRUAR Y 2001 − REVISED SEPTEMBER 2001
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
detailed description (continued)
low-battery detector (TPS60204)
The low-battery comparator trips at 1.18 V ±4% when the voltage on pin LBI ramps down. The voltage V(TRIP)
at which the low-battery warning is issued can be adjusted with a resistive divider as shown in Figure 2. The
sum of resistors R1 and R2 is recommended to be in the 100-kΩ to 1-MΩ range. When choosing R1 and R2,
be aware of the input leakage current into the LBI pin.
LBO is an open drain output. An external pullup resistor to OUT, or any other voltage rail in the appropriate range,
in the 100-kΩ to 1-MΩ range is recommended. During start-up, the LBO output signal is invalid for the first
500 µs. LBO is high impedance when the device is disabled. If the low-battery comparator function is not used,
connect LBI to ground and leave LBO unconnected. The low-battery detector is disabled when the device is
switched off.
V(TRIP) +1.18 V ǒ1)R1
R2Ǔ
_
+
+
−
VREF
VBAT
IN
R1
LBI
R2
LBO
R3
V
O
Figure 2. Programming of the Low-Battery Comparator Trip Voltage
A 100-nF ceramic capacitor should be connected in parallel to R2 if large line transients are expected. These
voltage drops can inadvertently trigger the low-battery comparator and produce a wrong low-battery warning
signal at the LBO pin.
Formulas to calculate the resistive divider for low-battery detection, with VLBI = 1.13 V to 1.23 V and the sum
of resistors R1 and R2 equal 1 MΩ:
R2 +1MW VLBI
VBat
R1 +1MW*R2
(1)
(2)
Formulas to calculate the minimum and maximum battery voltage:
VBat(min) +VLBI(min)
R1
(min) )
R2
(max)
R2(max)
V
Bat(max) +VLBI(max) R1(max) )R2(min)
R2
(min)
(3
)
(4
)
SLVS354A − FEBRUAR Y 2001 − REVISED SEPTEMBER 2001
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
detailed description (continued)
Table 1. Recommended Values for the Resistive Divider From the E96 Series (±1%)
VIN/V R1/kΩR2/kΩVTRIP(MIN)/V VTRIP(MAX)/V
1.6 267 750 1.524 1.677
1.7 301 681 1.620 1.785
1.8 340 649 1.710 1.887
1.9 374 619 1.799 1.988
2.0 402 576 1.903 2.106
power-good detector (TPS60205)
The power-good output is an open-drain output that pulls low when the output is out of regulation. When the
output rises to within 90% of its nominal voltage, the power-good output is released. Power-good is high
impedance in shutdown. In normal operation, an external pullup resistor must be connected between PG and
OUT, or any other voltage rail in the appropriate range. The resistor should be in the 100-kΩ to 1-MΩ range.
If the PG output is not used, it should remain unconnected.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Voltage range: IN, OUT, EN, LBI, LBO, PG to GND −0.3 V to 3.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C1+, C2+ to GND −0.3 V to (VO + 0.3 V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C1−, C2− to GND −0.3 V to (VI + 0.3 V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See dissipation rating table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current TPS60204, TPS60205 150 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −55°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum junction temperature, TJ150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATING TABLE
PACKAGE TA ≤ 25°C
POWER RATING DERATING FACTOR
ABOVE TA = 25°CTA = 70°C
POWER RATING TA = 85°C
POWER RATING
DGS 424 mW 3.4 mW/_C187 mW 136 mW
The thermal resistance junction to ambient of the DGS package is RTH−JA = 294°C/W.
recommended operating conditions
MIN NOM MAX UNIT
Input voltage range, VI1.6 3.6 V
Input capacitor, Ci2.2 µF
Flying capacitors, C1, C2 1µF
Output capacitor, Co2.2 µF
Operating junction temperature, TJ−40 125 °C
SLVS354A − FEBRUAR Y 2001 − REVISED SEPTEMBER 2001
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at Ci = 2.2 µF, C1 = C2 = 1 µF, CO = 2.2 µF, TA = −40°C to 85°C, VI = 2.4 V,
EN = VI (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IO(MAX) Maximum continuous output current VI = 2 V 100 mA
1.6 V < VI < 1.8 V, 0 < IO < 0.25 × IO(MAX) 3
VO
Output voltage
1.8 V < VI < 2 V, 0 < IO < 0.5 × IO(MAX) 3.17 3.43
V
V
O
Output voltage
2 V < VI < 3.3 V, 0 < IO < IO(MAX) 3.17 3.43
V
3.3 V < VI < 3.6 V, 0 < IO < IO(MAX) 3.17 3.47
VPP Output voltage ripple IO = IO(MAX) 5 mVPP
I(Q) Quiescent current (no-load input current) IO = 0 mA, VI = 1.8 V to 3.6 V 35 70
µA
I(SD) Shutdown supply current EN = 0 V 0.05 1 µ
A
f(OSC) Internal switching frequency 200 300 400
kHz
f(SYNC) External clock signal frequency 400 600 800
kHz
External clock signal duty cycle 30% 70%
VIL EN input low voltage VI = 1.6 V to 3.6 V 0.3 × VI
V
VIH EN input high voltage VI = 1.6 V to 3.6 V 0.7 × VI
V
Ilkg(EN) EN input leakage current EN = 0 V or VI0.01 0.1 µA
Output capacitor auto discharge time EN is set from VI to GND,
Time until VO < 0.5 V 0.6 ms
Output leakage current in shutdown
EN = 0 V, TA = −40 to 85°C 5
µA
Output leakage current in shutdown
EN = 0 V, TA ≤ 65°C 3 µ
A
LinSkip threshold VI = 2.2 V 7 mA
Output load regulation 10 mA < IO < IO(MAX); TA = 25°C 0.01 %/mA
Output line regulation 2 V < VI < 3.3 V, IO = 0.5 x IO(MAX),
TA = 25°C0.6 %/V
I(SC) Short circuit current VI = 2.4 V, VO = 0 V 60 mA
electrical characteristics for low-battery comparator of devices TPS60204 at TA = −40°C to 85°C,
VI = 2.4 V and EN = VI (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V(LBI) LBI trip voltage VI = 1.6 V to 2.2 V, Tc = 0°C to 70°C 1.13 1.18 1.23 V
LBI trip voltage hysteresis For rising voltage at LBI 10 mV
II(LBI) LBI input current V(LBI) = 1.3 V 2 50 nA
VO(LBO) LBO output voltage low V(LBI) = 0 V, I(LBO) = 1 mA 0.4 V
Ilkg(LBO) LBO leakage current V(LBI) = 1.3 V, V(LBO) = 3.3 V 0.01 0.1 µA
NOTE: During start-up of the converter the LBO output signal is invalid for the first 500 µs.
electrical characteristics for power-good comparator of devices TPS60205 at TA = −40°C to 85°C,
VI = 2.4 V and EN = VI (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V(PG) Power-good trip voltage Tc = 0°C to 70°C0.87 × VO0.91 × VO0.95 × VOV
Vhys(PG) Power-good trip voltage hysteresis VO decreasing, Tc = 0°C to 70°C 1%
VO(PG) Power-good output voltage Low VO = 0 V, I(PG) = 1 mA 0.4 V
Ilkg(PG) Power-good leakage current VO = 3.3 V, V(PG) = 3.3 V 0.01 0.1 µA
NOTE: During start-up of the converter the PG output signal is invalid for the first 500 µs.
SLVS354A − FEBRUAR Y 2001 − REVISED SEPTEMBER 2001
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURES
Efficiency
vs Output current (TPS60204, TPS60205) 3
ηEfficiency vs Input voltage 4
IQQuiescent supply current vs Input voltage 5
VO
Output voltage
vs Output current 6
VOOutput voltage vs Input voltage 7
VOOutput voltage ripple vs Time 8, 9, 10
Start-up timing 11
Load transient response 12, 13
IOPeak output current vs Input voltage 14
NOTE: All typical characteristics were measured using the typical application circuit of Figure 14 (unless otherwise noted).
Figure 3
0.1 IO − Output Current − mA
TPS60204, TPS60205
EFFICIENCY
vs
OUTPUT CURRENT
1 10 100 1000
VI = 2.4 V
VI = 1.8 V
VI = 2.7 V
Efficiency − %
100
90
80
70
60
50
40
30
20
10
0
Figure 4
EFFICIENCY
vs
INPUT VOLTAGE
0
10
20
30
40
50
60
70
80
90
100
1.6 2.0 2.4 2.8 3.2 3.6
VI − Input Voltage − V
Efficiency − %
IO = 50 mA
SLVS354A − FEBRUAR Y 2001 − REVISED SEPTEMBER 2001
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 5
30
28
24
22
20
38
26
1.6 1.8 2.0 2.2 2.4 2.6 2.8
34
32
36
V − Input Voltage − V
QUIESCENT SUPPLY CURRENT
vs
INPUT VOLTAGE
40
3.0 3.2 3.4 3.6
− Quiescent Supply Current − A
µ
I
IO = 0 mA
I(Q)
Figure 6
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
3.2
2.9
3.5
3.4
3.3
3.1
3.0
− Output Voltage − V
VI = 1.8 V
VI = 2.4 V
VI = 2.7 V
VI = 3.6 V
IO − Output Current − mA
10 100 10001
VO
Figure 7
− Output Voltage − V
VO
OUTPUT VOLTAGE
vs
INPUT VOLTAGE
3.0
2.9
2.8
2.71.6 2.0 2.4 2.8
3.1
3.2
3.4
3.2 3.6
3.3
1 mA
50 mA
100 mA
VI − Input Voltage − V
Figure 8
t − Time − µs
OUTPUT VOLTAGE RIPPLE
vs
TIME
050
3.22
3.24
3.34
3.38
3.36
3.32
3.30
3.26
3.28
5454035302510 15 20
− Output Voltage Ripple − V
VO
VI = 2.4 V
IO = 1 mA
SLVS354A − FEBRUAR Y 2001 − REVISED SEPTEMBER 2001
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 9
t − Time − µs
OUTPUT VOLTAGE RIPPLE
vs
TIME
010
3.22
3.24
3.34
3.38
3.36
3.32
3.30
3.26
3.28
198765234
− Output Voltage Ripple − V
VO
VI = 2.4 V
IO = 10 mA
Figure 10
t − Time − µs
OUTPUT VOLTAGE RIPPLE
vs
TIME
3.30
3.28
3.24
3.220123456
3.34
3.36
3.38
78910
VI = 2.4 V
IO = 100 mA
3.32
3.26
− Output Voltage Ripple − V
VO
Figure 11
START-UP TIMING
2
1
0
0 50 100 150 200 250 300
2.5
3
3.5
350 400 450 500
1.5
0.5
VO
EN
II
t − Time − µs
VI = 2.4 V
800
400
0
1000
1200
1400
600
200
− Input Current − mA
I
I
− Output Voltage − V
VO
Figure 12
LOAD TRANSIENT RESPONSE
100 mA
10 mA0 50 100 150 200 250 300
− Output Voltage − V
3.26
3.28
3.30
350 400 450 50
0
3.24
VO
− Output Current − mA
IO
t − Time − µs
VI = 2.4 V
SLVS354A − FEBRUAR Y 2001 − REVISED SEPTEMBER 2001
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 13 Figure 14
LINE TRANSIENT RESPONSE
3.30
3.26
2.2 V 0123456
3.32
78910
IO = 50 mA
3.28
2.8 V
− Output Voltage − V
VO
− Input Voltage − V
VI
t − Time − ms
PEAK OUTPUT CURRENT
vs
INPUT VOLTAGE
150
100
50
01.6 2.0 2.4 2.8
200
250
350
3.2 3.6
300
VI − Input Voltage − V
− Peak Output Current − mA
IO
SLVS354A − FEBRUAR Y 2001 − REVISED SEPTEMBER 2001
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APPLICATION INFORMATION
capacitor selection
The TPS6020x devices require only four external capacitors to achieve a very low output voltage ripple. The
capacitor values are closely linked to the required output current. Low ESR (<0.1 Ω) capacitors should be used
at input and output. In general, the transfer capacitors (C1 and C2) will be the smallest; a 1-µF value is
recommended for maximum load operation. With smaller capacitor values, the maximum possible load current
is reduced and the LinSkip threshold is lowered.
The input capacitor improves system efficiency by reducing the input impedance. It also stabilizes the input
current of the power source. The input capacitor should be chosen according to the power supply used and the
distance from the power source to the converter IC. Ci is recommended to be about two to four times as large
as the flying capacitors C1 and C2.
The output capacitor (Co) should be at minimum the size of the input capacitor. The minimum required
capacitance is 2.2 µF. Larger values will improve the load transient performance and will reduce the maximum
output ripple voltage.
Only ceramic capacitors are recommended for input, output, and flying capacitors. Depending on the material
used to manufacture them, ceramic capacitors might lose their capacitance over temperature and voltage.
Ceramic capacitors of type X7R or X5R material will keep their capacitance over temperature and voltage,
whereas Z5U- or Y5V-type capacitors will decrease in capacitance. Table 2 lists the recommended capacitor
values.
Table 2. Recommended Capacitor Values (Ceramic X5R and X7R)
LOAD CURRENT,
IL
(mA)
FLYING
CAPACITORS,
C1/C2
(µF)
INPUT
CAPACITOR,
Ci
(µF)
OUTPUT
CAPACITOR,
Co
(µF)
OUTPUT VOLTAGE
RIPPLE IN LINEAR MODE,
V(P-P)
(mV)
OUTPUT VOLTAGE
RIPPLE IN SKIP MODE,
V(P-P)
(mV)
0−100 1 2.2 2.2 3 20
0−100 1 4.7 4.7 3 10
0−100 1 2.2 10 3 7
0−100 2.2 4.7 4.7 3 10
0−50 0.47 2.2 2.2 3 20
0−25 0.22 2.2 2.2 5 15
0−10 0.1 2.2 2.2 5 15
Table 3. Recommended Capacitor Types
MANUFACTURER PART NUMBER SIZE CAPACITANCE TYPE
Taiyo Yuden UMK212BJ104MG 0805 0.1 µF Ceramic
Taiyo Yuden
EMK212BJ224MG 0805 0.22 µF Ceramic
EMK212BJ474MG 0805 0.47 µF Ceramic
LMK212BJ105KG 0805 1 µF Ceramic
LMK212BJ225MG 0805 2.2 µF Ceramic
EMK316BJ225KL 1206 2.2 µF Ceramic
LMK316BJ475KL 1206 4.7 µF Ceramic
JMK316BJ106ML 1206 10 µF Ceramic
AVX 0805ZC105KAT2A 0805 1 µF Ceramic
AVX
1206ZC225KAT2A 1206 2.2 µF Ceramic
SLVS354A − FEBRUAR Y 2001 − REVISED SEPTEMBER 2001
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
Table 4. Recommended Capacitor Manufacturers
MANUFACTURER CAPACITOR TYPE INTERNET SITE
Taiyo Yuden X7R/X5R ceramic http://www.t−yuden.com/
AVX X7R/X5R ceramic http://www.avxcorp.com/
OUTPUT
3.3 V, 100 mA
INPUT
1.6 V to 3.6 V
OFF/ON
C1
1µFC2
1µF
Co
2.2 µF
Ci
2.2 µFR1
R2
1
2
3
4
5
6
7
8
9
10 R3
Low Battery
Warning
IN
EN
C1−
C1+
LBI
TPS60204
OUT
C2−
C2+
LBO
GND
Figure 15. Typical Operating Circuit TPS60204 With Low-Battery Detector
OUTPUT
3.3 V, 100 mA
INPUT
1.6 V to 3.6 V
OFF/ON
C1
1µFC2
1µF
Co
2.2µF
Ci
2.2 µF
3
4
5
6
7
8
9
10 R1
Power-Good
IN
EN
C1−
C1+
TPS60205
OUT
C2−
C2+
PG
GND
1,2
Signal
Figure 16. Typical Operating Circuit TPS60205 With Power-Good Detector
SLVS354A − FEBRUAR Y 2001 − REVISED SEPTEMBER 2001
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APPLICATION INFORMATION
power dissipation
The power dissipated in the TPS6020x devices depends mainly on input voltage and output current and is
approximated by:
P(DISS) +IOxǒ2xV
I*VOǓfor I(Q) tIO(5)
By observing equation 5, it can be seen that the power dissipation is worst for highest input voltage VI and
highest output current IO. For an input voltage of 3.6 V and an output current of 100 mA the calculated power
dissipation P (DISS) is 390 mW. This is also the point where the charge pump operates with its lowest efficiency.
With the recommended maximum junction temperature of 125°C and an assumed maximum ambient operating
temperature of 85°C, the maximum allowed thermal resistance junction to ambient of the system can be
calculated.
RQJA(max) +TJ(MAX) *TA
PDISS(max) +125°C*85°C
390 mW +102°CńW(6)
PDISS must be less than that allowed by the package rating. The thermal resistance junction to ambient of the
used 10-pin MSOP is 294°C/W for an unsoldered package. The thermal resistance junction to ambient with
the IC soldered to a printed circuit using a board layout as described in the application information section, the
RΘJA is typically 200°C/W, which is higher than the maximum value calculated above. However, in a battery
powered application, both VI and TA will typically be lower than the worst case ratings used in equation 6 , and
power dissipation should not be a problem in most applications.
layout and board space
Careful board layout is necessary due to the high transient currents and switching frequency of the converter.
All capacitors should be placed in close proximity to the device. A PCB layout proposal for a one-layer board
is given in Figure 17. There is no specific EVM available for the TPS60204. However, the TPS60200EVM−145
can be used to evaluate the device.
The evaluation module for the TPS60200 can be ordered under product code TPS60200EVM−145. The EVM
uses the layout shown in Figure 17. All components including the pins are shown. The EVM is built so that it
can be connected to a 14-pin dual inline socket, therefore, the space needed for the IC, the external parts, and
eight pins is 17,9 mm x 10,2 mm = 182,6 mm2.
SLVS354A − FEBRUAR Y 2001 − REVISED SEPTEMBER 2001
16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
Figure 17. Recommended Component Placement and Board Layout
Table 5. Component Identification
IC1 TPS60204
C1, C2 Flying capacitors
C3 Input capacitors
C4 Output capacitors
C5 Stabilization capacitor for LBI
R1, R2 Resistive divider for LBI
R3 Pullup resistor for LBO
R4 Pullup resistor for EN
Capacitor C5 should be included if large line transients are expected. This capacitor suppresses toggling of the
LBO due to these line changes.
device family products
Other charge pump dc-dc converters in this family are:
Table 6. Product Identification
PART NUMBER DESCRIPTION
TPS60100 2-cell to regulated 3.3 V, 200-mA low-noise charge pump
TPS60101 2-cell to regulated 3.3 V, 100-mA low-noise charge pump
TPS60110 3-cell to regulated 5.0 V, 300-mA low-noise charge pump
TPS60111 3-cell to regulated 5.0 V, 150-mA low-noise charge pump
TPS60120 2-cell to regulated 3.3 V, 200-mA high efficiency charge pump with low battery comparator
TPS60121 2-cell to regulated 3.3 V, 200-mA high efficiency charge pump with power-good comparator
TPS60122 2-cell to regulated 3.3 V, 100-mA high efficiency charge pump with low battery comparator
TPS60123 2-cell to regulated 3.3 V, 100-mA high efficiency charge pump with power-good comparator
TPS60130 3-cell to regulated 5.0 V, 300-mA high efficiency charge pump with low battery comparator
TPS60131 3-cell to regulated 5.0 V, 300-mA high efficiency charge pump with power-good comparator
TPS60132 3-cell to regulated 5.0 V, 150-mA high efficiency charge pump with low battery comparator
TPS60133 3-cell to regulated 5.0 V, 150-mA high efficiency charge pump with power-good comparator
TPS60140 2-cell to regulated 5.0 V, 100-mA charge pump voltage tripler with low battery comparator
TPS60141 2-cell to regulated 5.0 V, 100-mA charge pump voltage tripler with power-good comparator
SLVS354A − FEBRUAR Y 2001 − REVISED SEPTEMBER 2001
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
DGS (S-PDSO-G10) PLASTIC SMALL-OUTLINE PACKAGE
0,69
0,41
0,25
0,15 NOM
Gage Plane
4073272/B 08/01
4,98
0,17
6
3,05 4,78
2,95
10
5
3,05
2,95
1
0,27
0,15
0,05
1,07 MAX
Seating Plane
0,10
0,50 M
0,08
0°−ā6°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Falls within JEDEC MO-187
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TPS60204DGS ACTIVE MSOP DGS 10 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS60204DGSG4 ACTIVE MSOP DGS 10 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS60204DGSR ACTIVE MSOP DGS 10 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS60204DGSRG4 ACTIVE MSOP DGS 10 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS60205DGS ACTIVE MSOP DGS 10 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS60205DGSG4 ACTIVE MSOP DGS 10 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS60205DGSR ACTIVE MSOP DGS 10 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS60205DGSRG4 ACTIVE MSOP DGS 10 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 5-Feb-2007
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS60204DGSR MSOP DGS 10 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TPS60205DGSR MSOP DGS 10 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Jul-2008
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS60204DGSR MSOP DGS 10 2500 340.5 338.1 20.6
TPS60205DGSR MSOP DGS 10 2500 340.5 338.1 20.6
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Jul-2008
Pack Materials-Page 2
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