MK3722GTR - Integrated Circuit Solution, Inc.

MDS 3722 B 1Revisi on 092502

Integrated C ircuit Systems ● 5 25 Race Street, San Jose, CA 95126 ● tel (408) 2 95-9800 ● www.icst.com

VCXO PLUS AUDIO CLOCK FOR STB

MK3722

Description

The MK3722 is a low cost, low jitter, high performance

VCXO and PLL clock synthesizer designed to replace

expensive discrete VCXOs and multipliers. The

patented on-chip Voltage Controlled Crystal Oscillator

accepts a 0 to 3.3 V input voltage to cause the output

clocks to vary by ±115 ppm. Using ICS’ analog/digital

Phase-Locked Loop (PLL) techniques, the device uses

an inexpensive 27 MHz pullable crystal input to

produce a reference output and a selectable audio

clock.

ICS manufactures the largest variety of VCXO based

timing devices for all applications. Consult ICS to

eliminate VCXOs, crystals, and oscillators from your

board.

The frequency of the on-chip VCXO is adjusted by an

external control voltage connected to VIN. Because

VIN is a high impedance input, it can be driven directly

from an PWM RC integrator circuit.

Features

•Packaged in 16 pin TSSOP

•Replaces a VCXO and oscillator

•Operating voltage of 3.3V

•Provides output of 27 MHz plus audio clock

•Uses an inexpensive 27 MHz pullable crystal

•On-chip patented VCXO with pull range of 230 ppm

(minimum)

•VCXO tuning voltage of 0 to 3.3 V

•Advanced, low power, sub-micron CMOS process

Block Diagram

Voltage

Controlled

Crystal

Oscillator

VIN

27 MHz

Pullable

Crystal

PLL/Clock

Synthesis

Circuitry ACLK

27MHz

S2:S0

VDD

GND

PDTS

VCXO PLUS AUDIO CLOCK FOR STB

MDS 3722 B 2Revision 092502

Integrated C ircuit Systems ● 525 R ace Street, San Jose, CA 95126 ● tel (40 8) 295-9800 ● www.icst.com

MK3722

Pin A ssign ment

Pin Descriptions

Audio Cloc k Select Table

VDD

VIN

VDD

27M

GND GND

GND ACLK

PDTS

16 Pin 4.40m m bod y, 0.65m m pitch TSS O P

S2 S1 S0 ACLK (MHz)

000 8.192

0 0 1 11.2896

0 1 0 12.288

0 1 1 16.9344

1 0 0 18.432

1 0 1 16.384

1 1 0 22.5792

1 1 1 24.576

Number Pin

Name Pin

Type Pin Description

1 X2 Output Crystal connection. Connect to a 27MHz fundamental mode

pullable crystal.

2 X1 Input Crystal connection. Connect to a 27MHz fundamental mode

pullable crystal.

3 VDD Power Connect to +3.3 V.

4 VDD Power Connect to +3.3 V.

5 VIN Input Voltage input to VCXO. Zero to 3.3V signal which controls the

VCXO frequency.

6 GND Power Connect to ground.

7 GND Power Connect to ground.

8PDTS

Power Power Down Tri-state. This pin powers down entire chip and

tri-states the outputs when low. Internal pull-up.

9 S2 Input Select input S2. Selects ACLK per table above. Internal pull-up.

10 ACLK Output Audio clock output per table above.

11 GND Power Connect to ground.

12 27M Output 27MHz reference clock output.

13 S0 Input Select input S0. Selects ACLK per table above. Internal pull-up.

14 VDD Power Connect to +3.3V.

15 NC -- No connect. Do not connect anything to this pin.

16 S1 Input Select input S1. Selects ACLK per table above. Internal pull-up.

VCXO PLUS AUDIO CLOCK FOR STB

MDS 3722 B 3Revision 092502

Integrated C ircuit Systems ● 525 R ace Street, San Jose, CA 95126 ● tel (40 8) 295-9800 ● www.icst.com

MK3722

External Component Selection

The MK3722 requires a minimum number of external

components for proper operation.

Decoupling Capacitors

Decoupling capacitors of 0.01µF should be connected

between VDD and GND on pins 3 and 4, pins 6 and 7,

and pins 11 and 14 as close to the MK3722 as

possible. For optimum device performance, the

decoupling capacitors should be mounted on the

component side of the PCB. Avoid the use of vias in the

decoupling circuit.

Series Termination Resistor

When the PCB traces between the clock outputs and

the loads are over 1 inch, series termination should be

used . To series terminate a 50Ω trace (a commonly

used trace impedance) place a 33Ω resistor in series

with the clock line, as close to the clock output pin as

poss ible. T he nomi nal impedan ce of the cl ock out put i s

20Ω.

Quartz Crysta l

The MK3722 VCXO function consists of the external

crystal and the integrated VCXO oscillator circuit. To

assure the best system performance (frequency pull

range) and reliability, a crystal device meeting ICS’

recommended parameters must be used, and the

layout guidelines discussed in the following section

must be followed.

See Application Note MAN05 for a full list of crystal

parameters.

The frequency of oscillation of a quartz crystal is

determined by its “cut” and by the load capacitors

connected to it. The MK3722 incorporates on-chip

variable load capacitors that “pull” (change) the

frequency of the crystal. The crystal specified for use

with the MK3722 is designed to have zero frequency

error when the total of on-chip + stray capacitance is

14pF.

The external crystal must be connected as close to the

chip as possible and should be on the same side of the

PCB as the MK3722. There should be no via’s between

the crystal pins and the X1 and X2 device pins. There

should be no signal traces underneath or close to the

crystal.

Crystal Tun ing Load Capacitors

The crystal traces should include pads for small fixed

capacitors, one between X1 and ground, and another

between X2 and ground. Stuf fing of these capacitors

on the PCB is optional. The need for these capacitors

is determined at system prototype evaluation, and is

influenced by the particular crystal used (manufacture

and frequency) and by PCB layout. The typical required

capacitor value is 1 to 4 pF.

To determine the need for and value of the crystal

adjustment capacitors, you will need a PC board of

your final layout, a frequency counter capable of about

1 ppm resolution and accuracy, two power supplies,

and samples of the crystals which you plan to use in

production. You will also need measured initial

accuracy for e ach crystal at the specified crystal load

capacitance (CL).

To determine the value of the crystal capacitors:

1. Connect VDD to 3.3V. Connect pin 5 to the second

power supply. Adjust the voltage on pin 5 to 0V.

Measure and record the frequency of the CLK output.

2. Adjust the voltage on pin 5 to 3.3V. Measure and

record the frequency of the same output.

To calculate the centering error:

Where:

ftarget = nominal crystal frequency

errorxtal =actual initial accuracy (in ppm) of the crystal

being measured

If the centering error is less than ±25 ppm, no

adjustment is needed. If the centering error is more

than 25ppm negative, the PC board has excessive

stray capacitance and a new PCB layout should be

considered to reduce stray capacitance. (Alternately,

the crystal may be re-specified to a higher load

capacitance. Contact ICS for details.) If the centering

error is more than 25ppm positive, add identical fixed

centering capacitors from each crystal pin to ground.

The value for each of these caps (in pF) is given by:

Error 106xf3.3 3.0

()

Vftetarg

–()f0V ftetarg

–()+

ftetarg

---------------------------------------------------------------------------------------- errorxtal

–=

VCXO PLUS AUDIO CLOCK FOR STB

MDS 3722 B 4Revision 092502

Integrated C ircuit Systems ● 525 R ace Street, San Jose, CA 95126 ● tel (40 8) 295-9800 ● www.icst.com

MK3722

External Capacitor =

2 x (centering error)/(trim sensitivity)

Trim sensitivity is a parameter which can be supplied

by yo ur crystal vendor. If you do not know the v alue,

assume it is 30 ppm/pF. After any changes, repeat the

measurement to verify that the remaining error is

acceptably low (typically less than ±25ppm).

Absolute Maximum Rating s

Stresses above the ratings listed below can cause permanent damage to the MK3722. These ratings,

which are standard values for ICS commercially rated parts, are stress ratings only . Functional operation of

the device at these or any other conditions above those indicated in the operational sections of the

specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can

affect product reliability. Electrical parameters are guaranteed only over the recommended operating

temperature range.

Recommended Oper ation Conditio ns

DC Electrical Characteristics

VDD=3.3V ±5% , Ambient temperature 0 to +70°C, unless stated otherwise

Item Rating

Supply Voltage, VDD 7V

All Inputs and Outputs -0.5V to VDD+0.5V

Ambient Operating Temperature 0 to +70°C

Storage Temperature -65 to +150°C

Soldering Te mpe ra tur e 260°C

Parameter Min. Typ. Max. Units

Ambient Operating Temperature 0 +70 °C

Power Supply Voltage (measured in respect to GND) +3.15 +3.45 V

Reference crystal parameters Refer to page 3

Parameter Symbol Conditions Min. Typ. Max. Units

Operati ng Voltage VDD 3.15 3.45 V

Output High Volta ge VOH IOH = -12 mA 2.4 V

Output Low Voltage VOL IOL = 12 mA 0.4 V

Output High Voltage (CMOS

Level) VOH IOH = -4 mA VDD-0.4 V

Input High Voltage (S1:S0) VIH 2.0 V

Input High Voltage (S2) VIH 2.5 V

Input Low Voltage (S1:S0) VIL 0.8 V

Input Low Voltage (S2) VIL 0.5 V

VCXO PLUS AUDIO CLOCK FOR STB

MDS 3722 B 5Revision 092502

Integrated C ircuit Systems ● 525 R ace Street, San Jose, CA 95126 ● tel (40 8) 295-9800 ● www.icst.com

MK3722

AC Electrical Characteristics

VDD = 3.3V ±5%, Ambient Temperature 0 to +70° C, unless stated otherwise

Note 1: External crystal device must conform with Pullable Crystal Specifications listed on page 3.

Thermal Characteristics

Operating Supply Current IDD No load, 2

outputs 11 mA

Short Circuit Current IOS ±50 mA

VIN, VCXO Control Voltage VIA 03.3V

On Chip Pull-up Resistor,

inputs RPU S0, S1, S2 150 kΩ

Input Capacitance CIN S0, S1, S2 5 pF

Nominal Output Impedance ZOUT 20 Ω

Parameter Symbol Conditions Min. Typ. Max. Units

Crystal Pullability fP0V< VIN < 3.3V, Note 1 + 100 ppm

VCXO Ga in VIN = VDD/2 + 1V, Note 1 80 ppm/V

Output Rise Time tOR 0.8 to 2.0V, CL=15pF 0.75 1.5 ns

Output Fall Time tOF 2.0 to 0.8V, CL=15pF 0.75 1.5 ns

Output Clock Duty Cycle tDMeasured at 1.65V, CL=15pF 40 50 60 %

Maximum Output Jitter,

short term tJCL=15pF +150 ps

Parameter Symbol Conditions Min. Typ. Max. Units

Thermal Resistance Junction to

Ambient θJA Stil l air 78 °C/W

θJA 1 m/s air flow 70 °C/W

θJA 3 m/s air flow 68 °C/W

Thermal Resistance Junction to Case θJC 37 °C/W

Parameter Symbol Conditions Min. Typ. Max. Units

VCXO PLUS AUDIO CLOCK FOR STB

MDS 3722 B 6Revision 092502

Integrated C ircuit Systems ● 525 R ace Street, San Jose, CA 95126 ● tel (40 8) 295-9800 ● www.icst.com

MK3722

Package Outline and Package Dimensions (16 pin TSSOP, 4.40 mm Body, 0.65 mm Pitch)

Package dimensions are kept current with JEDEC Publication No. 95

Ordering Information

While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)

assumes no responsibil ity for either its us e or fo r the infringement of any paten ts or other rights of third parties, which would

result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial

applications. Any oth er ap pl ic atio ns su ch as those req uiring ext end ed tem pera ture range, hig h re lia bi lity, or other ex trao rdi nary

environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any

circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or

critical medical instruments.

Part / Order Number Marking Shipping

packaging Package Temperature

MK3722G MK3722G Tubes 16 pin TSSOP 0 to +70° C

MK3722GTR MK3722G Tape and Reel 16 pin TSSOP 0 to +70° C

INDEX

AREA

1 2

E1 E

SEATING

PLANE

- C -

.10 (.004) C

Millimeters Inches

Symbol Min Max Min Max

A -- 1.20 -- 0.047

A1 0.05 0.15 0.002 0.006

A2 0.80 1.05 0.032 0.041

b 0.19 0.30 0.007 0.012

C 0.09 0.20 0.0035 0.008

D 4.90 5.1 0.193 0.201

E 6.40 BASIC 0.252 BASIC

E1 4.30 4.50 0.169 0.177

e 0.65 Basic 0.0256 Basic

L 0.45 0.75 0.018 0.030

α0°8°0°8°