MT9M114 1/6inch 720p HighDefinition (HD) SystemOnaChip (SOC) Digital Image Sensor www.onsemi.com The MT9M114 from ON Semiconductor is a 1/6-inch 1.26 Mp CMOS digital image sensor with an active-pixel array of 1296 (H) x 976 (V). It includes sophisticated camera functions such as auto exposure control, auto white balance, black level control, flicker avoidance, and defect correction. It is designed for low light performance. The MT9M114 produces extraordinarily clear, sharp digital pictures, making it the perfect choice for a wide range of applications, including mobile phones, PC and notebook cameras, and gaming systems. ORDERING INFORMATION Table 1. KEY PERFORMANCE PARAMETERS See detailed ordering and shipping information on page 2 of this data sheet. Typical Value Parameter ODCSP55 4.7x3.9 CASE 570BP Optical Format 1/6-inch Active Pixels 1296 (H) x 976 (V) = 1.26 Mp Pixel Size 1.9 mm x 1.9 mm Color Filter Array RGB Bayer Shutter Electronic Rolling Shutter (ERS) Input Clock Range 6-54 MHz Output MIPI Data Rate Maximum 768 Mb/s * Max. Frame Rate 30 fps Full Res 36.7 fps 720p 75 fps VGA 120 fps QVGA (Note 2) * * Responsivity 2.24 V/Lux-sec (550 nm) SNRMAX 37 dB Dynamic Range 70.8 dB Supply Voltage Digital Analog I/O PLL PHY 1.7-1.95 V 2.5-3.1 V 1.7-1.95 V or 2.5-3.1 V 2.5-3.1 V 1.7-1.95 V Power Consumption 135 mW (Note 1) Operating Temperature Range (Ambient) - TA -30C to 70C Chief Ray Angle 27.7 * * * Active Imager Size 2.46 mm (H) x 1.85 mm (V), 3.08 mm Diagonal Applications Package Options Bare Die, CSP * * * * Phase-locked Loop (PLL) Oscillator Electronic Rolling Shutter (ERS), Progressive Scan Integrated Image Flow Processor (IFP) for Single-die Camera Module Automatic Image Correction and Enhancement Arbitrary Image Scaling with Anti-aliasing Two-wire Serial Interface Providing Access to Registers and Microcontroller Memory Selectable Output Data Format: YCbCr, 565RGB, 555RGB, 444RGB, Processed Bayer, BT656, RAW8- and RAW8+2-bit Parallel and MIPI Data Output Independently Configurable Gamma Correction Adaptive Polynomial Lens Shading Correction UVC Interface Perspective Correction Multi-camera Synchronization * Embedded Notebook, Netbook, and Desktop Monitor Cameras * Tethered PC Cameras * Game Consoles * Cell Phones, Mobile Devices, and Consumer Features * Superior Low-light Performance * Ultra-low Power * 720p HD Video at 30 fps June, 2019 - Rev. 13 * * 1. Power consumption for typical voltages and 720p output. 2. Reduced FOV. (c) Semiconductor Components Industries, LLC, 2016 * Internal Master Clock Generated by On-chip Video Communications * Surveillance, Medical, and Industrial Applications 1 Publication Order Number: MT9M114/D MT9M114 ORDERING INFORMATION Table 2. AVAILABLE PART NUMBERS Part Number Product Description MT9M114D00STCZK24BC1-200 1 MP 1/6 SOC Orderable Product Attribute Description Die Sales, 200 mm Thickness MT9M114EBLSTCZ-CR1 1 MP 1/6 SOC CIS Chip Tray without Protective Film MT9M114EBLSTCZ-CR 1 MP 1/6" SOC CIS Chip Tray without Protective Film See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at www.onsemi.com. FUNCTIONAL DESCRIPTION The MT9M114 from ON Semiconductor is a 1/6-inch 1.26 Mp CMOS digital image sensor with an integrated advanced camera system. This camera system features a microcontroller (MCU), a sophisticated image flow processor (IFP), MIPI and parallel output ports (only one output port can be used at a time). The microcontroller manages all functions of the camera system and sets key operation parameters for the sensor core to optimize the quality of raw image data entering the IFP. The IFP will be responsible for processing and enhancing the image. The entire system-on-a-chip (SOC) has superior low-light performance that is particularly suitable for PC camera applications. The MT9M114 features ON Semiconductor's breakthrough low-noise CMOS imaging technology that achieves near-CCD image quality (based on signal-to-noise ratio and low-light sensitivity) while maintaining the inherent size, cost, and integration advantages of CMOS. The MT9M114 can be operated in its default mode or programmed for frame size, exposure, gain, and other parameters. The default mode output is a 720p image size at 30 frames per second (fps), assuming a 24 MHz input clock. It outputs 8-bit data, using the parallel output port. ARCHITECTURE OVERVIEW The MT9M114 combines a 1.26 Mp sensor core with an IFP to form a stand-alone solution for both image acquisition and processing. Both the sensor core and the IFP have internal registers that can be controlled by the user. In normal operation, an integrated microcontroller Pixel Array Color Pipeline Output Interface Formatter Image Flow Processor (IFP) FIFO Sensor Core autonomously controls most aspects of operation. The processed image data is transmitted to the host system either through the parallel or MIPI interface. Figure 1 shows the major functional blocks of the MT9M114. Stats Engine Internal Register Bus POR ROM Microcontroller Two-wire Serial IF System Control Microcontroller Unit (MCU) Figure 1. MT9M114 Block Diagram www.onsemi.com 2 SRAM MIPI Parallel MT9M114 Sensor Core System Interfaces The MT9M114 has a color image sensor with a Bayer color filter arrangement and a 1.2 Mp active-pixel array with electronic rolling shutter (ERS). The sensor core readout is 10 bits and can be flipped and/or mirrored. The sensor core also supports separate analog and digital gain for all four color channels (R, Gr, Gb, B). Figure 2 shows typical MT9M114 device connections. For low-noise operation, the MT9M114 requires separate power supplies for analog and digital sections of the die. Both power supply rails must be decoupled from ground using capacitors as close as possible to the die. The use of inductance filters is not recommended on the power supplies or output signals. The MT9M114 provides dedicated signals for digital core, PHY, and I/O power domains that can be at different voltages. The PLL and analog circuitry require clean power sources. Table 3 provides the signal descriptions for the MT9M114. Image Flow Processor (IFP) The advanced IFP features and flexible programmability of the MT9M114 can enhance and optimize the image sensor performance. Built-in optimization algorithms enable the MT9M114 to operate with factory settings as a fully automatic and highly adaptable system-on-a-chip (SOC) for most camera systems. These algorithms include black level conditioning, shading correction, defect correction, color interpolation, edge detection, color correction, vertical perspective correction, aperture correction, and image formatting with cropping and scaling. Microcontroller Unit (MCU) The MCU communicates with all functional blocks by way of an internal ON Semiconductor proprietary bus interface. The MCU firmware configures all the registers in the sensor core and IFP. System Control The MT9M114 has a phase-locked loop (PLL) oscillator that can generate the internal sensor clock from a common wireless system clock. The PLL adjusts the incoming clock frequency up, allowing the MT9M114 to run at almost any desired resolution and frame rate within the sensor's capabilities. Low-power consumption is a very important requirement. The MT9M114 provides power-conserving features including a soft standby mode. A two-wire serial interface bus enables read and write access to the MT9M114's internal registers and variables. The internal registers control the sensor core, the color pipeline flow, and the output interface. Variables are located in the microcontroller's RAM memory and are used to configure and control the auto-algorithms and camera control functions. Output Interface The output interface block can select either raw data or processed data. Image data is provided to the host system either by an 8-bit parallel port or by a serial MIPI port. The parallel output port provides 8-bit RGB data or extended 10-bit Bayer data. The MT9M114 also includes programmable I/O slew rate to minimize EMI. www.onsemi.com 3 MT9M114 I/O Power5 VDD_IO RPULL-UP4 PHY Power2 PLL Power Digital Core Power Analog Power VDD_PHY VDD_PLL VDD VAA SADDR Two-wire Serial Interface Active LOW Reset DOUT[7:0] SDATA SCLK PIXCLK RESET_BAR Parallel Port LINE_VALID External Clock In (6-54 MHz) EXTCLK Active HIGH Default Settings CONFIG6 FRAME_VALID OR3 DATA_N DATA_P CLK_N CLK_P TRST_BAR8 OE_BAR9 DGND VDD_IO5,7 AGND GND_PLL VDD_PHY2,7 VDD_PLL7 MIPI Serial Port VDD7 VAA7 Notes: 1. This typical configuration shows only one scenario out of multiple possible variations for this sensor. 2. If a MIPI Interface is not required, the following signals must be left floating: DATA_P, DATA_N, CLK_P, and CLK_N. The VDD_PHY power signal must always be connected to the 1.8 V supply. 3. Only one of the output modes (serial or parallel) can be used at any time. 4. ON Semiconductor recommends a 1.5 kW resistor value for the two-wire serial interface RPULL-UP; however, greater values may be used for slower transmission speed. 5. All inputs must be configured with VDD_IO. 6. RESET_BAR and CONFIG both have internal pull-up resistors and can be left floating. 7. ON Semiconductor recommends that 0.1 mF and 1 mF decoupling capacitors for each power supply are mounted as close as possible to the pad. Actual values and numbers may vary depending on layout and design considerations. 8. TRST_BAR connects to GND for normal operation. 9. OE_BAR should be connected HIGH when using MIPI interface. Figure 2. Typical Configuration www.onsemi.com 4 MT9M114 Table 3. PIN DESCRIPTIONS 1. 2. 3. 4. Name Type EXTCLK Input RESET_BAR Input/PU OE_BAR Input Parallel interface enable pad, active LOW SCLK Input Two-wire serial interface clock SDATA I/O Two-wire serial interface data Description Input clock signal Master reset signal, active LOW. This signal has an internal pull up SADDR Input FRAME_VALID (FV) Output Selects device address for the two-wire serial interface Identifies rows in the active image. Data can be sampled with PIXCLK when both LV and FV are high (except when BT656 is used) LINE_VALID (LV) Output Identifies pixels in the active line. Data can be sampled with PIXCLK when both LV and FV are high (except when BT656 is used) PIXCLK Output Pixel clock DOUT[7:0] Output DOUT[7:0] for 8-bit image data output or DOUT[9:2] for 10-bit image data output DOUT_LSB[1:0] Output LSBs when outputting 10-bit image data CLK_N (Note 2) Output Differential MIPI clock (sub-LVDS, negative) CLK_P (Note 2) Output Differential MIPI clock (sub-LVDS, positive) DATA_N (Note 2) Output Differential MIPI data (sub-LVDS, negative DATA_P (Note 2) Output Differential MIPI data (sub-LVDS, positive) CONFIG (Note 4) Input/PU FLASH (Note 2) Output CHAIN (Note 2) Output/PU TRST_BAR Input If on power-up CONFIG = 1 then the part shall go into streaming (default option, PU ensures this will occur). If CONFIG = 0 then the part will go to standby state waiting for host to update Used as a flash signal To synchronize a number of sensors together Must be tied to GND in normal operation VDD Supply Digital power DGND (Note 1) Supply Digital ground VDD_IO Supply I/O power supply GND_IO Supply I/O ground VAA Supply Analog power AGND (Note 1) Supply Analog ground VDD_PLL Supply PLL supply GND_PLL Supply PLL GND VDD_PHY (Note 3) Supply I/O power supply for the MIPI interface AGND and DGND are not connected internally. To be left floating if not using feature. If not using the feature, then there is no need to bond out the relevant pads. Must always be connected even when not using MIPI. When CONFIG = 1 the EXTCLK must be in the range 20-24 MHz. www.onsemi.com 5 MT9M114 DECOUPLING CAPACITOR RECOMMENDATIONS It is important to provide clean, well regulated power to each power supply. The ON Semiconductor recommendation for capacitor placement and values are based on our internal demo camera design and verified in hardware. Note: Because hardware design is influenced by many factors, such as layout, operating conditions, and component selection, the customer is ultimately responsible to ensure that clean power is provided for their own designs. In order of preference, ON Semiconductor recommends: 1. Mount 0.1 mF and 1 mF decoupling capacitors for each power supply as close as possible to the pad and place a 10 mF capacitor nearby off-module. 2. If module limitations allow for only six decoupling capacitors for a three-regulator design use a 0.1 mF and 1 mF capacitor for each of the three regulated supplies. ON Semiconductor also recommends placing a 10 mF capacitor for each supply off-module, but close to each supply. 3. If module limitations allow for only three decoupling capacitors, use a 1 mF capacitor (preferred) or a 0.1 mF capacitor for each of the three regulated supplies. ON Semiconductor recommends placing a 10 mF capacitor for each supply off-module but close to each supply. 4. Give priority to the VAA supply for additional decoupling capacitors. 5. Inductive filtering components are not recommended. 6. Follow best practices when performing physical layout. Refer to application note AND9503/D. Output Data Format The MT9M114 image data is read out in a progressive scan. Valid image data is surrounded by horizontal blanking and vertical blanking, as shown in Figure 3. LINE_VALID is HIGH in the shaded region of the figure. P0,1 P0,2 ... P0,n-1 P0,n 00 00 00 ... 00 00 00 P1,0 P1,1 P1,2 ... P1,n-1 P1,n 00 00 00 ... 00 00 00 ... P0,0 Valid Image Pm-1,0 Pm,0 Pm-1,1 Pm,1 Pm-1,2 Pm,2 ... ... Horizontal Blanking Pm-1,n-1 Pm,n-1 Pm-1,n 00 00 00 ... 00 00 00 Pm,n 00 00 00 ... 00 00 00 00 00 00 00 00 00 ... 00 00 00 00 00 00 ... 00 00 00 00 00 00 ... 00 00 00 ... 00 00 00 ... Vertical/Horizontal Blanking Vertical Blanking 00 00 00 ... 00 00 00 00 00 00 ... 00 00 00 00 00 00 ... 00 00 00 00 00 00 ... 00 00 00 Figure 3. Spatial Illustration of Image Readout www.onsemi.com 6 MT9M114 POWER-UP AND POWER-DOWN SEQUENCE Powering up and powering down the sensor requires voltages to be applied in a particular order, as seen in Figure 4. The timing requirements are shown in Table 4. The sensor includes a power-on reset feature that initiates a reset upon power up of the sensor VDD_IO t1 t7 VDD, VDD_PHY VAA, VDD_PLL t6 t2 EXTCLK t5 t3 SCLK t4 SDATA Figure 4. Power-Up and Power-Down Sequence Table 4. POWER-UP AND DOWER-DOWN SIGNAL TIMING Symbol Parameter Min Typ Max Unit t1 Delay from VDD_IO to VDD and VDD_PHY 0 - 50 ms t2 Delay from VDD_IO to VAA and VDD_PLL 0 - 50 ms t3 EXTCLK Activation t2 - - ms t4 First Serial Command (Notes 1, 2) - 44.5 - ms t5 EXTCLK Cutoff t6 - - ms t6 Delay from VAA and VDD_PLL to VDD_IO 0 - 50 ms t7 Delay from VDD and VDD_PHY to VDD_IO 0 - 50 ms 1. Under the condition of EXTCLK = 24 MHz and default settings with CONFIG = 1. 2. The host should poll the Command register to determine when the device is initialized. www.onsemi.com 7 MT9M114 Reset The MT9M114 has 3 types of reset available: * A hard reset is issued by toggling the RESET_BAR signal; * A soft reset is issued by writing commands through the two-wire serial interface; * An internal power-on reset. The output states during hard reset are shown in Table 5. Table 5. STATUS OF OUTPUT SIGNALS DURING HARD RESET, SOFT STANDBY, AND POWER OFF Signal Reset Soft Standby (EXTCLK Running) Soft Standby (Without EXTCLK) Power Off DOUT[7:0] High-Z High-Z High-Z High-Z PIXCLK High-Z High-Z High-Z High-Z LV High-Z High-Z High-Z High-Z FV High-Z High-Z High-Z High-Z DOUT_LSB[1:0] High-Z High-Z High-Z High-Z DATA_N 0 0 0 High-Z DATA_P 0 0 0 High-Z CLK_N 0 0 0 High-Z CLK_P 0 0 0 High-Z SCLK Input Active Active (Pads are active, but due to no EXTCLK serial comms will not work) High-Z SDATA Input Active Active (Pads are active, but due to no EXTCLK serial comms will not work) High-Z A soft reset sequence to the sensor has the same effect as the hard reset and can be activated by writing to a register through the two-wire serial interface. On-chip power-on-reset circuitry can generate an internal reset signal in case an external reset is not provided. The RESET_BAR and CONFIG signals have internal pull-up resistors and can be left floating. www.onsemi.com 8 MT9M114 Hard Reset The MT9M114 enters the reset state when the external RESET_BAR signal is asserted LOW, as shown in Figure 5. All the output signals will be in High-Z state. When OE_BAR is in HIGH state, the outputs pins will be High-Z during the internal boot time t4 t1 t2 t3 EXTCLK RESET_BAR SDATA All Outputs Data Active Controlled by OE_BAR Data Active Mode Reset Internal Boot Time Entering Streaming Mode OE_BAR Figure 5. Hard Reset Operation Table 6. POWER-UP AND DOWER-DOWN SIGNAL TIMING Parameter Symbol Min Typ Max Unit EXTCLK cycles t1 RESET_BAR Pulse Width 50 - - t2 Active EXTCLK Required after RESET_BAR Asserted 10 - - t3 Active EXTCLK Required before RESET_BAR De-asserted 10 - - t4 Internal Boot Time (Notes 1, 2) - 44.5 - 1. Under the condition of EXTCLK = 24MHz and default settings with CONFIG = 1. 2. The host should poll the Command register to determine when the device is initialized. www.onsemi.com 9 ms MT9M114 Soft Reset The host processor can reset the MT9M114 using the two-wire serial interface by writing to SYSCTL 0x001A. SYSCTL 0x001A[0] is used to reset the MT9M114 which is similar to external RESET_BAR signal. 1. Set SYSCTL 0x001A[0] to 0x1 to initiate internal reset cycle. 2. Reset SYSCTL 0x001A[0] to 0x0 for normal operation. 3. Delay of 44.5 ms. t1 EXTCLK SCLK SDATA Mode Write Soft Reset Command Reseting Registers Enter Streaming Mode Figure 6. Soft Reset Operation Table 7. SOFT RESET SIGNAL TIMING Symbol t1 Parameter Soft Reset Time (Notes 1, 2) Min Typ Max Unit - 44.5 - ms 1. Under the condition of EXTCLK = 24 MHz and default settings with CONFIG = 1. 2. The host should poll the Command register to determine when the device is initialized. www.onsemi.com 10 MT9M114 Soft Standby Mode The MT9M114 can enter soft standby mode by receiving a host command through the two-wire serial interface. EXTCLK can be stopped to reduce the power consumption during soft standby mode. However, since two-wire serial interface requires EXTCLK to operate, ON Semiconductor recommends that EXTCLK run continuously. Entering Standby Mode 1. Send the sequence [Enter Standby] to put the MT9M114 into standby. 2. After the part is in standby for 100 EXTCLK cycles the EXTCLK can be turned off. [Enter Standby] FIELD_WR=SYSMGR_NEXT_STATE, 0x50 //(Optional) First check that the FW is ready to accept a new command ERROR_IF=COMMAND_REGISTER, HOST_COMMAND_1, !=0, "Set State cmd bit is already set" //(Mandatory) Issue the Set State command //We set the 'OK' bit so we can detect if the command fails //Note 0x8002 is equivalent to (HOST_COMMAND_OK | HOST_COMMAND_1) FIELD_WR=COMMAND_REGISTER, 0x8002 //Wait for the FW to complete the command (clear the HOST_COMMAND_1 bit) POLL_FIELD=COMMAND_REGISTER, HOST_COMMAND_1, !=0, DELAY=10, TIMEOUT=100 //Check the 'OK' bit to see if the command was successful ERROR_IF=COMMAND_REGISTER, HOST_COMMAND_OK, !=1, "Set State cmd failed", //Wait for the FW to fully-enter standby (SYSMGR_CURRENT_STATE=0x52) POLL_FIELD=SYSMGR_CURRENT_STATE,!=0x52,DELAY=50,TIMEOUT=10 Exiting Standby Mode 1. Turn EXTCLK on. 2. After 100 EXTCLK cycles send the following sequence entitled [Exit Standby] to bring the MT9M114 out of standby. [Exit Standby] FIELD_WR=SYSMGR_NEXT_STATE, 0x54 //(Optional) First check that the FW is ready to accept a new command ERROR_IF=COMMAND_REGISTER, HOST_COMMAND_1, !=0, "Set State cmd bit is already set" //(Mandatory) Issue the Set State command //We set the 'OK' bit so we can detect if the command fails //Note 0x8002 is equivalent to (HOST_COMMAND_OK | HOST_COMMAND_1) FIELD_WR=COMMAND_REGISTER, 0x8002 //Wait for the FW to complete the command (clear the HOST_COMMAND_1 bit) POLL_FIELD=COMMAND_REGISTER, HOST_COMMAND_1, !=0, DELAY=10, TIMEOUT=100 //Check the 'OK' bit to see if the command was successful ERROR_IF=COMMAND_REGISTER, HOST_COMMAND_OK, !=1, "Set State cmd failed", ERROR_IF=SYSMGR_CURRENT_STATE, !=0x31, "System state is not STREAMING" www.onsemi.com 11 MT9M114 IMAGE DATA OUTPUT INTERFACE The user can select either the 8-bit parallel or serial MIPI output to transmit the sensor image data to host system. Only one of the output modes can be used at any time. The MT9M114 has an output FIFO to retain a constant pixel output clock independent from the data output rate variations due to scaling factor. blanking and vertical blanking. The amount of horizontal blanking and vertical blanking are programmable. MT9M114 output data is synchronized with the PIXCLK output. When LV is HIGH, one pixel value is output on the 8-bit DOUT port every TWO PIXCLK periods as shown in Figure 7. PIXCLK is continuously running, even during the blanking period. (If the user wishes to have PIXCLK turned off during blanking this is possible through a variable setting) PIXCLK phase can be varied by 50 percent, controlled using a register. Parallel Port The MT9M114 image data is read out in a progressive scan mode. Valid image data is surrounded by horizontal LINE_VALID PIXCLK P0 (9:2) DOUT[7:0] P0 (1:0) P1 (9:2) P1 (1:0) Blanking P2 (9:2) Pn-1 (9:2) Pn-1 (1:0) Pn (9:2) Pn (1:0) Blanking Valid Data Figure 7. Pixel Data Timing Example FRAME_VALID LINE_VALID Data Modes P1 A2 Q3 AQ A P Notes: 1. P: Frame start and end blanking time. 2. A: Active data time. 3. Q: Horizontal blanking time. Figure 8. Row Timing, FV, and LV Signals Serial Port 1. After the PLL has locked and the bias generator for the MIPI drivers has stabilized, the MIPI interface transitions from the ULPS state to the ULPS-exit state (signaling code LP-10). 2. After a delay (TWAKEUP), the MIPI interface transitions from the ULPS-exit state to the TX-stop state (signaling code LP-11). 3. After a short period of time (the programmed integration time plus a fixed overhead), frames of pixel data start to be transmitted on the MIPI interface. Each frame of pixel data is transmitted as a number of high-speed packets. The transition from the TX-stop state to the high-speed signaling states occurs in accordance with the MIPI This section describes how frames of pixel data are represented on the high-speed MIPI serial interface. The MIPI output transmitter implements a serial differential sub-LVDS transmitter capable of up to 768 Mb/s. It supports multiple formats, error checking, and custom short packets. MT9M114 is designed to MIPI D-PHY version v1.0. When the sensor is in the software standby system state, the MIPI signals (CLK_P, CLK_N, DATA_P, DATA_N) indicate ultra low-power state (ULPS) corresponding to (nominal) 0 V levels being driven on CLK_P, CLK_N, DATA_P, and DATA_N. This is equivalent to signaling code LP-00. When the sensor enters the streaming system state, the interface goes through the following transitions: www.onsemi.com 12 MT9M114 rows of the array, resetting and then reading each row in turn. In the time interval between resetting a row and reading that row, the pixels in the row integrate incident light. The exposure is controlled by varying the time interval between reset and readout. Once a row has been selected, the data from each column is sequenced through an analog signal chain, including offset correction, gain adjustment, and ADC. The final stage of sensor core converts the output of the ADC into 10-bit data for each pixel in the array. The pixel array contains optically active and light-shielded (dark) pixels. The dark pixels are used to provide data for the offset-correction algorithms (black level control). The sensor core contains a set of control and status registers that can be used to control many aspects of the sensor behavior including the frame size, exposure, and gain setting. These registers are controlled by the MCU firmware and are also accessible by the host processor through the two-wire serial interface. The output from the sensor core is a Bayer pattern; alternate rows are a sequence of either green and red pixels or blue and green pixels. The offset and gain stages of the analog signal chain provide per-color control of the pixel data. specifications. Between high-speed packets and between frames, the MIPI interface idles in the TX-stop state. The transition from the high-speed signaling states and the TX-stop state takes place in accordance with the MIPI specifications. 4. If the sensor is reset, any frame in progress is aborted immediately and the MIPI signals switch to indicate the ULPS. 5. If the sensor is taken out of the streaming system state and reset_register[4] = 1 (standby end-of-frame), any frame in progress is completed and the MIPI signals switch to indicate the ULPS. If the sensor is taken out of the streaming system state and reset_register[4] = 0 (standby end-of-frame), any frame in progress is aborted as follows: 1. Any long packet in transmission is completed. 2. The end of frame short packet is transmitted. After the frame has been aborted, the MIPI signals switch to indicate the ULPS. Sensor Control The sensor core of the MT9M114 is a progressive-scan sensor that generates a stream of pixel data at a constant frame rate. Figure 9 shows a block diagram of the sensor core. The timing and control circuitry sequences through the Control Registers System Control Timing and Control VGA Active-Pixel Sensor (APS) Array Green 1/Green2 Channel Analog Processing G1/G2 R/B ADC Red/Blue Channel Sensor Core Figure 9. Sensor Core Block Diagram www.onsemi.com 13 G1/G2 R/B Digital Processing 10-bit Data Out MT9M114 The sensor core uses a Bayer color pattern, as shown in Figure 10. The even-numbered rows contain green and red pixels; odd-numbered rows contain blue and green pixels. Even-numbered columns contain green and blue pixels; odd-numbered columns contain red and green pixels. Row Readout Direction B Gb B Gb B Gr R Gr R Gr B Gb B Gb B Gr R Gr R Gr First Active Pixel (Column 8, Row 2) Black and Empty Pixels Figure 10. Pixel Color Pattern Detail (Bottom Left Corner) For the MT9M114 the first active pixel is defined as the first pixel that would be used as part of the demosaic border. When the sensor is operating in a system, the active surface of the sensor faces the scene as shown in Figure 11. When the image is read out of the sensor, it is read one row at a time, with the rows and columns sequenced. Lens Scene Sensor (Rear View) Row Readout Order Column Readout Order Pixel (0,0) Figure 11. Imaging a Scene When the sensor is configured to mirror the image horizontally, the order of pixel readout within a row is reversed, so that readout starts from the last column address and ends at the first column address. Figure 12 shows a sequence of 3 pixels being read out with normal readout and reverse readout. This change in sensor core output is corrected by the IFP. The sensor core supports different readout options to modify the image before it is sent to the IFP. The readout can be limited to a specific window size of the original pixel array. By changing the readout directions, the image can be flipped in the vertical direction and/or mirrored in the horizontal direction. The image output size is set by programming row and column start and end address variables. www.onsemi.com 14 MT9M114 LINE_VALID Normal Readout DOUT[7:0] G0 (9:2) G0 (1:0) R0 (9:2) R0 (1:0) G1 (9:2) G1 (1:0) G1 (1:0) G1 (9:2) R0 (1:0) R0 (9:2) G0 (1:0) G0 (9:2) Reverse Readout DOUT[7:0] Figure 12. Three Pixels in Normal and Column Mirror Readout Mode When the sensor is configured to flip the image vertically, the order in which pixel rows are read out is reversed, so that row readout starts from the last row address and ends at the first row address. Figure 13 shows a sequence of 3 rows being read out with normal readout and reverse readout. This change in sensor core output is corrected by the IFP. FRAME_VALID Normal Readout DOUT[7:0] Row0 (9:2) Row0 (1:0) Row1 (9:2) Row1 (1:0) Row2 (9:2) Row2 (1:0) Row2 (1:0) Row2 (9:2) Row1 (1:0) Row1 (9:2) Row0 (1:0) Row0 (9:2) Reverse Readout DOUT[7:0] Figure 13. Three Rows in Normal and Row Mirror Readout Mode The MT9M114 sensor core supports subsampling with skipping to increase the frame rate. The proper image output size and cropped size must be programmed before enabling subsampling mode. Figure 14 shows the readout with 2X skipping. LINE_VALID Normal Readout DOUT[7:0] G0 (9:2) G0 (1:0) R0 (9:2) R0 (1:0) G1 (9:2) G1 (1:0) R1 (9:2) R1 (1:0) G0 (9:2) G0 (1:0) R0 (9:2) R0 (1:0) G2 (9:2) G2 (1:0) R2 (9:2) R2 (1:0) G2 (9:2) G2 (1:0) R2 (9:2) R2 (1:0) G3 (9:2) LINE_VALID Column Skip Readout DOUT[7:0] Figure 14. Eight Pixels in Normal and Column Skip 2X Readout Modes www.onsemi.com 15 G3 (1:0) R3 (9:2) R3 (1:0) MT9M114 Pixel Readouts The following diagrams show a sequence of data being read out with no skipping. The effect of the different subsampling on the pixel array readout is shown in Figure 15 through Figure 20. Y Incrementing X Incrementing Figure 15. Pixel Readout (No Skipping) Y Incrementing X Incrementing Figure 16. Pixel Readout (Column Skipping) www.onsemi.com 16 MT9M114 Y Incrementing X Incrementing Figure 17. Pixel Readout (Row Skipping) Y Incrementing X Incrementing Figure 18. Pixel Readout (Column and Row Skipping) www.onsemi.com 17 MT9M114 Binning and Summing The MT9M114 sensor core supports binning and summing. Binning has many of the same characteristics as subsampling but it gathers image data from all pixels in the active window (rather than a subset of them). Pixel binning will sample pixels and average the value together in the analog domain. Summing will add the charge Binning (x-Binnig, y-Summing) Summing (x/y-Summing) Avg Se Sv Se Se Avg Figure 19. Pixel Binning and Summing X Incrementing Figure 20. Pixel Readout (Column and Row Binning) www.onsemi.com 18 Se Sv Y Incrementing 2 x 2 Binning and Summing or voltage values of the neighboring pixels together. (Se means "charge summing", Sv means "voltage summing", and avg means "digital averaging (post ADC). The advantage of using summing is that the pixel data is added together and up to 4X increase in responsivity is achieved. MT9M114 IMAGE FLOW PROCESSOR Image control processing in the MT9M114 is implemented in the IFP hardware logic. For normal operation, the microcontroller automatically adjusts the operational parameters of the IFP. Figure 21 shows the image data processing flow within the IFP. RAW10 1.2 Mp Pixel Array ADC Raw Bayer 10 IFP Color Bar Test Pattern Generator MUX Raw Bayer 10 (8+2 Output Format) Digital Gain Control, Adaptive Shading Correction Default Correction, Noise Reduction, Color Interpolation Statistics Engine 8-Bit RGB RGB to YUV 10/12-Bit RGB 8-Bit YUV Color Correction Color Kill Scaler/ Perspective Correction Aperture Correction Hue Rotate Output Formatting YUV to RGB Gamma Correction (10-to-8 Lookup) Output Interface TX FIFO MIPI MIPI Output Parallel Output Mux Parallel Output Figure 21. Image Flow Processor www.onsemi.com 19 MT9M114 Color bar test pattern generation can be selected by programming variables. To select enter test pattern mode R0xC84C = 0x02; to exit this mode R0xC84C must be set to 0x00. A Change-Config command needs to be issued when switching to CAM mode to enable test pattern as well as when exiting. For normal operation of the MT9M114, streams of raw image data from the sensor core are continuously fed into the color pipeline. The MT9M114 features an automatic color bar test pattern generation function to emulate sensor images as shown in Table 8. The color bar test pattern is fed to the IFP for testing the image pipeline without sensor operation. Table 8. COLOR BAR TEST PATTERN Test Pattern Flat Field Registers/Variables R0xC84C = 0x02 R0xC84D = 0x01 R0xC84E = 0x01FF R0xC850 = 0x01FF R0xC852 = 0x01FF Load = Change-Config Changing the values in 0x4E-0x52 will change the color of the test pattern. 100% Color Bar R0xC84C = 0x02 R0xC84D = 0x04 Load = Change-Config Pseudo-Random R0xC84C = 0x02 R0xC84D = 0x05 Load = Change-Config Fade-to-Gray R0xC84C = 0x02 R0xC84D = 0x08 Load = Change-Config Walking Ones 10-bit R0xC84C = 0x02 R0xC84D = 0x0A Load = Change-Config Walking Ones 8-bit R0xC84C = 0x02 R0xC84D = 0x0B Load = Change-Config www.onsemi.com 20 Example MT9M114 Digital Gain Traditionally this would have been based off two sets of CCM, one for Warm light like Tungsten and the other for Daylight (the part would interpolate between the two matrixes). This is not an optimal solution for cameras used in a Cool White Fluorescent (CWF) environment, for example when using a webcam. A better solution is to provide three CCMs, which would include a matrix for CWF (interpolation now between three matrixes). The MT9M114 offers this feature which will give the user improved color fidelity when under CWF type lighting. Color correction should ideally produce output colors that are independent of the spectral sensitivity and color crosstalk characteristics of the image sensor. The optimal values of the color correction matrix elements depend on those sensor characteristics and on the spectrum of light incident on the sensor. The color correction settings can be adjusted using variables. To increase image sharpness, a programmable 2D aperture correction (sharpening filter) is applied. The gain and threshold for 2D correction can be defined through variable settings. Image stream processing starts with multiplication of all pixel values by a programmable digital gain. Independent color channel digital gain can be adjusted with registers. Adaptive PGA (APGA) Lenses tend to produce images whose brightness is significantly attenuated near the edges. There are also other factors causing fixed pattern signal gradients in images captured by image sensors. The cumulative result of all these factors is known as image shading. The MT9M114 has an embedded shading correction module that can be programmed to counter the shading effects on each individual R, Gb, Gr, and B color signal. In some cases, different illuminants can introduce different color shading response. The APGA feature on the MT9M114 will compensate for the dependency of the lens shading of the illuminant. The MT9M114 will allow for up to three different illuminants to be compensated. Color Interpolation and Edge Detection In the raw data stream fed by the sensor core to the IFP, each pixel is represented by a 10-bit integer, which can be considered proportional to the pixel's response to a one-color light stimulus, red, green, or blue, depending on the pixel's position under the color filter array. Initial data processing steps, up to and including the defect correction, preserve the one-color-per-pixel nature of the data stream, but after the defect correction it must be converted to a three-colors-per-pixel stream appropriate for standard color processing. The conversion is done by an edge-sensitive color interpolation module. The module adds the incomplete color information available for each pixel with information extracted from an appropriate set of neighboring pixels. The algorithm used to select this set and extract the information seeks the best compromise between preserving edges and filtering out high-frequency noise in flat field areas. The edge threshold can be set through variable settings. Gamma Correction The gamma correction curve (as shown in Figure 22) is implemented as a piecewise linear function with 19 knee points, taking 12-bit arguments and mapping them to 8-bit output. The abscissas of the knee points are fixed at 0, 64, 128, 256, 512, 768, 1024, 1280, 1536, 1792, 2048, 2304, 2560, 2816, 3072, 3328, 3584, 3840, and 4096. The 8-bit ordinates are programmable through variables. The MT9M114 IFP includes a block for gamma correction that has the capability to adjust its shape, based on brightness, to enhance the performance under certain lighting conditions. Two custom gamma correction tables may be uploaded, one corresponding to a contrast curve for brighter lighting conditions, the other one corresponding to a noise reduction curve for lower lighting conditions. Also included in this block is a Fade-to-Black curve which sets all knee points to zero and causes the image to go black in extreme low light conditions. The MT9M114 has the ability to calculate the 19 point knee points based on a small number of variable inputs from the host, another option is for the host to program one or both of the 19 knee points. The diagram below shows how the gamma feature interacts in MT9M114. Color Correction and Aperture Correction To achieve good color fidelity of the IFP output, interpolated RGB values of all pixels are subjected to color correction. The IFP multiplies each vector of three pixel colors by a 3 x 3 color correction matrix. The three components of the resulting color vector are all sums of three 10-bit numbers. Since such sums can have up to 12 significant bits, the bit width of the image data stream is widened to 12 bits per color (36 bits per pixel). The color correction matrix can either be programmed by the user or automatically selected by the AWB algorithm implemented in the IFP. www.onsemi.com 21 MT9M114 cam_ll_stop_contrast_gradient cam_ll_start_contrast_luma_percentage cam_ll_start_contrast_gradient cam_ll_stop_contrast_luma_percentage cam_ll_gamma cam_ll_mode[1:0] MT9M114 calculates 19 Knee Point Calculation Contrast Enhancement Noise Reduction ll_gamma_select Gamma Curve Selection Contrast Enhancement Noise Reduction ll_enable_fade_to_black Fade-to-Black Selection Final Gamma Curve Figure 22. Gamma Interaction Gamma Knee Point Calculation The MT9M114 allows for the 19 knee point curves to be programmed based off a small number of variables. The table below shows the variables which are required. Table 9. VARIABLES REQUIRED FOR GAMMA KNEE POINT CALCULATION Variable Name VAR(0x12,0x0124) or (R0xC924) cam_ll_llmode VAR(0x12,0x013C) or (R0xC93C) cam_ll_start_contrast_bm Interpolation start point for first curve VAR(0x12,0x013E) or (R0xC93E) cam_ll_stop_contrast_bm Interpolation stop point for second curve VAR(0x12,0x0140) or (R0xC940) cam_ll_gamma The value of the gamma curve, this is applied to both 19 knee point curves. The default is 220, this equates to a gamma of 2.2 VAR(0x12,0x0142) or (R0xC942) cam_ll_start_contrast_gradient The value of the contrast gradient which would be used for the first curve VAR(0x12,0x0143) or (R0xC943) cam_ll_stop_contrast_gradient The value of the contrast gradient which would be used for the second curve VAR(0x12,0x0144) or (R0xC944) cam_ll_start_contrast_luma_percentage The percentage of target luma for the inflexion point in the first curve VAR(0x12,0x0145) or (R0xC945) cam_ll_start_contrast_luma_percentage The percentage of target luma for the inflexion point second curve VAR(0x12,0x0156) or (R0xC956) cam_ll_inv_brightness_metric Function 0x00: User will program 19 knee point gamma curves 0x01: MT9M114 will calculate 19 knee point for contrast curve (first curve or table) 0x02: MT9M114 will calculate 19 knee point for noise reduction curve (second curve or table) 0x03: MT9M114 will calculate both 19 knee point curves. Measure of scene brightness, reference points for cam_ll_start_contrast_bm and cam_ll_stop_contrast_bm www.onsemi.com 22 MT9M114 The concept of how the variables cam_ll_XX_contrast_ gradient and cam_ll_XX_contrast_luma_percentage interact to produce a curve is shown below. 256 Contrast_gradient Target_luma 80% Target Luma Inflexion Point Figure 23. Automatic Gamma Curve Figure 24 shows the interaction of the variables and cam_ll_inv_brightness_metric. cam_ll_start_contrast_ luma_percentage = 80 cam_ll_start_contrast_gradient = 50 cam_ll_stop_contrast_gradient = 38 cam_ll_stop_contrast_ luma_percentage = 25 Bright Light cam_ll_inv_brightness_metric cam_ll_start_contrast_bm = 230 Low Light cam_ll_stop_contrast_bm = 1178 Figure 24. Gamma Reference Variables against Brightness Metric ON Semiconductor would recommend that cam_ll_start_ contrast_bm is set at 100 lux and cam_ll_stop_contrast_bm is set at 20 lux, but due to the flexibility of the MT9M114 it is at the discretion of the user. ON Semiconductor recommends setting cam_ll_mode = 0x03 as this will allow the MT9M114 to calculate both of the 19 knee point curves based on the user inputs, otherwise the user will have to program both of the 19-knee-point curves. www.onsemi.com 23 MT9M114 Gamma Curve Selection The MT9M114 allows the user to select between the two-curve interpolation or either of the curves Table 10. GAMMA CURVE SELECTION Variable Name VAR(0x0F,0x0007) or (R0xBC07) ll_gamma_select Function 0x00: Auto curve select. The curves will interpolate based on settings of cam_ll_start_contrast_bm and cam_ll_stop_contrast_bm 0x01: Contrast curve is only used 0x02: Noise reduction curve is only used Fade to Black Selection The final stage of the gamma flow is the enabling and use of Fade-to-Black. The MT9M114 IFP allows for the image to fade to black under extreme low-light conditions. This feature enables users to optimize the performance of the sensor under low-light conditions. It minimizes the perception of noise and artifacts while the available illumination is diminishing. This feature has two user-set points that reference the brightness of the scene. When the Fade-to-Black starts, it will interpolate to the end point as the light falls until it gets to the end point. When at the end point, the image will be black. Table 11. FADE-TO-BLACK SELECTION Variable Name VAR(0x0F,0x0007) or (R0xBC07) ll_mode VAR(0x12,0x014A) or (R0xC94A) cam_ll_start_fade_to_black_luma Starting point for Fade-to-Black to begin VAR(0x12,0x014C) or (R0xC94C) cam_ll_stop_fade_to_black_luma End point for Fade-to-Black, after this point the image will be black VAR(0x0F,0x003A) or (R0xBC3A) ll_average_luma_fade_to_black Function When bit 3 = 1, this will enable the Fade-to-Black feature Measure of scene brightness, reference points for cam_ll_start_fade_to_black_luma and cam_ll_stop_fade_to_black_luma By configuring the cropped and output windows to various sizes, different zooming levels for 4x, 2x, and 1x can be achieved. The location of the cropped window is configurable so that panning is also supported. The height and width definitions for the output window must be equal to or smaller than the cropped image. The image cropping and scaler module can be used together to implement a digital zoom and pan. ON Semiconductor would recommend that cam_ll_start_fade_to_black_luma is set at 3 lux and cam_ll_stop_fade_to_black_luma is set at 1 lux, but due to the flexibility of the MT9M114 it is at the discretion of the user. Image Scaling and Cropping To ensure that the size of images output by the MT9M114 can be tailored to the needs of all users, the IFP includes a scaler module. When enabled, this module performs rescaling of incoming images - shrinks them to the selected width (the output widths should be in multiples of 4) and height without reducing the field of view and without discarding any pixel values. Hue Rotate The MT9M114 has integrated hue rotate. This feature will help for improving the color image quality and give customers the flexibility for fine color adjustment and special color effects. Table 12. HUE CONTROL Variable Name VAR(0x12,0x73) or R0xC873 Hue Angle Function Adjusts the global hue angle adjustment: 0xEA = -22 0x00 = 0 0x16 = +22 www.onsemi.com 24 MT9M114 Vertical Perspective Correction The MT9M114 has vertical perspective correction (VPC) also known as the Tilt Connection; this allows the user to correct (within limits) for an off-horizontal axis camera. Original Image VPC Corrected Image Figure 25. Vertical Perspective Correction VPC is performed using a mixture of scale and crop, the variables that control this are: Table 13. VERTICAL PERSPECTIVE CORRECTION Variable Name Function VAR(0x12,0x005E) or (R0xC85E) cam_scale_vertical_tc_mode When set, the vertical stretching factor is applied to the center of the image, so top/bottom lines are cropped. When clear, the crop occurs in the top or bottom of the scene dependent on the percentage value (cam_scale_vertical_tc_percentage). VAR(0x12,0x0060) or (R0xC860) cam_scale_vertical_tc_percentage The amount of tilt (perspective) correction to be applied. If negative, this value represents % of FOV reduction with the bottom line unaffected. If positive, this value represents % of FOV reduction with the top line unaffected. VAR(0x12,0x0062) or (R0xC862) cam_scale_vertical_tc_stretch_factor Ratio of vertical stretching against the percentage applied. Vertical stretching = stretch factor x percentage/2. The effect of using cam_scale_vertical_tc_percentage can be seen below. Case1: CAM_SCALE_VERTICAL_TC_PERCENTAGE = 10% Uncorrected image Corrected vertical plane 90% w Vertical plane is tilted-away from the camera - therefore the bottom row of image represents the nearest point. The nearest point appears bigger in the uncorrected image, therefore top/bottom ratio will be greater than 1.0. w Case2: CAM_SCALE_VERTICAL_TC_PERCENTAGE = -10% w image Corrected vertical plane Uncorrected Vertical plane is tilted-towards the camera - therefore the top row of image represents the nearest point. The nearest point appears bigger in the uncorrected image, therefore the top/ bottom ratio with be less than 1.0 90% w Figure 26. The Effect of Using CAM_SCALE_VERTICAL_TC_PERCENTAGE www.onsemi.com 25 MT9M114 Cam_scale_vertical_tc_percentage defines how much tilt needs to be corrected for in percentage terms. The effect of using cam_scale_vertical_tc_mode can be seen below. Original Scene Tilted MODE_STRETCH_FROM_CENTRE_EN = 0 MODE_STRETCH_FROM_CENTRE_EN = 1 Figure 27. The Effect of Using CAM_SCALE_VERTICAL_TC_MODE CAMERA CONTROL AND AUTO FUNCTIONS Auto Exposure The auto exposure algorithm performs automatic adjustments of the image brightness by controlling exposure time and analog gains of the sensor core as well as digital gains applied to the image. Auto exposure is implemented by a firmware driver that analyzes image statistics collected by the exposure measurement engine, makes a decision, and programs the sensor core and color pipeline to achieve the desired exposure. The measurement engine subdivides the image into 25 windows organized as a 5 x 5 grid. Four auto exposure algorithm modes are available: * Average brightness tracking (ABT) or Average Y (ae_rule_algo VAR = 9, 0x0004, 0x0000 or W 0,0 W 0,1 W 0,2 W 0,3 W 0,4 W 1,0 W 1,1 W 1,2 W 1,3 W 1,4 W 2,0 W 2,1 W 2,2 W 2,3 W 2,4 W 3,0 W 3,1 W 3,2 W 3,3 W 3,4 W 4,0 W 4,1 W 4,2 W 4,3 W 4,4 * REG = 0xA404, 0x0000) The average brightness tracking AE uses a constant average tracking algorithm where a target brightness value is compared to a current brightness value, and the gain and integration time are adjusted accordingly to meet the target requirement. Weighted Average Brightness (ae_rule_algo VAR = 9, 0x0004, 0x0001 or REG = 0xA404, 0x0001) Each of the 25 windows can be assigned a weight relative to other window weights, which can be changed independently of each other. For example, the weights can be set to allow the center of the image to be weighted higher than the periphery. See Figure 28. Figure 28. 5 y 5 Grid www.onsemi.com 26 MT9M114 * Adaptive Weighted AE for highlights (ae_rule_algo * Adaptive Weighted AE for lowlights (ae_rule_algo VAR = 9, 0x0004, 0x0003 or REG = 0xA404, 0x0003) The scene will be exposed based on the brightness of each window, and will adapt to correctly expose the lowlights. This would correctly expose the foreground of an image when the background is brighter. VAR = 9, 0x0004, 0x0002 or REG = 0xA404, 0x0002) The scene will be exposed based on the brightness of each window, and will adapt to correctly expose the highlights (brighter windows). This would correctly expose the foreground of an image when the background is dark. Sample images below show the benefits of the different AE modes. Average Brightness Tracking or Average Y Weighted Average Brightness (Centre) Average Weighted Based on Zone Luma (Highlights) Adaptive Weighted Based on Zone Luma (Lowlights) NOTE: This mode is intended to expose the background vs. the Figure 29. Light Background In the use case above the Adaptive weighted for lowlights exposes the face slightly better when compared to the Weighted Average Brightness. However, if the foreground subject is moved off-center: Weighted Average Brightness (Centre) (Lowlights) Adaptive Weighted Based on Zone Luma Figure 30. www.onsemi.com 27 MT9M114 This shows the advantage of using the Adaptive Weighted AE for lowlights (ae_rule_algo = 0x03); when the face moves off center it still is exposed correctly. Average Brightness Tracking or Average Y Weighted Average Brightness (Centre) Average Weighted Based on Zone Luma (Highlights) Adaptive Weighted Based on Zone Luma (Lowlights) NOTE: This mode is correctly exposing the background of the image, hence you can see the shadows. Figure 31. Dark Background Auto White Balance In this use case the Adaptive Weighted AE for highlights will expose the face the best when compared to the other options. The MT9M114 has a built-in AWB algorithm designed to compensate for the effects of changing spectra of the scene illumination on the quality of the color rendition. The algorithm consists of two major parts: a measurement engine performing statistical analysis of the image and a driver performing the selection of the optimal color correction matrix and SOC digital gain. While default settings of these algorithms are adequate in most situations, the user can reprogram base color correction matrices, place limits on color channel gains, and control the speed of both matrix and gain adjustments. The MT9M114 AWB displays the current AWB position in color temperature, the range of which will be defined when programming the CCM matrixes. AE Track Driver Other algorithm features include the rejection of fast fluctuations in illumination (time averaging), control of speed of response, and control of the sensitivity to the small changes. While the default settings are adequate in most situations, the user can program target brightness, measurement window, and other parameters described above. The driver changes AE parameters (integration time, gains, and so on) to drive scene brightness to the programmable target. To avoid unwanted reaction of AE on small fluctuations of scene brightness or momentary scene changes, the AE track driver uses a temporal filter for luma and a threshold around the AE luma target. The driver changes AE parameters only if the filtered luma is larger than the AE target step and pushes the luma beyond the threshold. Flicker Avoidance Flicker occurs when the integration time is not an integer multiple of the period of the light intensity. The MT9M114 can be programmed to avoid flicker for 50 or 60 Hz. For integration times below the light intensity period (10 ms for www.onsemi.com 28 MT9M114 NOTE: 16 < Y601< 235; 16 < Cb < 240; 16 < Cr < 240; and 0 < = RGB < = 255. 50 Hz environment), flicker cannot be avoided. The MT9M114 supports an indoor AE mode, that will ensure flicker-free operation (VAR8 = 18, 0x0078[0] = 0x1 or REG = 0xC878[0] = 0x1). The MT9M114 will calculate all flicker parameters based on the sensor settings which are programmed in the Cam Control variables. This means the user only needs to select if 50- or 60-Hz flicker needs to be avoided (VAR 0x12, 0x008B or R0xC88B = 50 for 50-Hz flicker avoidance and 60 for 60-Hz avoidance). Y + (0.2126 R ) 0.7152 Cb + 0.5389 (B * Y) Cr + 0.635 (R * Y) Color Conversion Formulas Y'U'V': This conversion is BT 601 scaled to make YUV range from 0 through 255. This setting is recommended for JPEG encoding and is the most popular, although it is not well defined and often misused in various operating systems. B (B * Y) ) 128 (eq. 2) V + 0.713 (R * Y) ) 128 (eq. 3) (eq. 6) (224256) ) 128 R ) 0.7152 U + 0.5389 (B * Y) ) 128 + V + 0.635 + 0.5 G ) 0.0722 R * 0.3854 B (eq. 8) G ) 0.5 B ) 128 (R * Y) ) 128 + R * 0.4542 G * 0.0458 (eq. 7) (eq. 9) B ) 128 There is an option to disable adding 128 to U'V'. The reverse transform is as follows: (eq. 1) U + 0.564 (eq. 5) (224256) ) 128 Y + 0.2126 + * 0.1146 G ) 0.114 (eq. 4) Y'U'V' Using sRGB Formulas: These are similar to the previous set of formulas, but have YUV spanning a range of 0 through 255. The YUV data stream can either exit the color pipeline as is or be converted before exit to an alternative YUV or RGB data format. R ) 0.587 B) (219256) ) 16 Output Conversion and Formatting Y + 0.299 G ) 0.0722 R + Y ) 1.5748 (V * 128) G + Y * 0.1873 (U * 128) * 0.4681 B + Y ) 1.8556 (U * 128) (eq. 10) (V * 128) (eq. 11) (eq. 12) Uncompressed YUV/RGB Data Ordering The MT9M114 supports swapping YCbCr mode, as illustrated in Table 14. There is an option where 128 is not added to U'V'. Y'Cb'Cr' Using sRGB Formulas: The MT9M114 implements the sRGB standard. This option provides YCbCr coefficients for a correct 4:2:2 transmission. Table 14. YCbCr OUTPUT DATA ORDERING Mode Data Sequence Default (No Swap) Cbi Yi Cri Yi+1 Swapped CrCb Cri Yi Cbi Yi+1 Swapped YC Yi Cbi Yi+1 Cri Swapped CrCb, YC Yi Cri Yi+1 Cbi The RGB output data ordering in default mode is shown in Table 15. The odd and even bytes are swapped when luma/chroma swap is enabled. R and B channels are bitwise swapped when chroma swap is enabled. Table 15. RGB ORDERING IN DEFAULT MODE Mode (Swap Disabled) Byte D7 D6 D5 D4 D3 D2 D1 D0 565RGB Odd R7 R6 R5 R4 R3 G7 G6 G5 Even G4 G3 G2 B7 B6 B5 B4 B3 Odd 0 R7 R6 R5 R4 R3 G7 G6 555RGB 444xRGB x444RGB Even G4 G3 G2 B7 B6 B5 B4 B3 Odd R7 R6 R5 R4 G7 G6 G5 G4 Even B7 B6 B5 B4 0 0 0 0 Odd 0 0 0 0 R7 R6 R5 R4 Even G7 G6 G5 G4 B7 B6 B5 B4 www.onsemi.com 29 MT9M114 Uncompressed Raw Bayer Bypass Output Raw 10-bit Bayer data from the sensor core can be output in bypass mode by: 1. Using both DOUT[7:0] and DOUT_LSB[1:0]. 2. Using only DOUT[7:0] with a special 8 + 2 data format, shown in Table 16. 3. Using the MIPI interface. Table 16. 2-BYTE BAYER FORMAT 2-Byte Bayer Format Bits Used Bit Sequence Odd bytes 8 Data Bits D9 D8 D7 D6 D5 D4 D3 D2 Even bytes 2 Data Bits + 6 Unused Bits 0 0 0 0 0 0 D1 D0 www.onsemi.com 30 MT9M114 UVC INTERFACE The MT9M114 supports a set of UVC (USB Video Class) controls in order to simplify the integration of the MT9M114 with a host's USB bridge (or ISP) device. The MT9M114 firmware includes a `UVC Control' component that augments the CamControl variables. The UVC Control component sits above the CamControl interface (in terms of abstraction) and acts as a `virtual host'. The intention is that CamControl and all other components are unaware of the UVC Control component. UVC Control exposes a `UVC control' page of shared variables to the host. This page contains variables compliant with the UVC 1.1 specification (where possible). The variables on this page are named to match the UVC specification, and have matching data sizes, units and ranges as required. Each UVC variable is `virtual' - it does not control any MT9M114 function directly. MT9M114 therefore provides a `dual-personality' host interface: * The primary CamControl interface, this interface exposes the full feature-set of the device. * The secondary UVC Control interface, which simplifies integration of MT9M114 into a PC-Cam application. More details on this topic can be found in the Developer Guide. Table 17. SUMMARY OF UVC COMMANDS Variable Name R0xCC00 VAR(0x13,0x0000) UVC_AE_MODE_CONTROL R0xCC01 VAR(0x13,0x0001) UVC_WHITE_BALANCE_TEMPERATURE_AUTO_CONTROL R0xCC02 VAR(0x13,0x0002) UVC_AE_PRIORITY_CONTROL R0xCC03 VAR(0x13,0x0003) UVC_POWER_LINE_FREQUENCY_CONTROL R0xCC04 VAR(0x13,0x0004) UVC_EXPOSURE_TIME_ABSOLUTE_CONTROL R0xCC08 VAR(0x13,0x0008) UVC_BACKLIGHT_COMPENSATION_CONTROL R0xCC0A VAR(0x13,0x000A) UVC_BRIGHTNESS_CONTROL R0xCC0C VAR(0x13,0x000C) UVC_CONTRAST_CONTROL R0xCC0E VAR(0x13,0x000E) UVC_GAIN_CONTROL UINT16 R0xCC10 VAR(0x13,0x0010) UVC_HUE_CONTROL R0xCC12 VAR(0x13,0x0012) UVC_SATURATION_CONTROL UINT16 R0xCC14 VAR(0x13,0x0014) UVC_SHARPNESS_CONTROL R0xCC16 VAR(0x13,0x0016) UVC_GAMMA_CONTROL R0xCC18 VAR(0x13,0x0018) UVC_WHITE_BALANCE_TEMPERATURE_CONTROL R0xCC1C VAR(0x13,0x001C) UVC_FRAME_INTERVAL_CONTROL R0xCC20 VAR(0x13,0x0020) UVC_MANUAL_EXPOSURE_CONFIG R0xCC21 VAR(0x13,0x0021) UVC_FLICKER_AVOIDANCE_CONFIG www.onsemi.com 31 MT9M114 MULTI-CAMERA SYNC The MT9M114 supports more than one device to be connected in a "daisy-chain" type configuration. One of the devices will act as the master and the remainder will be slaves. A typical connection diagram is shown in Figure 32. All of the MT9M114 that are to communicate are: * Connected in a daisy-chain using SADDR as an input * * and CHAIN as an output Clocked from a common clock source Controlled from a single master, presumed to be under software control of a host system HOST SCLK SDATA MT9M114 EXTCLK SADDR CHAIN SCLK SDATA MT9M114 EXTCLK SADDR CHAIN GND Logic 1 MT9M114(1) (Master) Device = ID0 SCLK SDATA MT9M114 EXTCLK SADDR CHAIN Logic 1 SCLK SDATA MT9M114 EXTCLK SADDR CHAIN Logic 1 MT9M114(2) MT9M114(3) MT9M114(4) Device = ID1 Device = ID1 Device = ID1 Figure 32. Multi-Camera Connection SADDR is normally used as a static input that selects between two slave device addresses (See Figure 33. In order to implement the multi-sync function this input now has additional functionality that does not interfere with its use as device address selection. There is a single register to control this function, named CHAIN_CONTROL (R0x31FC). This register is controlled by the host. The register field assignment is shown in Table 18. R0x002E (USER_DEFINED_DEVICE_ADDRESS_IS) ID0 (Default: 0x90) ID1 (Default: 0xBA) Slave Device ID SADDR Figure 33. Normal Use of SADDR Table 18. CHAIN_CONTROL REGISTER Bit Name Default Description 15 chain_enable 0 0: multi-camera daisy-chain communication function is disabled 1: multi-camera daisy-chain communication function is enabled The result of toggling this bit while the sensor is streaming is UNDEFINED. 14 sync_enable 0 0: multi-sync function is disabled 1: multi-sync function is enabled The result of toggling this bit while the sensor is streaming is UNDEFINED. 13 master 0 0: this node is not the master 1: this node is the master The result of toggling this bit while the sensor is streaming is UNDEFINED. 12 RESERVED 11:8 position 0 A unique value assigned to each device in the daisy-chain. The device furthest from the master is assigned a position value of 0. The next device is assigned a position value of 1. For N devices in a daisy-chain, the master is assigned a position value of N-1. The result of toggling this bit while the sensor is streaming is UNDEFINED. 7:0 RESERVED www.onsemi.com 32 MT9M114 * When a slave device is placed in streaming mode Configuration Before the multi-sync function can be used, each MT9M114 in the daisy-chain must be configured. This process is performed by the host with no involvement from MT9M114 firmware. Configuration involves assigning a unique slave address to each MT9M114 and configuring the CHAIN_CONTROL register on each MT9M114. After reset (before configuration) the master MT9M114 has its SADDR input wired to `0' and all other MT9M114 in the daisy-chain have their SADDR inputs driven to `1'. Therefore, MT9M114 Master will respond to slave address ID0 (associated with SADDR = 0) and all the other MT9M114 in the daisy-chain will respond simultaneously to slave address ID1. Each MT9M114 has its CHAIN pin configured as an input. This situation is shown in Figure 32. The host configures each MT9M114 in sequence, starting with the master and ending with the farthest slave in the daisy-chain: * MT9M114(1) Master: The host uses slave address ID0 (associated with SADDR = 0) and therefore accesses registers on MT9M114(1) (the master). It writes to register (R0x002E) to change the slave addresses associated with ID0 and ID1 on this device to a single, new, unique value; call it ID-MT9M114(1). It then writes (using MT9M114(1) to register PAD_CONTROL (R0x0032) to configure CHAIN as an output. Finally, it writes (using MT9M114(1)) to the CHAIN_CONTROL register to set chain_enable = 1, sync_enable = 1, master = 1 and position = N-1 (where there are N devices in the daisy-chain). The effect of enabling TMS as an output is to drive the TMS output low. * MT9M114(2): This MT9M114 now has SADDR = 0 and so will respond to slave address ID0. The host configures this in the same way as MT9M114(1) with the exceptions that it assigns ID-MT9M114(2), sets master = 0 and position = N-2 (where there are N devices in the daisy-chain). As before, the effect of enabling CHAIN as an output is to drive the CHAIN output low. * MT9M114(3): As for MT9M114(2): assign ID-MT9M114(3), master = 0, position = N-3. * MT9M114(4): As for MT9M114(2): assign ID-MT9M114(4), master = 0, position = N-4. * (as the result of a mode change initiated by the host) it delays streaming until it has received an event on its SADDR input. Each slave in the daisy-chain propagates events received on its input. Each slave uses its local value of "position" to delay its respond to an event. This allows an event propagated down the daisy-chain to be acted upon simultaneously by all devices in the daisy-chain. Using Multi-Sync The host can use the normal mechanism to configure the MT9M114 and set them streaming. It can do this in any order provided that it sets the master streaming last. It is desirable (but not essential) for the master to be taken out of streaming mode first (by using a host command). At the time that the MT9M114 are placed in streaming mode, all MT9M114 must have the same integration time The recommended mechanism is: 1. Boot each device into standby by enabling `host-config' mode. 2. Reconfigure each device. 3. Wake each device and commence streaming using the Leave Standby command. The MT9M114 need not maintain the same integration time once they are streaming. All the MT9M114 must be operated with the same configuration (image size, output format, PLL bypassed and frame timing). Any time that the configuration is to be changed, all MT9M114 must be taken out of streaming mode (using host command), reconfigured, then placed back in streaming mode (master last). This will allow the output data to remain in synchronization. Clocking The multi-sync mechanism requires that all MT9M114 devices in the daisy-chain are operated synchronously on the same input clock. This constraint is imposed in order to allow the event codes to be propagated synchronously from the master through to each slave. Once this constraint has been met, the MT9M114 devices are required to operate in exact synchronization (such that a PIXCLK, FRAME_VALID and LINE_VALID out of one MT9M114 is valid for all MT9M114 in the daisy-chain). In this case, the MT9M114 internal PLL must be bypassed (and the MT9M114 must be using parallel output data). This feature can be used with the MIPI interface and PLL enabled, in that case the signals will be synchronized up to an accuracy of 2 PIXCLK cycles. Theory Of Operation When multiple MT9M114 devices have been connected and configured as described above, the multi-sync function operates as follows: * When the master device is placed in streaming mode (as the result of a mode change initiated by the host) it generates an event on its CHAIN output. It then delays its own streaming until the last of the slave devices has received an event signal. www.onsemi.com 33 MT9M114 HARDWARE FUNCTIONS Two-Wire Serial Interface Message Byte Message bytes are used for sending register addresses and register write data to the slave device and for retrieving register read data. The protocol used is outside the scope of the two-wire serial interface specification. The two-wire serial interface bus enables read and write access to control and status registers and variables within the MT9M114. The interface protocol uses a master/slave model in which a master controls one or more slave devices. The MT9M114 always operates in slave mode. The host (master) generates a clock (SCLK) that is an input to the MT9M114 and is used to synchronize transfers. Data is transferred between the master and the slave on a bidirectional signal (SDATA). The host should always ensure that the following relationship is adhered to. S CLK v Acknowledge Bit Each 8-bit data transfer is followed by an acknowledge bit or a no-acknowledge bit in the SCLK clock period following the data transfer. The transmitter (which is the master when writing, or the slave when reading) releases SDATA. The receiver indicates an acknowledge bit by driving SDATA LOW. As for data transfers, SDATA can change when SCLK is LOW and must be stable while SCLK is HIGH. PIXEL CLOCK 22 No-Acknowledge Bit The no-acknowledge bit is generated when the receiver does not drive SDATA low during the SCLK clock period following a data transfer. A no-acknowledge bit is used to terminate a read sequence. Protocol Data transfers on the two-wire serial interface bus are performed by a sequence of low-level protocol elements, as follows: 1. a (repeated) start condition 2. a slave address/data direction byte 3. a 16-bit register address (8-bit addresses are not supported) 4. an (a no) acknowledge bit 5. a 16-bit data transfer (8-bit data transfers are not supported) 6. a stop condition Stop Condition A stop condition is defined as a LOW-to-HIGH transition on SDATA while SCLK is HIGH. Typical Serial Transfer A typical read or write sequence begins by the master generating a start condition on the bus. After the start condition, the master sends the 8-bit slave address/data direction byte. The last bit indicates whether the request is for a read or a write, where a "0" indicates a write and a "1" indicates a read. If the address matches the address of the slave device, the slave device acknowledges receipt of the address by generating an acknowledge bit on the bus. If the request was a write, the master then transfers the 16-bit register address to which a write should take place. This transfer takes place as two 8-bit sequences and the slave sends an acknowledge bit after each sequence to indicate that the byte has been received. The master then transfers the data as an 8-bit sequence; the slave sends acknowledge bit at the end of the sequence. After 8 bits have been transferred, the slave's internal register address is automatically incremented, so that the next 8 bits are written to the next register address. The master stops writing by generating a (re)start or stop condition. If the request was a read, the master sends the 8-bit write slave address/data direction byte and 16-bit register address, just as in the write request. The master then generates a (re)start condition and the 8-bit read slave address/data direction byte, and clocks out the register data, 8 bits at a time. The master generates an acknowledge bit after each 8-bit transfer. The slave's internal register address is automatically incremented after every 8 bits are transferred. The data transfer is stopped when the master sends a no-acknowledge bit. The bus is idle when both SCLK and SDATA are HIGH. Control of the bus is initiated with a start condition, and the bus is released with a stop condition. Only the master can generate the start and stop conditions. A start condition is defined as a HIGH-to-LOW transition on SDATA while SCLK is HIGH. At the end of a transfer, the master can generate a start condition without previously generating a stop condition; this is known as a repeated start or restart condition. A stop condition is defined as a LOW-to-HIGH transition on SDATA while SCLK is HIGH. Data is transferred serially, 8 bits at a time, with the most significant bit (MSB) transmitted first. Each byte of data is followed by an acknowledge bit or a no-acknowledge bit. This data transfer mechanism is used for the slave address/data direction byte and for message bytes. One data bit is transferred during each SCLK clock period. SDATA can change when SCLK is LOW and must be stable while SCLK is HIGH. Slave Address Bits [7:1] of this byte represent the device slave address and bit [0] indicates the data transfer direction. A "0" in bit [0] indicates a WRITE, and a "1" indicates a READ. If the SADDR signal is driven LOW, then addresses used by the MT9M114 are R0x090 (write address) and R0x091 (read address). If the SADDR signal is driven HIGH, then addresses used by the MT9M114 are R0x0BA (write address) and R0x0BB (read address). www.onsemi.com 34 MT9M114 Single READ from Random Location NOTE: If a customer is using direct memory writes (XDMA), AND the first write ends on an odd address boundary AND the second write starts on an even address boundary AND the first write is not terminated by a STOP, the write data can become corrupted. To avoid this, ensure that a serial write is terminated by a STOP. This sequence (see Figure 34) starts with a dummy write to the 16-bit address that is to be used for the read. The master terminates the write by generating a restart condition. The master then sends the 8-bit read slave address/data direction byte and clocks out one byte of register data. The master terminates the read by generating a no-acknowledge bit followed by a stop condition. Figure 34 shows how the internal register address maintained by the MT9M114 is loaded and incremented as the sequence proceeds. Previous Reg Address, N S Slave Address 0 A S = Start Condition P = Stop Condition Sr = Restart Condition A = Acknowledge A = No-acknowledge Reg Address[15:8] Reg Address, M Reg Address[7:0] A A Sr Slave Address 1 A M+1 A Read Data P Slave to Master Master to Slave Figure 34. Single READ from Random Location Single READ from Current Location master terminates the read by generating a no-acknowledge bit followed by a stop condition. The figure shows two independent read sequences. This sequence (Figure 35) performs a read using the current value of the MT9M114 internal register address. The Previous Reg Address, N S Slave Address 1 A Read Data [15:8] Reg Address, N+1 A Read Data [7:0] A P S Slave Address N+2 Read Data [15:0] 1 A A P Figure 35. Single READ from Current Location Sequential READ, Start from Random Location This sequence (Figure 36) starts in the same way as the single read from random location (Figure 34). Instead of generating a no-acknowledge bit after the first byte of data has been transferred, the master generates an acknowledge bit, and continues to perform byte reads until L bytes have been read. Previous Reg Address, N S Slave Address 0 A Reg Address[15:8] M+1 Read Data A Reg Address[7:0] M+2 A Read Data Reg Address, M M+3 A Sr Slave Address M+L-2 A Read Data 1 A M+L-1 A Read Data Figure 36. Sequential READ, Start from Random Location www.onsemi.com 35 M+1 Read Data M+L A P A MT9M114 Sequential READ, Start from Current Location This sequence (Figure 37) starts in the same way as the single read from current location (Figure 35). Instead of generating a no-acknowledge bit after the first byte of data Previous Reg Address, N S Slave Address 1 A has been transferred, the master generates an acknowledge bit, and continues to perform byte reads until L bytes have been read. N+1 Read Data A N+2 Read Data A N+L-1 Read Data A N+L Read Data A P Figure 37. Sequential READ, Start from Current Location Single WRITE to Random Location This sequence (Figure 38) begins with the master generating a start condition. The slave address/data direction byte signals a write and is followed by the high then low bytes of the register address that is to be written. The master follows this with the byte of write data. The write is terminated by the master generating a stop condition. Previous Reg Address, N S Slave Address 0 A Reg Address[15:8] Reg Address, M A A Reg Address[7:0] M+1 A A Write Data P Figure 38. Single WRITE to Random Location Sequential WRITE, Start at Random Location has been transferred, the master generates an acknowledge bit, and continues to perform byte writes until L bytes have been written. The write is terminated by the master generating a stop condition. This sequence (Figure 39) starts in the same way as the single write to random location (Figure 38). Instead of generating a no-acknowledge bit after the first byte of data Previous Reg Address, N S Slave Address 0 A M+1 Write Data Reg Address[15:8] A M+2 A Write Data Reg Address, M Reg Address[7:0] M+3 A Write Data M+L-2 A Write Data www.onsemi.com 36 A M+L-1 A Figure 39. Sequential WRITE, Start at Random Location PATCH RAM MT9M114 has Patch Ram, this allows for issues to be fixed without changing silicon version and also allows for new features to be added to the silicon. The patch would come in the format of Load and Apply sections, the user needs to implement both sections. Below includes detail of what can be achieved when in different host states. STANDBY - LOAD PATCHES ONLY STREAMING - LOAD AND APPLY PATCHES SUSPEND - LOAD AND APPLY PATCHES M+1 Write Data M+L A A P MT9M114 CHIEF RAY ANGLE CRA vs. Image Height Plot CRA (deg) (mm) 0 0 0 5 0.076 2.51 30 10 0.152 4.98 28 15 0.228 7.44 26 20 0.304 9.89 24 25 0.380 12.32 22 30 0.456 14.68 20 35 0.532 16.94 18 40 0.608 19.08 16 45 0.684 21.03 14 50 0.760 22.78 12 55 0.836 24.28 10 60 0.912 25.52 65 0.988 26.49 70 1.064 27.16 75 1.140 27.57 80 1.216 27.70 85 1.292 27.60 90 1.368 27.29 95 1.444 26.81 100 1.520 26.20 MT9M114 CRA Characteristic CRA (Degrees) Image Height (%) 8 6 4 2 0 0 10 20 30 40 50 60 70 80 90 100 110 Image Height (%) Figure 40. Chief Ray Angle 65 60 Red Green (B) Green (R) Blue 55 Quantum Efficiency (%) 50 45 40 35 30 25 20 15 10 5 0 350 450 550 650 750 Wavelength (nm) 850 Figure 41. Typical Quantum Efficiency www.onsemi.com 37 950 1050 1150 MT9M114 ELECTRICAL SPECIFICATIONS CAUTION: Stresses above those listed in Table 19 may cause permanent damage to the device Table 19. ABSOLUTE MAXIMUM RATINGS Symbol VDD_MAX VDD_IO_MAX VAA_MAX Parameter Min Max Unit Core Digital Voltage -0.3 2.4 V I/O Digital Voltage -0.3 4.0 V Analog Voltage -0.3 4.0 V VDD_PLL_MAX PLL Supply Voltage -0.3 4.0 V VDD_PHY_MAX PHY Supply Voltage -0.3 2.4 V VIN DC Input Voltage -0.3 VDD_IO + 0.3 V IIN Transient Input Current (0.5 sec. Duration) - 150 mA TOP Operating Temperature (Measure at Junction) -30 75 C TSTG Storage Temperature (Note 1) -40 85 C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the product specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Recommended Operating Conditions Table 20. OPERATING CONDITIONS Symbol VDD VDD_IO Parameter Min Typ Max Unit Core Digital Voltage 1.7 1.8 1.95 V I/O Digital Voltage 2.5 2.8 3.1 V 1.7 1.8 1.95 V Analog Voltage 2.5 2.8 3.1 V VDD_PLL PLL Supply Voltage 2.5 2.8 3.1 V VDD_PHY PHY Supply Voltage 1.7 1.8 1.95 V Operating Temperature (at Junction) -30 55 70 C Min Max Unit VAA TJ Table 21. CD ELECTRICAL CHARACTERISTICS Symbol Parameter Condition VIH Input HIGH Voltage (Note 1) VDD_IO * 0.7 - V VIL Input LOW Voltage (Note 1) - VDD_IO * 0.3 V IIN Input Leakage Current (Note 2) VIN = 0 V or VIN = VDD_IO - 10 mA VOH Output HIGH Voltage IOH = 2 mA VDD_IO * 0.75 - V VOL Output LOW Voltage IOH = 2 mA - VDD_IO * 0.25 V 1. VIL and VIH have min/max limitations specified by absolute ratings. 2. Excludes CONFIG and RESET_BAR as they have an internal pull-up resistor. www.onsemi.com 38 MT9M114 Table 22. OPERATING CURRENT CONSUMPTION (Default Setup Conditions: fEXTCLK = 24 MHz, fPIXCLK = 96 MHz, VAA = VDD_IO = VDD_PLL = 2.8 V, VDD = VDD_PHY = 1.8 V, TJ = 70C unless otherwise stated, PN9 enabled, specified under MIPI and Parallel output conditions) Conditions Min Typ Max Unit VDD 1.7 1.8 1.95 V VAA 2.5 2.8 3.1 V VDD_PHY 1.7 1.8 1.95 V VDD_PLL 2.5 2.8 3.1 V VDD_IO = 2.8 V 2.5 2.8 3.1 V VDD_IO = 1.8 V 1.7 Symbol VDD_IO IDD IAA IDD_PLL IDD_PHY Total Power Consumption (Note 1) 1.8 1.95 V Full Resolution 30 fps, Parallel 39 50 mA 720p, 30 fps, Parallel 33 45 mA VGA Binned, 60 fps, Parallel 25 40 mA Full Resolution, 30fps, MIPI 39 50 mA 720p, 30 fps, MIPI 33 45 mA VGA Binned, 60 fps, MIPI 25 40 mA Full Resolution, 30 fps, Parallel 19 35 mA 720p, 30 fps, Parallel 19 35 mA VGA Binned, 60 fps, Parallel 19 35 mA Full Resolution, 30 fps, MIPI 19 35 mA 720p, 30 fps, MIPI 19 35 mA VGA Binned, 60 fps, MIPI 19 35 mA Full Resolution, 30 fps, Parallel 8 20 mA 720p, 30 fps, Parallel 8 20 mA VGA, 60 fps, Parallel 8 20 mA Full Resolution, 30f ps, MIPI 25 40 mA 720p, 30 fps, MIPI 25 40 mA VGA Binned, 60 fps, MIPI 25 40 mA Full Resolution, 30 fps, Parallel 0.02 0.5 mA 720p, 30fps, Parallel 0.02 0.5 mA VGA Binned, 60 fps, Parallel 0.02 0.5 mA Full Resolution, 30 fps, MIPI 0.18 1 mA 720p, 30 fps, MIPI 0.18 1 mA VGA Binned, 60 fps, MIPI 0.18 1 mA Full Resolution, 30 fps, Parallel 146 mW 720p, 30fps, Parallel 135 mW VGA Binned, 60 fps, Parallel 121 mW Full Resolution, 30 fps, MIPI 194 mW 720p, 30 fps, MIPI 183 mW VGA Binned, 60 fps, MIPI 169 mW 1. Total power excludes VDD_IO current. Table 23. STANDBY CURRENT CONSUMPTION (PARALLEL AND MIPI) (Default Setup Conditions: fEXTCLK = 24 MHz, fPIXCLK = 96 MHz, VAA = VDD_IO = VDD_PLL = 2.8 V, VDD = VDD_PHY = 1.8 V, TJ = 70C unless otherwise stated) Typ Max Unit Soft Standby (CLK ON) Total Standby Current in Parallel and MIPI Mode 1.4 3 mA Total Power Consumption in Parallel and MIPI Mode 2.5 - mW Soft Standby (CLK OFF) Total Standby Current in Parallel and MIPI Mode 80 500 mA Total Power Consumption in Parallel and MIPI Mode 150 - mW NOTE: All power measurements exclude IO current. www.onsemi.com 39 MT9M114 Table 24. AC ELECTRICAL CHARACTERISTICS (EXTCLK = 6-54 MHz; VDD = VDD_PHY = 1.8 V; VDD_IO = VAA = VDD_PLL = 2.8 V; TJ = 25C unless otherwise stated) Parameter Min Typ Max Unit External Input Clock Frequency 6 - 54 MHz fEXTCLK External Clock Frequency (Note 1) 6 - 54 MHz DEXTCLK External Input Clock Duty Cycle 40 50 60 % External Input Clock Jitter (Note 2) - 500 - ps tPD PIXCLK to Data Valid - 2 5 ns tPFH PIXCLK to FV HIGH - 2 5 ns tPLH PIXCLK to LV HIGH - 2 5 ns tPFL PIXCLK to FV LOW - 2 5 ns tPLL PIXCLK to LV LOW - 2 5 ns tCP EXTCLK TO PIXCLK Propagation Delay tPIXCLK = PICXCLK Period - 0.1 * tPIXCLK - ns VDD_IO = 2.8 V, PLL Bypass, 6 MHz EXTCLK, CLOAD = 35 pF - 0.647 - V/ns VDD_IO = 1.8 V, PLL Bypass, 6 MHz EXTCLK, CLOAD = 35 pF - 0.27 - V/ns VDD_IO = 2.8 V, PLL Bypass, 6 MHz EXTCLK, CLOAD = 35 pF - 0.229 - V/ns VDD_IO = 1.8 V, PLL Bypass, 6 MHz EXTCLK, CLOAD = 35 pF - 0.112 - V/ns Symbol tJITTER Condition PIXCLK SLEW RATE Slew = 4 OUTPUT SLEW RATE Slew = 4 1. VIH/VIL restrictions apply. 2. Based on lab measurements. Could vary with noisier system-level electronics. tR tF 90% 90% 10% 10% tEXTCLK EXTCLK tCP (Note 4) PIXCLK tPD DOUT[7:0] tPD Data Data Data Data tPFH tPLH (Note 2) Data t (Note 3) tPFL PLL LINE_VALID/ FRAME_VALID Notes: 1. FRAME_VALID leads LINE_VALID by 6 PIXCLKs. 2. FRAME_VALID trails LINE_VALID by 6 PIXCLKs. 3. DOUT[7:0], FRAME_VALID, and LINE_VALID are shown with respect to the falling edge of PIXCLK. This feature is programmable and DOUT[7:0], FRAME_VALID, and LINE_VALID can be synchronized to the rising edge of PIXCLK. 4. Propagation delay is measured from 50% of rising and falling edges. Figure 42. Parallel Pixel Bus Timing Diagram www.onsemi.com 40 MT9M114 Table 25. TWO-WIRE SERIAL INTERFACE TIMING DATA (fEXTCLK = 50 MHz; VDD = 1.8 V; VDD_IO = 1.8 V; VAA = 2.8 V; TJ = 70C; CLOAD = 68.5 pF) Parameter Symbol Conditions Min Typ Max Unit fSCLK Serial Interface Input Clock Frequency 100 - 400 kHz tSCLK Serial Interface Input Clock Period 10 - 2.5 ?s SCLK Duty Cycle 45 50 55 % ns - - 300 tSRTS tr SCLK/SDATA Rise Time Start Setup Time Master Write to Slave 600 - - tSRTH Start Hold Time Master Write to Slave 300 - - ns tSDH SDATA Hold Master Write to Slave 300 - 650 ns tSDS SDATA Setup Master Write to Slave 300 - - ns tSHAW SDATA Hold to Ack Master Write to Slave 150 - - ns tAHSW Ack Hold to SDATA Master Write to Slave 150 - - ns tSTPS Stop Setup Time Master Write to Slave 300 - - ns tSTPH Stop Hold Time Master Write to Slave 600 - - ns tSHAR SDATA Hold to Ack Master Read from Slave 300 - - ns tAHSR Ack Hold to SDATA Master Read from Slave 300 - - ns tSDHR SDATA Hold Master Read from Slave 300 - 650 ns tSDSR SDATA Setup Master Read from Slave 350 - - ns Write Sequence t SRTS t SDS t SCLK t SRTH SCLK t STPS t SHAW t STPH t AHSW t SDH SDATA Write Start Write Address Bit 7 Write Address Bit 0 Read Sequence Register Value Bit 7 Ack Register Value Bit 0 t SDSR t SHAR t AHSR t SDHR SCLK SDATA Read Start Read Address Bit 7 Read Address Bit 0 Ack Register Value Bit 7 Figure 43. Two-wire Serial Bus Timing Parameters www.onsemi.com 41 Register Value Bit 0 Ack Stop MT9M114 MIPI AC and DC Electrical Characteristics Table 26. MIPI HIGH-SPEED TRANSMITTER DC CHARACTERISTICS Symbol Parameter VCMTX HS Transmit Static Common-Mode Voltage VCMTX Mismatch when Output is Differential-1 or Differential-0 |DVCMTX (1,0)| |VOD| HS Transmit Differential Voltage Min Nom Max Unit 150 200 250 mV - - 5 mV 140 200 270 mV - - 10 mV |DVOD| VOD Mismatch when Output is Differential-1 or Differential-0 VOHHS HS Output High Voltage - - 360 mV Single-ended Output Impedance 40 50 62.5 W Single-ended Output Impedance Mismatch - - 10 % Min Nom Max Unit - - 768 Mb/s ZOS DZOS Table 27. MIPI HIGH-SPEED TRANSMITTER AC CHARACTERISTICS Parameter Description Data Bit Rate tR and tF 20%-80% Rise Time and Fall Time - - 0.3 UI 150 - - ps Min Nom Max Unit Table 28. MIPI LOW-POWER TRANSMITTER DC CHARACTERISTICS Parameter Description VOH Thevenin Output High Level 1.1 1.2 1.3 V VOL Thevenin Output Low Level -50 - 50 mV ZOLP Output Impedance of LP Transmitter 110 - - W Table 29. MIPI LOW-POWER TRANSMITTER AC CHARACTERISTICS Parameter TRLP/TFLP TLP-PULSE-TX Description Min Nom Max Unit - - 25 ns 40 - - 20 - - - - - ns - - 35 ns - 30 30-0.075 * (VO,INST-700) - - - 150 - - mV/ns 0 - 70 pF 15-85% Rise Time and Fall Time Pulse Width of the LP Exclusive-OR Clock First LP exclusive-OR clock pulse after Stop state or last pulse before Stop state All other pulses TLP-PER-TX TREOT 30%-85% Rise Time and Fall Time dV/dtSR Slew Rate @ CLOAD = 70 pF Slew Rate @ CLOAD = 0 to 70 pF (Rising Edge Only) Slew Rate @ CLOAD = 0 to 70 pF (Rising Edge Only) CLOAD Load Capacitance ns Table 30. CLOCK SIGNAL SPECIFICATION Symbol UIINST Parameter UI Instantaneous Min Nom Max Unit - - 12.5 ns Min Nom Max Unit -0.15 - 0.15 UIINST Table 31. DATA-CLOCK TIMING SPECIFICATIONS Symbol TSKEW Parameter Data to Clock Skew (Measured at Transmitter) www.onsemi.com 42 MT9M114 PINOUT 1 2 3 4 5 6 7 8 A VAA Reserved (Note 1) DOUT[6] DOUT[4] DOUT[2] VDD DOUT[1] VDD B GND VAA VDD_IO DOUT[5] DOUT[3] GND DOUT[0] VDD_IO C VDD OE_BAR AGND GND VDD_IO FV LV D CONFIG SCLK SDATA DOUT[7] Reserved (Note 1) DOUT_ LSB1 GND VDD E VDD_IO CHAIN Reserved (Note 1) SADDR RESET_ BAR DOUT_ LSB0 GND VDD_PHY F EXTCLK PIXCLK GND TRST_BAR DATA_N DATA_P CLK_P CLK_N G VDD FLASH VDD PGND (Note 2) PGND (Note 2) VDD_PLL GND_PLL GND_PLL Top View (Ball Down) Notes: 1. Do not use. 2. To be used for EMI shielding. Figure 44. 4.7x3.9 ODCSP 55-Ball Package www.onsemi.com 43 MT9M114 PACKAGE DIMENSIONS Table 32. PACKAGE DIMENSIONS Nominal Parameter Min Max Nominal Millimeters Symbol Min Max Inches Package Body Dimension X A 4.648 4.623 4.673 0.183 0.182 0.184 Package Body Dimension Y B 3.848 3.823 3.873 0.151 0.151 0.152 Package Height C 0.690 0.635 0.745 0.027 0.025 0.029 Cavity height (Glass to Pixel Distance) C4 0.041 0.037 0.045 0.002 0.001 0.002 Glass Thickness C3 0.400 0.390 0.410 0.016 0.015 0.016 Package Body Thickness C2 0.570 0.535 0.605 0.022 0.021 0.024 Ball Height C1 0.120 0.090 0.150 0.005 0.004 0.006 Ball Diameter D 0.230 0.200 0.260 0.009 0.008 0.010 Total Ball Count N 55 Ball Count X axis N1 8 Ball Count Y axis N2 7 UBM U 0.240 0.230 0.250 0.009 0.009 0.010 Pins Pitch X axis J1 0.520 Pins Pitch Y axis J2 0.520 BGA Ball Center to Package Center Offset in X-direction X 0.000 -0.025 0.025 0.000 -0.001 0.001 BGA Ball Center to Package Center Offset in Y-direction Y 0.000 -0.025 0.025 0.000 -0.001 0.001 Edge to Ball Center Distance along X S1 0.504 0.474 0.534 0.020 0.019 0.021 Edge to Ball Center Distance along Y S2 0.364 0.334 0.394 0.014 0.013 0.016 www.onsemi.com 44 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS ODCSP55 4.7x3.9 CASE 570BP ISSUE A DOCUMENT NUMBER: DESCRIPTION: 98AON94096F ODCSP55 4.7x3.9 DATE 19 FEB 2020 Electronic versions are uncontrolled except when accessed directly from the Document Repository. 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