Copyright © Cirrus Logic, Inc. 2008
(All Rights Reserved)
http://www.cirrus.com
114 dB, 192 kHz 8-Channel D/A Converter
Features
24-bit Conversion
Up to 192 kHz Sample Rates
114 dB Dynamic Range
-100 dB THD+N
Supports PCM and DSD Data Formats
Selectable Digital Filters
Volume Control with Soft Ramp
– 1 dB Step Size
– Zero Crossing Click-Free Transitions
Dedicated DSD Inputs
Low Clock-Jitter Sensitivity
Simultaneous Support for Two Synchronous
Sample Rates for DVD Audio
μC or Stand-Alone Operation
Description
The CS4382 is a complete 8-channel digital-to-analog
system including digital interpolation, fifth-order delta-
sigma digital-to-analog conversion, digital de-empha-
sis, volume control and analog filtering. The advantages
of this architecture include: ideal differ ential linearity, no
distortion mechanisms due to resistor matching errors,
no linearity drift over time and temperature and a high
tolerance to clock jitter.
The CS4382 is available in a 48-pin LQFP package in
Commercial grade (-10°C to +70°C). The CDB4382
Customer Demonstration Board is also available for de-
vice evaluation and implementation suggestions.
Please see “Ordering Information” on page 42 for com-
plete details.
The CS4382 accepts PCM data at sample rates from
4 kHz to 192 kHz, DSD au dio data, and operate s over a
wide power supply range. These features are ideal for
multi-channel audio systems including DVD players,
SACD players, A/V receivers, digital TV’s, mixing con-
soles, effects processors, and automotive audio
systems.
I
External
Mute Control
RST
Volume Control Interpolation Filter Analog Filter
ΔΣ DAC
Mixer
Volume Control ΔΣ
DAC Analog Filter
Interpolation Filter
Volume Control Interpolation Filter Analog Filter
ΔΣ DAC
Mixer
Volume Control
ΔΣ
DAC Analog Filter
Interpolation Filter
Volume Control Interpolation Filter Analog Filter
ΔΣ DAC
Mixer
Volume Control
ΔΣ DAC Analog Filter
AOUTB4-
Interpolation Filter
MCLK
Serial Port
SCL/CCLK(M1) SDA/CDIN(M2) AD0/CS(M0)
VLC
÷2
VQ
FILT+
VA
GNDVD
MUTEC1
DSD_SCLK(M3)
GND
Control P ort(S tand-Alone M ode Select)
VLS
LRCK
SD IN1
SD IN2
SD IN3
2
SCLK
LRCK2
SCLK
DSDxx 8
AOUTB4+
AOUTA4-
AOUTA4+
AOUTB2-
AOUTB2+
AOUTA2-
AOUTA2+
AOUTB1-
AOUTB1+
AOUTA1-
AOUTA1+
Volume Control Interpolation Filter Analog Filter
ΔΣ DAC
Mixer
Volume Control
ΔΣ DAC Analog Filter
Interpolation Filter
AOUTB3-
AOUTB3+
AOUTA3-
AOUTA3+
SD IN4
MUTEC234
1
1
FEB '08
DS514F2
CS4382
2DS514F2
CS4382
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ..................................................................................... 5
ANALOG CHARACTERISTICS............................................................................................................. 5
ANALOG CHARACTERISTICS............................................................................................................. 6
POWER AND THERMAL CHARACTERISTICS ................................................................................... 6
ANALOG FILTER RESPONSE ............................................................................................................. 7
DIGITAL CHARACTERISTI CS............ ... ... ................ .... ... ................ ... ... ................. ... ... ................ ........ 8
ABSOLUTE MAXIMUM RATINGS........................................................................................................8
RECOMMENDED OPERATING CONDITIONS.................................................................................... 8
SWITCHING CHARACTERI S TI CS..... ... ... ... .... ... ... ................ .... ... ................ ... ................ ... .... ..............9
DSD - SWITCHING CHARACTERISTICS .......................................................................................... 10
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C® FORMAT........................................... 11
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI™ FORMAT......................................... 12
2. TYPICAL CONNECTION DIAGRAM ............................................................................................... 13
3. REGISTER QUICK REFERENCE ....... ... ................ ... .... ................ ... ... ................ .... ... ................ ... ...... 15
4. REGISTER DESCRIPTION . ... ... ... ................ .... ... ................ ... .... ................ ... ... ................ ... .... ............ 16
4.1 Mode Control 1 (Address 01h) ..................................................................................................... 16
4.1.1 Control Port Enable (CPEN) ............................................................................................ 16
4.1.2 Freeze Controls (FREEZE) .............................................................................................. 16
4.1.3 Master Clock Divide Enable (MCLKDIV) ......................................................................... 16
4.1.4 DAC Pair Disable (DACx_DIS) ........................................................................................ 16
4.1.5 Power Down (PDN) .......................................................................................................... 17
4.2 Mode Control 2 (Address 02h) .................................................................................................... 17
4.2.1 Digital Interface Format (DIF) .......................................................................................... 17
4.2.2 Serial Audio Data Clock Source (SDINXCLK) ................................................................. 18
4.3 Mode Control 3 (Address 03h) .................................................................................................... 18
4.3.1 Soft Ramp and Zero Cross Control (SZC) ....................................................................... 18
4.3.2 Single Volume Control (SNGLVOL) ................................................................................. 19
4.3.3 Soft Volume Ramp-Up After Error (RMP_UP) ................................................................. 19
4.3.4 Mutec Polarity (MUTEC+/-) .............................................................................................. 19
4.3.5 Auto-Mute (AMUTE) ........................................................................................................20
4.3.6 Mutec Pin Control (MUTEC) ............................................................................................ 20
4.4 Filter Control (Address 04h) . .... ... ... ... ... .... ...... ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ...... ... .... ............ 20
4.4.1 Interpolation Filter Select (FILT_SEL) . ... .... ... ... ................ ... .... ................ ... ... ................ ... 20
4.4.2 De-Emphasis Control (DEM) ........................................................................................... 20
4.4.3 Soft Ramp-Down Before Filter Mode Change (RMP_DN) ............ ... .... ... ... ... ... ....... ... ... ... 21
4.5 Invert Control (Address 05h) ....................................................................................................... 21
4.5.1 Invert Signal Polarity (INV_XX) ........................................................................................ 21
4.6 Mixing Control Pair 1 (Channels A1 & B1)(Address 06h)
Mixing Control Pair 2 (Channels A2 & B2)(Address 09h)
Mixing Control Pair 3 (Channels A3 & B3)(Address 0Ch)
Mixing Control Pair 4 (Channels A4 & B4)(Address 0Fh) ......................................................... 21
4.6.1 Channel A Volume = Channel B Volume (A=B) ......... ............. ............. ............ ............. ... 21
4.6.2 ATAPI Channel Mixing and Muting (ATAPI) .................................................................... 22
4.6.3 Functional Mode (FM) ............... ................. ... ... ................ ... .... ................ ... ... ................ ... 23
4.7 Volume Control (Addresses 07h, 08h, 0Ah, 0Bh, 0Dh, 0Eh, 10h, 11h) ...................... .... ... ... ... ... 23
4.7.1 Mute (MUTE) ................................................................................................................... 23
4.7.2 Volume Control (xx_VOL) ................................................................................................ 23
4.8 Chip Revision (Address 12h) ....................................................................................................... 24
4.8.1 Part Number ID (PART) [Read Only] ............................................................................... 24
5. PIN DESCRIPTION ................. ... ... ................ .... ................ ... ... ................ .... ... ................ ...................... 25
6. APPLICATIONS .................................................................................................................................. 28
6.1 Grounding and Power Supply Decoupling .................................................................................... 28
DS514F2 3
CS4382
6.2 PCM Mode Select ......................................................................................................................... 28
6.3 Recommended Power-Up Sequence ........................................................................................... 28
6.4 Analog Output and Filtering .......................................................................................................... 28
6.5 Interpolation Filter ......................................................................................................................... 28
6.6 Clock Source Selection ................................................................................................................ 29
6.7 Using DSD Mode .......................................................................................................................... 29
7. CONTROL PORT INTERFACE .... ................ .... ... ................ ... .... ................ ... ... ................ ... .... ............ 29
7.1 Enabling the Control Port ............................................................................................................. 30
7.2 Format Selection .......................................................................................................................... 30
7.3 I²C Format .................................................................................................................................... 30
7.3.1 Writing in I²C Format ................. ................. ... ... ................ ... .... ................ ... ... ................... 30
7.3.2 Reading in I²C Format ...................... ... ................ .... ... ................ ... ... ................ .... ... ......... 30
7.4 SPI Format ................................................................................................................................... 30
7.4.1 Writing in SPI ................ ... ... ... ... ................. ... ... ................ ... .... ................ ... ... ................... 31
7.5 Memory Address Pointer (MAP) .................................................................................................. 31
7.5.1 INCR (Auto Map Increment Enable) ................................................................................ 31
7.5.2 MAP4-0 (Memory Address Pointer) ................................................................................. 32
8. FILTER PLOTS .............................................................................................................................. 33
9. DIAGRAMS ..................................................................................................................... 37
10. PARAMETER DEFINITIONS ............................................................................................................. 40
11. REFERENCES ................................................................................................................................... 40
12. PACKAGE DIMENSIONS ................................................................................................................. 41
13. ORDERING INFORMATION ............................................................................................................. 42
14. REVISION HISTORY ......................................................................................................................... 42
LIST OF FIGURES
Figure 1. Serial Mode Input Timing.............................................................................................................. 9
Figure 2. Direct Stream Digital - Serial Audio Input Timing........................................................................ 10
Figure 3. Control Port Timing - I²C Format................................................................................................. 11
Figure 4. Control Port Timing - SPI Format................................................................................................ 12
Figure 5. Typical Connection Diagram Control Port ... ... ... .... ... ... ....... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ...... 13
Figure 6. Typical Connection Diagram Stand-Alone.................................................................................. 14
Figure 7. Control Port Timing, I²C Format.................................................................................................. 31
Figure 8. Control Port Timing, SPI Format................................................................................................. 31
Figure 9. Single-Speed (fast) Stopband Rejection..................................................................................... 33
Figure 10. Single-Speed (fast) Transition Band......................................................................................... 33
Figure 11. Single-Speed (fast) Transition Band (detail)............................................................................. 33
Figure 12. Single-Speed (fast) Passband Ripple.......................... .... ... ... ... ................ .... ... ................ ......... 33
Figure 13. Single-Speed (slow) Stopband Rejection .................... .... ... ................ ... ... ................ .... ... ......... 33
Figure 14. Single-Speed (slow) Transition Band........................................................................................ 33
Figure 15. Single-Speed (slow) Transition Band (detail)............................................................................ 34
Figure 16. Single-Speed (slow) Passband Ripple...................................................................................... 34
Figure 17. Double-Speed (fast) Stopband Rejection ................................................................................. 34
Figure 18. Double-Speed (fast) Transition Band........................................................................................ 34
Figure 19. Double-Speed (fast) Transition Band (detail)............................................................................ 34
Figure 20. Double-Speed (fast) Passband Ripple...................................................................................... 34
Figure 21. Double-Speed (slow) Stopband Rejection................................................................................ 35
Figure 22. Double-Speed (slow) Transition Band............ .... ... ................ ... ... ................. ... ... ................ ...... 35
Figure 23. Double-Speed (slow) Transition Band (detail)............. .... ... ................ ... ... ................ .... ............ 35
Figure 24. Double-Speed (slow) Passband Ripple.................................................................................... 35
Figure 25. Quad-Speed (fast) Stopband Rejection.... ... ... .... ... ... ... ................ .... ... ................ ... ... ................ 35
Figure 26. Quad-Speed (fast) Transition Band.......................................................................................... 35
Figure 27. Quad-Speed (fast) Transition Band (detail). ... .... ... ... ... .... ... ... ... ... ....... ... ... .... ... ... ... ... .... ... ... .. .... 36
4DS514F2
CS4382
Figure 28. Quad-Speed (fast) Passband Ripple........................................................................................ 36
Figure 29. Quad-Speed (slow) Stopband Rejection................................................................................... 36
Figure 30. Quad-Speed (slow) Transition Band......................................................................................... 36
Figure 31. Quad-Speed (slow) Transition Band (detail)............................................................................. 36
Figure 32. Quad-Speed (slow) Passband Ripple....................................................................................... 36
Figure 33. Format 0 - Left Justified up to 24-bit Data................................................................................. 37
Figure 34. Format 1 - I²S up to 24-bit Data................................................................................................ 37
Figure 35. Format 2 - Right Justified 16-bit Data....................................................................................... 37
Figure 36. Format 3 - Right Justified 24-bit Data....................................................................................... 37
Figure 37. Format 4 - Right Justified 20-bit Data....................................................................................... 38
Figure 38. Format 5 - Right Justified 18-bit Data....................................................................................... 38
Figure 39. De-Emphasis Curve.................................................................................................................. 38
Figure 40. Channel Pair Routing Diagram (x = Channel Pair 1, 2, 3, or 4)................................................ 38
Figure 41. ATAPI Block Diagram (x = channel pair 1, 2, 3, or 4)............................................................... 39
Figure 42. Recommended Output Filter..................................................................................................... 39
LIST OF TABLES
Table 1. Digital Interface Formats - PCM Mode......................................................................................... 17
Table 2. Digital Interface Formats - DSD Mode......................................................................................... 18
Table 3. ATAPI Decode ............................................................................................................................. 22
Table 4. Example Digital Volume Settings. ... ... ... ....................................................................................... 23
Table 5. Common Clock Frequencies........................................................................................................ 27
Table 6. Digital Interface Format, Stand-Alone Mode Options................................................................... 27
Table 7. Mode Selection, Stand-Alone Mode Options...............................................................................27
Table 8. Direct Stream Digital (DSD), Stand-Alone Mode Options............................................................ 27
DS514F2 5
CS4382
1. CHARACTERISTICS AND SPECIFICATIONS
ANALOG CHARACTERISTICS
(Full-Scale Output Sine Wave, 997 Hz; Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified; Test
load RL = 3 kΩ, CL = 100 pF, VA = 5 V, VD = 3.3 V (see Figure 5)
For Single-Speed Mode, Fs = 48 kHz, SCLK = 3.072 MHz, MCLK = 12.288 MHz;
For Double-Speed Mode, Fs = 96 kHz, SCLK = 6.144 MHz, MCLK = 12.288 MHz;
For Quad-Speed Mode, Fs = 192 kHz, SCLK = 12.288 MHz, MCLK = 24.576 MHz;
For Direct Stream Digital Mode, Fs = 128 x 48 kHz, DSD_SCLK = 6.144 MHz, MCLK = 12.288 MHz).
Notes: 1. CS4382-KQZ parts are tested at 25°C.
2. One-half LSB of triangular PDF dither is added to data.
3. Performance limited by 16-bit quantization noise.
Parameters Symbol Min Typ Max Unit
CS4382-KQZ Dynamic Performance - All PCM modes and DSD (Note 1)
Specified Temper ature Range TA-10 - 70 °C
Dynamic Range (Note 2) 24-bit unweighted
A-Weighted
16-bit unweighted
(Note 3) A-Weighted
105
108
-
-
111
114
94
97
-
-
-
-
dB
dB
dB
dB
Total Harmonic Distortion + Noise (Note 2)
24-bit 0 dB
-20 dB
-60 dB
16-bit 0 dB
(Note 3) -20 dB
-60 dB
THD+N -
-
-
-
-
-
-100
-91
-51
-94
-74
-34
-94
-
-
-
-
-
dB
dB
dB
dB
dB
dB
Idle Channel Noise / Signal-to-noise ratio - 114 - dB
Interchannel Isolation (1 kHz) - 90 - dB
6DS514F2
CS4382
ANALOG CHARACTERISTICS
(Continued)
POWER AND THERMAL CHARACTERISTICS
Notes: 4. VFS is tested under load RL and includes attenuation due to ZOUT
5. Current consumption increa ses with increasing FS within a given speed mode a nd is signal depe ndant.
Max values are based on highest FS and highest MCLK.
6. ILC measured with no external loading on the SDA pin.
7. This specification is violated when the VLC supply is greater than VD and when pin 16 (M1/SDA) is tied
or pulled low. Logic tied to pin 16 needs to be able to sink this current.
8. Power Down Mode is defined as RST pin = Low with all clock and data lines held static.
9. Valid with the recommended capacitor values on FILT+ and VQ as shown in Figures 5 and 6.
Parameters Symbol Min Typ Max Units
Analog Output - All PCM modes and DSD
Full Scale Differential Output Voltage (Note 4) VFS 86% VA91% VA96% VAVpp
Quiescent Voltage VQ- 50% V
A-VDC
Max Current from VQIQMAX -1 -μA
Interchannel Gain Misma tch - 0.1 - dB
Gain Drift - 100 - ppm/°C
Output Impedance (Note 4) ZOUT - 100 - Ω
AC-Load Resistance RL3- -kΩ
Load Capacitance CL- - 100 pF
Parameters Symbol Min Typ Max Units
Power Supplies
Power Supply Current normal operation, VA= 5 V
(Note 5) VD= 5 V
VD= 3.3 V
Interface current, VLC=5 V (Notes 6, 7)
VLS=5 V
power-down state (all supplies) (Note 8)
IA
ID
ID
ILC
ILS
Ipd
-
-
-
-
-
-
60
45
30
2
84
200
66
70
46
-
-
-
mA
mA
mA
μA
μA
μA
Power Dissipation (Note 5)
VA = 5 V, VD = 3.3 V normal operation
power-down (Note 8)
VA = 5 V, VD = 5 V normal operation
power-down (Note 8)
-
-
-
-
400
1
525
1
485
-
680
-
mW
mW
mW
mW
Package Thermal Resistance multi-layer
dual-layer θJA
θJA
θJC
-
-
-
48
65
15
-
-
-
°C/Watt
°C/Watt
°C/Watt
Power Supply Rejection Ratio (Note 9) (1 kHz)
(60 Hz) PSRR -
-60
40 -
-dB
dB
DS514F2 7
CS4382
ANALOG FILTER RESPONSE
Notes: 10. Slow Roll-Off interpolation filter is only available in Control Port Mode.
11. Filter response is not tested but is guaranteed by design.
12. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 9 to 32) have
been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.
13. Single and Double-Speed Mode Measurement Bandwidth is from stopband to 3 Fs.
Quad-Speed Mode Measurement Bandwidth is from stopband to 1.34 Fs.
14. De-emphasis is available only in Single-Speed Mode; Only 44.1 kHz De-emphasis is available in Stand-
Alone Mode
Parameter Fast Roll-Off Slow Roll-Off (N ot e 10) UnitMin Typ Max Min Typ Max
Combined Digital and On-chip Analog Filter Response - Single-Speed Mode (Note 11)
Passband (Note 12) to -0.01 dB corner
to -3 dB corner 0
0-
-.454
.499 0
0-
-0.417
0.499 Fs
Fs
Frequency Response 10 Hz to 20 kHz -0.01 - +0.01 -0.01 - +0.01 dB
StopBand .547 - - .583 - - Fs
StopBand Attenuation (Note 13) 90 - - 64 - - dB
Group Delay - 12/Fs - - 6.5/Fs - s
Passband Group Delay Deviation 0 - 20 kHz - - ±0.41/Fs - ±0.14/Fs s
De-emphasis Error (Note 14) Fs = 32 kHz
(Relative to 1 kHz) Fs = 44.1 kHz
Fs = 48 kHz
-
-
-
-
-
-
±0.23
±0.14
±0.09
-
-
-
-
-
-
±0.23
±0.14
±0.09
dB
dB
dB
Combined Digital and On-chip Analog Filter Response - Double-Speed Mode - 96 kHz (Note 11)
Passband (Note 12) to -0.01 dB corner
to -3 dB corner 0
0-
-.430
.499 0
0-
-.296
.499 Fs
Fs
Frequency Response 10 Hz to 20 kHz -0.01 - 0.01 -0.01 - 0.01 dB
StopBand .583 - - .792 - - Fs
StopBand Attenuation (Note 13) 80 - - 70 - - dB
Group Delay - 4.6/Fs - - 3.9/Fs - s
Passband Group Delay Deviation 0 - 20 kHz - - ±0.03/Fs - ±0.01/Fs s
Combined Digital and On-chip Analog Filter Response - Quad-Speed Mode - 192 kHz (Note 11)
Passband (Note 12) to -0.01 dB corner
to -3 dB corner 0
0-
-.105
.490 0
0-
-.104
.481 Fs
Fs
Frequency Response 10 Hz to 20 kHz -0.01 - 0.01 -0.01 - 0.01 dB
StopBand .635 - - .868 - - Fs
StopBand Attenuation (Note 13) 90 - - 75 - - dB
Group Delay - 4.7/Fs - - 4.2/Fs - s
Passband Group Delay Deviation 0 - 20 kHz - - ±0.01/Fs - ±0.01/Fs s
Combined Digital and On-chip Analog Filter Response - DSD Mode (Note 11)
Passband (Note 12) to -0.1 dB corner
to -3 dB corner -
--
--
-0
0-
-20
120 kHz
kHz
Frequency Response 10 Hz to 20 kHz - - - -.01 - 0.1 dB
8DS514F2
CS4382
DIGITAL CHARACTERISTICS
(For KQZ TA = -10°C to +70°C; VLC = VLS = 1.8 V to 5.5 V)
ABSOLUTE MAXIMUM RATINGS
(GND = 0 V; all voltages with respect to ground.)
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation
is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(GND = 0 V; all voltages with respect to ground .)
Parameters Symbol Min Typ Max Units
High-Level Input Voltage Serial Data Port
Control Port VIH
VIH
70% VLS
70% VLC -
--
-V
V
Low-Level Input Voltage Serial Data Port
Control Port VIL
VIL
-
--
-20% VLS
20% VLC V
V
Input Leakage Current (Note 7) Iin --±10μA
Input Capacitance - 8 - pF
Maximum MUTEC Drive Current - 3 - mA
MUTEC High-Level Output Voltage VOH -VA-V
MUTEC Low-Level Output Voltage VOL -0-V
Parameters Symbol Min Max Units
DC Power Supply Analog power
Digital internal power
Serial data port interfa ce p ow e r
Control po rt interface p ow e r
VA
VD
VLS
VLC
-0.3
-0.3
-0.3
-0.3
6.0
6.0
6.0
6.0
V
V
V
V
Input Current, Any Pin Except Supplies Iin -±10mA
Digital Input Voltage Serial data port interface
Control port interface VIND-S
VIND-C
-0.3
-0.3 VLS+ 0.4
VLC+ 0.4 V
V
Ambient Operating Tempe ratu r e (power applied) TA-55 125 °C
Storage Temperature Tstg -65 150 °C
Parameters Symbol Min Typ Max Units
DC Power Supply Analog power
Digital internal power
Serial data port interfa ce p ow e r
Control po rt interface p ow e r
VA
VD
VLS
VLC
4.5
3.0
1.8
1.8
5.0
3.3
5.0
5.0
5.5
5.5
5.5
5.5
V
V
V
V
DS514F2 9
CS4382
SWITCHING CHARACTERISTICS
(For KQZ TA = -10°C to +70°C; VLS = 1.8 V to 5.5 V; Inputs: Logic 0 = GND, Logic 1 = VLS, CL = 30 pF)
Notes: 15. See Table 5 on page 27 for suggested MCLK frequencies.
16. This serial clock is available only in Control Port Mode when the MCLK Divide bit is enabled.
17. The higher frequ ency LRCK must be an exact integer multiple (1, 2, or 4) of the lower freq uency LRCK.
.
Parameters Symbol Min Typ Max Units
MCLK Frequency (Note 15)
Single-Speed Mode 1.024 - 51.2 MHz
Double-S peed Mode 6.400 - 51.2 MHz
Quad-Speed Mode 6.400 - 51.2 MHz
MCLK Duty Cycle 405060%
Input Sample Rate Single-Speed Mode
Double-S peed Mode
Quad-Speed Mode
Fs
Fs
Fs
4
50
100
-
-
-
50
100
200
kHz
kHz
kHz
LRCK Duty Cycle 45 50 55 %
SCLK Pulse Width Low tsclkl 20 - - ns
SCLK Pulse Width High tsclkh 20 - - ns
SCLK Period tsclkw --ns
(Note 16) tsclkw --ns
SCLK rising to LRCK edge delay tslrd 20 - - ns
SCLK rising to LRCK edge setup time tslrs 20 - - ns
SDATA valid to SCLK rising setup time tsdlrs 20 - - ns
SCLK rising to SDATA hold time tsdh 20 - - ns
LRCK1 to LRCK2 frequency ratio (Note 17) 0.25 1.00 4.00
2
MCLK
-----------------
4
MCLK
-----------------
sclkh
t
slrs
t
slrd
t
sdlrs
t
sdh
t
sclkl
t
SDATA
SCLK
LRCK
Figure 1. Serial Mode Input Timing
10 DS514F2
CS4382
DSD - SWITCHING CHARACTERISTICS
(
For KQZ T
A
= -10
°C
to +70°C; Logic 0 = GND; VLS = 1.8 V to 5.5 V; Logic 1 = VLS Volts; C
L
=30pF)
Note:
18. Min is 4 tim es 64x DSD or 2 times 12 8x DSD, and Max is 12 times 64x DSD or 6 times 128x DSD. The
proper MCLK to DSD_SCLK ratio must be set either by the DIF registers or the M0:2 pins
Parameter Symbol Min Typ Max Unit
Master Clock Frequency (Note 18) 4.096 - 38.4 MHz
MCLK Duty Cycle (All DSD
modes) 40 50 60 %
DSD_SCLK Pulse Width Low tsclkl 20 - - ns
DSD_SCLK Pulse Width High tsclkh 20 - - ns
DSD_SCLK Frequency (64x Oversam-
pled) (128x Oversampled) 1.024
2.048 -
-3.2
6.4 MHz
MHz
DSD_L / _R valid to DSD_SCLK rising setup time tsdlrs 20 - - ns
DSD_SCLK rising to DSD_L or DSD_R hold time tsdh 20 - - ns
sclkh
t
sclkl
t
DSD_ L, DSD_R
DSD_SCLK
sdlrs
tsdh
t
Figure 2. Direct Stream Digital - Serial Audio Input Timing
DS514F2 11
CS4382
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C® FORMAT
(For KQZ TA = -10°C to +70°C; VLC = 1.8 V to 5.5 V; Inputs: Logic 0 = GND, Logic 1 = VLC, CL=30pF)
Notes: 19. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.
20. The acknowledge delay is based on MCLK and can limit the maximum transaction spee d.
21. for Single-Speed Mode, for Doub le-Speed Mode, for Quad-Speed Mode.
Parameter Symbol Min Max Unit
SCL Clock Frequency fscl - 100 kHz
RST Rising Edge to Start tirs 500 - ns
Bus Free Time Between Transmissions tbuf 4.7 - µs
St art Condition Hold T ime (prior to first clock pulse) thdst 4.0 - µs
Clock Low time tlow 4.7 - µs
Clock High Time thigh 4.0 - µs
Setup Time for Repeated Start Condition tsust 4.7 - µs
SDA Hold Time from SCL Falling (Note 19) thdd 0-µs
SDA Setup time to SCL Rising tsud 250 - ns
Rise Time of SCL and SDA trc, trc -1µs
Fall T ime SCL and SDA tfc, tfc - 300 ns
Setup Time for Stop Condition tsusp 4.7 - µs
Acknowledge Delay from SCL Fallin g (Note 20) tack -(Note 21) ns
15
256 Fs×
--------------------- 15
128 Fs×
--------------------- 15
64 Fs×
------------------
SDA
SCL
001100 ADDR
AD0 R/W
Start
ACK DATA
1-8
ACK
DATA
1-8
ACK
Stop
Note: If operation is a write, this byte contains the Memory Address Pointer, MAP.
Note 1
Figure 3. Control Port Timing - I²C Format
12 DS514F2
CS4382
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI™ FORMAT
(For KQZ T
A
= -10
°C
to +70°C; VLC = 1.8 V to 5.5 V; Inputs: Logic 0 = GND, Logic 1 = VLC, C
L
=30pF)
Notes: 22. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times.
23. Data must be held for sufficient time to bridge the transition time of CCLK.
24. For FSCK < 1 MHz.
Parameter Symbol Min Max Unit
CCLK Clock Frequency fsclk -MHz
RST Rising Edge to CS Falling tsrs 500 - ns
CCLK Edge to CS Falling (Note 22) tspi 500 - ns
CS High Time Between Transmissions tcsh 1.0 - µs
CS Falling to CCLK Edge tcss 20 - ns
CCLK Low Time tscl -ns
CCLK High Time tsch -ns
CDIN to CCLK Rising Setup Time tdsu 40 - ns
CCLK Rising to DATA Hold Time (Note 23) tdh 15 - ns
Rise Time of CCLK and CDIN (Note 24) tr2 - 100 ns
Fall Time of CCLK and CDIN (Note 24) tf2 - 100 ns
MCLK
2
-----------------
1
MCLK
-----------------
1
MCLK
-----------------
tr2 tf2
tdsu t
dh
t
sch
tscl
CS
CCLK
CDIN
tcss t
csh
tspi
tsrs
RST
Figure 4. Control Port Timing - SPI Format
DS514F2 13
CS4382
2. TYPICAL CONNECTION DIAGRAM
Figure 5. Typical Connection Diagram Control Port
Digital
Audio
Source
VLS CS4382
MCLK
VD AOUTA1+
10
8
32
0.1 µF +1 µF
+3.3 V to +5 V
SDIN1
9
1 µF 0.1 µ F
+
+
20
21
FILT+
VQ
7
6
LRCK1
SCLK1
SDIN3
SDIN2
39
40
0.1 µ F47 µ F
VA
0.1 µF
+
1 µF
0.1 µF
+ 1.8 V to + 5 V
+5 V
4
43
SDIN4
LRCK2
SCLK2
13
14
Analog Conditioning
and M uting
AOUTA1-
AOUTB1+
38
37
Analog Conditioning
and M uting
AOUTB1-
AOUTA2+
35
36 Analog Conditioning
and M uting
AOUTA2-
AOUTB2+
34
33 Analog Conditioning
and M uting
AOUTB2-
AOUTA3+ 29
30
Analog Conditioning
and M uting
AOUTA3-
AOUTB3+ 28
27
Analog Conditioning
and M uting
AOUTB3-
AOUTA4+ 25
26 Analog Conditioning
and M uting
AOUTA4-
AOUTB4+
24
23
Analog Conditioning
and M uting
AOUTB4-
MUTEC1
41
22
Mute
Drive
MUTEC234
11
12
PCM
31
GND
GND
5
Micro-
Controller
VLC
0.1 µF
+ 1 .8 V to + 5 V 18
DSD
Audio
Source
2
48 DSDB2
3
42
DSD_SCLK
DSDA1
DSDB3
DSDA3
DSDA4
DSDB1
DSDA2
46
45
47
1
44 DSDB4
16
15 SCL/CCLK
SDA/CDIN
ADO/CS
RST
19
17
2 KΩ
2 KΩ
Note: Necessary for I2C
control port operation
Note*
14 DS514F2
CS4382
Digital
Audio
Source
VLS CS4382
MCLK
VD AOUTA1+
10
8
32
0.1 µF +1 µF
+ 3.3 V to + 5 V
SDIN1
9
1 µF 0.1 µ F
+
+
20
21
FILT+
VQ
7
6
LRCK1
SCLK1
SDIN3
SDIN2
39
40
0.1 µ F47 µ F
VA
0.1 µF
+
1 µF
0.1 µF
+ 1.8 V to + 5 V
+5 V
4
43
SDIN4
LRCK2
SCLK2
13
14
Analog C onditioning
and M uting
AOUTA1-
AOUTB1+
38
37
Analog C onditioning
and M uting
AOUTB1-
AOUTA2+
35
36
Analog C onditioning
and M uting
AOUTA2-
AOUTB2+
34
33 Analog C onditioning
and M uting
AOUTB2-
AOUTA3+ 29
30 Analog C onditioning
and M uting
AOUTA3-
AOUTB3+
28
27 Analog C onditioning
and M uting
AOUTB3-
AOUTA4+
25
26
Analog C onditioning
and M uting
AOUTA4-
AOUTB4+
24
23
Analog C onditioning
and M uting
AOUTB4-
MUTEC234
22
41
Mute
Drive
MUTEC1
11
12
PCM
31
GND
GND
5
Stand-Alone
Mode
Configuration
VLC
0.1 µF
+ 1 .8 V to + 5 V 18
DSD
Audio
Source
2
48 DSDB2
3
42 M3(DSD_SCLK)
DSDA1
DSDB3
DSDA3
DSDA4
DSDB1
DSDA2
46
45
47
1
44 DSDB4
16
15 M2
M1
M0
RST
19
17
47 KΩ
VLS NoteDSD
NoteDSD: F or DS D operation:
1) LRC K1 m ust be tied to VLS and
rem ain static high.
2) M 3 PC M stand-alone configuration
pin becomes D SD _SCLK
Mute
Drive
47 K Ω
NoteDSD
NoteVLC
NoteVLC: If series resistors are
used they m ust be <1 kO hm . If
possible tie V LC to the VD supply
to reduce possible excess current
consum ption from V LC.
Figure 6. Typical Connection Diagram Stand-Alone
DS514F2 15
CS4382
3. REGISTER QUICK REFERENCE
AddrFunction76543210
01h Mode Control 1 CPEN FREEZE MCLKDIV DAC4_DIS DAC3_DIS DAC2_DIS DAC1_DIS PDN
default00000001
02h Mode Control 2 Reserved DIF2 DIF1 DIF0 SDIN4CLK SDIN3 CLK SD IN2 CLK SDIN1CLK
default00000000
03h Mode Control 3 SZC1 SZC0 SNGLVOL RMP_UP MUTEC+/- AMUTE Reserved MUTEC
default10000100
04h Filter Control Reserved Reserved Reserved FILT_SEL Reserved DEM1 DEM0 RMP_DN
default00000000
05h Invert Control INV_B4 INV_A4 INV_B3 INV_A3 INV_B2 INV_A2 INV_B1 INV_A1
default00000000
06h Mixing Control
Pair 1 (AOUTx1) P1_A=B P1ATAPI4 P1ATAPI3 P1ATAPI2 P1ATAPI1 P1ATAPI0 P1FM1 P1FM0
default00100100
07h Vol. Control A1 A1_MUTE A1_VOL6 A1_VOL5 A1_VOL4 A1_VOL3 A1_VOL2 A1_VOL1 A1_VOL0
default00000000
08h Vol. Control B1 B1_MUTE B1_VOL6 B1_VOL5 B1_VOL4 B1_VOL3 B1_VOL2 B1_VOL1 B1_VOL0
default00000000
09h Mixing Control
Pair 2 (AOUTx2) P2_A=B P2ATAPI4 P2ATAPI3 P2ATAPI2 P2ATAPI1 P2ATAPI0 P2FM1 P2FM0
default00100100
0Ah Vol. Control A2 A2_MUTE A2_VOL6 A2_VOL5 A2_VOL4 A2_VOL3 A2_VOL2 A2_VOL1 A2_VOL0
default00000000
0Bh Vol. Control B2 B2_MUTE B2_VOL6 B2_VOL5 B2_VOL4 B2_VOL3 B2_VOL2 B2_VOL1 B2_VOL0
default00000000
0Ch Mixing Control
Pair 3 (AOUTx3) P3_A=B P3ATAPI4 P3ATAPI3 P3ATAPI2 P3ATAPI1 P3ATAPI0 P3FM1 P3FM0
default00100100
0Dh Vol. Control A3 A3_MUTE A3_VOL6 A3_VOL5 A3_VOL4 A3_VOL3 A3_VOL2 A3_VOL1 A3_VOL0
default00000000
0Eh Vol. Control B3 B3_MUTE B3_VOL6 B3_VOL5 B3_VOL4 B3_VOL3 B3_VOL2 B3_VOL1 B3_VOL0
default00000000
0Fh Mixing Control
Pair 4 (AOUTx4) P4_A=B P4ATAPI4 P4ATAPI3 P4ATAPI2 P4ATAPI1 P4ATAPI0 P4FM1 P4FM0
default00100100
10h Vol. Control A4 A4_MUTE A4_VOL6 A4_VOL5 A4_VOL4 A4_VOL3 A4_VOL2 A4_VOL1 A4_VOL0
default00000000
11h Vol. Con tro l B4 B4_MUTE B4_VOL6 B4_VOL5 B4_VOL4 B4_VOL3 B4_VOL2 B4_VOL1 B4_VOL0
default00000000
12h Chip Revision PART3 PART2 PART1 PART0 Reserved Reserved Reserved Reserved
default1010----
16 DS514F2
CS4382
4. REGISTER DESCRIPTION
Note: All registers are re ad /w rite in I²C Mod e an d writ e- on ly in SPI, un le ss oth e rwis e no te d.
4.1 Mode Control 1 (Address 01h)
4.1.1 Control Port Enable (CPEN)
Default = 0
0 - Disabled
1 - Enabled
Function:
This bit defaults to 0, allowi ng the devic e to powe r-up in Stan d-Alone Mode. The Contro l Port Mod e can
be accessed by setting this bit to 1. This will allow the operation of the device to be controlled by the reg-
isters and the pin definitions will conform to Control Port Mode. To accomplish a clean power-up, the user
should write this bit within 10 ms following the release of Reset.
4.1.2 F reeze Controls (FREEZE)
Default = 0
0 - Disabled
1 - Enabled
Function:
This function allows modifications to be made to the registers without the changes taking effect until the
FREEZE is disabled. To make multiple changes in the Control port registers take effect simultaneously,
enable the FREEZE bit, make all register changes, then Disable the FREEZE bit.
4.1.3 Master Clock Divide Enable (MCLKDIV)
Default = 0
0 - Disabled
1 - Enabled
Function:
The MCLKDIV bit enables a circuit which divi des the externally applied MC LK signal by 2 prior to all other
internal circuitry.
4.1.4 DAC Pair Disable (DACx_DIS)
Default = 0
0 - DAC Pair x Enabled
1 - DAC Pair x Disabled
Function:
When the bit is set, the respective DAC channel pair (AOUTAx and AOUTBx) will remain in a reset state.
It is advised that chan ges to th ese bits be made wh ile the powe r-down (PDN) bit is ena bled to elimin ate
the possibility of audible artifacts.
76543210
CPEN FREEZE MCLKDIV DAC4_DIS DAC3_DIS DAC2_DIS DAC1_DIS PDN
00000001
DS514F2 17
CS4382
4.1.5 Power Down (PDN)
Default = 1
0 - Disabled
1 - Enabled
Function:
The entire device will enter a low-power state when this function is enabled, and the contents of the control
registers are retained in this mode. The power-down bit defaults to ‘enabled’ on power-up and must be
disabled before normal operation in Control Por t Mode can occur.
4.2 Mode Control 2 (Address 02h)
4.2.1 Digital Interface Format (DIF)
Default = 000 - Format 0 (Left Justified, up to 24-bit data)
Function:
These bits select the interface format for the serial audio input. The Functional Mode bits determine
whether PCM or DSD Mode is selected.
PCM Mode: The requ ired relationship between the Left/Right clock, serial clock and serial data is defined
by the Digital Interface Format and the options are detailed in Figures 33-38.
Note: While in PCM Mode, the DIF bits shou ld only be changed whe n the power- down (PDN) bi t is set
to ensure proper switching from one mode to another.
76543210
Reserved DIF2 DIF1 DIF0 SDIN4CLK SDIN3CLK SDIN2CLK SDIN1CLK
00000000
DIF2 DIF1 DIF0 DESCRIPTION Format FIGURE
000
Left Justified, up to 24-bit data 033
001
I²S, up to 24-bit data 134
010
Right Justified, 16-bit data 235
011
Right Justified, 24-bit data 336
100
Right Justified, 20-bit data 437
101
Right Justified, 18-bit data 538
110
Reserved
111
Reserved
Table 1. Digital Interface Formats - PCM Mode
18 DS514F2
CS4382
DSD Mode: The relationship between the oversampling ratio of the DSD audio data and the required
Master clock to DSD data rate is defined by th e Digital Interface Format pins. An additional write of 99h
to register 00h and 80h to register 1Ah is required to access the modes denoted with *.
4.2.2 Serial Audio Data Clock Source (SDINXCLK)
Default = 0
0 - SDINx clocked by SCLK1 and LRCK1
1 - SDINx clocked by SCLK2 and LRCK2
Function:
The SDINxCLK bit specifies which SCLK/LRCK input pair is used to clock in the data on the given SDINx
line. For more details see “Clock Source Selection” on page 29.
4.3 Mode Control 3 (Address 03h)
4.3.1 Soft Ramp and Zero Cross Control (SZC)
Default = 10
00 - Immediate Change
01 - Zero Cross
10 - Soft Ramp
11 - Soft Ramp on Zero Crossings
Function:
Immediate Ch an ge
When Immediate Change is selected all level changes will take effect immediately in one step.
Zero Cross
Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur
on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a tim-
eout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal
does not encounter a zero crossing. The zero cross function is independently monitored and implemented
for each channel.
DIF2 DIF1 DIFO DESCRIPTION Note
0 0 0 64x oversampled DSD data with a 4x MCLK to DSD data rate
0 0 1 64x oversampled DSD data with a 6x MCLK to DSD data rate *
0 1 0 64x oversampled DSD data with a 8x MCLK to DSD data rate *
0 1 1 64x oversampled DSD data with a 12x MCLK to DSD data rate *
1 0 0 128x oversampled DSD data with a 2x MCLK to DSD data rate
1 0 1 128x oversampled DSD data with a 3x MCLK to DSD data rate *
1 1 0 128x oversampled DSD data with a 4x MCLK to DSD data rate *
1 1 1 128x oversampled DSD data with a 6x MCLK to DSD data rate *
Table 2. Digital Interface Formats - DSD Mode
76543210
SZC1 SZC0 SNGLVOL RMP_UP Reserved AMUTE Reserved MUTEC
10000100
DS514F2 19
CS4382
Soft Ramp
Soft Ramp allows level changes, both muting and attenuation, to be imp lemented by incrementa lly ramp-
ing, in 1/8 dB steps, from the current level to the n ew level at a rate of 1 dB per 8 left/right clock periods.
Soft Ramp on Zero Crossing
Soft Ramp and Zero Cross Enable dictates that signal level changes, either by attenuation changes or
muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change
will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz
sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently
monitored and implemented for each channel.
4.3.2 Single Volume Control (SNGLVOL)
Default = 0
0 - Disabled
1 - Enabled
Function:
The individual channel volume levels are independently controlled by their respective Volume Control
Bytes when this function is disabled. The volume on all channels is determined by the A1 Channel Vol-
ume Control Byte, and the other Volume Control Bytes are ignored when this function is enabled.
4.3.3 Soft Volume Ramp-Up After Error (RMP_UP)
Default = 0
0 - Disabled
1 - Enabled
Function:
An un-mute will be performed after executing a filter mode change, af ter a LRCK/MCLK ratio change or
error, and after changing the Functional Mode. When this feature is enabled, this un-mute is effected,
similar to attenuation changes, by the Soft and Zero Cross bits in the Mode Control 3 register. When dis-
abled, an immediate un-mute is performed in these instances.
Note: For best results, it is recommende d that this feature be used in conjunction with the RMP_DN bit.
4.3.4 Mutec Polarity (MUTEC+/-)
Default = 0
0 - Active High
1 - Active Low
Function:
The active polarity of the MUTEC pin(s) is determined by this register. When set to 0 (default), the MUTEC
pins are high when active. When set to 1 the MUTEC pin(s) are low when active.
Note: When the onboard mute circuitry is designed for active low, the MUTEC outputs will be high (un-
muted) for the period of time during reset and before this bit is enabled to 1.
20 DS514F2
CS4382
4.3.5 Auto-Mute (AMUTE)
Default = 1
0 - Disabled
1 - Enabled
Function:
The Digital-to-Analog converter output will mute following the reception of 8192 consecutive audio sam-
ples of static 0 or -1. A single sample of non-static data will release the mute. Detection and muting is
done independently for each channel. The quiescent voltage on the output will be retained and the Mute
Control pin will go active during the mute period. The muting function is affected, similar to volume control
changes, by the Soft and Zero Cross bits in the Mode Control 3 register.
4.3.6 Mutec Pin Control (MUTEC)
Default = 0
0 - Two Mute control signals
1 - Single mute control signal on MUTEC1
Function:
Selects how the internal mute signals are routed to the MUTEC1 and MUTEC234 pins. When set to ‘0’,
a logical AND of DAC pair 1 mute control signals are output on MUTEC1 and a logical AND of the mute
control signals of DAC pairs 2, 3, and 4 are output on MUTEC234. When set to ‘1’, a logical AND of all
DAC pair mute control signals is ou tput on the MUTEC1 pin, MUTEC234 will remain stat ic. For more in-
formation on the use of the mute control function see the MUTEC1 and MUTEC234 pins in Section 5. Pin
Description.
4.4 Filter Control (Address 04h)
4.4.1 Interpolation Filter Select (FILT_SEL)
Default = 0
0 - Fast roll-off
1 - Slow roll-off
Function:
This Function allows the user to select whether the interpolation filter has a fast or slow roll off. For filter
characteristics please see Section 1.
4.4.2 De-Emphasis Control (DEM)
Default = 00
00 - Disabled
01 - 44.1 kHz
10 - 48 kHz
11 - 32 kHz
Function:
76543210
Reserved Reserved Reserved FILT_SEL Reserved DEM1 DEM0 RMP_DN
00000000
DS514F2 21
CS4382
Selects the appropriate digital filter to maintain the standard 15 ms/50 ms digital de-emphasis filter re-
sponse at 32, 44.1 or 48 kHz sample rates. (see Figure 39)
De-emphasis is only available in Single-Speed Mode.
4.4.3 Soft Ramp-Down Before Filter Mode Change (RMP_DN)
Default = 0
0 - Disabled
1 - Enabled
Function:
A mute will be performed prior to executing a filter mode change. When this feature is enabled, this mute
is effected, similar to attenuation changes, by the Soft and Zero Cross bits in the M ode Control 3 register .
When disabled, an immediate mute is performed prior to executing a filter mode change.
Note: For best results, it is recommended that this feature be used in conjunction with the RMP_UP bit.
4.5 Invert Control (Address 05h)
4.5.1 Invert Signal Polarity (INV_XX)
Default = 0
0 - Disabled
1 - Enabled
Function:
When enabled, these bits will invert the signal polarity of their respective channels.
4.6 Mixing Control Pair 1 (Channels A1 & B1)(Address 06h)
Mixing Control Pair 2 (Channels A2 & B2)(Address 09h)
Mixing Control Pair 3 (Channels A3 & B3)(Address 0Ch)
Mixing Control Pair 4 (Channels A4 & B4)(Address 0Fh)
4.6.1 Channel A Volume = Channel B Volume (A=B)
Default = 0
0 - Disabled
1 - Enabled
Function:
The AOUTAx and AOUTBx volume levels are independently controlled by the A and the B Channel Vol-
ume Control Bytes when this function is disabled. The volume on both AOUTAx and AOUTBx a re deter-
mined by the A Channel Attenuation and Volume Control Bytes (per A-B pair), and the B Channel Bytes
are ignored when this function is enabled.
76543210
INV_B4 INV_A4 INV_B3 INV_A3 INV_B2 INV_A2 INV_B1 INV_A1
00000000
76543210
Px_A=B PxATAPI4 PxATAPI3 PxATAPI2 PxATAPI1 PxATAPI0 PxFM1 PxFM0
00100100
22 DS514F2
CS4382
4.6.2 ATAPI Channel Mixing and Muting (ATAPI)
Default = 01001 - AOUTAx=aL, AOUTBx=bR (Stereo)
Function:
The CS4382 implements the channel mixing functions of the ATAPI CD-ROM specification. The ATAPI
functions are applied per A-B pair. Refer to Table 3 and Figure 41 for additional information.
ATAPI4 ATAPI3 ATAPI2 ATAPI1 ATAPI0 AOUTAx AOUTBx
00000 MUTE MUTE
00001 MUTE bR
00010 MUTE bL
00011 MUTE b[(L+R)/2]
00100 aR MUTE
00101 aR bR
00110 aR bL
00111 aR b[(L+R)/2]
01000 aL MUTE
01001 aL bR
01010 aL bL
01011 aL b[(L+R)/2]
0 1 1 0 0 a[(L+R)/2] MUTE
01101 a[(L+R)/2] bR
01110 a[(L+R)/2] bL
0 1 1 1 1 a[(L+R)/2] b[(L+R)/2]
10000 MUTE MUTE
10001 MUTE bR
10010 MUTE bL
10011 MUTE [(aL+bR)/2]
10100 aR MUTE
10101 aR bR
10110 aR bL
10111 aR [(bL+aR)/2]
11000 aL MUTE
11001 aL bR
11010 aL bL
11011 aL [(aL+bR)/2]
11100[(aL+bR)/2] MUTE
11101[(aL+bR)/2] bR
11110[(bL+aR)/2] bL
1 1 1 1 1 [(aL+bR)/2] [(aL+bR)/2]
Table 3. ATAPI Decode
DS514F2 23
CS4382
4.6.3 Functional Mode (FM)
Default = 00
00 - Single-Speed Mode (4 to 50 kHz sample rates)
01 - Double-Speed Mode (50 to 100 kHz sample rates)
10 - Quad-Speed Mode (100 to 200 kHz samp le rates)
11 - Direct Stream Digital Mode
Function:
Selects the required range of input sample rates or DSD Mode. When DSD Mode is selected for any chan-
nel pair then all pairs will switch to DSD Mode.
4.7 Volume Control (Addresses 07h, 08h, 0Ah, 0Bh, 0Dh, 0Eh, 10h, 11h)
4.7.1 Mute (MUTE)
Default = 0
0 - Disabled
1 - Enabled
Function:
The Digital-to-Analog converter output will mute when enabled. The quiescent voltage on the output will
be retaine d. The m uting fun ction is e ffected, similar to attenuation changes, by the Soft and Zero Cross
bits. The MUTEC pins will go active during the mute period according to the MUTEC register.
4.7.2 Volume Control (xx_VOL)
Default = 0 (No attenuation)
Function:
The Digital Volume Control registers allow independent control of the signal levels in 1 dB increments
from 0 to -127 dB. Volume settings are decoded as shown in Table 4. The volume changes are imple-
mented as dictated by the Soft and Zero Cross bits. All volume settings less than -127 dB are equivalent
to enabling the MUTE bit.
76543210
xx_MUTE xx_VOL6 xx_VOL5 xx_VOL4 xx_VOL3 xx_VOL2 xx_VOL1 xx_VOL0
00000000
Binary Code Decimal Value Volume Setting
0000000 0 0 dB
0010100 20 -20 dB
0101000 40 -40 dB
0111100 60 -60 dB
1011010 90 -90 dB
Table 4. Example Digital Volume Settings
DS514F2 25
CS4382
5. PIN DESCRIPTION
Pin Name # Pin Description
VD 4 Digital Power (Input) - Positive power supply for the digital section. Refer to the Recommended Operat-
ing Conditions for appropria te voltages.
GND 5
31 Ground (Input) - Ground reference. Should be connected to analog ground.
MCLK 6 Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters. Table 5 illustrates
several standard audio sample rates and the required master clock frequency.
LRCK1
LRCK2 7
10 Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial audio
data line. The frequency of the left/right clock must be at the audio sample rate, Fs.
SDIN1
SDIN2
SDIN3
SDIN4
8
11
13
14
Serial Audio Da ta Input (Input) - Input for two’s complement serial audio data.
SCLK1
SCLK2 9
12 Serial Clock (Input) - Serial clock for the serial audio interface.
VLC 18 Control Port Power (Input) - Determines the required signal level for the control port. Refer to the Rec-
ommended Operating Conditions for appropria te voltages.
RST 19 Reset (Input) - The device enters a low power mode and all internal registers are reset to their default
settings when low.
FILT+ 20 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.
Requires the capacitive decoupling to analog ground, as shown in the Typical Connection Diagram.
VQ 21
Quiescent Voltage (Output) - Filter connection for internal quiescent voltage. VQ mu st be capacitively
coupled to analog ground, as shown in the Typical Connection Diagram. The nominal voltage level is
specified in the Analog Characteristics and Specifications section. VQ presents an appreciable source
impedance and any current drawn from this pin will alter device performance.
However, VQ can be used to bias the analog circuitry assuming there is no AC signal component and
the DC current is less than the maximum specified in the Analog Characteristics and Specifications sec-
tion.
SDIN3
GND
AOUTB2-
AOUTA3+
AOUTB3-
AOUTB2+
VA
AOUTA3-
AOUTB3+
6
2
4
8
10
1
3
5
7
9
11
12 13 14 15 16 17 18 19 20 21 22 23 24
31
35
33
29
27
36
34
32
30
28
26
25
48 47 46 45 44 43 42 41 40 39 38 37
MCLK
DSDB1
VD
SDIN1
LRCK2
DSDA2
DSDA1
GND
SCLK1
SDIN2
SCLK2
LRCK1(DSD_EN)
M3(DSD_SCLK)
DSDB3
DSDA3
DSDA4
CS4382
DSDB4
VLS
SDIN4
M2(SCL/CCLK)
M1(SDA/CDIN)
VLC
RST
FILT+
VQ
MUTEC234
M0(AD0/CS)
AOUTA2+
AOUTA2-
AOUTB1+
AOUTB1-
AOUTA1-
AOUTA1+
DSDB2
MUTEC1
AOUTA4-
AOUTA4+
AOUTB4+
AOUTB4-
26 DS514F2
CS4382
MUTEC1
MUTEC234 41
22
Mute Control (Output) - The Mute Control pins go high during power-up initialization, reset, muting,
power-down or if the master clock to left/right clock frequency ratio is incorrect. These pins are intended
to be used as a control for external mute circuits to prevent the clicks and pops that can occur in any sin-
gle supply system. The use of external mute circuits are not mandatory but may be desired for designs
requiring the absolute minimum in extraneous clicks and pops.
AOUTA1 +,-
AOUTB1 +,-
AOUTA2 +,-
AOUTB2 +,-
AOUTA3 +,-
AOUTB3 +,-
AOUTA4 +,-
AOUTB4 +,-
39, 40
38, 37
35, 36
34, 33
29, 30
28, 27
25, 26
24, 23
Differential Analog Output (Output) - The full scale differential analog output level is specified in the
Analog Characteristics specificatio n table.
VA 32 Analog Power (Input) - Positive power supply for the analog section. Refer to the Recommended Oper-
ating Conditions for appropriate voltages.
VLS 43 Serial Audio Interface Power (Input) - Determines the requ ired signal level for the seria l audio inter-
face. Refer to the Recommended Operating Conditions for appropriate voltages.
Control Port Definitions
SCL/CCLK 15 Serial Control Port Clock (Input) - Serial clock for the serial control port. Requires an external pull-up
resistor to the logic interface voltage in I²C Mode as shown in the Typical Connection Diagram.
SDA/CDIN 16 Serial Control Dat a (Input/Output) - SDA is a data I/O line in I²C Mode and requires an external pull-up
resistor to the logic interface voltage, as shown in the Typical Connection Diagram. CDIN is the input
data line for the control port interface in SPI Mode.
AD0/CS 17 Addre ss Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pi n in I²C Mode;
CS is the chip select signal for SPI format.
Sta nd-Alone Definitions
M0
M1
M2
M3
17
16
15
42
Mode Selection (Input) - Determines the operational mode of the device as detailed in Tables 6 and 7.
DSD Definitions
DSD_SCLK 42 DSD Serial Clock (Input) - Serial clock for the Direct Stream Digit al audio interface.
DSD_EN 7 DSD-Enable (Input) - When held at logic ‘1’ the device will enter DSD Mode (Stand-Alone Mode only).
DSDA1
DSDB1
DSDA2
DSDB2
DSDA3
DSDB3
DSDA4
DSDB4
3
2
1
48
47
46
45
44
Direct Stream Digital Input (Input) - Input for Direct Stream Digital serial audio data.
Pin Name # Pin Description
DS514F2 27
CS4382
Mode
(sample-rate range) Sample
Rate
(kHz)
MCLK (MHz) Control port
only modes
MCLK Ratio 256x 384x 512x 768x* 1024x*
Single-Speed
(4 to 50 kHz) 32 8.1920 12.2880 16.3840 24.5760 32.7680
44.1 11.2896 16.9344 22.5792 33.8688 45.1584
48 12.2880 18.4320 24.5760 36.8640 49.1520
MCLK Ratio 128x 192x 256x 384x 512x*
Double-Speed
(50 to 100 kHz) 64 8.1920 12.2880 16.3840 24.5760 32.7680
88.2 11.2896 16.9344 22.5792 33.8688 45.1584
96 12.2880 18.4320 24.5760 36.8640 49.1520
MCLK Ratio 64x 96x 128x 192x 256x*
Quad-Speed
(100 to 200 kHz) 176.4 11.2896 16.9344 22.5792 33.8688 45.1584
192 12.2880 18.4320 24.5760 36.8640 49.1520
Note: *These modes are only available in Co ntrol Port Mode by setting the MCLKDIV bit = 1.
Table 5. Common Clock Frequencies
M1
(DIF1) M0
(DIF0) DESCRIPTION FORMAT FIGURE
0 0 Left Justified, up to 24-bit data 0 33
0 1 I²S, up to 24-bit data 1 34
1 0 Right Justified, 16-bit Data 2 35
1 1 Right Justified, 24-bit Data 3 36
Table 6. Digital Interface Forma t, Stand-Alone Mode Options
M3 M2
(DEM) DESCRIPTION
0 0 Single-Speed without De-Emphasis (4 to 50 kHz sample rates)
0 1 Single-Speed with 44.1 kHz De-Emphasis; see Figure 39
1 0 Double - Speed (50 to 100 kHz sample rates)
1 1 Quad-Speed (100 to 200 kHz sample rates)
Table 7. Mode Selection, Stand-Alone Mode Options
DSD_Mode
(LRCK1) M2 M1 M0 DESCRIPTION
1 0 0 0 64x oversampled DSD data with a 4x MCLK to DSD data rate
1001Reserved
1010Reserved
1011Reserved
1 1 0 0 128x oversample d DSD dat a w it h a 2x MCLK to DSD data rate
1101Reserved
1110Reserved
1111Reserved
Table 8. Direct Stream Digital (DSD), Stand-Alone Mode Options
28 DS514F2
CS4382
6. APPLICATIONS
6.1 Grounding and Power Supply Decoupling
As with any high resolution converter, the CS4382 requires careful attention to power supply and grounding arrange-
ments to optimize performance. Figures 5 and 6 show the recommend ed power arrangement with VA, VD, VLS and
VLC connected to clean supp lies. Decoupling capacitors should be located as close to the device package as pos-
sible. If desired, all supply pins may be connected to the same supply, but a decoupling capacitor should still be
placed on each supply pin (see Section 1. Char a cte ristics and Specif ica tio ns for recommended voltages).
6.2 PCM Mode Select
The CS4382 opera tes in one o f three PCM over sampling modes based on the input sam ple rate. Mode se-
lection is determined by the M3 and M2 pins in Stand-Alone Mode or the FM bits in Control Port Mode. Sin-
gle-Speed Mode supports input sample rates up to 50 kHz and uses a 128x oversampling ratio. Double-
Speed Mode supports input sample rates up to 100 kHz and uses an oversampling ratio of 64x. Quad-
Speed Mode supports input sample rates up to 200 kHz and uses an oversampling ratio of 32x. The PCM
digital interface fo rmat is determin ed by the M1 and M0 pins in Stand-Alo ne Mode or the DIF bits in Control
Port Mode.
In Stand-Alone Mode, the states of these pins are continually scanned for changes; however, the mode
should only be changed while the device is in reset (RST pin low) to ensure proper switching from one mode
to another.
6.3 Recommended Power-Up Sequence
1. Hold RST low until the power supply, master, and left/right clocks are stable. In this state, the control
port is reset to its default settings and VQ will remain low.
2. Bring RST high. The device will remain in a low power state with VQ low and will initiate the Stand-Alone
power-up sequence. The control port will be accessible at this time. If Control Port operation is desired,
write the CPEN bit prior to the completion of the Stand-Alone power-up sequence, approximately 512
LRCK cycles in Single-Speed Mode (1024 LRCK cycles in Double-Speed Mode, and 2048 LRCK cycles
in Quad-Speed Mode). Writing this bit will halt the Stand-Alone power-up sequence and initialize the
control port to its default settings. The desired register settings can be loaded while keeping the PDN
bit set to 1.
3. If Control Port Mode is selected via the CPEN bit, set the PDN bit to 0 which will initiate the pow er-up
sequence.
6.4 Analog Output and Filtering
The application note “Design Notes for a 2-Pole Filter with Differential Input” discusses the second-order
Butterworth filter and differential to single-ended converter which was implemented on the CS4382 evalua-
tion board, C DB438 2, as seen in Figu re 42. The CS4382 does not include phase or amplitude compensa-
tion for an external filter. Therefore, the DAC system phase and amplitude response will be dependent on
the external an alo g circu itry .
6.5 Interpolation Filter
To accommodate the increasingly complex requireme nts of digital audio systems, the CS4382 incorporates
selectable interpolation filters for each mode of operation. A “fast” and a “slow” roll-off filter is available in
each of Single, Double, and Qua d- Spee d mode s. Th ese filters h ave b een de signe d to acco mmodate a va-
riety of musical tastes and styles. The FILT_SEL bit is used to select which filter is used (see the control
port section for more details).
DS514F2 29
CS4382
When in Stand-Alone Mode, only the “fast” roll-off filter is available.
Filter specifications can be found in Section 1, and filter response plots can be foun d in Figures 9 to 32.
6.6 Clock Source Selection
The CS4382 has two serial clock and two left/right clock inputs. The SDINxCLK bits in the control port allow
the user to set which SCLK/LRCK pair is used to latch the data for each SDINx pin. The clocks applied to
LRCK1 and LRCK2 mus t be de rived from the sam e MC LK and must be exact frequency multiples of each
other as specified in the “Switching Characteristics” on page 9. When using both SCLK1/LRCK1 and
SCLK2/LRCK2, if either SCLK/LRCK pair loses synchronization then both SCLK/LRCK pairs will go through
a retime period where the device is re-evaluating clock ratios. During the retime period all DAC pair s are
temporarily inactive, outputs are muted, and the mute control pins will go activ e according to the MUTEC
register.
If unused, SCLK2 and LRCK2 should be tied static low and SDINx bits should all be set to SCLK1/LRCK1.
In Stand-Alo ne Mode, all D AC pairs use SCLK1 and LRCK1 for timing and SCLK2/LRCK2 should be tied
to ground.
6.7 Using DSD Mode
In Stand-Alone Mode, DSD operation is selected by holding DSD_EN(LRCK1) high and applying the DSD
data and clocks to the appropriate pins. The M2:0 pins set the expected DSD rate and MCLK ratio.
In Control Port Mode, the FM bits set the device into DSD Mode (DSD_EN pin is not required to be held
high). The DIF register then contro ls the expected DSD rate and MCLK ratio. To access the full range of
DSD clocking modes (other than 64 x DSD 4x MCLK and 128x DSD 2x MCLK) the following addition al reg-
ister sequence needs to be written:
99h to register 00h
80h to register 1Ah
00h to register 00h
When exiting DSD Mode the following additional sequence needs to be written:
99h to register 00h
00h to register 1Ah
00h to register 00h
During DSD operation, the PCM related pins should either be tied low or remain active with clocks (except
LRCK1 in Stand-Alone Mode). When the DSD related pins are not being used they should either be tied
static low, or remain active with clocks (except M3 in Stand-Alone Mode).
7. CONTROL PORT INTERFACE
The control port is used to load all the internal settings. The operation of the control port may be completely asyn-
chronous with the audio sample rate . However, to avoid potential interference problems, the control port pins should
remain static if no operation is required.
The CS4382 has MAP auto increment capability, enabled by the INCR bit in the MAP register, which is the MSB. If
INCR is 0, then the MAP will stay constant for successive writes. If INCR is set to 1, then MAP will auto increment
after each byte is written from register 01h to 08h and then from 09h and 11 h, allowing block rea ds or writes of suc-
cessive registers in two separate sections (the counter will not auto-increment to register 09h from register 08h).
30 DS514F2
CS4382
7.1 Enabling the Control Port
On the CS 4382 the cont rol p ort pins are shar ed w ith st and- alon e co nfigu ratio n pi ns. T o e nabl e the contr ol
port, the user must set the CPEN bit. This is done by perfor ming a I²C or SPI writ e. Once th e control port is
enabled, these pins are dedicated to control port functionality.
To prevent audible artifacts, the CPEN bit (see Section 4.1.1) should be set prior to the completion of the
Stand-Alone power-up sequence, approximately 1024 LRCK cycles. Writing this bit will halt the Stand-Alone
power-up sequence and initialize the control port to its default settings. Note, the CP_EN bit can be set any
time after RST goes high; however, setting this bit after the Stand-Alone power-up sequence has completed
can cause audible artifacts.
7.2 Format Selection
The control port has 2 formats: SPI and I²C, with the CS4382 operating as a slave device.
If I²C operation is desired, AD0/CS should be tied to VLC or GND. If the CS4382 ever detects a high to lo w
transition on AD0/CS after power-up and after the control port is activated, SPI format will be selected.
7.3 I²C Format
In I²C Format, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL,
with a clock to data relationship as shown in Figure 7. The receiving device should send an acknowledge
(ACK) after each byte received. There is no CS pin. Pin AD0 forms the partial chip address and should be
tied to VLC or GND as required. The upper 6 bits of the 7 bit address field must be 001100.
Note: MCLK is required during all I²C transactions. Please see “References” on page 40 to obtain addi-
tional information on the I²C Bus specification or visit http://www.semiconductors.philips.com.
7.3.1 Writing in I²C Format
To communicate with the CS4382, initiate a START condition of the bus. Next, send the chip address.
The eighth bit of the address byte is the R/W bit (low for a write). Th e next byte is the Memory Add ress
Pointer, MAP, which selects the re gister to be re ad or written. The MAP is then followed by the data to be
written. To write multiple registers, continue providing a clock and data, waiting for the CS4382 to ac-
knowledge between each byte. To end the transaction, send a STOP condition.
7.3.2 Reading in I²C Format
To communicate with the CS4382, initiate a START condition of the bus. Next, send the chip address.
The eighth bit of the address byte is the R/W bit (high for a read). The contents of the register pointed to
by the MAP will be output after the chip address. To read multiple registers, continue providing a clock
and issue an ACK after each byte. To end the transaction, send a STOP condition.
7.4 SPI Format
In SPI format, CS is the CS4382 chip select signal, CCLK is the control port bit clock, CDIN is the input data
line from the m icr ocontr olle r and the chip address is 0011000. CS, CCLK an d CDIN are a ll in puts a nd data
is clocked in on the rising edge of CCLK.
Note: The CS4382 is write-only when in SPI format.
DS514F2 31
CS4382
7.4.1 Writing in SPI
Figure 8 shows the operation of the control port in SPI format. To writ e to a register, bring CS low. The
first 7 bits on CDIN form the chip address and must be 0011000. The eighth bit is a read/write indicator
(R/W), which must be low to write. The next 8 bits form the Memory Address Pointer (MAP), which is set
to the address of the register that is to be updated. The next 8 bits are the data which will be placed into
register designated by the MAP. To write multiple registers, keep CS low and continue providing clocks
on CCLK. End the read transaction by setting CS high.
7.5 Memory Address Pointer (MAP)
7.5.1 INCR (Auto Map Increment Enable)
Default = ‘0’
0 - Disabled
1 - Enabled
Note: When Auto Map Increment is enabled, the register must be written it two s eparate blocks: from
register 01h to 08h and then from 09h and 11h. The counter will not auto-increment to register 09h from
register 08h
76543210
INCR Reserved Reserved MAP4 MAP3 MAP2 MAP1 MAP0
00000000
SDA
SCL
001100 ADDR
AD0 R/W
Start
ACK DATA
1-8 ACK DATA
1-8 ACK
Stop
Note: If operation is a write, this byte contains the Memory Address Pointer, MAP.
Note 1
Figure 7. Control Port Timing, I²C Format
MAP
MSB LSB
DATA
byte 1 byte n
R/W
MAP = Memory Address Pointer
ADDRESS
CHIP
CDIN
CCLK
CS
0011000
Figure 8. Control Port Timing, SPI Format
DS514F2 33
CS4382
8. FILTER PLOTS
0.4 0.5 0.6 0.7 0.8 0.9
1
120
100
80
60
40
20
0
Frequency(normalized to Fs)
Amplitude (dB)
0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0.
6
120
100
80
60
40
20
0
Frequency(normalized to Fs)
Amplitude (dB)
Figure 9. Single-Speed (fast) Stopband Rejection Figure 10. Single-Speed (fast) Transition Band
0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5
5
10
9
8
7
6
5
4
3
2
1
0
Frequency(normalized to Fs)
Amplitude (dB)
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.
5
0.02
0.015
0.01
0.005
0
0.005
0.01
0.015
0.02
Frequency(normalized to Fs)
Amplitude (dB)
Figure 11. Single-Speed (fast) Transition Band
(detail) Figure 12. Single-Speed (fast) Passband Ripple
0.4 0.5 0.6 0.7 0.8 0.9
1
120
100
80
60
40
20
0
Frequency(normalized to Fs)
Amplitude (dB)
0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0.
6
120
100
80
60
40
20
0
Frequency(normalized to Fs)
Amplitude (dB)
Figure 13. Single-Speed (slow) Stopband Reject ion Figure 14. Single-Speed (slow) Transition Band
34 DS514F2
CS4382
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.
5
0.02
0.015
0.01
0.005
0
0.005
0.01
0.015
0.02
Frequency(normalized to Fs)
Amplitude (dB)
0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5
5
10
9
8
7
6
5
4
3
2
1
0
Frequency(normalized to Fs)
Amplitude (dB)
Figure 15. Single-Speed (slow) Transition Band
(detail) Figure 16. Single-Speed (slow) Passband Ripple
0.4 0.5 0.6 0.7 0.8 0.9
1
120
100
80
60
40
20
0
Frequency(normalized to Fs)
Amplitude (dB)
0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0.
6
120
100
80
60
40
20
0
Frequency(normalized to Fs)
Amplitude (dB)
Figure 17. Double-Speed (fa st) Stopba nd Rejection Figure 18. Double-Speed (fast) Transition Band
0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5
5
10
9
8
7
6
5
4
3
2
1
0
Frequency(normalized to Fs)
Amplitude (dB)
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.
5
0.02
0.015
0.01
0.005
0
0.005
0.01
0.015
0.02
Frequency(normalized to Fs)
Amplitude (dB)
Figure 19. Double-Speed (fast) Transition Band
(detail) Figure 20. Double-Speed (fast) Passband Ripple
DS514F2 35
CS4382
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
120
100
80
60
40
20
0
Frequency(normalized to Fs)
Amplitude (dB)
0.2 0.3 0.4 0.5 0.6 0.7 0.
8
120
100
80
60
40
20
0
Frequency(normalized to Fs)
Amplitude (dB)
Figure 21. Double-Speed (slow) Stopba nd Rejection Figure 22. Double-Speed (slow) Transition Band
0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5
5
10
9
8
7
6
5
4
3
2
1
0
Frequency(normalized to Fs)
Amplitude (dB)
0 0.05 0.1 0.15 0.2 0.25 0.3 0.3
5
0.02
0.015
0.01
0.005
0
0.005
0.01
0.015
0.02
Frequency(normalized to Fs)
Amplitude (dB)
Figure 23. Double-Speed (slow) Transition Band
(detail) Figure 24. Double-Speed (slow) Passband Ripple
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
120
100
80
60
40
20
0
Frequency(normalized to Fs)
Amplitude (dB)
0.2 0.3 0.4 0.5 0.6 0.7 0.
8
120
100
80
60
40
20
0
Frequency(normalized to Fs)
Amplitude (dB)
Figure 25. Quad-Speed (fast) Stopband Rejection Figure 26. Quad-Speed (fast) Transition Band
36 DS514F2
CS4382
0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5
5
10
9
8
7
6
5
4
3
2
1
0
Frequency(normalized to Fs)
Amplitude (dB)
0 0.05 0.1 0.15 0.2 0.2
5
0.2
0.15
0.1
0.05
0
0.05
0.1
0.15
0.2
Frequency(normalized to Fs)
Amplitude (dB)
Figure 27. Quad-Speed (fast) Transition Band
(detail) Figure 28. Quad-Speed (fast) Passband Ripple
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
120
100
80
60
40
20
0
Frequency(normalized to Fs)
Amplitude (dB)
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
9
120
100
80
60
40
20
0
Frequency(normalized to Fs)
Amplitude (dB)
Figure 29. Quad-Speed (slow) Stopband Rejection Figure 30. Quad-Speed (slow) Transition Band
0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5
5
10
9
8
7
6
5
4
3
2
1
0
Frequency(normalized to Fs)
Amplitude (dB)
0 0.02 0.04 0.06 0.08 0.1 0.1
2
0.02
0.015
0.01
0.005
0
0.005
0.01
0.015
0.02
Frequency(normalized to Fs)
Amplitude (dB)
Figure 31. Quad-Speed (slow) Transition Band
(detail) Figure 32. Quad-Speed (slow) Passband Ripple
DS514F2 37
CS4382
9. DIAGRAMS
LRCK
SCLK
Left Channel Right Channel
SDINx +3 +2 +1+5 +4
-1 -2 -3 -4 -5 +3 +2 +1+5 +4
-1 -2 -3 -4
MSB LSB MSB LSB
Figure 33. Format 0 - Left Justified up to 24-bit Data
LRCK
SCLK
Left Channel Right Channel
SDINx +3 +2 +1+5 +4
-1 -2 -3 -4 -5 +3 +2 +1+5 +4
-1 -2 -3 -4
MSB MSB
LSB LSB
Figure 34. Format 1 - I²S up to 24-bit Data
LRCK
SCLK
Left Channel Right Channel
SDINx 6543210987
15 14 13 12 11 10 6543210987
15 14 13 12 11 10
32 clocks
Figure 35. Format 2 - Right Justified 16-bit Data
LRCK
SCLK
Left Channel
SDINx 65432107
23 22 21 20 19 18 65432107
23 22 21 20 19 18
32 clocks
0
Right Channel
Figure 36. Format 3 - Right Justified 24-bit Data
38 DS514F2
CS4382
LRCK
SCLK
Left Channel Right Channel
SDINx 6543210987
15 14 13 12 11 10
10 6543210987
15 14 13 12 11 10
17 16 17 16
32 clocks
19 18 19 18
Figure 37. Format 4 - Right Justified 20-bit Data
LRCK
SCLK
Left Channel Right Channel
SDINx 6543210987
15 14 13 12 11 10
10 6543210987
15 14 13 12 11 10
17 16 17 16
32 clocks
Figure 38. Format 5 - Right Justified 18-bit Data
Figure 39. De-Emphasis Curve
Gain
dB
-10dB
0dB
Frequency
T2 = 15 µs
T1=50 µs
F1 F2
3.1 83 kHz 10.61 kHz
SDINx Channel
Pair x
Control
DAC
DAC
AOUTAx+
AOUTAx-
AOUTBx+
AOUTBx-
L
R
Figure 40. Channel Pair Routing Diagram (x = Channel Pair 1, 2, 3, or 4)
40 DS514F2
CS4382
10.PARAMETER DEFINITIONS
Total Harmonic Distortion + Noise (THD+N)
The ratio of the rms valu e of th e signa l to th e rms sum of all other spectral components over the specified
bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels.
Dynamic Range
The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the
specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made
with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full
scale. This technique ensu res that the distortion components are be low the noise level and do not effect the
measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-
1991, and the Electronic Industries Association of Japan, EIAJ CP-307.
Interchannel Isolation
A measure of crosstalk between the left and right channels. Measured for each channel at the converter's
output with all zeros to the inpu t under test and a full-scale signal applied to the other channel. Units in deci-
bels.
Interchannel Gain Mismatch
The gain difference between left and right channels. Units in decibels.
Gain Error
The deviation from the nominal full scale analog output for a full scale digital input.
Gain Drift
The change in gain value with temperature. Units in ppm/°C.
11.REFERENCES
1. How to Achieve Optimum Performance from Delta-Sigma A/D & D/A Converters by Steven Harris. Paper
presented at the 93rd Convention of the Audio Engineering Society, October 1992.
2. CDB4382 Evaluation Board Datasheet
3. Design Notes for a 2-Pole Filter with Differential Input by Steven Green. Cirrus Logic Application Note AN48,
available at http:www.cirrus.com
4. The I²C-Bus Specification: Versio n 2. 0 Philips Semiconductors, December 1998.
http://www.semiconductors.philips.com
DS514F2 41
CS4382
12.PACKAGE DIMENSIONS
INCHES MILLIMETERS
DIM MIN NOM MAX MIN NOM MAX
A --- 0.055 0.063 --- 1.40 1.60
A1 0.002 0.004 0.006 0.05 0.10 0.15
B 0.007 0.009 0.011 0.17 0.22 0.27
D 0.343 0.354 0.366 8.70 9.0 BSC 9.30
D1 0.272 0.28 0.280 6.90 7.0 BSC 7.10
E 0.343 0.354 0.366 8.70 9.0 BSC 9.30
E1 0.272 0.28 0.280 6.90 7.0 BSC 7.10
e* 0.016 0.020 0.024 0.40 0.50 BSC 0.60
L 0.018 0.24 0.030 0.45 0.60 0.75
µ 0.000° 4° 7.000° 0.00° 4° 7.00°
* Nominal pin pitch is 0.50 mm
Controlling dimension is mm.
JEDEC Designation: MS022
48L LQFP PACKAGE DRAWING
E1
E
D1
D
1
e
L
∝
B
A1
A
42 DS514F2
CS4382
13.ORDERING INFORMATION
14.REVISION HISTORY
Product Description Package Pb-Free Grade Temp Range Container Order #
CS4382 114 dB, 192 kHz 8-
channel D/A Converter 48-pin
LQFP YES Commercial -10°C to +70°C Tray CS4382-KQZ
Tape and Reel CS4382-KQZR
CDB4382 CS4382 Evaluation Board - - - - CDB4382
Release Changes
F1
Removed -BQ orde ri n g op ti o n
Corrected specifications for Full Scale Differential Output Voltage
Updated Table 2 on page 18
Updated Section 6.7 “Using DSD Mode” on page 29
Updated legal text
F2
Corrected DAC Pair Disable register description in Section 4.1.4
Added note to Digital Interface Format in Se ction 4.2.1
Added PCM mode format changeable only in reset to Section 6.2
Updated Packa ge Thermal Resistance in “Power and Thermal Characteristics” on page 6
Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representative.
To find the one nearest you, go to www.cirrus.com.
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject
to change without not ice and is pr ovided "AS IS" witho ut warr anty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and co nditio ns of sa le
supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus
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copyrights, tradem arks, trade secrets or oth er intellectual p roperty rights. Cirrus o wns the copyrig hts associated with the information contained herein and gives con-
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or service marks of their respective owners.
I²C is a registered trademark of Philips Semiconductor.
SPI is a trademark of Motorola, Inc.
