ICS552-01B Dual 1 to 4 High-Speed Clock Buffer Description Features The ICS552-01B is a low cost, high-speed clock buffer which includes two identical single input to four output buffers. By combining the two buffers on one monolithic device, the propagation delays are matched through the device, maintaining any skew relationship present on the inputs. It is also possible to connect the inputs together, creating a one-to-eight buffer. See the ICS551M for a single 1 to 4 buffer in an 8-pin SOIC. For more than eight outputs, see the MK74CBxxx BuffaloTM series of clock drivers. * * * * * Packaged as 20-pin (150 mil) SSOP (QSOP) * * * * * 3.0 V to 5.5 V operating voltage ICS also makes many PLL-based low-skew output devices, as well as Zero Delay Buffers to synchronize clocks. Contact ICS for all of your clocking needs. Pb-free packaging available Up to 200 MHz clock input/output at 3.3 V Low skew of 250 ps maximum for any bank of four Inputs can be connected together for a 1 to 8 buffer with 250 ps skew between any outputs Non-inverting Ideal for networking clocks Output Enable mode tri-states outputs Full CMOS output swing with 25 mA output drive capability at TTL levels * Advanced, low power, sub-micron CMOS process * Industrial temperature version available Block Diagram QA1 INA QA2 QA3 S1 QA4 Control Logic S0 QB1 QB2 QB3 QB4 INB 1 MDS 552-01B E Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 Revision 012904 tel (408) 297-1201 www.icst.com ICS552-01B Dual 1 to 4 High-Speed Clock Buffer Pin Assignment Clock Output Select Table S1 S0 INA 1 20 S0 DC 2 19 INB DC 3 18 QB4 VDD 4 17 QB3 VDD 5 16 VDD GND 6 15 VDD QA1 7 14 GND QA2 8 13 QB2 QA3 9 12 QB1 QA4 10 11 S1 Mode 0 0 QA1:4 and QB1:4 running 0 1 Test mode 1 0 OE. All outputs in high impedance 1 1 QA1:4 only. QB1:4 stopped low 20-pin (150 mil) SSOP (QSOP) Pin Descriptions Pin Number Pin Name Pin Type 1 INA CI Input to buffer A. Outputs QA1:4 will be the same frequency. Internal pull-up resistor. 2 DC -- Do not connect. Pin Description 3 DC -- 4 VDD Power 5 VDD Power Connect to +3.3 V or 5.0 V. Must be same as other VDDs. Connect to +3.3 V or 5.0 V. Must be same as other VDDs. Do not connect. 6 GND Power Connect to ground. 7 QA1 Output Output 1 from buffer A. 8 QA2 Output Output 2 from buffer A. 9 QA3 Output Output 3 from buffer A. 10 QA4 Output 11 S1 I 12 QB1 Output Output 4 from buffer A. Mode Select pin 1. Selects mode for outputs. Must be at GND for all clocks on. Internal pull-up resistor. Output 1 from buffer B. 13 QB2 Output Output 2 from buffer B. 14 GND Power Connect to ground. 15 VDD Power 16 VDD Power Connect to +3.3 V or 5.0 V. Must be same as other VDDs. Connect to +3.3 V or 5.0 V. Must be same as other VDDs. 17 QB3 Output Output 3 from buffer B. 18 QB4 Output 19 INB CI Output 4 from buffer B. Input to buffer B. Outputs QA1:4 will be the same frequency. Internal pull-up resistor. 20 S0 I Mode Select pin 0. Selects mode for outputs. Must be at GND for all clocks on. Internal pull-up resistor. KEY: CI = clock input with pull-up resistor; I = input with internal pull-up resistor 2 MDS 552-01B E Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 Revision 012904 tel (408) 297-1201 www.icst.com ICS552-01B Dual 1 to 4 High-Speed Clock Buffer External Components PCB Layout Recommendations Series Termination Resistor Clock output traces over one inch should use series termination. To series terminate a 50 trace (a commonly used trace impedance), place a 33 resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20. Decoupling Capacitors As with any high-performance mixed-signal IC, the ICS552-01B must be isolated from system power supply noise to perform optimally. Decoupling capacitors of 0.01F must be connected between each VDD and GND on pins 4 and 6, and 16 and 14. Other VDDs and GNDs can be connected to these pins or directly to their respective ground planes. For optimum device performance and lowest output phase noise, the following guidelines should be observed. 1) Each 0.01F decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. 2) The external crystal should be mounted just next to the device with short traces. The X1 and X2 traces should not be routed next to each other with minimum spaces, instead they should be separated and away from other traces. 3) To minimize EMI, the 33 series termination resistor (if needed) should be placed close to the clock output. 4) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers. 3 MDS 552-01B E Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 Revision 012904 tel (408) 297-1201 www.icst.com ICS552-01B Dual 1 to 4 High-Speed Clock Buffer Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS552-01B. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Parameter Condition Min. Supply Voltage, VDD Referenced to GND Inputs Referenced to GND Clock Outputs Referenced to GND Storage Temperature Soldering Temperature Typ. Max. Units 7 V -0.5 VDD+0.5 V -0.5 VDD+0.5 V -65 150 C 260 C 125 C Max 10 seconds Junction Temperature Recommended Operation Conditions Parameter Min. Typ. Max. Units Ambient Operating Temperature (ICS552R-01B) 0 +70 C Ambient Operating Temperature (ICS552R-01BI) -40 +85 C DC Electrical Characteristics Unless stated otherwise, VDD = 5 V, Ambient Temperature -40 to +85C Parameter Symbol Conditions Operating Voltage VDD Input High Voltage VIH INA and INB Input Low Voltage VIL X1 pin only Input High Voltage VIH S1 and S0 Input Low Voltage VIL S1 and S0 Output High Voltage VOH VDD = 5 V, IOH = -25 mA Output Low Voltage VOL VDD = 5 V, IOL = 25 mA Output High Voltage VOH CMOS level, IOH = -8 mA Short Circuit Current IOS VDD = 3.3 V, each output Typ. 3.0 VDD/2+1 525 Race Street, San Jose, CA 95126 Max. Units 5.5 V VDD/2 VDD/2 V VDD/2-1 2 V V 0.8 2.4 V V 0.4 VDD-0.4 V V 50 mA 4 MDS 552-01B E Integrated Circuit Systems, Inc. Min. Revision 012904 tel (408) 297-1201 www.icst.com ICS552-01B Dual 1 to 4 High-Speed Clock Buffer Parameter Symbol Conditions Operating Supply Current IDD at 3.3 V, no load, all 135 MHz 35 mA All inputs 4 pF All inputs 55 k Input Capacitance Internal Pull-up resistor RPU Min. Typ. Max. Units AC Electrical Characteristics Unless stated otherwise, VDD = 5 V, Ambient Temperature -40 to +85 C Parameter Symbol Input Frequency Conditions Min. FIN Output Frequency FOUT Typ. Max. Units 0 200 MHz 3.3 V, 10 pF load, note 3. 200 MHz 3.3 V, 15 pF load, note 3. 180 MHz 5 V, 15 pF load, note 3. 135 MHz Output Rise Time tOR 0.8 to 2.0 V 1.5 ns Output Fall Time tOF 2.0 to 0.8 V 1.5 ns Propagation Delay at 3.3 V 4 ns at 5 V 3 ns Output-to-Output Skew within bank of four Rising edges at VDD/2 250 ps Output-to-Output Skew between banks Note 1 250 ps Notes: 1. When INA is connected to INB, all eight outputs are within 250 ps skew. 2. Duty cycle on outputs will match incoming clock duty cycle. Consult ICS for tight duty cycle clock generators. 3. With external series resistor of 33 positioned close to each output pin. Thermal Characteristics Parameter Symbol Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case Min. Typ. Max. Units JA Still air 135 C/W JA 1 m/s air flow 93 C/W JA 3 m/s air flow 78 C/W 60 C/W JC 5 MDS 552-01B E Integrated Circuit Systems, Inc. Conditions 525 Race Street, San Jose, CA 95126 Revision 012904 tel (408) 297-1201 www.icst.com ICS552-01B Dual 1 to 4 High-Speed Clock Buffer Package Outline and Package Dimensions (20-pin SSOP, 150 Mil. Wide Body) Package dimensions are kept current with JEDEC Publication No. 95 Millimeters 20 Symbol E1 Min A A1 A2 b c D E E1 e L aaa E INDEX AREA 1 2 D Max 1.35 1.75 0.10 0.25 -1.50 0.20 0.30 0.18 0.25 8.55 8.75 5.80 6.20 3.80 4.00 .635 Basic 0.40 1.27 0 8 -0.10 Inches Min Max 0.053 0.069 0.004 0.010 -0.059 0.008 0.012 0.007 0.010 0.337 0.344 0.228 0.244 0.150 0.157 .025 Basic 0.016 0.050 0 8 -0.004 A A2 A1 c -Ce SEATING PLANE b L aaa C Ordering Information Part / Order Number Marking Shipping packaging Package Temperature ICS552R-01B ICS552-01B Tubes 20-pin SSOP 0 to +70C ICS552R-01BT ICS552-01B Tape and Reel 20-pin SSOP 0 to +70C ICS552R-01BLF ICS552-01BLF Tubes 20-pin SSOP 0 to +70C ICS552R-01BLFT ICS552-01BLF Tape and Reel 20-pin SSOP 0 to +70C ICS552R-01BI ICS552-01BI Tubes 20-pin SSOP -40 to +85C ICS552R-01BIT ICS552-01BI Tape and Reel 20-pin SSOP -40 to +85C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 6 MDS 552-01B E Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 Revision 012904 tel (408) 297-1201 www.icst.com