Dual 1 to 4 High-Speed Clock Buffer
MDS 552-01B E 3Revision 012904
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS552-01B
External Components
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50Ω trace (a
commonly used trace impedance), place a 33Ω resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20Ω.
Decoupling Capacitors
As with any high-performance mixed-signal IC, the
ICS552-01B must be isolated from system power
supply noise to perform optimally.
Decoupling capacitors of 0.01µF must be connected
between each VDD and GND on pins 4 and 6, and 16
and 14. Other VDDs and GNDs can be connected to
these pins or directly to their respective ground planes.
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) Each 0.01µF decoupling capacitor should be
mounted on the component side of the board as close
to the VDD pin as possible. No vias should be used
between decoupling capacitor and VDD pin. The PCB
trace to VDD pin should be kept as short as possible,
as should the PCB trace to the ground via.
2) The external crystal should be mounted just next to
the device with short traces. The X1 and X2 traces
should not be routed next to each other with minimum
spaces, instead they should be separated and away
from other traces.
3) To minimize EMI, the 33Ω series termination resistor
(if needed) should be placed close to the clock output.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers.