PM25LQ032C-BCE - INTEGRATED SILICON SOLUTION

Pm25LQ032C

Chingis Technology Corp.

1

Date February. 2012, Rev: 1.6.1

FEATURES

• Single Power Supply Operation

- Low voltage range: 2.7 V - 3.6 V

• Memory Organization

- Pm25LQ032C: 4096K x 8 (32 Mbit)

• Cost Effective Sector/Block Architecture

- 32Mb : Uniform 4KByte sectors / sixty-four uniform

64KByte blocks

• Serial Peripheral Interface (SPI) Compatible

- Supports single-, dual- or quad-output

- Supports SPI Modes 0 and 3

- Maximum 33 MHz clock rate for normal read

- Maximum 104 MHz clock rate for fast read

- Maximum 208MHz clock rate equivalent Dual SPI

- Maximum 400MHz clock rate equivalent Quad SPI

• Byte Program Operation

- Typical 8 us/Byte

• Page Program (up to 256 Bytes) Operation

- Typical 1 ms per page program

• Sector, Block or Chip Erase Operation

- Sector Erase (4KB)50ms (Typ)

- Block Erase (64KB)500ms (Typ)

- Chip Erase 15S (32Mb)

•Deep power-down mode 1uA (Typ)

Security protect function

- sector unlock (Appendix 1)

32Mbit Single Operating

Voltage Serial Flash Memory

With 104 MHz Dual- or 100MHz

Quad-Output SPI Bus Interface

• Low Power Consumption

- Max 15 mA active read current

- Max 20 mA program/erase current

- Max 30uA standby current

• Hardware Write Protection

- Protect and unprotect the device from write

operation by Write Protect (WP#) Pin

• Software Write Protection

- The Block Protect (BP3, BP2, BP1, BP0) bits

allow partial or entire memory to be configured as

read-only

• High Product Endurance

- Guaranteed 100,000 program/erase cycles per

single sector

- Minimum 20 years data retention

• Industrial Standard Pin-out and Package

- 8-pin 208mil SOIC

- 8-contact WSON

- 16-pin 300mil SOP

- 8-pin 208mil VSOP

- Lead-free (Pb-free), halogen-free package

Additional 64-byte Security information one-time

programmable (OTP) area

GENERAL DESCRIPTION

The Pm25LQ032C are 32 Mbit Serial Peripheral Interface (SPI) Flash memories, providing single-, dual or

quad-output. The devices are designed to support a 33 MHz fclock rate in normal read mode, and 104 MHz in

fast read (Quad output is 100MHz), the fastest in the industry. The devices use a single low voltage power

supply, ranging from 2.7 Volt to 3.6 Volt, to perform read, erase and program operations. The devices can be

programmed in standard EPROM programmers.

The Pm25LQ032C are accessed through a 4-wire SPI Interface consisting of Serial Data Input/Output (Sl),

Serial Data Output (SO), Serial Clock (SCK), and Chip Enable (CE#) pins. The devices support page program

mode, where 1 to 256 bytes data can be programmed into the memory in one program operation. These

devices are divided into uniform 4 KByte sectors or uniform 64 KByte blocks.

The Pm25LQ032C are manufactured on pFLASH™’s advanced non-volatile technology. The devices are

offered in 8-pin SOIC 208mil and 8-contact WSON.

Pm25LQ032C

Chingis Technology Corp.

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Date February. 2012, Rev: 1.6.1

PRODUCT ORDERING INFORMATION

Pm25LQxxx - B C E

Environmental Attribute

E = Lead-free (Pb-free) package

Temperature Range

C = Commercial Grade (-40°C to +125°C)

Package Type

B = 8-pin SOIC 208 mil (8B)

K = 8-contact WSON (8K)

M= 16-pin SOIC 300mil (8M)

P= PDIP

F= 8-pin VSOP 208 mil (8F)

pFlash Device Number

Pm25Q032C

Part Number Operating Frequency (MHz)

Package Temperature

Range

Pm25LQ032C-BCE 104 8B

208mil SOIC

Pm25LQ032C-KCE 104 8Q

WSON

Pm25LQ032C-PCE 104 8P

300mil PDIP

Pm25LQ032C-MCE 104 8M

300mil SOIC

Pm25LQ032C-FCE 104 8F

208mil VSOP

Commercial Grade

(-40

o

C to +125

o

C)

Pm25LQ032C

Chingis Technology Corp.

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Date February. 2012, Rev: 1.6.1

CONNECTION DIAGRAMS

5

6

7

81

2

3

4

Vcc

NC(IO3)

SCK

SI(IO0)

SO(IO1)

GND

WP#(IO2)

CE#

16-Pin SOIC

CE# CE#

GND

Vcc

HOLD# (IO3)

SCK

SI (IO0

)

SI (IO0

)

SCK

HOLD#(IO3)

Vcc

SO (IO1)

WP# (IO2)

GND

1

2

3

4

8

7

6

5

1

2

3

4

8

7

6

5

8

-

Contact WSON

WP# (IO2)

SO (IO1)

8

-

Pin SOIC

/VSOP

8-Pin PDIP

HOLD#(IO3)

Pm25LQ032C

Chingis Technology Corp.

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Date February. 2012, Rev: 1.6.1

PIN DESCRIPTIONS

SYMBOL

TYPE DESCRIPTION

CE# INPUT

Chip Enable: CE# low activates the devices internal circuitries for

device operation. CE# high deselects the devices and switches into

standby mode to reduce the power consumption. When a device is not

selected, data will not be accepted via the serial input pin (Sl), and the

serial output pin (SO) will remain in a high impedance state.

SCK INPUT Serial Data Clock

SI (IO0) INPUT/OUTPUT

Serial Data Input/Output

SO (IO1)

INPUT/OUTPUT

Serial Data Input/Output

GND Ground

Vcc Device Power Supply

WP#

(IO2)

INPUT/OUTPUT

Write Protect/Serial Data Output: A hardware program/erase protection for all or

part of a memory array. When the WP# pin is low, memory array write-protection

depends on the setting of BP3, BP2, BP1 and BP0 bits in the Status Register.

When the WP# is high, the status register are not write-protected.

When the QE bit of is set “1”, the /WP pin (Hardware Write Protect) function is

not available since this pin is used for IO2

HOLD#

(IO3)

INPUT/OUTPUT

Hold: Pause serial communication by the master device without resetting

the serial sequence.

When the QE bit of Status Register-2 is set for “1”, the function is Serial Data

Input & Output (for 4xI/O read mode)

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Chingis Technology Corp.

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Date February. 2012, Rev: 1.6.1

BLOCK DIAGRAM

SI (IO0)

WP# (IO2)

HOLD#

(IO3)

SO (IO1)

Pm25LQ032C

Chingis Technology Corp.

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Date February. 2012, Rev: 1.6.1

SPI MODES DESCRIPTION

Multiple Pm25LQ032C devices can be connected on

the SPI serial bus and controlled by a SPI Master, i.e.

microcontroller, as shown in Figure 1. The devices

support either of two SPI modes:

Mode 0 (0, 0)

Mode 3 (1, 1)

The difference between these two modes is the clock

polarity when the SPI master is in Stand-by mode: the

serial clock remains at “0” (SCK = 0) for Mode 0 and

the clock remains at “1” (SCK = 1) for Mode 3. Please

refer to Figure 2. For both modes, the input data is

latched on the rising edge of Serial Clock (SCK), and

the output data is available from the falling edge of

SCK.

Figure 1. Connection Diagram among SPI Master and SPI Slaves (Memory Devices)

Figure 2. SPI Modes Supported

MSb

SCK

SO

SI

Input mode

Mode 0 (0,0)

Mode 3 (1,1)

SPI Master

(i.e. Microcontroller)

CS3 CS2 CS1

SPI Memory

Device

SPI Memory

Devic

e

SPI Memory

Device

SPI Interface with

(0,0) or (1,1)

SD

I

SDI

SCK

SO

SI

CE#

WP#

HOLD#

Note: 1.

The Write Protect (WP#) and Hold (HOLD#) signals should be driven high or low as

Pm25LQ032C

Chingis Technology Corp.

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Date February. 2012, Rev: 1.6.1

SYSTEM CONFIGURATION

The Pm25LQ032C devices are designed to interface directly with the synchronous Serial Peripheral Interface

(SPI) of the Motorola MC68HCxx series of microcontrollers or any SPI interface-equipped system controllers.

The devices have two superset features that can be enabled through specific software instructions and the

Configuration Register:

1. Configurable sector size: The memory array of

Pm25LQ032C is divided into uniform 4 KByte sectors or uniform 64 KByte blocks (a block consists of sixteen

adjacent sectors).

Table 1 illustrates the memory map of the devices. The Configuration Register controls how the memory is

mapped.

Pm25LQ032C

Chingis Technology Corp.

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Date February. 2012, Rev: 1.6.1

BLOCK/SECTOR ADDRESSES

Table 1. Block/Sector Addresses of Pm25LQ080C/016C/032C

Memory Density Block

No.

Block Size

(KBytes) Sector No.

Sector

Size

(KBytes)

Address Range

Sector 0 4 000000h - 000FFFh

Sector 1 4 001000h - 001FFFh

: : :

Block 0 64

Sector 15 4 00F000h - 00FFFFh

Sector 16 4 010000h - 010FFFh

Sector 17 4 011000h - 011FFFh

: : :

Block 1 64

Sector 31 4 01F000h - 01FFFFh

: : : : :

Block 7 64 Sector 127 4 070000h – 07FFFFh

Block 8 64 Sector 128 4 080000h – 08FFFFh

: : : : :

8 Mbit

Block 15

64 Sector 255 4 0F0000h – 0FFFFFh

Block 16

64 Sector 256 4 100000h – 10FFFFh

: : : : :

32Mbit

16

Mbit

Block 31

64 Sector511 4 1F0000h – 1FFFFFh

Block 32

64 Sector 512 4 200000h – 20FFFFh

: : : : :

Block 63

64 Sector 1023

4 3FF000h – 3FFFFFh

Pm25LQ032C

Chingis Technology Corp.

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Date February. 2012, Rev: 1.6.1

REGISTERS (CONTINUED)

STATUS REGISTER

Refer to Tables 5 and 6 for Status Register Format and

Status Register Bit Definitions.

The BP0, BP1, BP2, BP3 and SRWD are non-volatile

memory cells that can be written by a Write Status

Register (WRSR) instruction. The default value of the

BP2, BP1, BP0, and SRWD bits were set to “0” at

factory. The Status Register can be read by the Read

Status Register (RDSR). Refer to Table 10 for

Instruction Set.

The function of Status Register bits are described as

follows:

WIP bit: The Write In Progress (WIP) bit is read-only,

and can be used to detect the progress or completion

of a program or erase operation. When the WIP bit is

“0”, the device is ready for a write status register,

program or erase operation. When the WIP bit is “1”,

the device is busy.

WEL bit: The Write Enable Latch (WEL) bit indicates

the status of the internal write enable latch. When the

WEL is “0”, the write enable latch is disabled, and all

write operations, including write status register, write

configuration register, page program, sector erase,

block and chip erase operations are inhibited. When

the WEL bit is “1”, write operations are allowed. The

WEL bit is set by a Write Enable (WREN) instruction.

Each write register, program and erase instruction

must be preceded by a WREN instruction. The WEL bit

can be reset by a Write Disable (WRDI) instruction. It

will automatically be the reset after the completion of a

write instruction.

BP3, BP2, BP1, BP0 bits: The Block Protection (BP3,

BP2, BP1 and BP0) bits are used to define the portion

of the memory area to be protected. Refer to Tables 7,

8 and 9 for the Block Write Protection bit settings.

When a defined combination of BP3, BP2, BP1 and

BP0 bits are set, the corresponding memory area is

protected. Any program or erase operation to that area

will be inhibited.Note: a Chip Erase (CHIP_ER)

instruction is executed only if all the Block Protection

Bits are set as “0”s.

SRWD bit: The Status Register Write Disable (SRWD)

bits operates in conjunction with the Write Protection

(WP#) signal to provide a Hardware Protection Mode.

When the SRWD is set to “0”, the Status Register is

not write-protected. When the SRWD is set to “1” and

the WP# is pulled low (V

IL

), the bits of Status Register

(SRWD, BP3, BP2, BP1, BP0) become read-only, and

a WRSR instruction will be ignored. If the SRWD is set

to “1” and WP# is pulled high (V

IH

), the Status Register

can be changed by a WRSR instruction.

QE bit: The Quad Enable (QE) is a non-volatile bit in

the status register that allows Quad operation. When

the QE bit is set to “0”,the pin WP# and HOLD# are

enable. When the QE bit is set to “1”, the pin IO2 and

IO3 are enable.

WARNING: The QE bit should never be set to a 1

during standard SPI or Dual SPI operation if the

WP# or HOLD# pins are tied directly to the power

supply or ground.

Table 5. Status Register Format

Bit 7 Bit 6 Bit 5

Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SRWD1

QE BP3 BP2 BP1 BP0 WEL WIP

Default (flash bit)

0 0 0 0 0 0 0 0

* The default value of the BP3, BP2, BP1, BP0, and SRWD bits were set to “0” at factory.

Pm25LQ032C

Chingis Technology Corp.

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Date February. 2012, Rev: 1.6.1

REGISTERS (CONTINUED)

Table 6. Status Register Bit Definition

Bit

Name

Definition Read-

/Write

Non-Volatile

bit

Bit 0

WIP

Write In Progress Bit:

"0" indicates the device is ready

"1" indicates a write cycle is in progress and the device is busy

R No

Bit 1

WEL

Write Enable Latch:

"0" indicates the device is not write enabled (default)

"1" indicates the device is write enabled

R/W No

Bit 2

BP0

Bit 3

BP1

Bit 4

BP2

Bit 5

BP3

Block Protection Bit: (See Tables 7, 8 and 9 for details)

"0" indicates the specific blocks are not write-protected (default)

"1" indicates the specific blocks are write-protected

R/W Yes

Bit 6

QE

Quad Enable bit:

“0” indicates the Quad output function disable (default)

“1” indicates the Quad output function enable

R/W Yes

Bit 7

SRWD

Status Register Write Disable: (See Table 10 for details)

"0" indicates the Status Register is not write-protected (default)

"1" indicates the Status Register is write-protected

R/W Yes

Table 7. Block Write Protect Bits for Pm25LQ032C

\

Status Register Bits Protected Memory Area

BP3 BP2 BP1 BP0 32 Mbit

0 0 0 0

1 0 0 0 None

0 0 0 1 Upper sixty-forth (1 block : 63th):

0 0 1 0 Upper thirty-second (2 blocks :62th and 63th):

0 0 1 1 Upper sixteenth (4 blocks :60th to 63th):

0 1 0 0 Upper eight (8 blocks :56th to 63th):

0 1 0 1 Upper quarter (16 blocks :48th to 63th):

0 1 1 0 Upper half (32 blocks :32th to 63th)

0 1 1 1

1 1 1 1 All blocks (64 blocks : 0th to 63th)

1 0 0 1 (1 blocks :0th):

1 0 1 0 (2 blocks :0th to 1th):

1 0 1 1 (4 blocks :0th to 3th):

1 1 0 0 (8 blocks :0th to 7th):

1 1 0 1 (16blocks :0th to 15th):

1 1 1 0 (32 blocks :0th to 31th):

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Chingis Technology Corp.

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Date February. 2012, Rev: 1.6.1

REGISTERS (CONTINUED)

PROTECTION MODE

The Pm25LQ032C have two types of write-

protection mechanisms: hardware and software.

These are used to prevent irrelevant operation in a

possibly noisy environment and protect the data

integrity.

HARDWARE WRITE-PROTECTION

The devices provide two hardware write-protection

features:

a. When inputting a program, erase or write status

register instruction, the number of clock pulse is

checked to determine whether it is a multiple of

eight before the executing. Any incomplete

instruction command sequence will be ignored.

b. Write inhibit is 2.1V, all write sequence will be

ignored when Vcc drop to 2.1V and lower.

c. The Write Protection (WP#) pin provides a

hardware write protection method for BP3, BP2,

BP1, BP0 and SRWD in the Status Register. Refer

to the STATUS REGISTER description.

SOFTWARE WRITE PROTECTION

The Pm25LQ032C also provides two software write

protection features:

a. Before the execution of any program, erase or

write status register instruction, the Write Enable

Latch (WEL) bit must be enabled by executing a

Write Enable (WREN) instruction. If the WEL bit is

not enabled first, the program, erase or write

register instruction will be ignored.

b. The Block Protection (BP3, BP2, BP1, BP0) bits

allow part or the whole memory area to be write-

protected.

Table 10. Hardware Write Protection on Status

Register

SRWD

WP# Status Register

0 Low Writable

1 Low Protected

0 High Writable

1 High Writable

DEVICE OPERATION

The Pm25LQ032C utilize an 8-bit instruction register.

Refer to Table 11 Instruction Set for details of the

Instructions and Instruction Codes. All instructions,

addresses, and data are shifted in with the most

significant bit (MSB) first on Serial Data Input (SI). The

input data on SI is latched on the rising edge of Serial

Clock (SCK) after Chip Enable (CE#) is driven low (V

IL

).

Every instruction sequence starts with a one-byte

instruction code and is followed by address bytes, data

bytes, or both address bytes and data bytes,

depending on the type of instruction. CE# must be

driven high (V

IH

) after the last bit of the instruction

sequence has been shifted in.

The timing for each instruction is illustrated in the

following operational descriptions.

Table 11. Instruction Set

Instruction Name Hex

Code

Operation Comman

d Cycle

Maximum

Frequency

RDID ABh

Read Manufacturer and Product ID 4 Bytes 104 MHz

JEDEC ID READ 9Fh

Read Manufacturer and Product ID by JEDEC ID Command

1 Byte

104 MHz

RDMDID 90h

Read Manufacturer and Device ID 4 Bytes 104 MHz

WREN 06h

Write Enable 1 Byte

104 MHz

WRDI 04h

Write Disable 1 Byte

104 MHz

RDSR 05h

Read Status Register 1 Byte

104 MHz

WRSR 01h

Write Status Register 2 Bytes

104 MHz

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Chingis Technology Corp.

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Date February. 2012, Rev: 1.6.1

READ 03h

Read Data Bytes from Memory at Normal Read Mode 4 Bytes

33 MHz

FAST_READ 0Bh

Read Data Bytes from Memory at Fast Read Mode 5 Bytes

104 MHz

FRDO 3Bh

Fast Read Dual Output 5 Bytes

104 MHz

FRDIO BBh

Fast Read Dual I/O 3 Bytes 104MHz

FRQO 6Bh

Fast Read Quad Output 5 Bytes 100 MHz

FRQIO EBh

Fast Read Quad I/O 2 Bytes 100MHz

MR FFh

Mode Reset 2 Byte 104MHz

PAGE_ PROG 02h

Page Program Data Bytes Into Memory 4 Bytes

+ 256B

104 MHz

SECTOR_ER D7h/

20h

Sector Erase 4 Bytes

104 MHz

BLOCK_ER D8h

Block Erase 4 Bytes

104 MHz

CHIP_ER C7h/

60h

Chip Erase 1 Byte

104 MHz

Quad page program

32h

Page Program Data Bytes Into Memory with Quad interface

4 Bytes

+ 256B

Erase suspend 75h

Erase resume 7Ah

Program information

Raw

B1h

Program 65 bytes of Security area 4 Bytes

104 MHz

Read information

Raw

4Bh

Read 65 bytes of Security area 4 Bytes

33 MHz

HOLD OPERATION

HOLD# is used in conjunction with CE# to select

the Pm25LQ032C. When the devices are selected

and a serial sequence is underway, HOLD# can be

used to pause the serial communication with the

master device without resetting the serial sequence.

To pause, HOLD# is brought low while the SCK

signal is low. To resume serial communication,

HOLD# is brought high while the SCK signal is low

(SCK may still toggle during HOLD). Inputs to Sl will

be ignored while SO is in the high impedance state.

Pm25LQ032C

Chingis Technology Corp.

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Date February. 2012, Rev: 1.6.1

DEVICE OPERATION (CONTINUED)

RDID COMMAND (READ PRODUCT

IDENTIFICATION)/

Release Power-down

OPERATION

The Release from Power-down or High performance

Mode / Device ID instruction is a multi-purpose

instruction. The Read Product Identification (RDID)

instruction is for reading out the old style of 8-bit

Electronic Signature, whose values are shown as table

of ID Definitions. This is not same as RDID or JEDEC

ID instruction. It’s not recommended to use for new

design. For new design, please use RDID or JEDEC ID

instruction.

The RDES instruction code is followed by three dummy

bytes, each bit being latched-in on SI during the rising

edge of SCK. Then the Device ID is shifted out on SO

with the MSB first, each bit been shifted out during the

falling edge of SCK. The RDES instruction is ended by

CE# goes high. The Device ID outputs repeatedly if

continuously send the additional clock cycles on SCK

while CE# is at low.

To release the device from the power-down state Mode,

the instruction is issued by driving the CE# pin low,

shifting the instruction code “ABh” and driving CE#

high as shown in figure 3.

Release from power-down will take the time duration of

t

RES1

before the device will resume normal operation

and other instructions are accepted. The CE# pin must

remain high during the t

RES1

time duration. If the

Release from Power-down / RDID instruction is issued

while an Erase, Program or Write cycle is in process

(when BUSY equals 1) the instruction is ignored and

will not have any effects on the current cycle

Table 12. Product Identification

Product Identification Data

First Byte 9Dh

Manufacturer ID Second Byte

7Fh

Device ID: Device ID1 Device ID2

Pm25LQ032C

15h 46h

Figure 3. Read Product Identification Sequence

0 1 8 31 38 39 46 47 54

HIGH IMPEDANCE

Device ID1 Device ID1 Device ID1

SCK

CE#

SI

SO

INSTRUCTION

97

1010 1011b

3 Dummy Bytes

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Chingis Technology Corp.

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Date February. 2012, Rev: 1.6.1

DEVICE OPERATION (CONTINUED)

JEDEC ID READ COMMAND (READ PRODUCT IDENTIFICATION BY JEDEC ID)

OPERATION

The JEDEC ID READ instruction allows the user to

read the manufacturer and product ID of devices. Refer

to Table 12 Product Identification for pFlash

Manufacturer ID and Device ID. After the JEDEC ID

READ command is input, the second Manufacturer ID

(7Fh) is shifted out on SO with the MSB first, followed

by the first Manufacturer ID (9Dh) and the Device ID

(46h, in the case of the Pm25LQ032C), each bit shifted

out during the falling edge of SCK. If CE# stays low

after the last bit of the Device ID is shifted out, the

Manufacturer ID and Device ID will loop until CE# is

pulled high.

Figure 4. Read Product Identification by JEDEC ID READ Sequence

SCK

CE#

SI

INSTRUCTION

1001 1111b

0815 23 24 317 16

HIGH IMPEDANCE

SO

Device ID2Manufacture ID1Manufacture ID2

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Chingis Technology Corp.

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Date February. 2012, Rev: 1.6.1

DEVICE OPERATION (CONTINUED)

RDMDID COMMAND (READ DEVICE MANUFACTURER AND DEVICE ID)

OPERATION

The Read Product Identification (RDID) instruction

allows the user to read the manufacturer and product

ID of the devices. Refer to Table 12 Product

Identification for pFLASH™ manufacturer ID and

device ID. The RDID instruction code is followed by

two dummy bytes and one byte address (A7~A0), each

bit being latched-in on SI during the rising edge of SCK.

If one byte address is initially set to A0 = 0, then the

first manufacturer ID (9Dh) is shifted out on SO with

the MSB first, the device ID1 and the second

manufacturer ID (7Fh), each bit been shifted out during

the falling edge of SCK. If one byte address is initially

set to A0 = 1, then device ID1 will be read first, then

followed by the first manufacture ID (9Dh) and then

second manufacture ID (7Fh). The manufacture and

device ID can be read continuously, alternating from

one to the others. The instruction is completed by

driving CE# high.

Figure 5. Read Product Identification by RDMDID READ Sequence

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Date February. 2012, Rev: 1.6.1

Note :

(1) ADDRESS A0 = 0, will output the 1st manufacture ID (9Dh) first -> device ID1 -> 2nd manufacture ID (7Fh)

ADDRESS A0 = 1, will output the device ID1 -> 1st manufacture ID (9D) -> 2nd manufacture ID (7Fh)

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Chingis Technology Corp.

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Date February. 2012, Rev: 1.6.1

DEVICE OPERATION (CONTINUED)

WRITE ENABLE OPERATION

The Write Enable (WREN) instruction is used to set the

Write Enable Latch (WEL) bit. The WEL bit of the

Pm25LQ032C is reset to the write –protected state

after power-up. The WEL bit must be write enabled

before any write operation, including sector, block

erase, chip erase, page program, write status register,

and write configuration register operations. The WEL

bit will be reset to the write-protect state automatically

upon completion of a write operation. The WREN

instruction is required before any above operation is

executed.

Figure 6. Write Enable Sequence

WRDI COMMAND (WRITE DISABLE) OPERATION

The Write Disable (WRDI) instruction resets the WEL

bit and disables all write instructions. The WRDI

instruction is not required after the execution of a write

instruction, since the WEL bit is automatically reset.

Figure 7. Write Disable Sequence

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Chingis Technology Corp.

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Date February. 2012, Rev: 1.6.1

DEVICE OPERATION (CONTINUED)

RDSR COMMAND (READ STATUS REGISTER) OPERATION

The Read Status Register (RDSR) instruction provides

access to the Status Register. During the execution of

a program, erase or write status register operation, all

other instructions will be ignored except the RDSR

instruction, which can be used to check the progress or

completion of an operation by reading the WIP bit of

Status Register.

Figure 8. Read Status Register Sequence

WRSR COMMAND (WRITE STATUS REGISTER) OPERATION

The Write Status Register (WRSR) instruction allows

the user to enable or disable the block protection and

status register write protection features by writing “0”s

or “1”s into the non-volatile BP3, BP2, BP1, BP0 and

SRWD bits.

Figure 9. Write Status Register Sequence

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Chingis Technology Corp.

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Date February. 2012, Rev: 1.6.1

DEVICE OPERATION (CONTINUED)

READ COMMAND (READ DATA) OPERATION

The Read Data (READ) instruction is used to read

memory data of a Pm25LQ032C under normal mode

running up to 33 MHz.

The READ instruction code is transmitted via the Sl

line, followed by three address bytes (A23 - A0) of the

first memory location to be read. A total of 24 address

bits are shifted in, but only A

MS

(most significant

address) - A0 are decoded. The remaining bits (A23 –

A

MS

)

are ignored. The first byte addressed can be at

any memory location. Upon completion, any data on

the Sl will be ignored. Refer to Table 13 for the related

Address Key.

The first byte data (D7 - D0) addressed is then shifted

out on the SO line, MSb first. A single byte of data, or

up to the whole memory array, can be read out in one

READ instruction. The address is automatically

incremented after each byte of data is shifted out. The

read operation can be terminated at any time by driving

CE# high (V

IH

) after the data comes out. When the

highest address of the devices is reached, the address

counter will roll over to the 000000h address, allowing

the entire memory to be read in one continuous READ

instruction.

If a Read Data instruction is issued while an Erase,

Program or Write cycle is in process (BUSY=1) the

instruction is ignored and will not have any effects on the

current cycle

Table 13. Address Key

Address Pm25LQ032C

A

N (

A

MS

– A

0)

A21 - A0

Don't Care Bits A23 – A22

Figure 12. Read Data Sequence

Pm25LQ032C

Chingis Technology Corp.

20

Date February. 2012, Rev: 1.6.1

DEVICE OPERATION (CONTINUED)

FAST_READ COMMAND (FAST READ DATA) OPERATION

The FAST_READ instruction is used to read memory

data at up to a 104 MHz clock.

The FAST_READ instruction code is followed by three

address bytes (A23 - A0) and a dummy byte (8 clocks),

transmitted via the SI line, with each bit latched-in

during the rising edge of SCK. Then the first data byte

addressed is shifted out on the SO line, with each bit

shifted out at a maximum frequency f

CT

, during the

falling edge of SCK.

The first byte addressed can be at any memory

location. The address is automatically incremented

after each byte of data is shifted out. When the highest

address is reached, the address counter will roll over to

the 000000h address, allowing the entire memory to be

read with a single FAST_READ instruction. The

FAST_READ instruction is terminated by driving CE#

high (V

IH

).

If a Fast Read Data instruction is issued while

an Erase, Program or Write cycle is in process (BUSY=1)

the instruction is ignored and will not have any effects on

the current cycle

Figure 13. Fast Read Data Sequence

SIO

Pm25LQ032C

Chingis Technology Corp.

21

Date February. 2012, Rev: 1.6.1

DEVICE OPERATION (CONTINUED)

FRDO COMMAND (FAST READ DUAL OUTPUT) OPERATION

The FRDO instruction is used to read memory data on

two output pins each at up to a 104 MHz clock.

The FRDO instruction code is followed by three

address bytes (A23 – A0) and a dummy byte (8 clocks),

transmitted via the SI line, with each bit latched-in

during the rising edge of SCK. Then the first data byte

addressed is shifted out on the SO and SIO lines, with

each pair of bits shifted out at a maximum frequency

f

CT

, during the falling edge of SCK. The first bit (MSb)

is output on SO, while simultaneously the second bit is

output on SIO.

The first byte addressed can be at any memory

location. The address is automatically incremented

after each byte of data is shifted out. When the highest

address is reached, the address counter will roll over to

the 000000h address, allowing the entire memory to be

read with a single FRDO instruction. FRDO instruction

is terminated by driving CE# high (V

IH

).

If a FRDO

instruction is issued while an Erase, Program or Write

cycle is in process (BUSY=1) the instruction is ignored

and will not have any effects on the current cycle

Figure 14. Fast Read Dual-Output Sequence

012 3 4 5 6 7 8910 11 28 29 30 31

...

INSTRUCTION = 0011 1011b ...

23 22 21 3210

3 - BYTE ADDRESS

CE#

SCK

SI

SO HIGH IMPEDANCE

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

CE#

SCK

IO0

IO1 HIGH IMPEDANCE

DATA OUT 1 DATA OUT 2

HIGH IMPEDANCE

Pm25LQ032C

Chingis Technology Corp.

22

Date February. 2012, Rev: 1.6.1

DEVICE OPERATION (CONTINUED)

FRDIO COMMAND (FAST READ DUAL I/O) OPERATION

The FRDIO instruction is similar to the FRDO

instruction, but allows the address bits to be input two

bits at a time. This may allow for code to be executed

directly from the SPI in some applications.

The FRDIO instruction code is followed by three

address bytes (A23 – A0) and a mode byte,

transmitted via the IO0 and IO1 lines, with each pair of

bits latched-in during the rising edge of SCK. The

address MSb is input on IO1, the next bit on IO0, and

continues to shift in alternating on the two lines. The

mode byte contains the value Ax, where x is a “don’t

care” value. Then the first data byte addressed is

shifted out on the IO1 and IO0 lines, with each pair of

bits shifted out at a maximum frequency f

CT

, during the

falling edge of SCK. The MSb is output on IO1, while

simultaneously the second bit is output on IO0. Figure

15 illustrates the timing sequence.

The first byte addressed can be at any memory

location. The address is automatically incremented

after each byte of data is shifted out. When the highest

address is reached, the address counter will roll over to

the 000000h address, allowing the entire memory to be

read with a single FRDIO instruction. FRDIO

instruction is terminated by driving CE# high (V

IH

).

The device expects the next operation will be another

FRDIO. It remains in this mode until it receives a

Mode Reset (FFh) command. In subsequent FRDIO

execution, the command code is not input, saving

timing cycles as described in Figure 16.

If a FRDIO

instruction is issued while an Erase, Program or Write

cycle is in process (BUSY=1) the instruction is ignored

and will not have any effects on the current cycle

Figure 15. Fast Read Dual I/O Sequence (with command decode cycles)

Pm25LQ032C

Chingis Technology Corp.

23

Date February. 2012, Rev: 1.6.1

DEVICE OPERATION (CONTINUED)

Figure 16. Fast Read Dual I/O Sequence (without command decode cycles)

012 3 10 11 12 13 14 15 16 17 18 19 20 21

...

23 22

21 2064

3 - BYTE ADDRESS

CE#

SCK

IO0

5

4

3

2

1

0

7

6

5

4

DATA OUT 1 DATA OUT 2

...

22

20 317

IO1

19

5

MODE BITS

7

6

FRQO COMMAND (FAST READ QUAD OUTPUT) OPERATION

The FRQO instruction is used to read memory data on

four output pins each at up to a 100 MHz clock.

The FRQO instruction code is followed by three

address bytes (A23 – A0) and a dummy byte (8 clocks),

transmitted via the SI line, with each bit latched-in

during the rising edge of SCK. Then the first data byte

addressed is shifted out on the IO3, IO2, IO1 and IO0

lines, with each group of four bits shifted out at a

maximum frequency f

CT

, during the falling edge of SCK.

The first bit (MSb) is output on IO3, while

simultaneously the second bit is output on IO2, the

third bit is output on IO1, etc.

The first byte addressed can be at any memory

location. The address is automatically incremented

after each byte of data is shifted out. When the highest

address is reached, the address counter will roll over to

the 000000h address, allowing the entire memory to be

read with a single FRQO instruction. FRQO instruction

is terminated by driving CE# high (V

IH

).

If a FRQO

instruction is issued while an Erase, Program or Write

cycle is in process (BUSY=1) the instruction is ignored

and will not have any effects on the current cycle

Pm25LQ032C

Chingis Technology Corp.

24

Date February. 2012, Rev: 1.6.1

DEVICE OPERATION (CONTINUED)

Figure 17. Fast Read Quad-Output Sequence

Pm25LQ032C

Chingis Technology Corp.

25

Date February. 2012, Rev: 1.6.1

DEVICE OPERATION (CONTINUED)

FRQIO COMMAND (FAST READ QUAD I/O) OPERATION

The FRQIO instruction is similar to the FRQO

instruction, but allows the address bits to be input four

bits at a time. This may allow for code to be executed

directly from the SPI in some applications.

The FRQIO instruction code is followed by three

address bytes (A23 – A0) and a mode byte,

transmitted via the IO3, IO2, IO0 and IO1 lines, with

each group of four bits latched-in during the rising edge

of SCK. The address MSb is input on IO3, the next bit

on IO2, the next bit on IO1, the next bit on IO0, and

continue to shift in alternating on the four. The mode

byte contains the value Ax, where x is a “don’t care”

value. After four dummy clocks, the first data byte

addressed is shifted out on the IO3, IO2, IO1 and IO0

lines, with each group of four bits shifted out at a

maximum frequency f

CT

, during the falling edge of SCK.

The first bit (MSb) is output on IO3, while

simultaneously the second bit is output on IO2, the

third bit is output on IO1, etc. Figure 18 illustrates the

timing sequence.

The first byte addressed can be at any memory

location. The address is automatically incremented

after each byte of data is shifted out. When the highest

address is reached, the address counter will roll over to

the 000000h address, allowing the entire memory to be

read with a single FRQIO instruction. FRQIO

instruction is terminated by driving CE# high (V

IH

).

The device expects the next operation will be another

FRQIO. It remains in this mode until it receives a

Mode Reset (FFh) command. In subsequent FRDIO

execution, the command code is not input, saving

cycles as described in Figure 19.

If a FRQIO instruction

is issued while an Erase, Program or Write cycle is in

process (BUSY=1) the instruction is ignored and will not

have any effects on the current cycle

Pm25LQ032C

Chingis Technology Corp.

26

Date February. 2012, Rev: 1.6.1

Figure 18. Fast Read Quad I/O Sequence (with command decode cycles)

012 3 4 5 6 7 8910 11 12 13 14 15

INSTRUCTION = 1110 1011b

21 17

16 404

3 - BYTE ADDRESS

CE#

SCK

IO0

16 17 18 19 20 21 22 23 24 25

1

0

5

4

1

0

5

4

1

0

5

4

1

0

5

4

CE#

SCK

IO0

IO1

DATA OUT 1

20

13 515

IO1

12

MODE BITS

5

4

22 18 14 626

23 19 15 737

IO2

IO3 11

10

9

8

3

2

7

6

3

2

7

6

3

2

7

6

3

2

7

6

7

6

IO2

IO3

DATA OUT 2 DATA OUT 3 DATA OUT 44 dummy cycles

26 27

Pm25LQ032C

Chingis Technology Corp.

27

Date February. 2012, Rev: 1.6.1

DEVICE OPERATION (CONTINUED)

Figure 19. Fast Read Quad I/O Sequence (without command decode cycles)

MR COMMAND (MODE RESET) OPERATION

The Mode Reset command is used to conclude

subsequent FRDIO and FRQIO operations. It

resets the Mode bits to a value that is not Ax. It

should be executed after an FRDIO or FRQIO

operation, and is recommended also as the first

command after a system reset. The timing

sequence is different depending whether the MR

command is used after an FRDIO or FRQIO, as

shown in Figure 20.

Figure 20, Mode Reset Command

Pm25LQ032C

Chingis Technology Corp.

28

Date February. 2012, Rev: 1.6.1

DEVICE OPERATION (CONTINUED)

PAGE_PROG COMMAND (PAGE PROGRAM) OPERATION

The Page Program (PAGE_PROG) instruction allows

up to 256 bytes data to be programmed into memory in

a single operation. The destination of the memory to be

programmed must be outside the protected memory

area set by the Block Protection (BP2, BP1, BP0) bits.

A PAGE_PROG instruction which attempts to program

into a page that is write-protected will be ignored.

Before the execution of PAGE_PROG instruction, the

Write Enable Latch (WEL) must be enabled through a

Write Enable (WREN) instruction.

The PAGE_PROG instruction code, three address

bytes and program data (1 to 256 bytes) are input via

the Sl line. Program operation will start immediately

after the CE# is brought high, otherwise the

PAGE_PROG instruction will not be executed. The

internal control logic automatically handles the

programming voltages and timing. During a program

operation, all instructions will be ignored except the

RDSR instruction. The progress or completion of the

program operation can be determined by reading the

WIP bit in Status Register via a RDSR instruction. If

the WIP bit is “1”, the program operation is still in

progress. If WIP bit is “0”, the program operation has

completed.

If more than 256 bytes data are sent to a device, the

address counter rolls over within the same page, the

previously latched data are discarded, and the last 256

bytes data are kept to be programmed into the page.

The starting byte can be anywhere within the page.

When the end of the page is reached, the address will

wrap around to the beginning of the same page. If the

data to be programmed are less than a full page, the

data of all other bytes on the same page will remain

unchanged.

Note: A program operation can alter “1”s into “0”s, but

an erase operation is required to change “0”s back to

“1”s. A byte cannot be reprogrammed without first

erasing the whole sector or block.

Figure 21. Page Program Sequence

Pm25LQ032C

Chingis Technology Corp.

29

Date February. 2012, Rev: 1.6.1

DEVICE OPERATION (CONTINUED)

Quad Input Page Program operation

The Quad Input Page Program instruction allows up

to 256 bytes data to be programmed into memory in

a single operation with four pins (IO0, IO1, IO2 and

IO3). The destination of the memory to be

programmed must be outside the protected memory

area set by the Block Protection (BP3, BP2, BP1,

BP0) bits. A Quad Input Page Program instruction

which attempts to program into a page that is write-

protected will be ignored. Before the execution of

Quad Input Page Program instruction, the QE bit in

the status register must be set to “1” and the Write

Enable Latch (WEL) must be enabled through a Write

Enable (WREN) instruction.

The Quad Input Page Program instruction code,

three address bytes and program data (1 to 256

bytes) are input via the four pins (IO0, IO1, IO2 and

IO3). Program operation will start immediately after

the CE# is brought high, otherwise the Quad Input

Page Program instruction will not be executed. The

internal control logic automatically handles the

programming voltages and timing. During a program

operation, all instructions will be ignored except the

RDSR instruction. The progress or completion of the

program operation can be determined by reading the

WIP bit in Status Register via a RDSR instruction. If

the WIP bit is “1”, the program operation is still in

progress. If WIP bit is “0”, the program operation has

completed.

If more than 256 bytes data are sent to a device, the

address counter rolls over within the same page, the

previously latched data are discarded, and the last

256 bytes data are kept to be programmed into the

page. The starting byte can be anywhere within the

page. When the end of the page is reached, the

address will wrap around to the beginning of the

same page. If the data to be programmed are less

than a full page, the data of all other bytes on the

same page will remain unchanged.

Note: A program operation can alter “1”s into “0”s,

but an erase operation is required to change “0”s

back to “1”s. A byte cannot be reprogrammed without

first erasing the whole sector or block.

Pm25LQ032C

Chingis Technology Corp.

30

Date February. 2012, Rev: 1.6.1

00110010

b

Pm25LQ032C

Chingis Technology Corp.

31

Date February. 2012, Rev: 1.6.1

DEVICE OPERATION (CONTINUED)

ERASE OPERATION

The memory array of the Pm25LQ032C is organized

into uniform 4 Kbyte sectors or 64 Kbyte uniform

blocks (a block consists of sixteen adjacent sectors).

Before a byte can be reprogrammed, the sector or

block that contains the byte must be erased (erasing

sets bits to “1”). In order to erase the devices, there are

three erase instructions available: Sector Erase

(SECTOR_ER), Block Erase (BLOCK_ER) and Chip

Erase (CHIP_ER). A sector erase operation allows any

individual sector to be erased without affecting the data

in other sectors. A block erase operation erases any

individual block. A chip erase operation erases the

whole memory array of a device. A sector erase, block

erase or chip erase operation can be executed prior to

any programming operation.

SECTOR_ER COMMAND (SECTOR ERASE)

OPERATION

A SECTOR_ER instruction erases a 4 Kbyte sector

Before the execution of a SECTOR_ER instruction, the

Write Enable Latch (WEL) must be set via a Write

Enable (WREN) instruction. The WEL bit is reset

automatically after the completion of sector an erase

operation.

A SECTOR_ER instruction is entered, after CE# is

pulled low to select the device and stays low during the

entire instruction sequence The SECTOR_ER

instruction code, and three address bytes are input via

SI. Erase operation will start immediately after CE# is

pulled high. The internal control logic automatically

handles the erase voltage and timing. Refer to Figure

22 for Sector Erase Sequence.

During an erase operation, all instruction will be

ignored except the Read Status Register (RDSR)

instruction. The progress or completion of the erase

operation can be determined by reading the WIP bit in

the Status Register using a RDSR instruction. If the

WIP bit is “1”, the erase operation is still in progress. If

the WIP bit is “0”, the erase operation has been

completed.

BLOCK_ER COMMAND (BLOCK ERASE)

OPERATION

A Block Erase (BLOCK_ER) instruction erases a 64

Kbyte block of the Pm25LQ032C. Before the execution

of a BLOCK_ER instruction, the Write Enable Latch

(WEL) must be set via a Write Enable (WREN)

instruction. The WEL is reset automatically after the

completion of a block erase operation.

The BLOCK_ER instruction code and three address

bytes are input via SI. Erase operation will start

immediately after the CE# is pulled high, otherwise the

BLOCK_ER instruction will not be executed. The

internal control logic automatically handles the erase

voltage and timing. Refer to Figure 23 for Block Erase

Sequence.

CHIP_ER COMMAND (CHIP ERASE) OPERATION

A Chip Erase (CHIP_ER) instruction erases the entire

memory array of a Pm25LQ032C. Before the execution

of CHIP_ER instruction, the Write Enable Latch (WEL)

must be set via a Write Enable (WREN) instruction.

The WEL is reset automatically after completion of a

chip erase operation.

The CHIP_ER instruction code is input via the SI.

Erase operation will start immediately after CE# is

pulled high, otherwise the CHIP_ER instruction will not

be executed. The internal control logic automatically

handles the erase voltage and timing. Refer to Figure

24 for Chip Erase Sequence.

Pm25LQ032C

Chingis Technology Corp.

32

Date February. 2012, Rev: 1.6.1

DEVICE OPERATION (CONTINUED)

Figure 22. Sector Erase Sequence

Figure 23. Block Erase Sequence

Figure 24. Chip Erase Sequence

Pm25LQ032C

Chingis Technology Corp.

33

Date February. 2012, Rev: 1.6.1

DEVICE OPERATION (CONTINUED)

Program Security information Row instruction (PSIR)

The PSIR instructions can read and programmed (Erase) using three dedicated instructions. The program

information Raw instruction is used to program at most 65 bytes to the security memory area (by changing bits

from ‘1’ to ‘0’, only). Before it can be accepted, a write enable (WREN) instruction must previously have been

executed. After the write enable (WREN) instruction has been decoded, the device sets the write enable latch

(WEL) bit. The program information Row instruction is entered by driving CE# pin Low, followed by the

instruction code, three address bytes and at least one data byte on serial data input (SI). CE# pin must be

driven High after the eighth bits of the last data byte has been latched in, otherwise the Program information

Row instruction is not executed. If more than 64 bytes data are sent to a device, the address counter can not roll

over.

After CE# pin is driven High, the self-timed page program cycle (whose duration is t

potp

) is initiated. While the

program OTP cycle is in progress, the status register may be read to check the value of the write in progress

(WIP) bit. The write in progress (WIP) bit is 1 during the self-timed program cycle, and it is 0 when it is

completed. At some unspecified time before the cycle is complete, the write enable latch (WEL) bit is reset.

Note: 1 ≤ n ≤ 65

Figure 30. Program information Raw Sequence

Note: 1. The SIR address is from 000000h to 00003Fh.

2. The SIR protection bit is in the address 000040h

Pm25LQ032C

Chingis Technology Corp.

34

Date February. 2012, Rev: 1.6.1

DEVICE OPERATION (CONTINUED)

To lock the OTP memory:

Bit 0 of the OTP control byte, that is byte 64, is used to permanently lock the OTP memory array.

When bit 0 of byte 64 = ’1’, the 64 bytes of the OTP memory array can be programmed.

When bit 0 of byte 64 = ‘0’, the 64 bytes of the OTP memory array are read-only and

cannot be programmed anymore.

Once a bit of the OTP memory has been programmed to ‘0’, it can no longer be set to ‘1’.

Therefore, as soon as bit 0 of byte 64 (control byte) is set to ‘0’, the 64 bytes of the OTP

memory array become read-only in a permanent way.

Any program OTP (POTP) instruction issued while an erase, program or write cycle is in

progress is rejected without having any effect on the cycle that is in progress

Pm25LQ032C

Chingis Technology Corp.

35

Date February. 2012, Rev: 1.6.1

DEVICE OPERATION (CONTINUED)

Read Security Information Row (RSIR)

The RSIR instruction read the security information Row. There is no rollover mechanism with the read OTP

(ROTP) instruction. This means that the read OTP (ROTP) instruction must be sent with a maximum of 65 bytes

to read, since once the 65

th

byte has been read, the same (65

th

) byte keeps being read on the SO pin.

Fig 33. Read Security information Row instruction

Pm25LQ032C

Chingis Technology Corp.

36

Date February. 2012, Rev: 1.6.1

ABSOLUTE MAXIMUM RATINGS

(1)

Storage Temperature -55

o

C to +125

o

C

Standard Package

240

o

C 3 Seconds

Surface Mount Lead Soldering Temperature

Lead-free Package

260

o

C 3 Seconds

Input Voltage with Respect to Ground on All Pins (2) -0.5 V to VCC + 0.5 V

All Output Voltage with Respect to Ground -0.5 V to VCC + 0.5 V

VCC (2) -0.5 V to +6.0 V

Notes:

1. Applied conditions greater than those listed in “Absolute Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only. The functional operation of the device conditions that exceed those

indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating

condition for extended periods may affect device reliability.

2. Maximum DC voltage on input or I/O pins is V

CC

+ 0.5 V. During voltage transitions, input or I/O pins may

overshoot V

CC

by

+ 2.0 V for a period of time not to exceed 20 ns. Minimum DC voltage on input or I/O pins is

-0.5 V. During voltage transitions, input or I/O pins may undershoot GND by -2.0 V for a period of time not to

exceed 20 ns.

DC AND AC OPERATING RANGE

Part Number Pm25LQ032C

Operating Temperature (Commercial Grade) -40

o

C to 125

o

C

Vcc Power Supply 2.7 V – 3.6 V

DC CHARACTERISTICS

Applicable over recommended operating range from:

T

AC

= -40°C to +125°C, V

CC

= 2.7 V to 3.6 V (unless otherwise noted).

Symbol

Parameter Condition Min Ty

p Max Units

I

CC1

Vcc Active Read Current V

CC

= 3.6V at 33 MHz, SO = Open 10

15 mA

I

CC2

Vcc Program/Erase Current V

CC

= 3.6V at 33 MHz, SO = Open 15

30 mA

I

SB1

Vcc Standby Current CMOS

V

CC

= 3.6V, CE# = V

CC

10 µA

I

SB2

Vcc Standby Current TTL V

CC

= 3.6V, CE# = V

IH

to V

CC

3 mA

I

LI

Input Leakage Current V

IN

= 0V to V

CC

1 µA

I

LO

Output Leakage Current V

IN

= 0V to V

CC

, T

AC

= 0

o

C to 130

o

C

1 µA

V

IL

Input Low Voltage -0.5 0.3Vcc V

V

IH

Input High Voltage 0.7V

CC

V

CC

+ 0.3

V

OL

Output Low Voltage I

OL

= 2.1 mA 0.45 V

V

OH

Output High Voltage 2.7V < V

CC

< 3.6V

I

OH

= -100 µA

V

CC

– 0.2

V

Pm25LQ032C

Chingis Technology Corp.

37

Date February. 2012, Rev: 1.6.1

AC CHARACTERISTICS

Applicable over recommended operating range from T

A

= -40°C to +125°C, V

CC

= 2.7 V to 3.6 V

C

L

= 1 TTL Gate and 30 pF (unless otherwise noted).

Symbol

Parameter Min Typ Max Units

f

CT

Clock Frequency for fast read mode 0 104 MHz

f

C

Clock Frequency for read mode 0 33 MHz

t

RI

Input Rise Time 8 ns

t

FI

Input Fall Time 8 ns

t

CKH

SCK High Time 4 ns

t

CKL

SCK Low Time 4 ns

t

CEH

CE# High Time 7 ns

t

CS

CE# Setup Time 5 ns

t

CH

CE# Hold Time 5 ns

t

DS

Data In Setup Time 2 ns

t

DH

Data in Hold Time 2 ns

t

HS

Hold Setup Time 15 ns

t

HD

Hold Time 15 ns

t

V

Output Valid 8 ns

t

OH

Output Hold Time Normal Mode 0 ns

t

LZ

Hold to Output Low Z 7 ns

t

HZ

Hold to Output High Z 12 ns

t

DIS

Output Disable Time 100 ns

Secter Erase Time 50 150 ms

Block Erase Time 500 2000 ms

t

EC

Chip Erase Time (32Mb) 15 20 s

t

PP

Page Program Time 1 2 ms

t

VCS

V

CC

Set-up Time 50 µs

t

res1

3 µs

t

dp

3 µs

t

w

Write Status Register time 2 ms

Pm25LQ032C

Chingis Technology Corp.

38

Date February. 2012, Rev: 1.6.1

AC CHARACTERISTICS (CONTINUED)

SERIAL INPUT/OUTPUT TIMING

(1)

Note: 1. For SPI Mode 0 (0,0)

Pm25LQ032C

Chingis Technology Corp.

39

Date February. 2012, Rev: 1.6.1

AC CHARACTERISTICS (CONTINUED)

HOLD TIMING

PIN CAPACITANCE (f = 1 MHz, T = 25°C )

Typ Max Units Conditions

C

IN

4 6 pF V

IN

= 0 V

C

OUT

8 12 pF V

OUT

= 0 V

Note: These parameters are characterized but not 100% tested.

OUTPUT TEST LOAD INPUT TEST WAVEFORMS

AND MEASUREMENT LEVEL

30pF

Pm25LQ032C

Chingis Technology Corp.

40

Date February. 2012, Rev: 1.6.1

POWER-UP AND POWER-DOWN

At Power-up and Power-down, the device must not be

selected (CE# must follow the voltage applied on Vcc)

until Vcc reaches the correct value:

- Vcc(min) at Power-up, and then for a further delay of

tVCE

-

Vss at Power-down

Usually a simple pull-up resistor on CE# can be used

to insure safe and proper Power-up and Power-down.

To avoid data corruption and inadvertent write

operations during power up, a Power On Reset (POR)

circuit is included. The logic inside the device is held

reset while Vcc is less than the POR threshold value

(Vwi) during power up, the device does not respond to

any instruction until a time delay of tPUW has elapsed

after the moment that Vcc rised above the VWI

threshold. However, the correct operation of the device

is not guaranteed if, by this time, Vcc is still below

Vcc(min). No Write Status Register, Program or Erase

instructions should be sent until the later of:

- tPUW after Vcc passed the VWI threshold

- tVCE after Vcc passed the Vcc(min) level

At Power-up, the device is in the following state:

- The device is in the Standby mode

- The Write Enable Latch (WEL) bit is reset

At Power-down, when Vcc drops from the operating

voltage, to below the Vwi, all write operations are

disabled

and the device does not respond to any write

instruction.

Chip Selection Not Allowed

All Write Commands are Rejected

tVCE Read Access Allowed Device fully accessible

tPUW

Vcc

Vcc(max)

Vcc(min)

Reset State

V (write inhibit)

Time

Symbol Parameter Min. Max. Unit

t

VCE

*1

Vcc(min) to CE# Low 10 us

t

PUW

*1

Power-Up time delay to Write instruction 1 10 ms

V

WI

*1

Write Inhibit Voltage 2.4 V

Note : *1. These parameters are characterized only.

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Date February. 2012, Rev: 1.6.1

PROGRAM/ERASE PERFORMANCE

Parameter Unit

Typ

Max

Remarks

Sector Erase Time ms

50 150 From writing erase command to erase completion

Block Erase Time ms

500

2000

From writing erase command to erase completion

Chip Erase Time (32Mb)

s 15 20 From writing erase command to erase completion

Page Programming Time

ms

1 2 From writing program command to program completion

Byte Program us 8 25

Note: These parameters are characterized and are not 100% tested.

RELIABILITY CHARACTERISTICS

Parameter Min Typ Unit Test Method

Endurance 100,000 Cycles JEDEC Standard A117

Data Retention 20 Years JEDEC Standard A103

ESD – Human Body Model 2,000 Volts JEDEC Standard A114

ESD – Machine Model 200 Volts JEDEC Standard A115

Latch-Up 100 + I

CC1

mA JEDEC Standard 78

Note: These parameters are characterized and are not 100% tested.

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Chingis Technology Corp.

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Date February. 2012, Rev: 1.6.1

PACKAGE TYPE INFORMATION (CONTINUED)

`

8B

8-Pin JEDEC 208mil Broad Small Outline Integrated Circuit (SOIC) Package

(measure in millimeters)

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Chingis Technology Corp.

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Date February. 2012, Rev: 1.6.1

PACKAGE TYPE INFORMATION (CONTINUED)

`

8F

8-Pin 208mil VSOP Package

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Chingis Technology Corp.

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Date February. 2012, Rev: 1.6.1

PACKAGE TYPE INFORMATION (CONTINUED)

8K

8-Contact Ulta-Thin Small Outline No-Lead (WSON) Package (measure in millimeters)

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Chingis Technology Corp.

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Date February. 2012, Rev: 1.6.1

PACKAGE TYPE INFORMATION (CONTINUED)

8P

8-pin 300mil wide body, Plastic Dual In-Line Package PDIP (measure in millimeters)

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Chingis Technology Corp.

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Date February. 2012, Rev: 1.6.1

PACKAGE TYPE INFORMATION (CONTINUED)

8M

16 pin – 16-lead Plastic Small Outline, 300 mils body width, package outline

2.4

2.25

2.35

2.65

7.4

7.6

10.0

10.65

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Date February. 2012, Rev: 1.6.1

Appendix1: Sector Unlock function

Instruction Name Hex

Code

Operation Command

Cycle

Maximum

Frequency

SECT_UNLOCK 26h Sector unlock 4 Bytes

100 MHz

SECT_LOCK 24h Sector lock 1 Byte

100 MHz

SEC_UNLOCK COMMAND OPERATION

The Sector unlock command allows the user to

select a specific sector to allow program and erase

operations. This instruction is effective when the

blocks are designated as write-protected through

the BP0, BP1, BP2 and BP3 bits in the status

register. Only one sector can be enabled at any

time. To enable a different sector, a previously

enabled sector must be disabled by executing a

Sector Lock command. The instruction code is

followed by a 24-bit address specifying the target

sector, but A0 through A11 are not decoded. The

remaining sectors within the same block remain in

read-only mode.

Figure d. Sector Unlock Sequence

Note: 1.If the clock number will not match 8 clocks(command)+ 24 clocks (address), it will be ignored.

2.It must be executed write enable (06h) before sector unlock instructions.

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Date February. 2012, Rev: 1.6.1

SECT_LOCK COMMAND OPERATION

The Sector Lock command reverses the function of

the Sector Unlock command. The instruction code

does not require an address to be specified, as only

one sector can be enabled at a time. The remaining

sectors within the same block remain in read-only

mode.

Figure e. Sector Lock Sequence

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Chingis Technology Corp.

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Date February. 2012, Rev: 1.6.1

REVISION HISTORY

Date Revision No. Description of Changes Page No.

November, 2008 0.0 Preliminary Product Specification All

March, 2009 0.1 Official Release to customer All

March, 2009 0.2 Modify the block protect area 10,11

April, 2009 0.3 Add the SIR into datasheet 35,36,37

June, 2009 0.4 Change the WP# description

October, 2009 0.5 Add the BP define 10

Feb, 2010 0.6 Modify the speed from 100MHz to

104MHz

Modify the temp range from

40

o

C~85

o

C to -40

o

C~125

o

C

ALL

March, 2010 0.7 Modify the Fig 18 with 4 dummy clock

27

August, 2010 0.8 1. Modify Vih to 0.3Vcc

2. Improve the chip erase speed

December,2010 0.9 1. modify the erase time

2. Remove the 150mil SOP package

February, 2011 1.0 1. modify the read ID description 16

March, 2011 1.1 1. Add the Hold pin in the package

map.

3

May,2011 1.2 1. Independent 32Mb all

May, 2011 1.3 Remove the power down function

May, 2011 1.4 Add the sector unlock function

June, 2011 1.5 Add the VSOP package

June,2011 1.6 Modify the BP table 10

Feb,2012 1.6.1 Revise the active read current max to

15mA

1