ICS91730AMLF-T - Integrated Device Technology

Integrated

Circuit

Systems, Inc.

ICS91730

0794D—05/23/05

Block Diagram

Pin Configuration

Features:

• ICS91730 is a Spread Spectrum Clock targeted for

Mobile PC and LCD panel applications that

generates an EMI-optimized clock signal (EMI peak

reduction of 7-14 dB on 3rd-19th harmonics) through

use of Spread Spectrum techniques.

• ICS91730 focuses on the lower input frequency

range of 14.318 to 80.00 MHz with a spread

modulation of 20kHz to 40kHz.

Specifications:

• Supply Voltages: VDD = 3.3V ±0.3V

• Frequency range: 14.318 MHz ≤ Fin ≥ 80 MHz

• Cyc to Cyc jitter: <150ps

• Output duty cycle 45-55%

• Guarantees +85°C operational condition.

• 8-pin SOIC

• Reference input

Low EMI, Spread Modulating, Clock Generator

Functionality

CLK

REFOUT

OUT

PD#

CLKIN

PLL1

Spread

Spectr

SCLK

FS_IN1

Control

Logic

Config.

Reg.

FSIN_1

0-0.8 down spread

1-1.25 down spread

27.00MHz in --> 27.00MHz out

MHz Spread % default

14.318 MHz in --> 27MHz out

CLKIN 18

PD#*

VDD 27

SCL

GND 36

SDATA

CLKOUT 45

REF_OUT/FS_IN1*

8 Pin SOIC

* Internal Pull-Up Resistor

ICS91730

0794D—05/23/05

Pin Descriptions

PIN # PIN NAME PIN

TYPE DESCRIPTION

1CLKIN PWRIn

ut for reference clock.

2 VDD IN Power su

, nominal 3.3V

3 GND OUT Ground

in.

4 CLKOUT I/O Modulated clock out

ut.

Un-modulated 3.3V reference clock out

ut.

Fre

uenc

select latch in

ut. Refer to the functionalit

table.

6SDATA PWRData

in for SMBus circuitr

, 5V tolerant.

7 SCLK PWR Clock

in of SMBus circuitr

, 5V tolerant.

8PD#* PWR

Asynchronous active low input pin, with 120Kohm internal pull-up resistor,

used to power down the device. The internal clocks are disabled and the

VCO and the crystal are stopped.

* Internal Pull-Up Resistor ** Internal Pull-Down Resistor

I/OREF_OUT/FS_IN1*5

ICS91730

0794D—05/23/05

Table 1: Frequency Configuration Table

(See I2C Byte 0)

Above is the hard coded 5 bit (32 entry) ROM table.

FS3:0 are ONLY accessible through I2C software programming bits (byte0 bits5:7). FS4 can also be decoded from

FS_IN1 latched input hardware pins.

FS_IN1 → FS4. Upon power-up the default is to use hardware selection of FS_IN1 latched value.

FS3 = 0, FS2 = 0, FS1 = 0, FS0 = 1 upon power-up (refer to the functionality table on page 1).

To access non-default spread entries in the ROM, byte0 programming should be used. In order to change the power

up default of FS_IN1 = 1 (-1.25% down spread) to any other spread % entry, first change byte0bit 0 to software

selection by switching this bit to a ‘1’ and then program the desired percentage by changing byte0 bits 7:3.

FS4 FS3 FS2 FS1 FS0 Sprd Type Sprd %

00000 0.60

00001 0.80

00010 1.00

00011 1.25

00100 1.50

00101 2.00

00110 0.50

00111 1.00

01000 0.60

01001 1.00

01010 0.80

01011CTR SPD0.3

01100

1.50

01101 1.75

01110 2.00

01111 2.50

10000 3.00

10001 1.25

10010 0.40

10011 0.50

10100 0.70

10101 1.00

10110 1.20

10111 1.50

11000 0.60

11001 0.80

11010 1.00

11011 1.25

11100 1.50

11101 2.00

11110 0.50

11111 1.00

48in/48out

66in/66out

DOWN

SPREAD

(-)

CENTER SPD

(+/-)

14in/27out

DOWN

SPREAD

(-)

CENTER SPD

(+/-)

14in/14out

27in/27out

CENTER SPD

(+/-)

DOWN

SPREAD

(-)

DOWN

SPREAD

(-)

ICS91730

0794D—05/23/05

General I2C serial interface information

How to Write:

•Controller (host) sends a start bit.

• Controller (host) sends the write address D4 (H)

• ICS clock will

acknowledge

• Controller (host) sends the begining byte location = N

• ICS clock will

acknowledge

• Controller (host) sends the data byte count = X

• ICS clock will

acknowledge

• Controller (host) starts sending

Byte N through

Byte N + X -1

(see Note 2)

• ICS clock will

acknowledge

each byte

one at a time

• Controller (host) sends a Stop bit

How to Read:

• Controller (host) will send start bit.

• Controller (host) sends the write address D4 (H)

• ICS clock will

acknowledge

• Controller (host) sends the begining byte

location = N

• ICS clock will

acknowledge

• Controller (host) will send a separate start bit.

• Controller (host) sends the read address D5 (H)

• ICS clock will

acknowledge

• ICS clock will send the data byte count = X

• ICS clock sends

Byte N + X -1

• ICS clock sends

Byte 0 through byte X (if X

(H)

was written to byte 8)

• Controller (host) will need to acknowledge each byte

• Controllor (host) will send a not acknowledge bit

• Controller (host) will send a stop bit

ICS (Sla ve/Rece iver)

ACK

Byte N + X - 1

Data Byte Count = X

Beginning Byte N

stoP bit

X Byte

Index Block Writ e Operatio n

Slave Address D4(H)

Beginning Byte = N

WRite

starT bit

Controlle r (Host)

TstarT bit

WR WRite

RT Repeat starT

RD ReaD

Beginning Byte N

Byte N + X - 1

N Not acknowledge

PstoP bit

ICS (Sla ve/Rece iver)

Controll er (Host)

X Byte

ACK

Data Byte Count = X

ACK

Slave Address D5(H)

Index Block Read O pe ration

Slave Address D4(H)

Beginning Byte = N

ACK

ICS91730

0794D—05/23/05

0 Pin # Name Control Function 0 1 PWD

Bit 7 - FS0 Spread/FS0 RW 1

Bit 6 - FS1 Spread/FS1 RW 0

Bit 5 FS2 Spread/FS2 RW 0

Bit 4 FS3 Spread/FS3 RW 0

Bit 3 FS4 FS4 RW 0

Bit 2 PD# Tri_Sate PD# Tri_Sate RW Hi-Z LOW 1

Bit 1 Spread Enable Spread Enable RW OFF ON 1

Bit 0 HW/SW Control

Spread Spectrum Control

FS 3:4 Hard/Software

Select RW HW SW 0

1 Pin # Name Control Function 0 1 PWD

Bit 7 REF_OUT REF_OUT_Enable RW Disable Enable 1

Bit 6 - REF_OUT Slew Rate REF-OUT RW Nominal Fast 1

Bit 5 FS-IN_1 FS-IN_1 Readback R - - X

Bit 4 (Reserved) (Reserved) R - - 0

Bit 3 CLK_OUT Slew Rate CLK-OUT RW Nominal Fast 1

Bit 2 CLK_OUT CLK_OUT_Enable RW Disable Enable 1

Bit 1 (Reserved) (Reserved) R - - 1

Bit 0 (Reserved) (Reserved) R- -1

2 Pin # Name Control Function 0 1 PWD

Bit 7 x - (Reserved) - - - 1

Bit 6 x (Reserved) (Reserved) RW Disable Enable 1

Bit 5 x (Reserved) (Reserved) RW Disable Enable 1

Bit 4 x (Reserved) (Reserved) RW Disable Enable 1

Bit 3 x (Reserved) (Reserved) RW Disable Enable 1

Bit 2 x (Reserved) (Reserved) RW Disable Enable 1

Bit 1 x (Reserved) (Reserved) RW Disable Enable 1

Bit 0 x(Reserved) (Reserved) RW Disable Enable 1

Affected Pin

Srpead Pecentage

See Table1

These are I2C bits

only

Bit Control

ICS91730

0794D—05/23/05

3 Pin # Name Control Function 0 1 PWD

Bit 7 X (Reserved) (Reserved) RW - - 1

Bit 6 X (Reserved) (Reserved) RW - - 1

Bit 5 X (Reserved) (Reserved) RW - - 1

Bit 4 X (Reserved) (Reserved) RW - - 1

Bit 3 x (Reserved) (Reserved) RW - - 1

Bit 2 X (Reserved) (Reserved) RW - - 1

Bit 1 X (Reserved) (Reserved) RW - - 1

Bit 0 X(Reserved) (Reserved) RW - - 1

4 Pin # Name Control Function 0 1 PWD

Bit 7 X (Reserved) (Reserved) RW - - 1

Bit 6 X (Reserved) (Reserved) RW - - 1

Bit 5 X (Reserved) (Reserved) RW - - 1

Bit 4 X (Reserved) (Reserved) RW - - 1

Bit 3 X (Reserved) (Reserved) RW - - 1

Bit 2 X (Reserved) (Reserved) RW - - 1

Bit 1 X (Reserved) (Reserved) RW - - 1

Bit 0 X (Reserved) (Reserved) RW --

5 Pin # Name Control Function 0 1 PWD

Bit 7 X (Reserved) (Reserved) - - - 1

Bit 6 X (Reserved) (Reserved) - - - 1

Bit 5 X (Reserved) (Reserved) - - - 1

Bit 4 X (Reserved) (Reserved) - - - 1

Bit 3 X (Reserved) (Reserved) RW - - 1

Bit 2 X (Reserved) (Reserved) RW - - 1

Bit 1 X (Reserved) (Reserved) RW - - 1

Bit 0 X (Reserved) (Reserved) RW --

Affected Pin Bit Control

Affected Pin

Bit ControlAffected Pin

Bit Control

ICS91730

0794D—05/23/05

6 Pin # Name Control Function 0 1 PWD

Bit 7 X Revision ID Bit 3 (Reserved) R - - 1

Bit 6 X Revision ID Bit 2 (Reserved) R - - 1

Bit 5 X Revision ID Bit 1 (Reserved) R - - 1

Bit 4 X Revision ID Bit 0 (Reserved) R - - 1

Bit 3 X Vendor ID Bit 3 (Reserved) R - - 1

Bit 2 X Vendor ID Bit 2 (Reserved) R - - 1

Bit 1 X Vendor ID Bit 1 (Reserved) R - - 1

Bit 0 X Vendor ID Bit 0 (Reserved) R- -1

Bit ControlAffected Pin

ICS91730

0794D—05/23/05

Absolute Maximum Ratings

Stresses above those listed under

Absolute Maximum Ratings

may cause permanent damage to the device. These

ratings are stress specifications only and functional operation of the device at these or any other conditions above those

listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions

for extended periods may affect product reliability.

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 3.7 V

Voltage on any pin with respect to GND . . . -0.5 to +3.7 V

Storage Temperature . . . . . . . . . . . . . . . . . . . . –55°C to +150°C

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . 0.5 W

Electrical Characteristics - Input/Supply/Common Output Parameters

TA = 0 - 85°C; Supply Voltage VDD = 3.3 V +/-5%

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Input High Voltage VIH 2V

DD + 0.3 V

Input Low Voltage VIL VSS - 0.3 0.8 V

Input High Current IIH VIN = VDD -5 5 mA

Input Low Current IIL1 VIN = 0 V; Inputs with no pull-up resistors -5 mA

Powerdown Current IDD3.3PD 15mA

Input Frequency Fi VDD = 3.3 V 14.318 MHz

Pin Inductance Lpin 7nH

CIN Logic Inputs 5 pF

COUT Output pin capacitance 6 pF

CINX X1 & X2 pins 27 36 45 pF

Transition time

Ttrans To 1st crossing of target frequency 3 ms

Settlin

time1Ts From 1st crossing to 1% target frequency 3 ms

Clk Stabilization1TSTAB From VDD = 3.3 V to 1% target frequency 3 ms

Delay

tPZH,tPZL Output enable delay (all outputs) 1 10 ns

1Guaranteed by design, not 100% tested in production.

Input Capacitance1

ICS91730

0794D—05/23/05

Electrical Characteristics - CLKOUT

TA = 0 - 85°C; VDD = 3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Output High Voltage VOH3 IOH = -1 mA 2.4 V

Output Low Voltage VOL3 IOL = 1 mA 0.4

Rise Time tr3 VOL = 0.41V, VOH = 0.86V 0.5 0.6 1 ns

Fall Time tf3 VOH = 0.86V VOL = 0.41V 0.5 0.6 1 ns

Duty Cycle dt3

measurement from differential wavefrom -

0.35V to +035V 45 50 55 %

Jitter, Cycle to cycle tjcyc-cyc

VT = 50% 50 150 ps

1Guaranteed by design, not 100% tested in production.

Electrical Characteristics - REF

TA = 0 - 85°C; VDD = 3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Output Impedance RDSP11VO = VDD*(0.5) 20 48 60 Ω

Output High Voltage VOH1IOH = -1 mA 2.4 V

Output Low Voltage VOL1IOL = 1 mA 0.4 V

Output High Current IOH1V OH@MIN = 1.0 V, V OH@MAX = 3.135 V -29 -23 mA

Output Low Current IOL1VOL @MIN = 1.95 V, VOL @MAX = 0.4 V 29 27 mA

Rise Time tr11VOL = 0.4 V, VOH = 2.4 V 1 1.2 2 ns

Fall Time tf11VOH = 2.4 V, VOL = 0.4 V 1 1.2 2 ns

Duty Cycle dt11V

= 1.5 V 45 51 55 %

Jitter tjcyc-cyc1VT = 1.5 V 105 300 ps

1Guaranteed by design, not 100% tested in production.

ICS91730

0794D—05/23/05

8-pin SOIC

Ordering Information

ICS91730yMLF-T

MIN MAX MIN MAX

A 1.35 1.75 .0532 .0688

A1 0.10 0.25 .0040 .0098

B 0.33 0.51 .013 .020

C 0.19 0.25 .0075 .0098

E 3.80 4.00 .1497 .1574

H 5.80 6.20 .2284 .2440

h 0.25 0.50 .010 .020

L 0.40 1.27 .016 .050

α0° 8° 0° 8°

VARIATIONS

MIN MAX MIN MAX

8 4.80 5.00 .1890 .1968

10-0030

150 mil (Na rrow Body) SOIC

SYMBOL

In Millimeters In Inches

COMMON DIMENSIONS COMMON DIMENSIONS

SEE VARIATIONS SEE VARIATIONS

1.27 BASIC 0.050 BASIC

Reference Doc.: JEDEC Publication 95, MS-012

SEE VARIATIONS SEE VARIATIONS

ND mm. D (inch)

Example:

Designation for tape and reel packaging

RoHS Compliant (Optional)

Package Type

M = SOIC

Revision Designator (will not correlate with datasheet revision)

Device Type

Prefix

ICS = Standard Device

ICS XXXX y M LF- T

ICS91730

0794D—05/23/05

Revision History

Issue Date Descri

tion Pa

e #

06/25/04 Add Lead Free packa

e description to Orderin

Information 10

06/29/04 Add Revision History table to datasheet. 11

05/23/05

1. Revise ABS Max Ratings.

2. Updated REF Electrical Characteristics Table.

3. Updated LF Orderin

Information from "Lead Free" to "RoHS Compliant". 8-10

Rev.

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Home > Products > Timing Solutions > PC-Notebook-Server Clocks > Clock Synthesizer by Chipset Vendor > Notebook Chipsets > 91730

dd to m

IDT

[

]

91730 (Notebook Chipsets)

Description

Low EMI, Spread Modulating, Clock Generator

Market Group

PC CLOCK

Additional Info

• ICS91730 is a Spread Spectrum Clock targeted for Mobile PC and LCD panel applications that generates an EMI-optimized clock signal (EMI

peak reduction of 7-14 dB on 3rd-19th harmonics) through use of Spread Spectrum techniques. • ICS91730 focuses on the lower input frequency

range of 14.318 to 80.00 MHz with a spread modulation of 20kHz to 40kHz.