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Functional Description
Oscillator
The oscillator circuit of the 82C84A is designed primarily for
use with an external parallel resonant, fundamental mode
crystal from which the basic operating frequency is deri ved.
The crystal frequency should be selected at three times the
required CPU clock. X1 and X2 are the two crystal input
crystal connections. For the most stable operation of the
oscillator (OSC) output circuit, two capacitors (C1 = C2) as
shown in the waveform figures are recommended. The out-
put of the oscillator is buffered and brought out on OSC so
that other system timing signals can be derived from thi s sta -
ble, crystal-controlled source.
Capacitors C1, C2 are chosen such that their combined
capacitance
matches the load capacitance as specified by the crystal
manufacturer. This ensures operation within the frequency
tolerance specifi ed by the crystal manufacturer.
Clock Generator
The clock generator consists of a synchronous divide-by-
three counter with a special clear input that inhibits the
counting. This clear input (CSYNC) allows the output clock
to be synchronized with an external event (such as another
82C84A clock). It is necessary to synchronize the CSYNC
input to t he EFI clock external to t he 82C84A. This is accom-
plished with two flip-flops. (See Figure 1). The counter out-
put is a 33% duty cycle clock at one-third the input
frequency.
NOTE: The F/C input is a strapping pin that selects either the crystal
os cillator or the EFI in put as the cloc k for the ÷ 3 counte r. If
the EFI i nput is selected as the clock source, the oscill ator
section can be used independently for another clock source.
Ou tpu t is taken from OS C.
Clock Outputs
The CLK ou tput is a 33% duty cy cle clock driver desi gned to
drive the 80C86, 80C88 processors directly. PCLK is a periph-
eral clock signal whose output frequency is 1/2 that of CLK.
PCLK has a 50% duty cycle.
Reset Logi c
The reset logic provides a Schmitt trigger input (RES) and a
synchron izing flip-flop to generate the reset timing. The reset
signal is synchronized to the falling edge of CLK. A simple RC
network can be used to provide power-on reset by utilizing this
function of the 82C84A.
READY Synchronization
Two REA DY input (RDY 1, RDY2) are p rovided to acc ommo-
date two system busses. Each input has a qualifier (AEN1 and
AEN2, respectively). The AEN signals validate their respective
RDY signals. If a Multi-Master system is not being used the
AEN pin should be tied LOW.
Synchron ization is requi red for all async hronous active-going
edges of either RDY input to guarantee that the RDY setup
and hol d times are m et. Inactive-going edg es of RDY in nor-
mally read y systems do not re quire synchroniza tion but must
satisfy RDY setup and hold as a matter of proper system
design.
The A SYN C input defin es two mode s of RE ADY s ynch roniza -
tion operation.
When ASYN C is LOW, two stages of synchronization are pro-
vided for active READY input signals. Positive-going asyn-
chronous READY inputs will first be synchronized to flip-flop
one of the rising edge of CLK (requiring a setup time tR1VCH)
and the synchron ized to flip-flop two at the next falling edge of
CLK, after which time the READY output will go active (HIGH).
Negative -going a synchrono us READ Y inputs will be synchro -
nized directly to flip-flop two at the falling edge of CLK, after
which the R EAD Y outp ut will go ina ctive. This m ode of opera-
tion is in tende d for use by a sync hrono us (nor mally n ot ready )
devices i n the syste m which c annot be g uarantee d by desig n
to meet the required RDY setup timing, TR1VCL, on each bus
cycle.
When AS YNC is hi gh or left o pen, the first READ Y flip-flop is
bypassed in the R EAD Y sy nchronization logic. REA DY inputs
are synchronized by flip-flop two on the falling edge of CLK
before they are presented to the processor. This mode is
available for synchr onous devic es that can be guaranteed to
meet the required RDY setup time.
ASYNC can be changed on every bus cycle to select the
appropriate mode of synchronization for each device in the
system.
TABLE 1. CRYSTAL SPECIFICATIONS
PARAMETER TYPICAL CRYSTAL SPEC
Frequency 2.4 - 25MHz, Fundamental, “AT” cut
Type of Operation Parallel
Unwanted Modes 6dB (Mini m um)
Load Capacitance 18 - 32pF
CT = C1 x C2
C1 + C2
---------------------- (Including stray capacitance)
EFI
EFI
82C84A
CSYNC
(TO OTHER 82C84As)
CLOCK
SYNCHRONIZE DQ
>
DQ
>
FIGURE 1. CSYNC SYNCHRONIZATION
NOTE: If EFI input is used, then crystal input X1 must be tied to VCC or GND and X2 should be left op en. If the crys tal inp uts are used,
then EFI sh ould be tied to VCC or GND.
82C84A