287
TM
March 1997
82C84A
C MOS Cloc k Gener at or Driver
Features
• Generates the System Clock For CMOS or NMOS
Microprocessors
• Up to 25MHz Operat ion
• Uses a Parallel Mode Crystal Circ uit or External
Frequency Source
• Provides Ready Synchronization
• Generates System Reset O utput From Schmitt Tr igger
Input
• TTL Compatible Inputs/Outputs
• Very Low Power Consumptio n
• Single 5V Power Supply
• Operating Temperature Ranges
- C82 C84A . . . . . . . . . . . . . . . . . . . . . . . . .0oC to +70oC
- I82C84A . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
- M82C84A . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
Description
The Intersil 82C84A is a high performanc e CMOS Clock Generator-
driver which is de signed to service the requirements of both CMOS
and NMOS microprocessors such as the 80C86, 80C88, 8086 and
the 8088. The chip contains a crystal controlled oscillator, a divide-by-
three counter and complete “Ready” synchronization and reset logic.
Static CMOS circuit design permits operation with an external fre-
quency source from DC to 25MHz. Crystal controlled operation to
25MHz is guaranteed with the use of a parallel, fundamental mode
c ryst al and two small load capacitors.
All inputs (except X1 and RES) are TTL compatible over tempera-
ture and voltage ranges .
Po w er c on s um ptio n is a fracti on of t hat of the equivalent bi po la r cir-
cuits. This speed-power characteristic of CMOS permits the
designer to custom tailor his system design with respect to power
and/or sp ee d r eq ui r em en ts .
Ordering Information
PART
NUMBER TEMP. RANGE PACKAGE PKG.
NO.
CP82C84A 0oC to +70oC 18 Ld PDIP E18.3
IP82C84A -40oC to +85oCE18.3
CS82C84A 0oC to +70oC 20 Ld PL CC N20.35
IS82C84A -40oC to +85oCN20.35
CD82C84A 0oC to +70oC 18 Ld CERDIP F18.3
ID82C84A -40oC to +85oCF18.3
MD82C84A/B -55oC to +125oCF18.3
8406801VA SMD# F18.3
MR82C84A/B -55oC to +125oC 20 Pad CLCC J20.A
84068012A SMD# J20.A
Pinouts
82C84A (PDIP, CERDIP)
TOP VIEW 82C84A (PLCC, CLCC)
TOP VIEW
10
11
12
13
14
15
16
17
18
9
8
7
6
5
4
3
2
1 VCC
X2
EFI
F/C
OSC
RES
X1
GND
ASYNC
RESET
CSYNC
PCLK
RDY1
READY
RDY2
CLK
AEN1
AEN2
4
5
6
7
8
910111213
3212019
15
14
18
17
16
RDY1
AEN2
NC
READY
RDY2
NC
F/C
EFI
X2
CLK
RESET
GND
OSC
RES VCC
CSYNC
PCLK
X1
AEN1
ASYNC
FN2974.1
CA UTION: The se devices are s ensi tiv e to el ectrosta tic di schar ge; follow proper IC H andling Procedures.
1-888-INTERSIL or 321-724-7143 |Intersil (and desi gn) is a trademark of Intersil Americas Inc.
Copyr ight © Intersil America s Inc. 20 02. All Rights R eserved
288
Functional Diag ram
CONTROL PIN LOGICAL 1 LOGICAL 0
F/C External Clock Crystal Drive
RES Normal Reset
RDY1, RDY2 Bus Ready Bus Not Ready
AEN1, AEN2 Address Disabled Address Enable
ASYNC 1 Stage Ready
Synchronization 2 Stage Ready
Synchronization
X1
X2
EF1
CSYNC
RDY1
RDY2
11
17
16
13
14
1
4
3
6
7
15
RESET
OSC
PCLK
CLK
READY
XTAL
OSCILLATOR
CK
DQ
FF1
CK
D
CK
DQ
FF2
Q
12
2
8
5
10
RES
F/C
AEN1
AEN2
ASYNC
SYNC
÷ 2
SYNC
÷ 3
82C84A
289
Pin Descr iption
SYMBOL NUMBER TYPE DESCRIPTION
AEN1,
AEN2 3, 7 I ADDRESS ENABLE: AEN is an acti ve LOW si gnal. AEN serves to qualify its respective Bus
Ready Signal (RDY1 or RDY2). AE N1 validates R DY1 w hile AE N2 valida tes RDY2. Two AEN
signal inputs are useful in system configurations which permit the proc es sor to access two Multi-
Master System Busses. In non-Multi-Master configuratio ns, the AEN signal inputs are tied true
(LOW).
RDY1,
RDY2 4, 6 I BUS READY (Trans fer C omplete). RDY is an active HIGH signal which i s an indication from a
device located on the system data bus that data has been received, or is available RDY1 is qual-
ified by AEN1 whil e RDY 2 is qual ifi ed by AEN2.
ASYNC 15 I READY SYNCHRONIZATION SELECT: AS Y NC is an input which d efines the sy nchr onization
mode of th e REA DY logic. When ASYNC is low, two stages of READY synchronization are pro-
vided. When ASYNC is le ft o pe n or H IG H, a sing le st ag e of R EADY sy nc hron iz at i on is p r ovi ded.
READ Y 5 O RE ADY: READY is an active HI GH si gnal whi ch is the synchronized RDY sign al input. READY
is cleared af ter the guarantee d hol d time to the processor has bee n met .
X1, X2 17, 16 I O CRYSTAL IN: X1 and X2 are the pi ns to which a crystal is attached. The crystal frequency is 3
times the desired processor clock frequency, (Note 1).
F/C 13 I FREQUENCY/CRYSTAL SELECT: F/C is a st ra ppi n g o pti on . When s tra pp ed LO W. F/C per mi ts
the pr oces sor ’ s cl ock to be g en erat e d by the cr ysta l. When F/ C is strapped HIGH, CLK is gener-
ated for the EFI input, (Note 1).
EFI 14 I EXTERNAL FREQUENCY IN: When F/ C is st ra ppe d HI GH , C LK i s g en er ate d f rom th e i nput f re-
quency appearing on this pin. The input signal is a square wave 3 times the frequency of the de-
s ire d CLK output.
CLK 8 O PROCESSOR CLOCK: CLK is the clock output used by the processor and all devices which di-
rectly connect to the processor’s local bus. CLK has an output frequency which is 1/3 of the crys-
tal or EFI input frequency and a 1/3 duty cycle.
PCL K 2 O PERIPH ERA L CLO CK: PCLK is a p eripheral clock signal whose output frequency is 1/2 that of
CLK and has a 50% duty cycle.
OSC 12 O OSCILLATOR OUTPUT: OSC is the output of the internal oscillator circuitry. Its frequency is
equal to that of the crystal.
RES 11 I RESET IN: RES is an active LO W signal w hich is us ed to generate RESET. The 82 C84A pr o-
v ides a Schmitt trigger input so that an RC connection can be used to establish the power-up
reset of proper duration.
RESET 10 O RESET: RESET is an active HIGH signal which is used to reset the 80C86 family processors. Its
timing characteristics are determined by RES.
CSYNC 1 I CLOCK SYNCHRONIZATION: CSYNC is an active HIGH signal wh ic h all ows multiple 82 C84As
to be synchronized to provide clocks tha t are in pha se. When CS YNC is HIGH the inte rnal
c ount ers ar e re set . When CSY NC go es LOW th e i nte rn al co un te rs a re allo w ed t o r esume co un t-
ing. CSYNC needs to be externally synchronized to EFI. When using the internal oscillator
CSYNC should be hardwired to ground.
GND 9 Ground
VCC 18 VCC: The +5V power supply pin. A 0.1µF cap ac it or bet we en VCC a nd GN D is rec omm end ed f or
decoupling.
NOTE:
1. If the crystal inputs are not used X1 must be tied to VCC or GND and X2 should be left open.
82C84A
290
Functional Description
Oscillator
The oscillator circuit of the 82C84A is designed primarily for
use with an external parallel resonant, fundamental mode
crystal from which the basic operating frequency is deri ved.
The crystal frequency should be selected at three times the
required CPU clock. X1 and X2 are the two crystal input
crystal connections. For the most stable operation of the
oscillator (OSC) output circuit, two capacitors (C1 = C2) as
shown in the waveform figures are recommended. The out-
put of the oscillator is buffered and brought out on OSC so
that other system timing signals can be derived from thi s sta -
ble, crystal-controlled source.
Capacitors C1, C2 are chosen such that their combined
capacitance
matches the load capacitance as specified by the crystal
manufacturer. This ensures operation within the frequency
tolerance specifi ed by the crystal manufacturer.
Clock Generator
The clock generator consists of a synchronous divide-by-
three counter with a special clear input that inhibits the
counting. This clear input (CSYNC) allows the output clock
to be synchronized with an external event (such as another
82C84A clock). It is necessary to synchronize the CSYNC
input to t he EFI clock external to t he 82C84A. This is accom-
plished with two flip-flops. (See Figure 1). The counter out-
put is a 33% duty cycle clock at one-third the input
frequency.
NOTE: The F/C input is a strapping pin that selects either the crystal
os cillator or the EFI in put as the cloc k for the ÷ 3 counte r. If
the EFI i nput is selected as the clock source, the oscill ator
section can be used independently for another clock source.
Ou tpu t is taken from OS C.
Clock Outputs
The CLK ou tput is a 33% duty cy cle clock driver desi gned to
drive the 80C86, 80C88 processors directly. PCLK is a periph-
eral clock signal whose output frequency is 1/2 that of CLK.
PCLK has a 50% duty cycle.
Reset Logi c
The reset logic provides a Schmitt trigger input (RES) and a
synchron izing flip-flop to generate the reset timing. The reset
signal is synchronized to the falling edge of CLK. A simple RC
network can be used to provide power-on reset by utilizing this
function of the 82C84A.
READY Synchronization
Two REA DY input (RDY 1, RDY2) are p rovided to acc ommo-
date two system busses. Each input has a qualifier (AEN1 and
AEN2, respectively). The AEN signals validate their respective
RDY signals. If a Multi-Master system is not being used the
AEN pin should be tied LOW.
Synchron ization is requi red for all async hronous active-going
edges of either RDY input to guarantee that the RDY setup
and hol d times are m et. Inactive-going edg es of RDY in nor-
mally read y systems do not re quire synchroniza tion but must
satisfy RDY setup and hold as a matter of proper system
design.
The A SYN C input defin es two mode s of RE ADY s ynch roniza -
tion operation.
When ASYN C is LOW, two stages of synchronization are pro-
vided for active READY input signals. Positive-going asyn-
chronous READY inputs will first be synchronized to flip-flop
one of the rising edge of CLK (requiring a setup time tR1VCH)
and the synchron ized to flip-flop two at the next falling edge of
CLK, after which time the READY output will go active (HIGH).
Negative -going a synchrono us READ Y inputs will be synchro -
nized directly to flip-flop two at the falling edge of CLK, after
which the R EAD Y outp ut will go ina ctive. This m ode of opera-
tion is in tende d for use by a sync hrono us (nor mally n ot ready )
devices i n the syste m which c annot be g uarantee d by desig n
to meet the required RDY setup timing, TR1VCL, on each bus
cycle.
When AS YNC is hi gh or left o pen, the first READ Y flip-flop is
bypassed in the R EAD Y sy nchronization logic. REA DY inputs
are synchronized by flip-flop two on the falling edge of CLK
before they are presented to the processor. This mode is
available for synchr onous devic es that can be guaranteed to
meet the required RDY setup time.
ASYNC can be changed on every bus cycle to select the
appropriate mode of synchronization for each device in the
system.
TABLE 1. CRYSTAL SPECIFICATIONS
PARAMETER TYPICAL CRYSTAL SPEC
Frequency 2.4 - 25MHz, Fundamental, “AT” cut
Type of Operation Parallel
Unwanted Modes 6dB (Mini m um)
Load Capacitance 18 - 32pF
CT = C1 x C2
C1 + C2
---------------------- (Including stray capacitance)
EFI
EFI
82C84A
CSYNC
(TO OTHER 82C84As)
CLOCK
SYNCHRONIZE DQ
>
DQ
>
FIGURE 1. CSYNC SYNCHRONIZATION
NOTE: If EFI input is used, then crystal input X1 must be tied to VCC or GND and X2 should be left op en. If the crys tal inp uts are used,
then EFI sh ould be tied to VCC or GND.
82C84A
291
Absolute Maximum Ratin gs Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+8.0V
Input, Output or I/O Voltage . . . . . . . . . . . GND -0.5 V to VCC +0.5V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Ope rat i ng Conditio ns
Operating Volta ge Ra nge. . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range
C82 C84A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to +70oC
I82C84A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
M82C84A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 oC to +1 25oC
Thermal Resistance . . . . . . . . . . . . . . . . θJA (oC/W) θJC (oC/W)
CERDIP Package . . . . . . . . . . . . . . . . 80 20
CLCC Package . . . . . . . . . . . . . . . . . . 95 28
PDIP Package. . . . . . . . . . . . . . . . . . . 85 N/A
PLCC Package . . . . . . . . . . . . . . . . . . 85 N/A
Storage Tem perature Range . . . . . . . . . . . . . . . . .-65oC to +150oC
Max Juncti on Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
Lead Temperature (Soldering 10 s). . . . . . . . . . . . . . . . . . . . +300oC
(PLCC - Lead Tips Only)
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specifi cation is not implied.
DC Electrical Speci fications VCC = +5.0V ±10%,
TA = 0oC to +70oC (C82C84A),
TA = -40oC to +85oC (I 82C84A),
TA = -55oC to +125oC (M82C84A)
SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS
VIH Logical On e Input Vo ltage 2.0
2.2 -V
VC82C84A, I82C84
M8 2C84A , No tes 1, 2
VIL Logi cal Zero Input Voltage - 0.8 V Notes 1, 2, 3
VIHR Reset Input High Voltage VCC -0.8 - V
VILR Reset Input L ow Voltage - 0.5 V
VT+ - VT- Reset Input Hysteresis 0.2 VCC --
VOH Logical On e Output Current VCC -0.4 - V IOH = -4.0mA for CLK Output
IOH = -2 .5mA for All Others
VOL Logical Zero Outpu t Voltag e - 0.4 V IOL = +4.0mA for CLK Output
IOL = +2.5mA for All Othe rs
II Input Leakage Current -1.0 1.0 µAV
IN = VCC or GND e xce pt A SYNC,
X1: (Note 4)
ICCOP Operati ng Po wer Supply Curren t - 40 mA Cr ystal Fr equency = 25MHz
Outp ut s Open, N ote 5
NOTES:
1. F/C is a strap option and should be held either ≤ 0.8V or ≥ 2.2V . Does not ap pl y to X 1 or X 2 pin s .
2. Due to test equipment limitations related to noise, the actual tested value may differ from that specified, but the specified limit is
guaranteed.
3. CSYNC pin is tested with V IL ≤ 0.8V.
4. ASYNC pin includes an internal 17.5kΩ nominal pull-up resistor. For ASYNC input at GND, ASYNC input le akage cur re nt = 300µA
nominal, X1 - crystal feedback input.
5. f = 25MHz may be tested using the extrapolated value based on measurements taken at f = 2MHz and f = 10MHz.
Capacitance TA = +25oC
SYMBOL PARAMETER TYPICAL UNITS TEST CONDITIONS
CIN Input Capacitance 10 pF FREQ = 1MHz, all measurements are
referenced to device GND
COUT Output Capacitance 15 pF
82C84A
292
AC Electrical Specifications VCC = + 5V ± 10%,
TA = 0oC to +70oC (C82C84A),
TA = -40oC to +85oC (I82C84A),
TA = -55oC to +125oC (M82C84A)
SYMBOL PARAMETER
LIMITS
UNITS
(NOTE 1)
TEST
CONDITIONS MIN MAX
TIMING REQUIREMENTS
(1) TEHEL External Frequency HIGH Time 13 - ns 90%-90% VIN
(2) TELEH External Frequency LOW Time 13 - ns 10%-10% VIN
(3) TEL EL EFI Period 36 - ns
XTAL Frequency 2.4 25 MHz Note 2
(4) TR2VCL RDY1, RDY2 Active Setup to CL K 35 - n s ASYNC = HIGH
(5) TR1VCH RDY1, RDY2 Active Setup to CLK 35 - n s ASYNC = LOW
(6) TR1VCL RDY1, RDY2 Inactive Setup to CL K 35 - ns
(7) TCLR1X RDY1, RDY2 Hold to CLK 0 - ns
(8) TAYVCL ASYNC Setu p to CLK 5 0 - ns
(9) TCLAYX ASYNC Ho ld to CLK 0 - ns
(10) TA1VR1V AEN1, AEN2 Setup to RDY1, RDY2 15 - ns
(11) TCLA1X AEN1, AEN2 Hold to CLK 0 - ns
(12) T Y HE H CSYNC Setup to EFI 20 - ns
(13) T E HY L CSYNC Hold to EFI 20 - ns
(14) T Y HY L CSYNC Wi dth 2 TELEL - ns
(15) TI1HCL RES Setup to CLK 65 - ns Not e 3
(16) TCLI1H RES Hold to CLK 20 - ns Note 3
TIMING RESPONSES
(17) TCLCL CLK Cycle Period 125 - ns Note 6
(18) T CHCL CLK HIGH Time (1/3 TCLCL) + 2.0 - ns Note 6
(19) T CLCH CLK LO W Ti me (2 /3 TC L C L) - 15 .0 - ns Not e 6
(20)
(21) TCH1CH2
TCL2CL1 CLK Rise or Fall Time - 10 ns 1.0V to 3.0V
(22) TPHPL PCLK HIGH Time TCLCL-20 - ns Note 6
(23) TPLPH PCLK LOW Time TCLCL-20 - ns Note 6
(24) TRYLCL Ready Inactive to CLK (See Note 4) -8 - ns Note 4
(25) TRYHCH Ready Active to CLK (See Note 3) (2/3 TCLCL) -15.0 - ns Note 5
(26) T CL I L CLK to R es et Delay - 4 0 ns
(27) T CL P H CLK to P CL K HIGH Delay - 2 2 ns
(28) TCLPL CLK to PCLK LOW Delay - 22 ns
(29 ) T OLCH OS C to CLK HIGH Delay -5 22 ns
(30) TOLCL OSC to CLK LOW Delay 2 35 ns
NOTES:
1. Tes ted as follows: f = 2.4MHz, VIH = 2 . 6V , VIL = 0.4V, CL = 50pF, VOH ≥ 1.5V, VOL ≤ 1.5V, unless otherwise specif ied. RES and F/C must
switch between 0.4V and VCC -0.4V. Input rise and fall times driven at 1ns/V. VIL ≤ VIL (max) - 0.4V for CSYNC pin. VCC = 4.5V and 5.5V.
2. Tested using EFI or X1 input pin.
3. Se t u p an d hold necessa r y on ly to gua rante e rec og nitio n at ne xt clock .
4. Applies only to T2 states.
5. Applies only to T3 TW states.
6. Tested with EFI input frequency = 4.2MHz.
82C84A
293
Timing Waveforms
NOTE: All timing measurements are made at 1.5V, unless otherwise noted.
FIGURE 2. WAVEFORMS FOR CLOCKS AND RESETS SIGNALS
FIGURE 3. WAV E FORMS FOR READY SIGNALS (FOR ASYNCHRONOUS DEVI CES)
FIGURE 4. WAV E FORM S FOR READY SIGNALS (FOR SY NCHRONOUS DEVICES)
tEHYL
(13)
NAME
EFI
OSC
CLK
PCLK
CSYNC
RES
RESET
I/O
I
O
O
O
O
I
ItYHYL
(14)
(12)
tYHEH
(20)
tCH1CH2
(29)
tOLCH
tELEL
(3)
(30)
tOLCL
(21)
tCL2CL1
(27)
tCLPH
(23)
tPLPH
tCLI1H
(16)
tCLCH
(19)
(17) tCLCL
tCLIL
(26)
(28)
tCLPL
(18)
tCHCL
(1) tEHEL
(2)
tELEH
tPHPL
(22)
tI1HCL
(15)
tCLR1XtR1VCH
(5)
tA1VR1V
(7)
(10)
tAYVCL
(8)
tCLAYX (9)
(25)
tRYHCH
(11)
(24) tRYLCL
tCLA1X
(7)tCLR1X
tR1VCL
(6)
CLK
RDY1, 2
AEN1, 2
ASYNC
READY
CLK
RDY 1, 2
READY
ASYNC
AEN1, 2
(25)
tRYHCH (24)
tRYLCL
tCLR1X
(8)
(4)
(7)
(9)
(11)
(7)
(6)
(10)
tR1VCL
tCLR1X
tCLA1X
tR1VCL
tAYVCL
tCLAYX
tA1VRIV
82C84A
294
AC Testing Input, Output Waveform
Test Lo ad Circu its
NOTES:
1. CL =100pF for CLK output.
2. CL = 50pF for all outputs except CLK.
3. CL = Includes probe and jig capacitance.
FIGURE 5. TEST LOAD MEAS UREMENT CONDITIONS
FIGURE 6. TCHCL , TCLCH LOAD CIRCUITS
FIGURE 7. TRYLCL, TRYHCH LOAD CIRCUITS
CL
OUT P U T FRO M
DEVICE UNDER TEST
(SEE NOTE 3)
R = 740Ω FOR ALL OUTPUTS
EXCEPT CLK
463Ω FOR CLK OUTPUT
2.25V
C1
C2
X1
X2
CSYNC
CLK LOAD
(SEE NOTE 1)
F/C
EF1
CSYNC
CLK LOAD
(SEE NOTE 1)
F/C
VCC
PULSE
GENERATOR
C1
C2
X1
X2
CLK LOAD
(SEE NOTE 1)
LOAD
(SEE NOTE 2)
CSYNC
F/C
AEN2
PULSE
GENERATOR
TRIGGER
VCC
24MHz READY
OSC
AEN1
RDY2
EF1 CLK LOAD
(SEE NOTE 1)
F/C
VCC
PULSE
GENERATOR
CSYNC
RDY2
AEN2
LOAD
(SEE NOTE 2)
AEN1 READY
TRIGGER
PULSE
GENERATOR
1.5V 1.5V
VOL
VIL - 0.4V
INPUT
VIH + 0.4V OUTPUT
VOH
NOT E: Inpu t tes t si gnal s m ust s wit ch b et wee n VIL (maximum) -0.4V and VIH (minimum) +0.4V. RES an d F/C m ust s w itch b etw ee n 0. 4V a nd
VCC -0.4V. Input rise a nd fall times driven at 1ns/V. VIL ≤ VIL (max) -0. 4V f or CSYNC pin. VCC -4. 5V an d 5.5V.
82C84A
295
Burn-In Circuits
MD82C84A CERDIP
MR82C84A CLCC
NOTES:
VCC = 5.5V ±0.5V , GND = 0V.
VIH = 4.5V ±10%.
VIL = -0.2 to 0.4V.
R1 = 4 7kΩ, ±5%.
R2 = 1 0kΩ, ±5%.
R3 = 2.2kΩ, ±5%.
R4 = 1.2kΩ, ±5%.
C1 = 0.01µF (minimum).
F0 = 100kHz ±10%.
F1 = F0/2, F2 = F1/2, . . . F12 = F11/2.
10
11
12
13
14
15
16
17
18
9
8
7
6
5
4
3
2
1
R2
R2
R1
R1
R1
R1
R1
R2
R2
R2
R2
R1
R2
R2
R2
R2
R2
R1
R1
R1
R3
VCC C1
VCC
GND
VCC
GND
F11
F1
F10
OPEN
F0
F12
VCC
GND
VCC
GND
VCC
GND
F9
F6
F5
F7
F8
4
5
6
7
8
9101112
13
3 2 1 20 19
15
14
18
17
16
VCC C1
R4
R4
R4
R4
R4
R4
R4
OPEN
F8
F7
VCC / 2
F5
R4
R4
R4
R4
VCC / 2
F12
VCC / 2
VCC / 2
OPEN
F11
F1
F10
OPEN
R4
F0
R4
R4
R4
F9
VCC / 2
F6
82C84A
296
All Intersil U.S. pro ducts are manufactured, assembl ed and tested uti lizin g ISO9000 quality system s.
Intersil Corporati on’s quali ty certifi cations can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsi diaries for its use; nor for any infringements of patents or other rights of thi rd parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For informat ion regarding Inter sil Corporati on and its produc ts, see www.i ntersil.com
Sales Office Headquarters
NO R TH AMERIC A
Intersil Corporation
7585 Irvine Center Drive
Suite 100
Irvine, CA 92618
TEL: (949) 341-7000
FAX: (949) 341-7123
Intersil Corporation
2401 Palm Bay Rd.
Palm Bay, FL 32905
TEL: (321) 724-7000
FAX: (321) 724-7946
EUROPE
Intersil Europe Sar l
Ave. William Grais se, 3
1006 Lausanne
Switzerland
TEL: +41 21 6140560
FAX: +41 21 6140579
ASIA
I n te rsil Co rpo ra tion
Unit 1804 18/F Guangdong Water Building
83 Austin Road
TST, Kowloon Hong Kong
TEL: +852 2723 6339
FAX: +852 2730 1433
Die Charact eris tics
DIE DIMENSIONS:
66.1 x 70.5 x 19 ± 1mils
METALLIZATION:
Type: Si - AI
Thickness: 11kÅ ± 1kÅ
GLASSIVATION:
Type: SiO2
Thickness: 8kÅ ± 1kÅ
WORST CASE CURRENT DENSITY:
1.42 x 10 5 A/cm2
Metallization Mask Layout
82C84A
AEN1 PCLK CSYNC VCC X1
RDY1
READY
RDY2
AEN2
CLK
GND RESET RES OSC
X2
ASYNC
EFI
F/C
82C84A
