853210AY www.icst.com/products/hiperclocks.html REV. A NOVEMBER 12, 2003
1
Integrated
Circuit
Systems, Inc.
ICS853210
LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
GENERAL DESCRIPTION
The ICS853210 is a low skew, high perfor-
mance dual 1-to-5 Differential-to-2.5V/3.3V
LVPECL/ECL Fanout Buffer and a member of
the HiPerClockS™ f amily of High Performance
Clock Solutions from ICS. The ICS853210
is characterized to operate from either a 2.5V or a 3.3V
power supply. Guaranteed output and part-to-part skew
characteristics make the ICS853210 ideal for those clock
distribution applications demanding well defined perfor-
mance and repeatability.
FEATURES
•2 differential 2.5V/3.3V LVPECL / ECL bank outputs
•2 differential clock input pairs
•PCLKx, nPCLKx pairs can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
•Maximum output frequency: >3GHz
•Translates any single ended input signal to 3.3V
LVPECL levels with resistor bias on nPCLKx input
•Output skew: 13ps (typical)
•Part-to-part skew: 85ps (typical)
•Propagation delay: 485ps (typical)
•LVPECL mode operating voltage supply range:
VCC = 2.375V to 3.8V, VEE = 0V
•ECL mode operating voltage supply range:
VCC = 0V, VEE = -2.375V to -3.8V
•-40°C to 85°C ambient operating temperature
•Pin compatible with MC100EP210 and MC100LVEP210
BLOCK DIAGRAM PIN ASSIGNMENT
HiPerClockS™
ICS
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
QA0
nQA0
QA1
nQA1
QA2
nQA2
QA3
nQA3
QA4
nQA4
PCLKA
nPCLKA
QB0
nQB0
QB1
nQB1
QB2
nQB2
QB3
nQB3
QB4
nQB4
PCLKB
nPCLKB
ICS853210
24 23 22 21 20 19 18 17
1 2 3 4 5 6 7 8
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
QA3
nQA3
QA4
nQA4
QB0
nQB0
QB1
nQB1
VCCO
QB2
nQB2
QB3
nQB3
QB4
nQB4
VCCO
VCCO
nQA2
QA2
nQA1
QA1
nQA0
QA0
VCCO
VCC
nc
PCLKA
nPCLKA
VBB
PCLKB
nPCLKB
VEE
VBB
853210AY www.icst.com/products/hiperclocks.html REV. A NOVEMBER 12, 2003
2
Integrated
Circuit
Systems, Inc.
ICS853210
LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
TABLE 2. PIN CHARACTERISTICS
rebmuNemaNepyTnoitpircseD
1V
CC
rewoP.nipylppuseroC
2cndesunU.tcennocoN
3AKLCPtupnInwodlluP.tupnikcolclaitnereffidgnitrevni-noN
4AKLCPntupnI /pullu
P
nwodlluP V.tupnikcolC
CC
.gnitaolftfelnehwtluafed2/
5V
BB
tuptuO.egatlovsaiB
6BKLCPtupnInwodlluP.tupnikcolclaitnereffidgnitrevni-noN
7BKLCPntupnI /pulluP
nwodlluP V.tupnik
colC
CC
.gnitaolftfelnehwtluafed2/
8V
EE
rewoP.nipylppusevitageN
23,52,9V
OCC
rewoP.snipylppustuptuO
11,014BQ,4BQntuptuO.slevelecafretniLCEPVL.riaptuptuolaitnereffiD
31,213BQ,3BQntuptuO.sl
evelecafretniLCEPVL.riaptuptuolaitnereffiD
51,412BQ,2BQntuptuO.slevelecafretniLCEPVL.riaptuptuolaitnereff
iD
81,711BQ,1BQntuptuO.slevelecafretniLCEPVL.riaptuptuolaitnereffiD
02,910BQ,0BQntuptuO.slevelecafretniLCEPVL
.riaptuptuolaitnereffiD
22,124AQ,4AQntuptuO.slevelecafretniLCEPVL.riaptuptuolaitnereffiD
42,323AQ,3AQntuptuO.
slevelecafretniLCEPVL.riaptuptuolaitnereffiD
72,622AQ,2AQntuptuO.slevelecafretniLCEPVL.riaptuptuolaitnere
ffiD
92,821AQ,1AQntuptuO.slevelecafretniLCEPVL.riaptuptuolaitnereffiD
13,030AQ,0AQntuptuO.slevelecafretniLCEP
VL.riaptuptuolaitnereffiD
:ETON
pulluP
dna
nwodlluP
.seulavlacipytrof,scitsiretcarahCniP,2elbaTeeS.srotsisertupnilanretniotrefer
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
R
NWODLLUP
rotsiseRnwodlluPtupnI 57KΩ
R
2/CCV
srotsiseRnwodlluP/pulluP 05KΩ
TABLE 3. CLOCK INPUT FUNCTION TABLE
stupnIstuptuO
edoMtuptuOottupnIytiraloP
roAKLCP
BKLCP
roAKLCPn
BKLCPn
,4AQ:0AQ
4BQ:0BQ
,4AQn:0AQn
4BQn:0BQn
01WOLHGI
HlaitnereffiDotlaitnereffiDgnitrevnInoN
10 HGIHWOLlaitnereffiDotlaitnereffiDgnitrevnInoN
01ETON;desaiBWOLHGIHlaitne
reffiDotdednEelgniSgnitrevnInoN
11ETON;desaiBHGIHWOLlaitnereffiDotdednEelgniSgnitrevnInoN
1ETON;desaiB0HGIHWOLlai
tnereffiDotdednEelgniSgnitrevnI
1ETON;desaiB1WOLHGIHlaitnereffiDotdednEelgniSgnitrevnI
."sleveLdednEelgniStpe
ccAottupnIlaitnereffiDehtgniriW",noitamrofnInoitacilppAehtotreferesaelP:1ETON
853210AY www.icst.com/products/hiperclocks.html REV. A NOVEMBER 12, 2003
3
Integrated
Circuit
Systems, Inc.
ICS853210
LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V; VEE = 0V
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
CC
egatloVylppuSeroC 573.23.38.3V
I
EE
tnerruCylppuSrewoP 08Am
TABLE 4B. LVPECL DC CHARACTERISTICS, VCC = 3.3V; VEE = 0V
ABSOLUTE MAXIMUM RATINGS
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage
to the device. These ratings are stress specifi-
cations only. Functional operation of product at
these conditions or any conditions beyond those
listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may
affect product reliability.
Supply Voltage, VCC 4.6V (LVPECL mode, VEE = 0)
Negative Supply Voltage, VEE -4.6V (ECL mode, VCC = 0)
Inputs, VI (LVPECL mode) -0.5V to VCC + 0.5V
Inputs, VI (ECL mode) 0.5V to VEE - 0.5V
Outputs, IO
Continuous Current 50mA
Surge Current 100mA
VBB Sink/Source, IBB ± 0.5mA
Operating Temperature Range, TA -40°C to +85°C
Storage Temperature, TSTG -65°C to 150°C
Package Thermal Impedance, θJA 47.9°C/W (0 lfpm)
(Junction-to-Ambient)
lobmySretemaraP C°04-C°52C°58 stinU
niMpyTxaMniMpyTxaMniMpyTxaM
V
HO
1ETON;egatloVhgiHtuptuO
571.2572.283.2522.2592.273.2592.233.2563.2V
V
LO
1ETON;egatloVwoLtuptuO
504.1545.186.1524.125.1516.144.1535.136.1V
V
HI
egatloVhgiHtupnI
)dednE-elgniS(
570.263.2570.263.2570.263.2V
V
LI
egatloVwoLtupnI
)dednE-elgniS(
34.1567.134.1567.134.1567.1V
V
BB
2ETON;ecnerefeRegatloVtuptuO
68.189.168.189.168.189.1V
V
PP
egatloVtupnIkaeP-ot-kaeP
051008002105100800210510080021
m
V
V
RMC
egatloVhgiHtupnI
4,3ETON;egnaRedoMnommoC
2.13.32.13.32.13.3V
I
HI
tupnI
tnerruChgiH
1KLCP,0KLCP
1KLCPn,0KLCPn
051051051Aµ
I
LI
tupnI
tnerruCwoL
1KLCP,0KLCP
01-01-
01-
Aµ
1KLCPn,0KLCPn
051-051-
051-
Aµ
Vhtiw1:1yravsretemaraptuptuodnatupnI
CC
V.
EE
.V5.0-otV529.0+yravnac
05htiwdetanimretstuptuO:1ETON ΩVot
OCC
.V2-
V.detimilsinoitarepotupnidedne-elgniS:2ETON
CC
≥.edomLCEPVLniV3
VsadenifedsiegatlovedomnommoC:3ETON
HI
.
1KLCPn,1KLCPdna0KLCPn,0KLCProfegatlovtupnimumixameht,snoitacilppadedne-elgnisroF:4ETON
Vsi
CC
.V3.0+
853210AY www.icst.com/products/hiperclocks.html REV. A NOVEMBER 12, 2003
4
Integrated
Circuit
Systems, Inc.
ICS853210
LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = 2.5V; VEE = 0V
TABLE 4D. ECL DC CHARACTERISTICS, VCC = 0V; VEE = -2.375 TO -3.8V
lobmySretemaraP C°04-C°52C°58 stinU
niMpyTxaMniMpyTxaMniMpyTxaM
V
HO
1ETON;egatloVhgiHtuptuO
573.1574.185.1524.1594.175.1594.135.1565.1V
V
LO
1ETON;egatloVwoLtuptuO
506.0547.088.0526.027.0518.046.0537.038.0V
V
HI
egatloVhgiHtupnI
)dednE-elgniS(
572.165.1572.165.1572.1
38.0-
V
V
LI
egatloVwoLtupnI
)dednE-elgniS(
36.0569.036.0569.036.0569.0V
V
PP
egatloVtupnIkaeP-ot-kaeP
051008002105100800210510080021
m
V
V
RMC
egatloVhgiHtupnI
3,2ETON;egnaRedoMnommoC
2.15.22.15.22.15.2V
I
HI
tupnI
tnerruChgiH
1KLCP,0KLCP
1KLCPn,0KLCPn
051051051Aµ
I
LI
tupnI
tnerruCwoL
1KLCP,0KLCP
01-01-01-Aµ
1KLCPn,0KLCPn
051-051-051-Aµ
Vhtiw1:1yravsretemaraptuptuodnatupnI
CC
V.
EE
.V5.0-otV529.0+yravnac
05htiwdetanimretstuptuO:1ETON ΩVot
OCC
.V2-
VsadenifedsiegatlovedomnommoC:2ETON
HI
.
1KLCPn,1KLCPdna0KLCPn,0KLCProfegatlovtupnimumixameht,snoitacilppadedne-elgnisroF:3ETON
Vsi
CC
.V3.0+
lobmySretemaraP C°04-C°52C°58 stinU
niMpyTxaMniMpyTxaMniMpyTxaM
V
HO
1ETON;egatloVhgiHtuptuO
521.1-520.1-29.0-570.1-500.1-39.0-500.1-79.0-539.0-V
V
LO
1ETON;egatloVwoLtuptuO
598.1-557.1-26.1-578.1-87.1-586.1-68.1-567.1-76.1-V
V
HI
egatloVhgiHtupnI
)dednE-elgniS(
522.1-49.0-522.1-49.0-522.1-49.0-V
V
LI
egatloVwoLtupnI
)dednE-elgniS(
78.1-535.1-78.1-535.1-78.1-535.1-V
V
BB
2ETON;ecnerefeRegatloVtuptuO
44.1-23.1-44.1-23.1-44.1-23.1-V
V
PP
egatloVtupnIkaeP-ot-kaeP
051008002105100800210510080021
m
V
V
RMC
egatloVhgiHtupnI
4,3ETON;egnaRedoMnommoC
V
EE
V2.1+0V
EE
V2.1+0V
EE
V2.1+0V
I
HI
tupnI
tnerruChgiH
1KLCP,0KLCP
1KLCPn,0KLCPn
051051051Aµ
I
LI
tupnI
tnerruCwoL
1KLCP,0KLCP
01-01-01-Aµ
1KLCPn,0KLCPn
051-051-051-Aµ
Vhtiw1:1yravsretemaraptuptuodnatupnI
CC
V.
EE
.V5.0-otV529.0+yravnac
05htiwdetanimretstuptuO:1ETON ΩVot
OCC
.V2-
V.detimilsinoitarepotupnidedne-elgniS:2ETON
CC
≥.edomLCEPVLniV3
VsadenifedsiegatlovedomnommoC:3ETON
HI
.
1KLCPn,1KLCPdna0KLCPn,0KLCProfegatlovtupnimumixameht,snoitacilppadedne-elgnisroF:4ETON
Vsi
CC
.V3.0+
853210AY www.icst.com/products/hiperclocks.html REV. A NOVEMBER 12, 2003
5
Integrated
Circuit
Systems, Inc.
ICS853210
LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
TABLE 5. AC CHARACTERISTICS, VCC = 0V; VEE = -2.375 TO -3.8V OR VCC = 2.375 TO 3.8V; VEE = 0V
lobmySretemaraP C°04-C°52C°58 stinU
niMpyTxaMniMpyTxaMniMpyTxaM
f
XAM
ycneuqerFtuptuO3>3>3>zHG
Pt
HL
1ETON;hgiH-ot-woL,yaleDnoitagaporP514074025034584545534515585sp
Pt
LH
,yaleDnoitagaporP
1ETON;woL-ot-hgiH V5.2@004074045524094055544515585sp
t
)o(ks4,2ETON;wekStuptuO315231523152sp
t
)pp(ks4,3ETON;wekStraP-ot-traP580615806158061sp
t
R
/t
F
emiTllaF/esiRtuptuO%08ot%02511881062031091052541091532sp
detsetsretemarapllA ≤.detonesiwrehtosselnuzHG1
.tniopgniss
orctuptuolaitnereffidehtottniopgnissorctupnilaitnereffidehtmorfderusaeM:1ETON
.snoitidnocdaollauqehtiw
dnaegatlovylppusemasehttastuptuoneewtebwekssadenifeD:2ETON
.stniopssorclaitnereffidtuptuoehttaderusaeM
segatlovylppusemasehttagnitareposecivedtnereffidnostuptuoneewtebwekssadenifeD:3ETON
derusaemerastuptuo
eht,ecivedhcaenostupnifoepytemasehtgnisU.snoitidnocdaollauqehtiwdna
.stniopssorclaitnereffidehtta
.56dr
adnatSCEDEJhtiwecnadroccanidenifedsiretemarapsihT:4ETON
853210AY www.icst.com/products/hiperclocks.html REV. A NOVEMBER 12, 2003
6
Integrated
Circuit
Systems, Inc.
ICS853210
LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL
OUTPUT SKEW
PART-TO-PART SKEW
OUTPUT RISE/FALL TIME PROPAGATION DELAY
V
CMR
Cross Points
V
PP
VEE
nPCLKA,
nPCLKB
VCC
PCLKA,
PCLKB
SCOPE
Qx
nQx
LVPECL
2V
-0.375V to -1.8V
t
sk(pp)
t
sk(o)
nQx
Qx
nQy
Qy
PART 1
PART 2
nQx
Qx
nQy
Qy
Clock
Outputs 20%
80% 80%
20%
t
R
t
F
V
SWING
tp
LH
tp
HL
nPCLKA,
nPCLKB
QA0:QA4,
QB0:QB4,
nQA0:nQA4,
nQB0:nQB4,
PCLKA,
PCLKB
VCC,
VCCO
V EE
853210AY www.icst.com/products/hiperclocks.html REV. A NOVEMBER 12, 2003
7
Integrated
Circuit
Systems, Inc.
ICS853210
LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
Figure 1A
shows an example of the differential input that can
be wired to accept single ended levels. The reference voltage
level VBB generated from the device is connected to the
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LVPECL LEVELS
FIGURE 1A. SINGLE ENDED LVPECL SIGNAL DRIVING DIFFERENTIAL INPUT
negative input. The C1 capacitor should be located as close
as possible to the input pin.
VCC(or VDD)
CLK_IN PCLK
nPCLK
VBB
Figure 1B
shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF ~ VCC/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
FIGURE 1B. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
VCC
R2
1K
V_REF
C1
0.1u
R1
1K
Single Ended Clock Input
PCLK
nPCLK
853210AY www.icst.com/products/hiperclocks.html REV. A NOVEMBER 12, 2003
8
Integrated
Circuit
Systems, Inc.
ICS853210
LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
V
CC
- 2V
50Ω50Ω
RTT
Z
o
= 50Ω
Z
o
= 50Ω
FOUT FIN
RTT = Z
o
1
((V
OH
+ V
OL
) / (V
CC
– 2)) – 2
3.3V
125Ω125Ω
84Ω84Ω
Z
o
= 50Ω
Z
o
= 50Ω
FOUT FIN
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
50Ω transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion.
Figures 2A and 2B
show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
TERMINATION FOR 3.3V LVPECL OUTPUTS
FIGURE 2B. LVPECL OUTPUT TERMINATIONFIGURE 2A. LVPECL OUTPUT TERMINATION
853210AY www.icst.com/products/hiperclocks.html REV. A NOVEMBER 12, 2003
9
Integrated
Circuit
Systems, Inc.
ICS853210
LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 3A and Figure 3B
show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminat-
ing 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to
ground level. The R3 in
Figure 3B
can be eliminated and the
termination is shown in
Figure 3C.
FIGURE 3C. 2.5V LVPECL TERMINATION EXAMPLE
R2
50
Zo = 50 Ohm
VCCO=2.5V
R1
50
Zo = 50 Ohm
+
-
2.5V
2,5V LVPECL
Driv er
FIGURE 3B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
VCCO=2.5V
R1
50
R2
50
Zo = 50 Ohm
R3
18
2,5V LVPECL
Driv er
Zo = 50 Ohm
+
-
2.5V
FIGURE 3A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
R2
62.5
2.5V
2,5V LVPECL
Driv er
R3
250
Zo = 50 Ohm
Zo = 50 Ohm
R4
62.5
2.5V
+
-
R1
250
VCCO=2.5V
853210AY www.icst.com/products/hiperclocks.html REV. A NOVEMBER 12, 2003
10
Integrated
Circuit
Systems, Inc.
ICS853210
LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
LVPECL CLOCK INPUT INTERFACE
The PCLKx /nPCLKx accepts LVPECL, CML, SSTL and other
differential signals. Both VSWING and VOH must meet the VPP
and VCMR input requirements.
Figures 4A to 4E
show inter-
face examples for the HiPerClockS PCLKx/nPCLKx input
driven by the most common driver types. The input interfaces
suggested here are examples only. If the driver is from an-
other vendor, use their termination recommendation. Please
consult with the vendor of the driver component to confirm
the driver termination requirements.
FIGURE 4A. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY A CML DRIVER
FIGURE 4B. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY AN SSTL DRIVER
FIGURE 4C. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER
FIGURE 4D. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY A 3.3V LVDS DRIVER
HiPerClockS
PCLK
nPCLK
PCLK/nPCLK
3.3V
R2
50
R1
50
3.3V
Zo = 50 Ohm
CML
3.3V
Zo = 50 Ohm
PCLK/nPCLK
2.5V
Zo = 60 Ohm
SSTL
HiPerClockS
PCLK
nPCLK
R2
120
3.3V
R3
120
Zo = 60 Ohm
R1
120
R4
120
2.5V
FIGURE 4E. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER WITH AC COUPLE
3.3V
R5
100 - 200
3.3V
3.3V
HiPerClockS
PCLK
nPCLK
R1
125
PCLK/nPCLK
R2
125
R3
84
C1
C2
Zo = 50 Ohm
R4
84
Zo = 50 Ohm
R6
100 - 200
3.3V LVPECL
3.3V
HiPerClockS
PCLK
nPCLK
R2
84
R3
125
Input
Zo = 50 Ohm
R4
125
R1
84
LVPECL
3.3V
3.3V
Zo = 50 Ohm
C2
R2
1K
R5
100
Zo = 50 Ohm
3.3V
3.3V
C1
R3
1K
LVDS
R4
1K
HiPerClockS
PCLK
nPCLK
R1
1K
Zo = 50 Ohm
3.3V
PCLK/n PCLK
853210AY www.icst.com/products/hiperclocks.html REV. A NOVEMBER 12, 2003
11
Integrated
Circuit
Systems, Inc.
ICS853210
LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
θθ
θθ
θ
JA
by Velocity (Linear Feet per Minute)
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 55.9°C/W 50.1°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 47.9°C/W 42.1°C/W 39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS853210.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS853210 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.8V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•Power (core)MAX = VCC_MAX * IEE_MAX = 3.8V * 80mA = 304mW
•Power (outputs)MAX = 30.94mW/Loaded Output pair
If all outputs are loaded, the total power is 10 * 30.94mW = 309.4mW
Total Power_MAX (3.8V, with all outputs switching) = 304mW + 309.4mW = 613.4mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA
must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.613W * 42.1°C/W = 110.8°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θθ
θθ
θJA FOR 32-PIN LQFP, FORCED CONVECTION
853210AY www.icst.com/products/hiperclocks.html REV. A NOVEMBER 12, 2003
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Integrated
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ICS853210
LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
3. Calculations and Equations.
LVPECL output driver circuit and termination are shown in Figure 5.
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V
CCO
- 2V.
• For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.935V
(VCC_MAX - VOH_MAX
) = 0.935V
• For logic low, VOUT = VOL_MAX = VCCO_MAX
– 1.67V
(VCCO_MAX - VOL_MAX
) = 1.67V
Pd_H = [(VOH_MAX
– (VCCO_MAX
- 2V))/R
L
] * (VCCO_MAX
- VOH_MAX) = [(2V - (V
CCO_MAX - VOH_MAX
))/R
L
] * (VCCO _MAX- VOH_MAX) =
[(2V - 0.935V)/50Ω] * 0.935V = 19.92mW
Pd_L = [(VOL_MAX
– (VCCO_MAX
- 2V))/R
L
] * (VCCO_MAX
- VOL_MAX) = [(2V - (V
CCO_MAX - VOL_MAX
))/R
L
] * (VCCO_MAX
- VOL_MAX) =
[(2V - 1.67V)/50Ω] * 1.67V = 11.02mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW
Figure 5. LVPECL Driver Circuit and Termination
VCCO - 2V
Q1
VOUT
RL
50
VCCO
853210AY www.icst.com/products/hiperclocks.html REV. A NOVEMBER 12, 2003
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Integrated
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ICS853210
LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
RELIABILITY INFORMATION
TRANSISTOR COUNT
The transistor count for ICS853210 is: 437
TABLE 6. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP
θθ
θθ
θ
JA
by Velocity (Linear Feet per Minute)
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 55.9°C/W 50.1°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 47.9°C/W 42.1°C/W 39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
853210AY www.icst.com/products/hiperclocks.html REV. A NOVEMBER 12, 2003
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Integrated
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ICS853210
LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP
TABLE 7. PACKAGE DIMENSIONS
Reference Document: JEDEC Publication 95, MS-026
NOITAIRAVCEDEJ
SRETEMILLIMNISNOISNEMIDLLA
LOBMYS
ABB
MUMINIMLANIMONMUMIXAM
N23
A----06.1
1A 50.0--51.0
2A 53.104.154.1
b03.073.054.0
c90.0--02.0
DCISAB00.9
1D CISAB00.7
2D .feR06.5
ECISAB00.9
1E CISAB00.7
2E .feR06.5
eCISAB08.0
L54.006.057.
0
θθ
θ
θθ 0
°
-- 7
°
ccc ----01.0
853210AY www.icst.com/products/hiperclocks.html REV. A NOVEMBER 12, 2003
15
Integrated
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Systems, Inc.
ICS853210
LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
TABLE 8. ORDERING INFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
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