CM1213A-04SO - ON Semiconductor - Datasheet.Directory

July, 2012 − Rev. 9

1Publication Order Number:

CM1213A/D

CM1213A

1, 2 and 4-Channel

Low Capacitance

ESD Protection Arrays

Product Description

The CM1213A family of diode arrays has been designed to provide

ESD protection for electronic components or subsystems requiring

minimal capacitive loading. These devices are ideal for protecting

systems with high data and clock rates or for circuits requiring low

capacitive loading. Each ESD channel consists of a pair of diodes in

series which steer the positive or negative ESD current pulse to either

the positive (VP) or negative (VN) supply rail. A Zener diode is

embedded between VP and VN, offering two advantages. First, it

protects the VCC rail against ESD strikes, and second, it eliminates the

need for a bypass capacitor that would otherwise be needed for

absorbing positive ESD strikes to ground. The CM1213A will protect

against ESD pulses up to 8 kV per the IEC 61000−4−2 standard.

These devices are particularly well−suited for protecting systems

using high−speed ports such as USB 2.0, IEEE1394 (Firewire®,

iLinkt), Serial ATA, DVI, HDMI and corresponding ports in

removable storage, digital camcorders, DVD−RW drives and other

applications where extremely low loading capacitance with ESD

protection are required in a small package footprint.

Features

•One, Two, and Four Channels of ESD Protection

Note: For 6 and 8−channel Devices, See the CM1213 Datasheet

•Provides ESD Protection to IEC61000−4−2 Level 4

♦±8 kV Contact Discharge

•Low Channel Input Capacitance of 0.85 pF Typical

•Minimal Capacitance Change with Temperature and Voltage

•Channel Input Capacitance Matching of 0.02 pF Typical is Ideal for

Differential Dignals

•Zener Diode Protects Supply Rail and Eliminates the Need for

External By−pass Capacitors

•Each I/O Pin Can Withstand Over 1000 ESD Strikes*

•These Devices are Pb−Free and are RoHS Compliant

Applications

•USB2.0 Ports at 480 Mbps in Desktop PCs, Notebooks and Peripherals

•IEEE1394 Firewire® Ports at 400 Mbps/800 Mbps

•DVI Ports, HDMI Ports in Notebooks, Set Top Boxes, Digital TVs,

LCD Displays

•Serial ATA Ports in Desktop PCs and Hard Disk Drives

•PCI Express Ports

•General Purpose High−Speed Data Line ESD Protection

*Standard test condition is IEC61000−4−2 level 4 test circuit with each pin subjected to ±8 kV contact discharge for 1000 pulses. Discharges

are timed at 1 second intervals and all 1000 strikes are completed in one continuous test run. The part is then subjected to standard production

test to verify that all of the tested parameters are within spec after the 1000 strikes.

MSOP−10

(Pb−Free)

SC70−6

(Pb−Free)

3,000 /

Tape & Reel

SC−74

(Pb−Free)

MARKING DIAGRAM

Device Package Shipping†

ORDERING INFORMATION

SOT23−3

SO SUFFIX

CASE 318

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CM1213A−01SO SOT23−3

(Pb−Free)

3,000 /

Tape & Reel

SOT143−4

(Pb−Free)

3,000 /

Tape & Reel

CM1213A−02SR

3,000 /

Tape & Reel

CM1213A−02SO

CM1213A−04S7

4,000 /

Tape & Reel

CM1213A−04MR

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specification

Brochure, BRD8011/D.

SOT−143

SR SUFFIX

CASE 318A

SC70−6

S7 SUFFIX

CASE 419AD

XXXMG

MSOP−10

MR SUFFIX

CASE 846AE

XXXMG

XXX = Specific Device Code

M = Date Code

G= Pb−Free Package

(*Note: Microdot may be in either loca-

tion)

SC−74

SO SUFFIX

CASE 318F

CM1213A

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CH4 VP

CH3

CH1 CH2

CM1213A−04MR

CM1213A−04S7

CH1

CM1213A−02SR

CM1213A−02SO

CH2

BLOCK DIAGRAM

CH1

CM1213A−01SO

CM1213A

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Table 1. PIN DESCRIPTIONS

1−Channel, 3−Lead SOT23−3 Package (CM1213A−01SO)

Pin Name Type Description

1 CH1 I/O ESD Channel

2 VPPWR Positive Voltage Supply Rail

3 VNGND Negative Voltage Supply Rail

2−Channel, 4−Lead SOT143−4 Package (CM1213A−02SR)

Pin Name Type Description

1 VNGND Negative Voltage Supply Rail

2 CH1 I/O ESD Channel

3 CH2 I/O ESD Channel

4 VPPWR Positive Voltage Supply Rail

2−Channel, SC−74 Package (CM1213A−02SO)

Pin Name Type Description

1 NC −No Connect

2 VN GND Negative Voltage Supply Rail

3 CH1 I/O ESD Channel

4 CH2 I/O ESD Channel

5 NC −No Connect

6 VP PWR Positive Voltage Supply Rail

4−Channel, 6−Lead SC70−6 (CM1213A−04S7)

Pin Name Type Description

1 CH1 I/O ESD Channel

2 VNGND Negative Voltage Supply Rail

3 CH2 I/O ESD Channel

4 CH3 I/O ESD Channel

5 VPPWR Positive Voltage Supply Rail

6 CH4 I/O ESD Channel

4−Channel, 10−Lead MSOP−10 Package (CM1213A04MR)

Pin Name Type Description

1 CH1 I/O ESD Channel

2 NC −No Connect

3 VPPWR Positive Voltage Supply Rail

4 CH2 I/O ESD Channel

5 NC −No Connect

6 CH3 I/O ESD Channel

7 NC −No Connect

8 VNGND Negative Voltage Supply Rail

9 CH4 I/O ESD Channel

10 NC −No Connect

PACKAGE/PINOUT DIAGRAMS

Top View

CH1

CH2

CH4

CH356

10−Lead MSOP−10

Top View

CH1 (1)

VN (3)

3−Lead SOT23−3

VP (2)

Top View

CH1 (2)

VP (4)

4−Lead SOT143−4

VN (1)

CH2 (3)

Top View

CH2

6−Lead SC70−6

CH3

CH1 1

6 CH4

Top View

CH1 (3)

NC (5)

6−Lead SC−74

VN (2)

CH2 (4)

NC (1) VP (6)

231 D232 D38233 D238

CM1213A

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SPECIFICATIONS

Table 2. ABSOLUTE MAXIMUM RATINGS

Parameter Rating Units

Operating Supply Voltage (VP − VN) 6.0 V

Operating Temperature Range –40 to +85 °C

Storage Temperature Range –65 to +150 °C

DC Voltage at any channel input (VN − 0.5) to (VP + 0.5) V

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

Table 3. STANDARD OPERATING CONDITIONS

Parameter Rating Units

Operating Temperature Range –40 to +85 °C

Package Power Rating

SOT23−3, SOT143−4, SC−74, and SC70−6 Packages

MSOP−10 Package

225

400

Table 4. ELECTRICAL OPERATING CHARACTERISTICS (Note1)

Symbol Parameter Conditions Min Typ Max Units

VPOperating Supply Voltage (VP−VN) 3.3 5.5 V

IPOperating Supply Current (VP−VN) = 3.3 V 8.0 mA

VFDiode Forward Voltage

Top Diode

Bottom Diode

IF = 8 mA; TA = 25°C

0.60

0.80

0.95

ILEAK Channel Leakage Current TA = 25°C; VP = 5 V, VN = 0 V 0.1 1.0 mA

CIN Channel Input Capacitance At 1 MHz, VP = 3.3 V, VN = 0 V, VIN = 1.65 V

(Note 2)

0.85 1.2 pF

DCIN Channel Input Capacitance Matching At 1 MHz, VP = 3.3 V, VN = 0 V, VIN = 1.65 V

(Note 2)

0.02 pF

VESD ESD Protection − Peak Discharge

Voltage at any channel input, in system

Contact discharge per

IEC 61000−4−2 standard TA = 25°C (Notes 2 and 3) 8

VCL Channel Clamp Voltage

Positive Transients

Negative Transients

TA = 25°C, IPP = 1A, tP = 8/20 mS

(Note 2) +10

–1.7

RDYN Dynamic Resistance

Positive Transients

Negative Transients

IPP = 1A, tP = 8/20 mS

Any I/O pin to Ground

(Note 2)

0.9

0.5

1. All parameters specified at TA = –40°C to +85°C unless otherwise noted.

2. Standard IEC 61000−4−2 with CDischarge = 150 pF, RDischarge = 330 W, VP = 3.3 V, VN grounded.

3. These measurements performed with no external capacitor on VP (VP floating).

CM1213A

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PERFORMANCE INFORMATION

Input Channel Capacitance Performance Curves

Figure 1. Typical Variation of CIN vs. VIN

(f = 1 MHz, VP = 3.3 V, VN = 0 V, 0.1 F Chip Capacitor between VP and VN, 255C)

Figure 2. Typical Variation of CIN vs. Temp

(f = 1 MHz, VIN = 30 mV, VP = 3.3 V, VN = 0 V, 0.1 F Chip Capacitor between VP and VN)

CM1213A

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PERFORMANCE INFORMATION (Cont’d)

Typical Filter Performance (nominal conditions unless specified otherwise, 50 Ohm Environment)

Figure 3. Insertion Loss (S21) vs. Frequency (0 V DC Bias, VP=3.3 V)

Figure 4. Insertion Loss (S21) vs. Frequency (2.5 V DC Bias, VP=3.3 V)

CM1213A

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APPLICATION INFORMATION

Design Considerations

In order to realize the maximum protection against ESD pulses, care must be taken in the PCB layout to minimize parasitic

series inductances on the Supply/Ground rails as well as the signal trace segment between the signal input (typically

a connector) and the ESD protection device. Refer to Application of Positive ESD Pulse between Input Channel and Ground,

which illustrates an example of a positive ESD pulse striking an input channel. The parasitic series inductance back to the power

supply is represented by L1 and L2. The voltage VCL on the line being protected is:

VCL = Fwd Voltage Drop of D1 + VSUPPLY + L1 x d(IESD) / dt + L2 x d(IESD) / dt

where IESD is the ESD current pulse, and VSUPPLY is the positive supply voltage.

An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact discharge

per the IEC61000−4−2 standard results in a current pulse that rises from zero to 30 Amps in 1 ns. Here d(IESD)/dt can be

approximated by DIESD/Dt, or 30/(1x10−9). So just 10 nH of series inductance (L1 and L2 combined) will lead to a 300 V

increment in VCL!

Similarly for negative ESD pulses, parasitic series inductance from the VN pin to the ground rail will lead to drastically

increased negative voltage on the line being protected.

The CM1213A has an integrated Zener diode between VP and VN. This greatly reduces the effect of supply rail inductance

L2 on VCL by clamping VP at the breakdown voltage of the Zener diode. However, for the lowest possible VCL, especially when

VP is biased at a voltage significantly below the Zener breakdown voltage, it is recommended that a 0.22 mF ceramic chip

capacitor be connected between VP and the ground plane.

As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of expected

electrostatic discharges. The power supply bypass capacitor mentioned above should be as close to the VP pin of the Protection

Array as possible, with minimum PCB trace lengths to the power supply, ground planes and between the signal input and the

ESD device to minimize stray series inductance.

Additional Information

See also ON Semiconductor Application Note “Design Considerations for ESD Protection”, in the Applications section.

ÇÇÇÇÇÇ

POSITIVE SUPPLY RAIL

CHANNEL

INPUT

GROUND RAIL

CHASSIS GROUND

SYSTEM OR

CIRCUITRY

BEING

PROTECTED

LINE BEING

PROTECTED

ONE

CHANNEL

CM1213

D1L1

L2VCC

VCL

0.22 mF

PATH OF ESD CURRENT PULSE IESO

0 A

25 A

Figure 5. Application of Positive ESD Pulse between Input Channel and Ground

CM1213A

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PACKAGE DIMENSIONS

SOT−23 (TO−236)

CASE 318−08

ISSUE AP

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH

THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM

THICKNESS OF BASE MATERIAL.

4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH,

PROTRUSIONS, OR GATE BURRS.

ǒmm

inchesǓ

SCALE 10:1

0.8

0.031

0.9

0.035

0.95

0.037

0.95

0.037

2.0

0.079

SOLDERING FOOTPRINT*

VIEW C

0.25



SEE VIEW C

DIM

MIN NOM MAX MIN

MILLIMETERS

0.89 1.00 1.11 0.035

INCHES

A1 0.01 0.06 0.10 0.001

b0.37 0.44 0.50 0.015

c0.09 0.13 0.18 0.003

D2.80 2.90 3.04 0.110

E1.20 1.30 1.40 0.047

e1.78 1.90 2.04 0.070

L0.10 0.20 0.30 0.004

0.040 0.044

0.002 0.004

0.018 0.020

0.005 0.007

0.114 0.120

0.051 0.055

0.075 0.081

0.008 0.012

NOM MAX

2.10 2.40 2.64 0.083 0.094 0.104

0.35 0.54 0.69 0.014 0.021 0.029

0−−− 10 0 −−− 10

°°°°

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

CM1213A

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PACKAGE DIMENSIONS

SOT−143

CASE 318A−06

ISSUE U

DIM

MIN MAX

2.80 3.05

MILLIMETERS

E1 1.20 1.40

A0.80 1.12

b0.30 0.51

b1 0.76 0.94

e1.92 BSC

L0.35 0.70

c0.08 0.20

L2 0.25 BSC

e1 0.20 BSC

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIM

UM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE

MATERIAL.

4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PRO

TRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS,

AND GATE BURRS SHALL NOT EXCEED 0.25 PER SIDE.

DIMENSION E1 DOES NOT INCLUDE INTERLEAD FLASH OR

PROTRUSION. INTERLEAD FLASH AND PROTRUSION SHALL

NOT EXCEED 0.25 PER SIDE.

5. DIMENSIONS D AND E1 ARE DETERMINED AT DATUM H.

6. DATUMS A AND B ARE DETERMINED AT DATUM H.

A-B

0.20 DC

0.10 C

SIDE VIEW SEATING

PLANE

SOLDERING FOOTPRINT*

0.75

DIMENSIONS: MILLIMETERS

0.54

1.92

RECOMMENDED

A1 0.01 0.15

TOP VIEW

3X b

AA1 C

END VIEW

SEATING

PLANE

L2 L

GAUGE

PLANE

DETAIL A

2.70

0.20

0.96

E2.10 2.64

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

CM1213A

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PACKAGE DIMENSIONS

SC−88 (SC−70 6 Lead), 1.25x2

CASE 419AD−01

ISSUE A

L1 L2

bA1

TOP VIEW

SIDE VIEW END VIEW

Notes:

(1) All dimensions are in millimeters. Angles in degrees.

(2) Complies with JEDEC MO-203.

SYMBOL MIN NOM MAX

0º 8º

0.00

0.15

0.10

0.26

1.80

1.15

0.65 BSC

0.15 BSC

1.10

0.10

0.30

0.18

0.46

2.20

2.40

1.35

0.80

θ1 4º 10º

A2 0.80 1.00

0.42 REF

0.36

2.00

2.10

1.25

CM1213A

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PACKAGE DIMENSIONS

SC−74

CASE 318F−05

ISSUE N

SCALE 2:1

456

0.05 (0.002)

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. MAXIMUM LEAD THICKNESS INCLUDES

LEAD FINISH THICKNESS. MINIMUM LEAD

THICKNESS IS THE MINIMUM THICKNESS

OF BASE MATERIAL.

4. 318F−01, −02, −03, −04 OBSOLETE. NEW

STANDARD 318F−05.

0.7

0.028

1.9

0.074

0.95

0.037

2.4

0.094

1.0

0.039

0.95

0.037

ǒmm

inchesǓ

SCALE 10:1

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

DIM

MIN NOM MAX MIN

MILLIMETERS

0.90 1.00 1.10 0.035

INCHES

A1 0.01 0.06 0.10 0.001

b0.25 0.37 0.50 0.010

c0.10 0.18 0.26 0.004

D2.90 3.00 3.10 0.114

E1.30 1.50 1.70 0.051

e0.85 0.95 1.05 0.034

0.20 0.40 0.60 0.008

0.039 0.043

0.002 0.004

0.015 0.020

0.007 0.010

0.118 0.122

0.059 0.067

0.037 0.041

0.016 0.024

NOM MAX

2.50 2.75 3.00 0.099 0.108 0.118

− −

0°10°0°10°



CM1213A

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PACKAGE DIMENSIONS

MSOP 10, 3x3

CASE 846AE−01

ISSUE O

E1E

A1 eb

TOP VIEW

SIDE VIEW

END VIEW

DETAIL A

Notes:

(1) All dimensions are in millimeters. Angles in degrees.

(2) Complies with JEDEC MO-187.

SYMBOL MIN NOM MAX

0º 8º

0.00

0.75

0.17

0.13

0.40

2.90

4.75

2.90

0.50 BSC

0.25 BSC

1.10

0.15

0.95

0.27

0.23

0.80

3.10

5.05

3.10

0.60

3.00

4.90

3.00

L1 0.95 REF

0.05

0.85

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limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications

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PUBLICATION ORDERING INFORMATION

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5817−1050

CM1213A/D

FireWire is a registered trademark of Apple Computer, Inc.

iLink is a trademark of S. J. Electro Systems, Inc.

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