2001 Microchip Technology Inc. DS80088A-page 1
PIC16C73A
The PIC1 6C73A (R ev. A) pa rt s yo u have received con-
form functionally to the Device Data Sheet
(DS30390E), except for the anomalies described
below.
All the problems listed here will be addressed in future
revisions of the P IC16C73A silicon.
1. Module: 8-bit A/D Module
If the Analog Port is configured so that all analog
pins are digital inputs (PCFG2:PCFG0 = 11x),
then doing a conversion on any pin of the analog
port will give a result o f ADRES = 0xFF.
Work around
Configure the PCFG2:PCFG0 bits to a value that
has any pin of the analog port configured as an
analog input (such as PCFG2:PCFG0 = 100).
Conversion on any pin of the analog port (analog
or digital) will now convert as expected.
2. Module: CCP (Compare Mode)
The Compare mode may not operate as expected
when configuring the compare match to drive the
I/O pin low (CCPxM<3:0> = 1001).
When the CCP module is changed to compare
output low (CCPxM<3:0> = 1001) from any other
non- compare C CP mo de, the I/O p in wil l imme di-
ately be driven low, regardless of the state of the
I/O data latch. The pin will remain low when the
compare match occurs (see Table 1).
However, when the CCP module is changed to
compare output high (CCPxM<3:0> = 1000) from
any other CCP mode, the I/O pin will immediately
be driven low, regardless of the state of the I/O
data latch. The pin will be driven high when the
compare match occurs.
TABLE 1: COMPARE OUTPUT LOW
SWITCHING
Work around
To have the I/O pin high until the compare match
low occurs , fo rce a comp a re m atc h hi gh to get th e
I/O pin into the high state, then reconfigure the
comp are match to force the I /O low w hen the c om-
pare condition occurs.
CCP Mode
CCPxM<3:0> = I/O pin
State
Change CCP to
CCPxM<3:0> =
1001 1000
0xxx HLL
LLL
1000 HH—
LL—
1001 H—L
L—L
101x HLL
LLL
11xx HLL
LLL
PIC16C73A Rev. A Silicon Errata Sheet
PIC16C73A
DS80088A-page 2 2001 Microchip Technology Inc.
3. Module: CCP (Compare Mode)
The special event trigger of the Compare mode
may not occur if both of the following conditions
exist:
•An instructi on, one cyc le (TCY) prior to a
Timer1/Compare register match has literal
data equal to the address of a CCP register
being used. Specific cases include:
•An instruction in the same cycle as a
Timer1/Compare register match has an
MSb of ‘0’.
The interrupt for the compare event will still be
generated, but no special event trigger will occur.
Work around
Use the Interru pt Serv ic e Ro uti ne in ste ad of usin g
the speci al even t trigg er to res et Timer1 (and st art
an A/D conversion, if applicable).
4. Module: SSP (SPI Mode)
When the SPI is using Timer2/2 as the clock
source, a shorter than expected SCK pulse may
occur on the first bit of the transmitted/received
data (Figure 1).
FIGURE 1: SCK PULSE VARIATION
USING TIMER2/2
Work around
To avoid produ cing t he sho rt puls e, turn o ff Timer2
and clear the TMR2 register, load the SSPBUF
with the data to transmit, and then turn Timer2
back on. Refer to Example 1 for sample code.
EXAMPLE 1: AVOIDING THE INITIAL
SHORT SCK PULSE
5. Module: SSP Module (I2C™ mode)
If the bus is active when the I2C mode is enabled,
and the next 8 bits of data on the bus match the
address of the device, then the SSP module will
generate an Acknowledge pulse.
Work around
Before enab ling the I2C mod e, ensure tha t the bus
is not active.
6. Module: Timer0
The TMR0 register may increment when the WDT
postscaler is switched to the Timer0 prescaler. If
TMR0 = FFh, this will cause TMR0 to overflow
(setting T0IF).
Work around
Follow the following sequence:
a) Read the 8-bit TMR0 register into the
W register
b) Clear the TMR0 register
c) Assign WDT p ostscaler to Timer0
d) Write W register to TMR0
Unit Register Literal Data
CCP1 CCPR1L 15h
CCPR1H 16h
CCP1CON 17h
CCP2 CCPR2L 1Bh
CCPR2H 1Ch
CCP2C0N 1Dh
SD0
SCK
Write SSPBUF
bit0=1 bit1=0 bit2=1 . . . .
BSF STATUS, RP0 ;Bank 1
LOOP BTFSS SSPSTAT,BF ;Data received?
;(Xmit complete?)
GOTO LOOP ;No
BCF STATUS, RP0 ;Bank 0
MOVF SSPBUF, W ;W = SSPBUF
MOVWF RXDATA ;Save in user RAM
MOVF TXDATA, W ;W = TXDATA
BCF T2CON, TMR2ON ;Timer2 off
CLR TMR2 ;Clear Timer2
MOVWF SSPBUF ;Xmit New data
BSF T2CON, TMR2ON ;Timer2 on
2001 Microchip Technology Inc. DS80088A-page 3
PIC16C73A
7. Module: Timer1
The Timer1 value may unexpectedly increment if
either the TMR1H, or the TMR1L register is writ-
ten. If Timer1 is ON and t hen turned OFF, perform-
ing any write instruction with TMR1H as the
destination, may cause TMR1L to increment.
EXAMPLE 2: TMR1L INCREMENT
(CASE 1)
EXAMPLE 3: TMR1L INCREMENT
(CASE 2)
If Timer1 is ON and then turned OFF when
TMR1H:TMR1L = xx:FF, performing any write
instruction with TMR1L as the destination may
cause TMR1H to incremen t.
EXAMPLE 4: TMR1H INCREMENT
Work around
To preserve Timer1 register values:
a) Read Timer1 register values into “shadow”
registers.
b) Perform any write instruction(s) on the
shadow registers.
c) Write the shadow register values back into
the Timer1 registers.
8. Module: USART
When the USART (SCI) is configured in Asynchro-
nous mode with the BRGH bit set, a high number
of receive errors may be experienced. For asyn-
chronous receive operations, it is recommended
that the USART be configured with the BRGH bit
cleared.
BSF T1CON, TMR1ON
:
BCF T1CON, TMR1ON
MOVF TMR1H, 1
TMR1 value before MOVF instruction:
TMR1H:TMR1L = 3F:00
TMR1 value after MOVF instruction:
TMR1H:TMR1L = 3F:01
BSF T1CON, TMR1ON
:
BCF T1CON, TMR1ON
MOVF TMR1H, 1
TMR1 value before MOVF instruction:
TMR1H:TMR1L = FF:FF
TMR1 value after MOVF instruction:
TMR1H:TMR1L = FF:00
BSF T1CON, TMR1ON
BCF T1CON, TMR1ON
CLRF TMR1L
TMR1 value before CLRF instruction:
TMR1H:TMR1L = FF:FF
TMR1 value after CLRF instruction:
TMR1H:TMR1L = 00:00
(TMR1IF is not set.)
PIC16C73A
DS80088A-page 4 2001 Microchip Technology Inc.
Clarifications/Corrections to the Data
Sheet:
In the Device Data Sheet (DS30390E), the following
clarifications and c orrect ions should be noted.
1. Module: I/O Ports
The specification for the High Voltage Open Drain
I/O (parameter D150, the RA4 pin) cannot be met
withou t possi ble lon g term reliab ility i ssues on that
I/O pin. If a high voltage drive is required, use an
external transistor that can support the required
voltage. The new value is shown in Table 1.
TABLE 1: DC SPECIFICATION CHANGES FROM DATA SHEET
2. Module: 8-Bit A/D
The minimum A/D reference voltage (parameter
A20) has been improved. Th e ne w va lue is show n
in Table 2.
TABLE 2: DC SPECIFICATION CHANGES FROM DATA SHEET
Param
No. Sym. Characteristic New Spec ific ation Data Shee t
Specification Units
Min Typ Max Min Typ Max
D150 VOD RA4 Open Drain High Voltage ——10 ——14 V
Param
No. Sym. Characteristic New Specification Data Sheet
Specification Units
Min Typ Max Min Typ Max
A20 VREF Reference Voltage 2.5* —VDD +
0.3 V 3.0 —VDD +
0.3 V V
* This parameter is characterized but not tested.
2001 Microchip Technology Inc. DS80088A-page 5
PIC16C73A
3. Module: SSP (SPITM Mode Timing
Specifications)
The SPI interface timings (parameters 71, 71A, 72,
72A, 73, and 73A) have been modified. The new
values are shown in Table 3.
TABLE 3: DC SPECIFICATION CHANGES FROM DAT A SHEET
4. Module: Timer1
The operation of Timer1 needs some clarification
when the timer registers are written when the
TMR1ON bit is set.
The internal clock signal that is the input to the
TMR1 prescaler af fects the incrementing of T imer1
(TMR1H:TMR1L registers and the Timer1 pres-
caler). W hen the T imer1 re gisters ar e NOT written,
the Timer1 w il l inc rem en t on the risi ng ed ge of the
TMR1 incr em en t cloc k.
When the TMR1H and/or TMR1L registers are
written while this clock is high, TMR1 will incre-
ment on the next rising edge of this clock.
When the TMR1H and/or TMR1L registers are
written while this clock is low, TMR1 will not incre-
ment on the next rising edg e of this clock, but must
first have a falling clock and the rising clock, for
TMR1 to increment.
Figure 1 shows the two cases of writes to the
TMR1H and/or TMR1L registers. Due to the VIH
and VIL thresholds on the oscillator/clock pins,
external Timer1 oscillator components, and exter-
nal clock frequency, the Timer1 increment clock
may not be of a 50% duty cycle.
The TMR1 increment clock is out of phase of the
T1OSO/T 1C KI pin by a sma ll propagatio n dela y.
FIGURE 1: WRITES TO TIMER1 (EXTERNAL CLOCK/OSCILLATOR MODE)
Param
No. Sym. Characteristic New Specification Data Sheet
Specification Units
Min Typ Max Min Typ Max
71 TSCHSCK input high time
(Slave mode) Continuous 1.25 TCY
+ 30 ns —— TCY
+ 20 ns —— ns
71A Single Byte(1) 40 —— N.A. ns
72 TSCLSCK input low time
(Slave mode) Continuous 1.25 TCY
+ 30 ns —— TCY
+ 20 ns —— ns
72A Single Byte(1) 40 —— N.A. ns
73A TB2B Last clock edge of the Byte1 to 1st
clock edge of the Byte2(1) 1.5 TCY
+ 40 ns —— N.A. ns
* This parameter is characterized but not tested.
Note 1: Specification 73A is only required if specifications 71A and 72A are used.
TMR1 Increment
Write to TMR1H
TMR1H:TMR1L Increments
Write to TMR1H
TMR1H:TMR1L Increments
Clock (Input to Prescaler)
and/or TMR1L Register(s) and/or TMR1L Register(s)
PIC16C73A
DS80088A-page 6 2001 Microchip Technology Inc.
5. Module: RC Oscillator
The table for RC Oscillator Frequencies in the
Device Characterization section of the Data Sheet
is incorrect. The correct characterization informa-
tion is shown in Table 4.
TABLE 4: RC OSCILLATOR FREQUENCIES CHARACTERIZATION CHANGES
FROM DATA SHEET
6. Module: Brown-Out Reset (BOR)
The levels specified for the BOR module thresh-
olds (parameter D005) have changed. The new
values are shown in Table 5. .
CEXT REXT Correct Characterization Data Current Data Sheet Va lues
Average % Variation Average % Variation
22 pF 5.1 K 3.55 MHz ± 9.63% 4.12 MHz ± 1.4%
10 K 1.99 MHz ± 10.53% 2.35 MHz ± 1.4%
100 K 221.9 kHz ± 12.10% 268 kHz ± 1.1%
100 pF 3.3 K 1.77 MHz ± 10.67% 1.80 MHz ± 1.0%
5.1 K 1.22 MHz ± 10.41% 1.27 MHz ± 1.0%
10 K 669.4 kHz ± 10.92% 688 kHz ± 1.2%
100 K 71.5 kHz ± 11.21% 77.2 kHz ± 1.0%
330 pF 3.3 K 625.1 kHz ± 10.6 8% 707 kHz ± 1.4%
5.1 K 428.5 kHz ± 10.96% 501 kHz ± 1.2%
10 K 231.9 kHz ± 11.32% 269 kHz ± 1.6%
100 K 24.4 kHz ± 12.93% 28.3 kHz ± 1.1%
The per cent age va riation indica ted here is part-to -p art vari ation du e to normal pr ocess dis tributi on. The varia tion
indicated is ±3 standard deviation from the average value for VDD = 5V.
TABLE 5: MINIMUM AND MAXIMUM BOR RESET VOLTAGES
Param
No. Sym. Characteristic New Spec ific ation Data Shee t
Specification Units
Min Typ Max Min Typ Max
D005 VBOR Brown-out Reset Voltage 3.65 —4.35 3.70 —4.30 V
2001 Microchip Technology Inc. DS80088A - page 7
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