8701CY www.idt.com REV. E JULY 31, 2010
1
ICS8701
LOW SKEW,
÷
1,
÷
2
LVCMOS/LVTTL CLOCK GENERATOR
GENERAL DESCRIPTION
The ICS8701 is a low skew, ÷1, ÷2 LVCMOS/LVTTL Clock
Generator . The low impedance LVCMOS outputs are
designed to drive 50Ω series orparallel terminated
transmission lines. The effective fanout can be increased
from 20 to 40 by utilizing the ability of the outputs to drive
two series terminated lines.
The divide select inputs, DIV_SELx, control the output
frequency of each bank. The outputs can be utilized in the
÷1, ÷2 or a combination of ÷1 and ÷2 modes. The bank
enable inputs, BANK_EN0:1, support enabling and
disabling each bank of outputs individually. The master
reset input, nMR/OE, resets the internal frequency dividers
and also controls the active and high impedance states of
all outputs.
The ICS8701 is characterized at 3.3V and mixed
3.3V input supply, and 2.5V output supply operating
modes. Guaranteed bank, output and part-to-part skew
characteristics make the ICS8701 ideal for those clock
distribution applications demanding well defined
performance and repeatability.
FEATURES
• Twenty LVCMOS outputs, 7Ω typical output impedance
• One LVCMOS/LVTTL clock input
• Maximum output frequency: 250MHz
• Bank enable logic allows unused banks to be disabled
in reduced fanout applications
• Output skew: 250ps (maximum)
• Part-to-part skew: 600ps (maximum)
• Bank skew: 200ps (maximum)
• Multiple frequency skew: 300ps (maximum)
• 3.3V or mixed 3.3V input, 2.5V output operating
supply modes
• 0°C to 70°C ambient operating temperature
• Other divide values available on request
• Available in both standard and lead-free RoHS compliant
packages
BLOCK DIAGRAM PIN ASSIGNMENT
DIV_SELA
DIV_SELB
DIV_SELC
DIV_SELD
nMR/OE
BANK_EN0
BANK_EN1
QA0:QA4
QB0:QB4
QC0:QC4
QD0:QD4
CLK
48 47 46 45 44 43 42 41 40 39 38 37
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
QC3
VDDO
QC4
QD0
VDDO
QD1
GND
QD2
GND
QD3
VDDO
QD4
QB1
VDDO
QB0
QA4
VDDO
QA3
GND
QA2
GND
QA1
VDDO
QA0
DIV_SELA
DIV_SELB
CLK
GND
VDD
BANK_EN0
GND
BANK_EN1
VDD
nMR/OE
DIV_SELC
DIV_SELD
GND
QB2
GND
QB3
VDDO
QB4
QC0
VDDO
QC1
GND
QC2
GND
48-Pin LQFP
7mm x 7mm x 1.4mm
Y Package
Top View
ICS8701
1
0
÷1
÷2
1
0
1
0
1
0
Bank Enable
Logic
8701CY www.idt.com REV. E JULY 31, 2010
2
ICS8701
LOW SKEW,
÷
1,
÷
2
LVCMOS/LVTTL CLOCK GENERATOR
TABLE 1. PIN DESCRIPTIONS
rebmuNemaNepyTnoitpircseD
,11,5,2
,53,23,62
44,14
V
ODD
rewoP.snipylppustuptuO
,12,81,9,7
,73,03,82
84,64,93
DNGrewoP.dnuorgylppusrewoP
02,61V
DD
rewoP.snipylppusevitisoP
,92,72,52
33,13
,2AQ,1AQ,0AQ
4AQ,3AQ tuptuO .slevelecafretniLTTVL/SOMCVL.stuptuoAkn
aB
7Ω.ecnadepmituptuolacipyt
,83,63,43
24,04
,2BQ,1BQ,0BQ
4BQ,3BQ tuptuO .slevelecafretniLTTVL/SOMCVL.stuptu
oBknaB
7Ω.ecnadepmituptuolacipyt
,74,54,34
3,1
,2CQ,1CQ,0CQ
4CQ,3CQ tuptuO .slevelecafretniLTTVL/SOMCVL.stuptuoCknaB
7Ω.ecnadepmituptuolacipyt
,8,6,4
21,01
,2DQ,1DQ,0DQ
4DQ,3DQ tuptuO .slevelecafretniLTTVL/SOMCVL.stuptuoDknaB
7Ω.ecnadepmituptuolacipyt
22KLCtupnInwodlluP.tupnikcolcLTTVL/SOMCVL
31DLES_VIDtupnIpulluP .stuptuoDkna
BrofnoisividycneuqerfslortnoC
.slevelecafretniLTTVL/SOMCVL
41CLES_VIDtupnIpulluP .stuptuoCknaBrofnoisividyc
neuqerfslortnoC
.slevelecafretniLTTVL/SOMCVL
32BLES_VIDtupnIpulluP .stuptuoBknaBrofnoisividycneuqerfslortnoC
.slevelecafretniLTTVL/SOMCVL
42ALES_VIDtupnIpulluP .stuptuoAknaBrofnoisividycneuqerfslortnoC
.slevelecafretniLTTVL/SOMCVL
91,71 ,1NE_KNAB
0NE_KNAB tupnIpulluP .sknabybstuptuoselbasiddnaselbanE
.slevelecafretniLTTVL
/SOMCVL
51EO/RMntupnIpulluP
erasrevirdtuptuo,HGIHnehW.elbanetuptuodnateseRretsaM
.tesererasredividdnaZiHnierasrevirdtuptuo,WOLehW.delbane
.slevelecafretniLTTVL/SOMCVL
:ETON
pulluP
dna
nwodlluP
.seulavlacipytrof,scitsiretcarahCniP,2elbaTeeS.srotsisertupnilanretniotrefer
8701CY www.idt.com REV. E JULY 31, 2010
3
ICS8701
LOW SKEW,
÷
1,
÷
2
LVCMOS/LVTTL CLOCK GENERATOR
TABLE 2. PIN CHARACTERISTICS
TABLE 3. FUNCTION TABLE
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
C
NI
ecnaticapaCtupnI 4Fp
R
PULLUP
rotsiseRpulluPtupnI 15kΩ
R
NWODLLUP
rotsiseRnwodlluPtupnI 15kΩ
C
DP
ecnaticapaCnoitapissiDrewoP
)tuptuorep( V
DD
V,
ODD
V564.3=51Fp
R
TUO
ecnadepmItuptuO 7 Ω
stupnIstuptuO
EO/RMn1NE_KNAB0NE_KNABxLES_VID4AQ:0AQ4BQ:0BQ4CQ:0CQ4DQ:0DQycneuqerFxQ
0X X X ZiHZiHZiHZiHorez
10 0 0 evitcAZiHZiHZiH2/NIf
11 0 0 evitcAevitcAZiHZiH2/NIf
10 1 0 evitcAevitcAevitcAZiH2/NIf
11 1 0 evitcAevitcAevitcAevitcA2/NIf
10 0 1 evitcAZiHZiHZiHNIf
11 0 1 evitcAevitcAZiHZiHNIf
10 1 1 evit
cAevitcAevitcAZiHNIf
11 1 1 evitcAevitcAevitcAevitcANIf
8701CY www.idt.com REV. E JULY 31, 2010
4
ICS8701
LOW SKEW,
÷
1,
÷
2
LVCMOS/LVTTL CLOCK GENERATOR
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 3.3V±5% OR 2.5V±5%, TA = 0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
DD
egatloVylppuSevitisoP 531.33.3564.3V
V
ODD
egatloVylppuStuptuO 531.33.3564.3V
573.25.2526.2V
I
DD
tnerruCylppuSrewoP 59Am
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
DD 4.6V
Inputs, VI-0.5V to VDD + 0.5 V
Outputs, VO-0.5V to VDDO + 0.5V
Package Thermal Impedance, θJA 47.9°C/W (0 lfpm)
Storage Temperature, T
STG -65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Func-
tional operation of product at these conditions or any condi-
tions beyond those listed in the
DC Characteristics
or
AC
Characteristics
is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may affect prod-
uct reliability.
8701CY www.idt.com REV. E JULY 31, 2010
5
ICS8701
LOW SKEW,
÷
1,
÷
2
LVCMOS/LVTTL CLOCK GENERATOR
TABLE 4B. LVCMOS DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 3.3V±5% OR 2.5V±5%, TA = 0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
HI
tupnI
egatloVhgiH
,BLES_VID,ALES_VID
,DLES_VID,CLES_VID
,1NE_KNAB,0NE_KNAB
EO/RMn
2V
DD
3.0+V
KLC2V
DD
3.0+V
V
LI
tupnI
egatloVwoL
,BLES_VID,ALES_VID
,DLES_VID,CLES_VID
,1NE_KNAB,0NE_KNAB
EO/RMn
3.0-8.0V
KLC3.0-3.1V
I
HI
tupnI
tnerruChgiH
,BLES_VID,ALES_VID
,DLES_VID,CLES_VID
,1NE_KNAB,0NE_KNAB
EO/RMn
V
DD
=V
NI
V564.3=5Aµ
KLCV
DD
=V
NI
V564.3=051Aµ
I
LI
tupnI
tnerruCwoL
,BLES_VID,ALES_VID
,DLES_VID,CLES_VID
,1NE_KNAB,0NE_KNAB
EO/RMn
V
DD
,V564.3=V
NI
V0=051-Aµ
KLCV
DD
,V564.3=V
NI
V0=5-Aµ
V
HO
egatloVhgiHtuptuO
V
DD
V=
ODD
V531.3=
I
HO
Am63-= 6.2V
V
DD
,V531.3=
V
ODD
573.2=
I
HO
Am72-=
8.1V
V
LO
egatloVwoLtuptuO
V
DD
V=
ODD
V531.3=
I
LO
Am63= 5.0V
V
DD
,V531.3=
V
ODD
573.2=
I
LO
Am72=
5.0V
8701CY www.idt.com REV. E JULY 31, 2010
6
ICS8701
LOW SKEW,
÷
1,
÷
2
LVCMOS/LVTTL CLOCK GENERATOR
TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 70°C
TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA =0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
f
XAM
ycneuqerFtuptuO 052zHM
t
DP
1ETON;yaleDnoitagaporPf≤zHM0022.24.3sn
t
)b(ks7,2ETON;wekSknaBtaegdegnisirnoderusaeMV
ODD
2/002sp
t
)o(ks7,3ETON;wekStuptuOtaegdegnisirnoderusaeMV
ODD
2/052sp
t
(ksw) ;wekSycneuqerFelpitluM
7,4ETON taegdegnisirnoderusaeMV
ODD
2/003sp
t
)pp(ks7,5ETON;wekStraP-ot-traPtaegdegnisirnoderusaeMV
ODD
2/006sp
t
R
6ETON;emiTesiRtuptuO%07ot%03082058sp
t
F
6ETON;emiTllaFtuptuO%07ot%03082058sp
cdoelcyCytuDtuptuO f≤zHM002 2/ELCYCt
5.0- 2/ELCYCt 2/ELCYCt
5.0+ sn
zHM002=f25.23s
n
t
NE
;emiTelbanEtuptuO
6ETON zHM01=f6sn
t
SID
;emiTelbasiDtuptuO
6ETON zHM01=f6sn
.esiwrehtodetonsselnuzHM002taderusaemsretemarapllA
ehtmorfderusaeM:1ETO
NV
DD
ottupniehtfo2/V
ODD
/.tuptuoehtfo2
.snoitidnocdaollauqehtiwdnasegatlovylppusemasehttastuptuofoknabanihtiwwekssadenifeD:2ETO
N
.snoitidnocdaollauqehtiwdnaegatlovylppusemasehttastuptuoneewtebwekssadenifeD:3ETON
VtaderusaeM
ODD
.2/
segatlovylppusemasehthtiwycneuqerftnereffidtagnitarepostuptuofosknabssorcawekssadenifeD:4ETON
.snoi
tidnocdaollauqedna
dnasegatlovylppusemasehttagnitareposecivedtnereffidnostuptuoneewtebwekssadenifeD:5E
TON
Vtaderusaemerastuptuoeht,ecivedhcaenostupnifoepytemasehtgnisU.snoitidnocdaollauqehtiw
ODD
.2/
.noitcudorpnidetsettoN.noitaziretcarahcybdeetnaraugerasretemarapesehT:6ETON
.56dradnatSCEDEJhtiwecn
adroccanidenifedsiretemarapsihT:7ETON
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
f
XAM
ycneuqerFtuptuO 052zHM
t
DP
1ETON;yaleDnoitagaporPf≤zHM0026.26.3sn
t
)b(ks7,2ETON;wekSknaBtaegdegnisirnoderusaeMV
ODD
2/522sp
t
)o(ks7,3ETON;wekStuptuOtaegdegnisirnoderusaeMV
ODD
2/052sp
t
(ksw) ;wekSycneuqerFelpitluM
7,4ETON taegdegnisirnoderusaeMV
ODD
2/003sp
t
)pp(ks7,5ETON;wekStraP-ot-traPtaegdegnisirnoderusaeMV
ODD
2/006sp
t
R
6ETON;emiTesiRtuptuO%07ot%03082058sp
t
F
6ETON;emiTllaFtuptuO%07ot%03082058sp
cdoelcyCytuDtuptuO f≤zHM002 2/ELCYCt
5.0- 2/ELCYCt 2/ELCYCt
5.0+ sn
zHM002=f25.23sn
t
NE
;emiTelbanEtuptuO
6ETON zHM01=f6sn
t
SID
;emiTelbasiDtuptuO
6ETON zHM01=f6sn
.evobaA5Teesesaelp,setonroF
8701CY www.idt.com REV. E JULY 31, 2010
7
ICS8701
LOW SKEW,
÷
1,
÷
2
LVCMOS/LVTTL CLOCK GENERATOR
t
PD
V
DD
2
V
DDO
2
PARAMETER MEASUREMENT INFORMATION
OUTPUT SKEW
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
SCOPE
Qx
LVCMOS
1.65V±5%
-1.165V±5%
PART-TO-PART SKEW
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIIOD OUTPUT RISE/FALL TIME
t
sk(o)
V
DDO
2
V
DDO
2
Qy
Qx
Clock
Outputs
30%
70% 70%
30%
tRtF
GND
VDD,
VDDO
BANK SKEW (where X denotes outputs in the same bank)PROPAGATION DELAY
QA0:QA4,
QB0:QB4,
QC0:QC4,
QD0:QD4
CLK
t
PW
t
PERIOD
V
DDO
2
V
DDO
2
V
DDO
2
t
PW
t
PERIOD
odc =
QA0:QA4,
QB0:QB4,
QC0:QC4,
QD0:QD4
t
sk(pp)
V
DDO
2
V
DDO
2
Qy
Qx
Part 1
Part 2
SCOPE
Qx
LVCMOS
V
DDO
2
2.05V±5%
-1.25V±5%
GND
VDD
1.25V±5%
VDDO
t
sk(b)
V
DDO
2
V
DDO
2
QX0:QX4
QX0:QX4
8701CY www.idt.com REV. E JULY 31, 2010
8
ICS8701
LOW SKEW,
÷
1,
÷
2
LVCMOS/LVTTL CLOCK GENERATOR
POWER CONSIDERATIONS
For Power Dissipation, please refer to a separate Application
Note:
Power Dissipation for LVCMOS Buffer.
Driver Termination
For LVCMOS Output Termination, please refer to a separate
Application Note:
LVCMOS Driver Termination.
APPLICATION INFORMATION
INPUTS:
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
OUTPUTS:
LVCMOS OUTPUT:
All unused LVCMOS output can be left floating. We
recommend that there is no trace attached.
8701CY www.idt.com REV. E JULY 31, 2010
9
ICS8701
LOW SKEW,
÷
1,
÷
2
LVCMOS/LVTTL CLOCK GENERATOR
RELIABILITY INFORMATION
TRANSISTOR COUNT
The transistor count for ICS8701 is: 1743
TABLE 6. θJAVS. AIR FLOW TABLE FOR 48 LEAD LQFP
θθ
θθ
θJA by Velocity (Linear Feet per Minute)
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 55.9°C/W 50.1°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 47.9°C/W 42.1°C/W 39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
8701CY www.idt.com REV. E JULY 31, 2010
10
ICS8701
LOW SKEW,
÷
1,
÷
2
LVCMOS/LVTTL CLOCK GENERATOR
NOITAIRAVCEDEJ
SRETEMILLIMNISNOISNEMIDLLA
LOBMYS CBB
MUMINIMLANIMONMUMIXAM
N84
A----06.1
1A 50.0--51.0
2A 53.104.154.1
b71.022.072.0
c90.0--02.0
DCISAB00.9
1D CISAB00.7
2D .feR05.5
ECISAB00.9
1E CISAB00.7
2E .feR05.5
eCISAB05.0
L54.006.057.
0
θθ
θ
θθ 0
°
-- 7
°
ccc ----80.0
PACKAGE OUTLINE - Y SUFFIX FOR 48 LEAD LQFP
TABLE 7. PACKAGE DIMENSIONS
Reference Document: JEDEC Publication 95, MS-026
8701CY www.idt.com REV. E JULY 31, 2010
11
ICS8701
LOW SKEW,
÷
1,
÷
2
LVCMOS/LVTTL CLOCK GENERATOR
TABLE 8. ORDERING INFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Inc. (IDT) assumes no responsibility for either its use or for infringement of
any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial
applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves
the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
rebmuNredrO/traPgnikraMegakcaPgnigakcaPgnippihSerutarepmeT
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.tnailpmocSHoReradnanoitarugifnoceerF-bPehterarebmuntrapehtotxi
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8701CY www.idt.com REV. E JULY 31, 2010
12
ICS8701
LOW SKEW,
÷
1,
÷
2
LVCMOS/LVTTL CLOCK GENERATOR
TEEHSYROTSIHNOISIVER
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VotmumixaM8.3morfswor
DD
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DD
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01/13/7
8701CY www.idt.com REV. E JULY 31, 2010
13
ICS8701
LOW SKEW,
÷
1,
÷
2
LVCMOS/LVTTL CLOCK GENERATOR
We’ve Got Your Timing Solution.
Sales
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
Fax: 408-284-2775
Tech Support
netcom@idt.com
6024 Silver Creek Valley Road
San Jose, CA 95138
© 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc.
Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of
their respective owners.
Printed in USA
